NT6TL64T64CI-G0I_技术文档

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

2Gb/4Gb LPDDR2-S4B SDRAM B-Die

Nanya Technology Corp.

2Gb(SDP):NT6TL64M32CQ(I/A)/NT6TL128M16CQ(I/A)

4Gb(DDP):NT6TL64T64CR(5)

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Commercial and Industrial Mobile LPDDR2 2Gb / 4Gb(DDP) SDRAM

Features

 Data Integrity

 JEDEC LPDDR2 Compliant

- Low Power Consumption

- DRAM built-in Temperature Sensor for Temperature

Compensated Self Refresh (TCSR)

- Double-data rate on DQs, DQS, DM and CA bus

- 4n Prefetch Architecture

- Auto Refresh and Self Refresh Modes

 Power Saving Modes

 Signal Integrity

- Deep Power Down Mode (DPD)

- Partial Array Self Refresh (PASR)

- Clock Stop capability during idle period

 HSUL12 interface and Power Supply

- VDD1= 1.70 to 1.95V

- Configurable DS for system compatibility

- ZQ calibration for the accuracy of output driver

strength over Process, Voltage and Temperature

 Training for Signals’ Synchronization

- DQ Calibration offering specific DQ output patterns

- VDD2/VDDQ/VDDCA = 1.14 to 1.3V

Options

 Temperature Range (Tc)

 Speed Grade (DataRate/Read Latency)

- Commercial Grade = - 25℃ to + 85℃

- Industrial Grade = - 40℃ to + 85℃

- 1066 Mbps / RL=8

Programmable functions

 Read Latency (3/4/5/6/7/8),Write Latency (1/2/3/4)

 nWR (3/4/5/6/7/8)

 Output Drive Impedance (34.3/40/48/60/80/120)

 Burst Lengths (4/8/16)

 PASR(bank/segment)

 Burst Type (Sequential/Interleaved)

Packages / Density information

Lead-free RoHS compliance and Halogen-free

Density and Addressing

Items

128Mb x 16 64Mb x 32 64Mb x 64

Items

Width x Length x Height

(mm)

Ball pitch

(mm)

(Org. / FBGA Package)

Die Quantity

Device Type

Number of Banks

Bank Address

Row ¹

Single Die Single Die

Dual Die

S4B

8

S4B

8

10.00 x 11.50 x 0.80

11.50 x 11.50 x 0.80

12.00 x 12.00 x 0.80

12.00 x 12.00 x 0.70

0.65

2Gb

134b

8

(64Mb x 32)

(128Mb x16)

BA[2:0]

R[13:0]

C[9:0]

3.9

BA[2:0]

R[13:0]

C[8:0]

3.9

BA[2:0]

R[13:0]

C[8:0]

3.9

0.50

0.40

168b PoP

216b PoP

(2CH)

Column ¹

4Gb

(64Mb x 64)

220b PoP

(2CH)

14.00 x 14.00 x 0.80

0.50

tREFI (us) ²

Notes:

3. Row and Column Address values on the CA bus that are not used are “don’t care.”

4.tREFI values for all bank refresh is within temperature specification (<= 85℃).

Version 1.4

06/2016

1

Nanya Technology Corp.

NTC has the rights to change any specifications or product without notification.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Ordering Information

Speed

Density Organization

Part Number

Package

TCK

(ns)

Data Rate

(Mb/s/pin)

RL

Commercial Grade

NT6TL64M32CI-G0

134-Ball

168-Ball

134-Ball

168-Ball

216-Ball

220-Ball

1.875

1066

8

64Mb x 32

NT6TL64M32CA-G0

NT6TL64M32CQ-G0

NT6TL128M16CI-G0

NT6TL128M16CA-G0

NT6TL128M16CQ-G0

NT6TL64T64CR-G0

NT6TL64T64C5-G0

2Gb

(SDP)

128Mb x 16

4Gb

64Mb x 64

(2CH)

(DDP)

Industrial Grade

NT6TL64M32CI-G0I

134-Ball

1.875

1066

8

64Mb x 32

NT6TL64M32CA-G0I

NT6TL128M16CI-G0I

NT6TL128M16CA-G0I

2Gb

(SDP)

128Mb x 16

Version 1.4

06/2016

2

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

LPDDR2 Part Number Guide

NT

6T

L

64M32

C

Q

G0

Grade

NANYA

N/A =Commercial Grade

Technology

I =Industrial Grade

Product Family

Speed

6T = LPDDR2-S4 SDRAM

G0 = 1066Mbps @ RL=8

Package Code

Interface & Power (V_DD1, V_DD2, V_DDQ, V_DDCA

)

ROHS+Halogen-Free

L = HSUL_12 (1.8V, 1.2V, 1.2V, 1.2V)

A = 134-Ball FBGA (10x11.5 (mm))

I = 134-Ball FBGA (11.5x11.5 (mm))

Q = 168-Ball PoP-FBGA

Organization (Depth,

Width)

R = 216-Ball PoP-FBGA

5 = 220-Ball 2-CH PoP-FBGA

2Gb = 64M32 / 128M16

4Gb = 64T64

Device Version

C = 3^rdversion

Version 1.4

06/2016

3

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Descriptions

LPDDR2-S4 uses the double data rate architecture on the Command/Address (CA) bus to reduce the number

of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information.

Each command uses one clock cycle, during which command information is transferred on both the positive

and negative edge of the clock.

To achieve high-speed operation, our LPDDR2-S4 SDRAM uses the double data rate architecture and adopt

4n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write

access for the LPDDR2-S4 effectively consists of a single 4n-bit wide, one clock cycle data transfer at the

internal SDRAM core and four corresponding n-bit wide, one-half-clock-cycle data transfer at the I/O pins.

Read and write accesses to the LPDDR2-S4 are burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a programmed sequence.

For LPDDR2-S4 devices, accesses begin with the registration of an Active command, which is then followed

by a Read or Write command. The address and BA bits registered coincident with the Active command are

used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or

Write command are used to select the Bank and the starting column location for the burst access.

Version 1.4

06/2016

4

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power, Ground, Signals of Single Die, Single Channel Package

Part Number: NT6TL64M32CI-XXX, NT6TL64M32CA-XXX

Availability: 134b

V_DD1V_DD2V_DDQV_DDCA

V_ss

V_REFCA

V_REFDQ



2Gb

Device

ZQ

RZQ

CKE

CK



(64M x 32)

Die 0

DM_[3:0]

CA_[9:0]

DQ_[31:0]

DQS_[3:0]

_[3:0]

Power, Ground, Signals of Single Die, Single Channel Package

Part Number: NT6TL128M16CI-XXX, NT6TL128M16CA-XXX

Availability: 134b

V_DD1V_DD2V_DDQV_DDCA

V_ss

V_REFCA

V_REFDQ



2Gb

Device

ZQ

RZQ

CKE

CK



(128M x 16)

Die 0

DM_[1:0]

CA_[9:0]

DQ_[15:0]

DQS_[1:0]

_[1:0]

Version 1.4

06/2016

5

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power, Ground, Signals of Single Die, Single Channel Package

Part Number: NT6TL64M32CQ-XXX

Availability: 168b

V_DD1V_DD2V_DDQV_DDCAV_SSQV_SSCA

V_ss

V_REFCA

V_REFDQ



2Gb

Device

ZQ

RZQ

CKE

CK



(64M x 32)

Die 0

DM_[3:0]

CA_[9:0]

DQ_[31:0]

DQS_[3:0]

_[3:0]

Power, Ground, Signals of Single Die, Single Channel Package

Part Number: NT6TL128M16CQ-XXX

Availability: 168b

V_DD1V_DD2V_DDQV_DDCAV_SSQV_SSCA

V_ss

V_REFCA

V_REFDQ



2Gb

Device

ZQ

RZQ

CKE

CK



(128M x 16)

Die 0

DM_[1:0]

CA_[9:0]

DQ_[15:0]

DQS_[1:0]

_[1:0]

Version 1.4

06/2016

6

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power, Ground, Signals of Dual Die, Dual Channel Package

Part Number: NT6TL64T64CR-XXX

Available: 216b (2-channel)

V_DD1(b)V_DD2(b)V_DDQ(b)V_DDCA(b)

V_ss

V_REFCA(b)

V_REFDQ(b)



ZQ(b)

RZQ

CKE(b)

CK(b)

2Gb

Device



DM_[3:0](b)

CA_[9:0](b)

(64M x 32)

Channel B

DQ_[31:0](b)

DQS_[3:0](b)

_[3:0](b)

ZQ(a)

RZQ



2Gb

CKE(a)

CK(a)

Device



(64M x 32)

Channel A

DM_[3:0](a)

CA_[9:0](a)

DQ_[31:0](a)

DQS_[3:0](a)

_[3:0](a)

V_REFCA(a)

V_REFDQ(a)

V_DD1(a)V_DD2(a)V_DDQ(a)V_DDCA(a)

Version 1.4

06/2016

7

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power, Ground, Signals of Dual Die, Dual Channel Package

Part Number: NT6TL64T64C5-XXX

Available: 220b (2-channel)

V_DD1(a)V_DD2(a)V_DDQ(a)V_DDCA(a)V_REFCA(a)V_REFDQ(a)V_SS

(a)

CKE(a)

CK(a)

ZQ(a)

RZQ

2Gb

Device

(a)

DM_[3:0](a)

CA_[9:0](a)

(64M x 32)

Channel A

DQ_[31:0](a)

DQS_[3:0](a)

_[3:0](a)

ZQ(b)

RZQ

(b)

CKE(b)

CK(b)

(b)

DM_[3:0](b)

CA_[9:0](b)

2Gb

Device

(64M x 32)

Channel B

DQ_[31:0](b)

DQS _[3:0](b)

_[3:0](b)

V_DD1(b)V_DD2(b)V_DDQ(b)V_DDCA(b)V_REFCA(b)V_REFDQ(b)

Version 1.4

06/2016

8

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

LPDDR2 134-ball FBGA SDP X32 ballout

(10.00mm x 11.50mm, 0.65mm pitch)

Part Number: NT6TL64M32CA-XXX

(11.50mm x 11.50mm, 0.65mm pitch)

Part Number: NT6TL64M32CI-XXX

< TOP View>

See the balls through the package

A1

a

1

2

3

4

5

6

7

8

9

10

DNU

VDD1

VSS

DNU

NC

DNU

DQ26

VSS

DNU

VDDQ

VSS

A

B

C

D

E

F

A

NC

VDD2

VSS

VDD1

VSS

DQ31

VDDQ

DQ27

DM3

DQ29

DQ25

DQS3

DQ15

DQ14

DQ9

B

C

D

E

F

VSS

VDD2

CA9

CA6

CA5

VSS

NC

ZQ

VDDQ

DQ28

VSS

DQ30

DQ24

DQ11

DQS1

VDDQ

DQS0

DQ4



VDDQ

DQ12

DQ8

VSS

CA8

CA7

VREFCA



VSS

VDDCA

VDD2

VDDCA

VSS

DQ13

DQ10

VDDQ

VSS



DM1

G

H

J

G

H

J

CK

VSS

VDD2

VSS

VREFDQ

CKE

NC

DM0

K

L

M

N

P

K

L

M

N

P



NC



VSS

DQ5

DQ2

DQ6

DQ1

DQ7

DQ3

VSS

VDDQ

VSS

CA4

CA3

VDDCA

VDD2

VSS

NC

CA2

CA1

CA0

NC

VSS

DQ19

VDDQ

VSS

DQ23

DQ17

VSS

DM2

DQ0

VDDQ



VSS

DQ20

VDDQ

DQ16

DQS2

DQ22

DQ18

VSS

VDD1

DNU

VDDQ

DNU

R

T

U

R

T

U

NC

VDD2

VDD1

DQ21

DNU

1

2

3

4

5

6

7

8

9

10

NB (No Ball)

DNU (Do Not Use)

NC (No Connect)

Version 1.4

06/2016

9

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

LPDDR2 134-ball FBGA SDP X16 ballout

(10.00mm x 11.50mm, 0.65mm pitch)

Part Number: NT6TL128M16CA-XXX

(11.50mm x 11.50mm, 0.65mm pitch)

Part Number: NT6TL128M16CI-XXX

< TOP View>

See the balls through the package

A1

a

1

2

3

4

5

6

7

8

9

10

DNU

VDD1

VSS

DNU

NC

DNU

NC

DNU

VDDQ

VSS

A

B

C

D

E

F

A

NC

VDD2

VSS

VDD1

VSS

NC

VDDQ

NC

B

C

D

E

F

VSS

VDD2

CA9

CA6

CA5

VSS

NC

VSS

NC

ZQ

VDDQ

NC

VSS

CA8

CA7

VREFCA



NC

DQ15

DQ14

DQ9

VDDQ

DQ12

DQ8

VSS

VDDCA

VDD2

VDDCA

VSS

DQ11

DQS1

VDDQ

DQS0

DQ4

DQ13

DQ10

VDDQ

VSS



DM1

VSS

G

H

J

G

H

J

CK

VDD2

VSS

VREFDQ

CKE

NC

DM0



VSS

K

L

M

N

P

K

L

M

N

P



NC

DQ5

DQ2

NC

DQ6

DQ1

DQ0

NC

DQ7

DQ3

VDDQ

NC

VSS

VDDQ

VSS

CA4

CA3

VDDCA

VDD2

VSS

NC

CA2

CA1

CA0

NC

VSS

NC

VSS

VDDQ

VSS

NC

VSS

VDD1

DNU

VSS

VDDQ

NC

VSS

NC

VDDQ

DNU

R

T

U

R

T

U

NC

VDD2

VDD1

NC

DNU

1

2

3

4

5

6

7

8

9

10

NB (No Ball)

DNU (Do Not Use)

NC (No Connect)

Version 1.4

06/2016

10

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

LPDDR2 168-ball PoP-FBGA SDP 1-channel x 32 ballout

(12.00mm x 12.00mm, 0.50mm ball pitch)

Part Number: NT6TL64M32CQ-XXX

< TOP View>

See the balls through the package

A1

a

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

A

NC

NC VDD1 VSSQ DQ30 DQ29 VSSQ DQ26 DQ25 VSSQ  VDD1 VSS

NC

A

B

NC VDD1 NC

VSS VDD2 DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 DQS3 VDDQ DM3 VDD2 NC

C

D

E

F

VSS VDD2

DQ15 VSSQ

VDDQ DQ14

DQ12 DQ13

DQ11 VSSQ

VDDQ DQ10

DQ8 DQ9

DQS1 VSSQ

VDDQ 

VDD2 DM1

C

D

E

F

NC

VSS

G

H

J

G

H

J

K

L

K

L

VREF

VSS

DQ

M

N

P

R

T

M

N

P

R

T

NC VDD1

VDD1 DM0

 VSSQ

VDDQ DQS0

DQ6 DQ7

DQ5 VSSQ

VDDQ DQ4

DQ2 DQ3

DQ1 VSSQ

VREF

ZQ

CA

VSS VDD2

CA9 CA8

VDD

CA7

U

V

W

Y

U

V

W

Y

CA

VSS

CA6

CA

VDD

CA5

CA



CK

AA VSS VDD2

VDDQ DQ0 AA

VSS

CA

AB

AC

NC

1

NC

2



CKE

3

NC VDD1 CA1

CA3 CA4 VDD2 VSS DQ16 VDDQ DQ18 DQ20 VDDQ DQ22 DQS2 VDDQ DM2 VDD2 NC

VDD

NC AB

NC AC

23

NC

4

VSS CA0 CA2

NC

NC VSSQ DQ17 DQ19 VSSQ DQ21 DQ23 VSSQ  VDD1 VSS

NC

CA

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

Version 1.4

06/2016

11

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

LPDDR2 168-ball PoP-FBGA SDP 1-channel x 16 ballout

(12.00mm x 12.00mm, 0.50mm ball pitch)

Part Number: NT6TL128M16CQ-XXX

< TOP View>

See the balls through the package

A1

a

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

A

NC

NC VDD1 VSSQ NC

NC VSSQ NC

NC VDDQ

NC VSSQ NC VDD1 VSS

NC NC VDDQ

NC

A

B

NC VDD1 NC

VSS VDD2 NC VDDQ NC

NC VDD2 NC

C

D

E

F

VSS VDD2

DQ15 VSSQ

VDDQ DQ14

DQ12 DQ13

DQ11 VSSQ

VDDQ DQ10

DQ8 DQ9

DQS1 VSSQ

VDDQ 

VDD2 DM1

C

D

E

F

NC

VSS

G

H

J

G

H

J

K

L

K

L

VREF

VSS

DQ

M

N

P

R

T

M

N

P

R

T

NC VDD1

VDD1 DM0

 VSSQ

VDDQ DQS0

DQ6 DQ7

DQ5 VSSQ

VDDQ DQ4

DQ2 DQ3

DQ1 VSSQ

VREF

ZQ

CA

VSS VDD2

CA9 CA8

VDD

CA7

U

V

W

Y

U

V

W

Y

CA

VSS

CA6

CA

VDD

CA5

CA



CK

AA VSS VDD2

VDDQ DQ0 AA

VSS

CA

AB

AC

NC

1

NC

2



CKE

3

NC VDD1 CA1

CA3 CA4 VDD2 VSS

VDD

NC

VDDQ

NC

VDDQ

NC

VDDQ

NC VDD2 NC

NC AB

NC AC

23

NC

4

VSS CA0 CA2

NC

NC VSSQ NC

NC VSSQ NC VDD1 VSS

NC

22

CA

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

Version 1.4

06/2016

12

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

LPDDR2 216-ball PoP-FBGA DDP 2-channel 2x32 ballout

(12.00mm x 12.00mm, 0.40mm ball pitch)

Part Number: NT6TL64T64CR-XXX

< TOP View>

See the balls through the package

A1

a

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

VDD2 DQ30 DQ29

_a _a _a

DQ26 DQ25

_a _a





DQ14 DQ13

_a _a

VDD1 VDD2 DQ11 DQ10 DQ9_ DQS1 DM1_ VDDQ DQS0 DQ7_ DQ6_ DQ4_ DQ3_

A

NC

VSS

NC

VSS

NC

A

B

_a

a

_a

a

_a

DM0_ 



_a

a

DQ31 VDDQ DQ28 DQ27 VDDQ DQ24 VDDQ DQS3 DM3_ DQ15 VDDQ

VREF VDD2 DQ12 VDDQ DQ8_ 

VDDQ DQ5_ DQ2_

B

VSS

_a

a

_a

DQ_a

_a

a



a

_a

a

VDD1 DQ16

_b _b

DQ17 VDDQ

_b _b

DQ18 DQ19

VDD1 VDD2

_a _a

DQ1_ VDDQ

C

D

E

a

_a

DQ0_

a

E

VSS

_b

DQ20

_b

DM2_ VDDQ

_a

DQS2 

F

VSS

F

a

DQ21 VDDQ

_b _b

DQ22 DQ23

G

H

J

_a



DQ23

_a

H

VSS

_b

VDDQ

_b

VDDQ DQ22

_a _a

DQ20 DQ21

J

VSS

 DQS2

 _b

DM2_ DQ0_

K

L

_a

DQ19

_a

L

VSS

b

DQ1_

b

VDDQ DQ18

_a _a

DQ16 DQ17

_a _a

VDD2 VDD1

M

N

VSS

M

N

P

DQ2_ VDD1

_b

b

P

VSS VSS

_b

VDD1 VREF

CA0_

b

R

VSS

R

_b

VDD2 VDD2

_b _b

VDDQ DQ3_

DQ_b

VDDC CA1_

A_b

VREF CA2_

T

b

U

V

W

Y

AA

_b

b

CA_b

b

DQ4_

b

CA3_

b

V

VSS

DQ6_ DQ5_

CA4_

b

W

Y

NC

b

VDDQ DQ7_

_b

DQS0 

 NC

b

VSSC CKE_

AA

AB

AC

AD

AE

AF

AG

AH

AJ

_b



A_b

b

DM0_

b

VSS

CK_b  AB

VDDQ DM1_

_b

 DQS1

VDDC CA5_

AC

b

A_b

b

CA7_ CA6_

AD

AE

AF



_b

b

DQ8_

b

CA8_ VDDC

VSS

b

A_b

DQ9_ VDDQ

_b

DQ10 DQ11

CA9_

b

VSS

b

VDD2

_b

ZQ_b AG

_b

VDD1 VDD2 DQ13

DQ15 DM3_ DQS3 VDDQ DQ26 DQ27 VDDQ DQ30

VDD2 VREF CA9_

_a CA_a

CA7_ CA6_

VDDC CKE_

CA3_ CA2_ CA1_ VDD1

VSS





VSS

NC

AH

AJ

_b

b

_b

a

A_a

a

_a

DQ12 VDDQ DQ14 VDDQ

 DQ24 DQ25

DQ28 DQ29 DQ31 VDD1

CA8_ VDDC CA5_

CA4_ VDDC CA0_

NC

VSS

VSS ZQ_a

CK_a VSS

NC

VSS

_b



_b

_a

a

A_a

a

A_a

a

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

Version 1.4

06/2016

13

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

LPDDR2 220-ball PoP-FBGA DDP 2-channel 2x32 ballout

(14.00mm x 14.00mm, 0.50mm pitch)

Part Number: NT6TL64T64C5-XXX

< TOP View>

See the balls through the package

A1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

VSS

NC

27

a

VDD2

_b

DQ29 DQ28

_b _b

DQ25 DQ24  DM3_ DQ15

DQ13 DQ11

_b _b

DQ9_  DM1_



VDD2  DQ7_

_b 

A

DNU

VSS

NC

VSS

VSS VSS

VSS

DNU

A

B

_b



b

_b

b

VDDQ DQ31 DQ30 VDDQ DQ27 DQ26 VDDQ DQS3

_b _b _b _b _b _b _b _b

VDDQ DQ14 DQ12 VDDQ DQ10 DQ8_ DQS1 VDDQ VREF VDD1 DM0_ DQS0 VDDQ DQ6_

VDD2_

b

B

VDD1_b

DQ16_a

DQ18_a

VSS

_b

b

_b

DQ_b

_b

b

_b

b

DQ17_

C

D

E

DQ5_b DQ4_b

C

D

E

a

VDDQ_

a

VDDQ

DQ3_b

_b

DQ20_ DQ19

DQ2_

b

DQ1_b VSS

a

VDDQ_

a

_a

VDDQ

DQ0_b

_b

F

DQ21_a

VSSQ

F

DQ22_ DQ23

DM2_ DQS2_

G

H

J

VSS

G

H

J

a

_a

b

 DQ23_

DQS2_a 



DQ21 DQ22_

_b

b

DQ0_

a

VSS

DQ1_a

VSS

DM2_a

VSS

b

VDDQ_

a

VDDQ DQ20_

K

_b

DQ19 DQ18_

_b

b

DQ3_

a

L

DQ2_a

VSS

L

b

VDDQ_

a

VDD2_ DQ17_

M

N

P

DQ4_a

VSS

M

N

P

b

DQ6_

a

DQ16 VDDQ

DQ5_a

VSS

_b

VDDQ_

a

VDDC

A_a

DQ7_a

VSS

CA0_a

DQS0

_a

CA1_

a

R

T



CA2_a VSS

CA3_a CA4_a

R

T

VDDQ_

a

DM0_a

VSS

VREF

DQ_a

U

V

VSS



NC

VSS

NC

U

V

VDD1_

a

VDD2_a

VSS

CKE_a

VDD2_ DM1_

W

Y

 CK_a

VSS

W

Y

a

DQS1_

a

VDDC

A_a



VSS

CA5_a

DQ10

_a

VREF

CA6_a

CA_a

VDD2_

a

AA

DQ9_a

AA

VDDQ_

a

AB DQ8_a

AC

VSS

AD DQ13_a

CA7_a VSS AB

CA9_a VSS AC

DQ11_ DQ12

CA8_

a

DQ14_

a

_a

VDDC VDD2_

AD

A_a

VDD1_

a

DQ15_

a

AE

AF

AG

VSS

DNU

1

ZQ_a AE

VDDQ_ DM3_ DQS3  DQ25 DQ27 VDDQ DQ29 DQ31 VDD2 VDD1 VDDC CA9_ CA7_ VDD2 VREF VDDC

CA4_ VDDC CA2_ CA0_ VDD2_

CK_b NC

CKE_



NC

VSS

AF

a

VDD2_

a

_a



_a

VSS VSS ZQ_b VSS

10 11 12 13

_a

A_b

b

_b

CA_b A_b

b

A_b

b

VDD1_

b

VDDQ DQ24 DQ26

DQ28 DQ30

CA8_ CA6_ CA5_

CA3_ CA1_

VSS

VSS VSS 

VSS

DNU AG

_a

4

_a

5

_a

6

_a

8

_a

9

b

2

3

7

14

15

16

17 18 19

20

21

22

23

24

25

26

27

Version 1.4

06/2016

14

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

134-ball Package Outline Drawing

Part Number: NT6TL64M32CI-XXX, NT6TL128M16CI-XXX

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.4

06/2016

15

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

134-ball Package Outline Drawing

Part Number: NT6TL64M32CA-XXX, NT6TL128M16CA-XXX

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.4

06/2016

16

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

168-ball Package Outline Drawing

Part Number: NT6TL64M32CQ-XXX, NT6TL128M16CQ-XXX

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.4

06/2016

17

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

216-ball Package Outline Drawing

Part Number: NT6TL64T64CR-XXX

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.4

06/2016

18

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

220-ball Package Outline Drawing

Part Number: NT6TL64T64C5-XXX

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.4

06/2016

19

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Ball Descriptions

Symbol

Type

Function

Clock: CK and  are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled

on both positive and negative edge of CK. Single Data Rate (SDR) inputs,  and CKE, are sampled

at the positive Clock edge. Clock is defined as the differential pair, CK and . The positive Clock

edge is defined by the crosspoint of a rising CK and a falling . The negative Clock edge is defined

by the crosspoint of a falling CK and a rising .

CK, 

Input

Clock Enable: CKE high activates, and CKE low deactivates internal clock signals, and device input

buffers and output drivers. Power saving modes are entered and exited through CKE transitions.

CKE is considered part of the command code. CKE is sampled at the positive Clock edge.

Chip Select:  is considered part of the command code.  is sampled at the positive Clock edge.

Command/Address Inputs: Uni-directional command/address bus inputs. Provide the command

and address inputs according to the command truth table. CA is considered part of the command

code.

CKE



Input

CA[9:0]

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of

DQS. Although DM pins are input-only, the DM loading matched the DQ and DQS (or ).

DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on DQ8-DQ15, DM2

corresponds to the data on DQ16-DQ23, and DM3 corresponds to the data on DQ24-DQ31.

For X16: DM[1:0]

For X32: DM[3:0]

Input

For X16:DQ[15:0]

For X32:DQ[31:0]

Input/output Data Bus: Bi-directional Input / Output data bus.

Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for read and write

data) and Differential (DQS and ). It is output with read data and input with write data. DQS is

edge-aligned to read data, and centered with write data.

DQS, 

For X16:

DQS[1:0], [1:0] Input/output

For X32:

DQS0 &  corresponds to the data on DQ0-DQ7, DQS1 &  corresponds to the data on

DQ8-DQ15, DQS2 &  corresponds to the data on DQ16-DQ23, DQS3 &  corresponds to

the data on DQ24-DQ31.

DQS[3:0], [3:0]

NC

ZQ

-

No Connect: No internal electrical connection is present.

Reference Pin for Output Drive Strength Calibration. External impedance (240-ohm): this signal

is used to calibrate the device output impedance.

Input

Supply

Core Power Supply 1: Core power supply

VDD1

VDD2

VDDQ

VDDCA

Core Power Supply 2: Core power supply

DQ Power Supply: Isolated on the die for improved noise immunity.

Input Receiver Power Supply: Power supply for CA0-9, CKE, , CK, and  input buffers.

Reference Voltage: VREFDQ is reference for DQ input buffers. VREFCA is reference for Command /

VREFDQ, VREFCA

Supply

Address input buffers.

Version 1.4

06/2016

20

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Symbol

VSS

Type

Function

Supply

Ground

VSSQ

DQ Ground: Isolated on the die for improved noise immunity.

VSSCA

Command / Address Ground: Isolated on the die for improved noise immunity.

NOTE 1: The signal may show up in a different symbol but it indicates to the same thing. e.g., /CK = CK# =  =

CKb, /DQS = DQS# =  = DQSb, /CS = CS# =  = CSb.

Version 1.4

06/2016

21

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Simplified State Diagram

Abbr.

ACT

Function

Abbr.

PD

Function

Abbr.

REF

Function

Active

Enter Power Down

Refresh

RD(A)

WR(A)

PR(A)

MRW

MRR

Read (w/ Autoprecharge)

Write (w/ Autoprecharge)

Precharge (All)

PDX

Exit Power Down

SREF

SREFX

Enter self refresh

Exit self refresh

DPD

Enter Deep Power Down

Exit Deep Power Down

Burst Terminate

DPDX

BST

Mode Register Write

Mode Register Read

RESET

Reset is achieved through MRW command

NOTE1: For LPDDR2-S4 SDRAM in the idle state, all banks are precharged.

Version 1.4

06/2016

22

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Units

V

V_DD1

V_DD2

Voltage on V_DD1pin relative to Vss

Voltage on V_DD2pin relative to Vss

Voltage on V_DDCApin relative to Vss

Voltage on V_DDQpin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature (plastic)

-0.4

-55

2.3

1.6

V

V_DDCA

V_DDQ

1.6

V

1.6

V

Vin, Vout

Tstg

1.6

+125

C

Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For measurement conditions,

refer to the JESD51-2 standard.

3. VDD2 and VDDQ / VDDCA must be within 200mV of each other at all times.

4. Voltage on any I/O may not exceed voltage on VDDQ; Voltage on any CA input may not exceed voltage on VDDCA.

5. VREF must always be less than all other supply voltages.

6. The voltage difference between any VSS, VSSQ, or VSSCA pins may not exceed 100mV.

Version 1.4

06/2016

23

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

AC/DC Operating Conditions

DC Operating Conditions

Symbol

Parameter

Min

Typical

Max

Unit

Notes

Power Supply

1.70

1.14

1.80

1.20

1.95

1.30

V

V_DD1

V_DD2

Core Supply voltage 1

Core Supply voltage 2

V_DDCA

V_DDQ

Leakage current

Input leakage current

Input Supply Voltage (Command / Address)

I/O Supply voltage (DQ)

Any input 0 ≦ V_IN≦ V_DDQ/ V_DDCA

,

-2

-1

-

2

1

uA

1

I_I

All other pins not under test = 0V

V_REFleakage current; V_REFDQ= V_DDQ/2 or

V_REFCA= V_DDCA/2 (all other pins not under test

= 0V)

I_VREF

Notes:

1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal.

Although DM is for input only, the DM leakage shall match the DQ and DQS,  output leakage specification.

Temperature Range

Symbol

Parameter

Standard

Extended

Min

-25

85

Max

85

Unit

T_OPER

C

105

Notes:

1. Operating temperature is the case surface temperature at the center of the top side of the device. For measurement conditions,

refer to the JESD51-2 standard.

2. Some applications require operation of LPDDR2 in the maximum temperature conditions in the Extended Temperature Range

between 85C and 105C case temperature. For LPDDR2 devices, some derating is necessary to operate in this range. See MR4.

3. Either the device case temperature rating or the temperature sensor (See “Temperature Sensor”) may be used to set an

appropriate refresh rate, determine the need for AC timing de-rating and/or monitor the operating temperature. When using

the temperature sensor, the actual device case temperature may be higher than the TOPER rating that applies for the Standard

or Extended Temperature Ranges. For example, TCASE may be above 85C when the temperature sensor indicates a

temperature of less than 85 C.

Version 1.4

06/2016

24

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

AC/DC Input Measurement Level

AC and DC Logic Levels for Single-Ended Signals

CA inputs (Address and Command) and  inputs

LPDDR2 1066

Symbol

Parameter

Unit Notes

Min

Max

AC Input logic HIGH voltage

DC Input logic HIGH voltage

AC Input logic LOW voltage

DC Input logic LOW voltage

mV

V

1,3

1

V_IHCA(AC)

V_IHCA(DC)

V_ILCA(AC)

V_ILCA(DC)

V_REFCA(DC)

V_REFCA+ 220 mV

V_REFCA+ 130 mV

-

V_DDCA

1,3

1

V_REFCA– 220 mV

V_REFCA– 130 mV

0.51 x V_DDCA

V_SSCA

Reference voltage for CA and 

4,5

0.49 x V_DDCA

inputs

Data inputs (DQ & DM)

AC Input logic HIGH voltage

mV

V

2,3

1

V_IHDQ(AC)

V_IHDQ(DC)

V_ILDQ(AC)

V_ILDQ(DC)

V_REFDQ(DC)

V_REFDQ+ 220 mV

V_REFDQ+ 130 mV

-

DC Input logic HIGH voltage

AC Input logic LOW voltage

DC Input logic LOW voltage

V_DDQ

2,3

1

V_REFDQ– 220 mV

V_REFDQ– 130 mV

0.51 x V_DDQ

V_SSQ

Reference voltage for DQ and DM

inputs

4,5

0.49 x V_DDQ

Clock enable inputs (CKE)

Symbol

Parameter

Min

Max

Unit Notes

CKE AC Input HIGH voltage

CKE AC Input LOW voltage

V

3

V_{IHCKE (AC)}

V_{ILCKE (AC)}

0.8 * V_DDCA

-

0.2 * V_DDCA

NOTE 1 For CA and  input only pins. Vref = VrefCA(DC).

NOTE 2 For DQ input only pins. Vref = VrefDQ(DC).

NOTE 3 See “Overshoot and Undershoot Specifications”

NOTE 4 The ac peak noise on VRefCA may not allow VRefCA to deviate from VRefCA(DC) by more than +/-1% VDDCA (for reference:

approx. +/- 12 mV).

NOTE 5 For reference: approx. VDDCA/2 +/- 12 mV.

Version 1.4

06/2016

25

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

V_REFTolerance

The DC tolerance limits and AC noise limits for the reference voltages V_REFCAand V_REFDQare illustrated bellow. This figure

shows a valid reference voltage V_REF(t) as a function of time. VDD is used in place of V_DDCAfor V_REFCA, and V_DDQfor

V_REFDQ. V_REF(DC)is the linear average of V_REF(t) over a very long period of time (e.g., 1 second) and is specified as a

fraction of the linear average of V_DDQor V_DDCA, also over a very long period of time (e.g., 1 second). This average must

meet the MIN/MAX requirements. Additionally, V_REF(t) can temporarily deviate from V_REF(DC)by no more than ±1% VDD.

V_REF(t) cannot track noise on V_DDQor V_DDCAif doing so would force V_REFoutside these specifications.

V_REFDC Tolerance and V_REFAC Noise Limits

The voltage levels for setup and hold time measurements V_IH(AC), V_IH(DC), V_IL(AC), and V_IL(DC)are dependent on V_REF. V_REF

DC variations affect the absolute voltage a signal must reach to achieve a valid HIGH or LOW, as well as the time from

which setup and hold times are measured. When V_REFis outside the specified levels, devices will function correctly with

appropriate timing deratings as long as:

• V_REFis maintained between 0.44 x V_DDQ(or V_DDCA) and 0.56 x V_DDQ(or V_DDCA), and the controller achieves the required

single-ended AC and DC input levels from instantaneous V_REF

.

System timing and voltage budgets must account for V_REFdeviations outside this range.

The setup/hold specification and derating values must include time and voltage associated with V_REFAC noise. Timing

and voltage effects due to AC noise on VREF up to the specified limit (±1% VDD) are included in LPDDR2 timings and

their associated deratings.

Version 1.4

06/2016

26

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Input Signal LPDDR2-1066 Input Signal

LPDDR2 1066 Input Signal

Notes:

1. Numbers reflect typical values.

2. For CA[9:0], CK, , , and CKE, VDD stands for VDDCA. For DQ, DM, DQS, and , VDD stands for VDDQ.

3. For CA[9:0], CK, , , and CKE, VSS stands for VSSCA. For DQ, DM, DQS, and , VSS stands for VSSQ.

Version 1.4

06/2016

27

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

AC and DC Logic Levels for Differential Signals

Differential AC and DC Input Levels

Differential Inputs logical levels (CK,  – V_REF= V_REFCA(DC); DQS, : V_REF= V_REFDQ(DC)

)

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

Differential input voltage HIGH AC

Differential input voltage LOW AC

Differential input voltage HIGH DC

Differential input voltage LOW DC

2 x (V_IH(AC)-V_REF

)

Note 3

2 x (V_REF-V_IL(AC)

Note 3

V_IHdiff(AC)

V_ILdiff(AC)

V_IHdiff(DC)

V_ILdiff(DC)

V

Note 3

)

2 x (V_IH(DC)-V_REF

)

Note 3

2 x (V_REF-V_IL(DC)

)

Notes:

1. Used to define a differential signal slew-rate. For CK –  use VIH/VIL(dc) of CA and VREFCA; for DQS – , use VIH/VIL(dc) of DQs

and VREFDQ; if a reduced dc-high or dc-low level is used for a signal group, then the reduced level applies also here.

2. For CK and , use V_IH/VIL(AC)of CA and V_REFCA; for DQS and , use V_IH/VIL(AC)of DQ and V_REFDQ. If a reduced AC HIGH or AC LOW

is used for a signal group, the reduced voltage level also applies.

3. These values are not defined, however the single-ended signals CK, , DQS, and  must be within the respective limits

(V_IH(DC)max, V_IL(DC)min) for single-ended signals and must comply with the specified limitations for overshoot and undershoot.

Version 1.4

06/2016

28

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

CK,  and DQS,  Time Requirement before Ring back (t_DVAC

)

t_DVAC(ps) at

Slew Rate

V_IH/V_ILdiff(AC)= 440 mV

(V/ns)

Min

175

170

167

163

162

161

159

155

150

>4.0

4.0

3.0

2.0

1.8

1.6

1.4

1.2

1.0

<1.0

Version 1.4

06/2016

29

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Single-Ended Requirements for Differential Signals

Each individual component of a differential signal (CK, , DQS, and ) must also comply with certain requirements

for single-ended signals. CK and  must meet V_SEH(AC)min/V_SEL(AC)max in every half cycle. DQS,  must meet

V_SEH(AC)min/V_SEL(AC)max in every half cycle preceding and following a valid transition.

The applicable AC levels for CA and DQ differ by speed-bin.

Single-Ended Requirement for Differential Signals

Note that while CA and DQ signal requirements are referenced to VREF, the single-ended components of differential signals also

have a requirement with respect to VDDQ/2 for DQS, and VDDCA/2 for CK. The transition of single-ended signals through the AC

levels is used to measure setup time. For single-ended components of differential signals, the requirement to reach V_SEL(AC)max or

V_SEH(AC)min has no bearing on timing; this requirement does, however, add a restriction on the common mode characteristics of

these signals.

Version 1.4

06/2016

30

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Single-Ended Levels for CK, , DQS, 

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

Single-ended HIGH level for strobes

Single-ended HIGH level for CK, 

Single-ended LOW level for strobes

Single-ended LOW level for CK, 

(V_DDQ/2) + 0.22

Note 3

V

V_SEH(AC)

(V_DDCA/2) + 0.22

Note 3

(V_DDQ/2) - 0.22

(V_DDCA/2) - 0.22

V_SEL(AC)

Note 3

Notes:

1. For CK and , use VSEH/VSEL(AC) of CA; for strobes (DQS[3:0] and [3:0]) use VIH/VIL(AC) of DQ.

2. VIH(AC) and VIL(AC) for DQ are based on VREFDQ; VSEH(AC) and VSEL(AC) for CA are based on VREFCA. If a reduced AC HIGH or AC

LOW is used for a signal group, the reduced level applies.

3. These values are not defined, however the single-ended signals CK, , DQS0, , DQS1, , DQS2, , DQS3,

 must be within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals, and must comply with the

specified limitations for overshoot and undershoot.

Version 1.4

06/2016

31

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Differential input Cross-Point Voltage

To ensure tight setup and hold times as well as output skew parameters with respect to clock and strobe, each

cross-point voltage of differential input signals (CK, , DQS, and ) must meet the specifications bellow. The

differential input cross-point voltage (V_IX) is measured from the actual cross point of true and complement signals to the

midlevel between VDD and Vss .

V_IXdefinition

Cross-Point Voltage for Differential Input Signals (CK, , DQS, )

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

Differential input cross-point voltage relative to VDDCA/2 for CK and 

Differential input cross-point voltage relative to VDDQ/2 for DQS and 

-120

+120

mV

V_IXCA(AC)

-120

+120

V_IXDQ(AC)

Notes:

1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and it is expected to track variations

in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.

2. For CK and , VREF = VREFCA(DC). For DQS and , VREF = VREFDQ(DC).

Version 1.4

06/2016

32

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Slew Rate Definitions for Single-Ended Input Signals

Refer to single-ended slew rate definition for address, command and data signals respectively.

Slew Rate Definitions for Differential Input Signals

Measured

From

Description

Defined by

To

Differential input slew rate for rising edge

(CK,  and DQS, )

[VIHdiffmin – VILdiffmax] / ΔTRdiff

[VIHdiffmin – VILdiffmax] / ΔTFdiff

VILdiffmax

VIHdiffmin

Differential input slew rate for falling edge

(CK,  and DQS, )

VILdiffmax

Notes:

1. The differential signals (CK,  and DQS, ) must be linear between these thresholds.

Differential Input Slew Rate Definition for CK, , DQS and 

Version 1.4

06/2016

33

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

AC/DC Output Measurement Level

Single-Ended AC and DC Output Levels

Symbol

Parameter

LPDDR2 1066

Unit Notes

VREF + 0.12

VREF – 0.12

0.9 x VDDQ

0.1 x VDDQ

-5

V

VOH(AC)

AC output HIGH measurement level (for output slew rate)

AC output LOW measurement level (for output slew rate)

DC output HIGH measurement level (for I-V curve linearity)

DC output LOW measurement level (for I-V curve linearity)

VOL(AC)

VOH(DC)

VOL(DC)

V

1

2

Min

uA

Output leakage current (DQ, DM, DQS, )

(DQ, DQS,  are disabled; 0V ≤ VOUT ≤ VDDQ)

IOZ

Max

5

Min

-15

15

%

Delta output impedance between pull-up and pull-down

for DQ/DM

MMpupd

Max

Notes:

1. I_OH= –0.1mA

2. I_OL= 0.1mA

Differential AC and DC Output Levels

Symbol

Parameter

LPDDR2 1066

Unit Notes

+ 0.20 x VDDQ

- 0.20 x VDDQ

V

1

2

VOHdiff(AC)

AC differential output HIGH measurement level (for output SR)

AC differential output LOW measurement level (for output SR)

VOLdiff(AC)

Notes:

1. I_OH= –0.1mA

2. I_OL= 0.1mA

Version 1.4

06/2016

34

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Single Ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured

between VOL(AC) and VOH(AC) for single ended signals as shown below.

Single-Ended Output Slew Rate Definition

Measured

Description

Defined by

From

To

[VOH(AC) – VOL(AC)] / ΔTRSE

[VOH(AC) – VOL(AC)] / ΔTFSE

Single-ended output slew rate for rising edge

VOL(AC)

VOH(AC)

Single-ended output slew rate for falling edge

VOH(AC)

VOL(AC)

Notes:

Output slew rate is verified by design and characterization, and may not be subject to production testing.

Single-Ended Output Slew Rate Definition

Version 1.4

06/2016

35

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Single-Ended Output Slew Rate

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

Single-ended output slew rate (output impedance = 40Ω ± 30%)

Single-ended output slew rate (output impedance = 60Ω ± 30%)

Output slew-rate-matching ratio (pull-up to pull-down)

1.5

1.0

0.7

3.5

V/ns

SRQSE

2.5

1.4

Definitions:

SR = slew rate, Q = query output (similar to DQ = data-in, query-output), se = single-ended signals

NOTE 1 Measured with output reference load.

NOTE 2 The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire

temperature and voltage range. For a given output, it represents the maximum difference between pull-up and

pull-down drivers due to process variation.

NOTE 3 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC).

NOTE 4 Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of

DQ signals per data byte driving logic-low.

Version 1.4

06/2016

36

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Differential Output Slew Rate

With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and

measured between V_Oldiff(AC)and V_Ohdiff(AC)for differential signals as shown below.

Differential Output Slew Rate Definition

Measured

Description

Defined by

From

To

Differential output slew rate for rising edge

[VOHdiff(AC) – VOLdiff(AC)] / ΔTRdiff

[VOHdiff(AC) – VOLdiff(AC)] / ΔTFdiff

VOLdiff(AC)

VOHdiff(AC)

Differential output slew rate for falling edge

VOHdiff(AC)

VOLdiff(AC)

Notes:

Output slew rate is verified by design and characterization, and may not be subject to production testing.

Differential Output Slew Rate Definition

Differential Output Slew Rate

LPDDR2 1066

Symbol

Parameter

Unit

Min

Max

3.0

2.0

7.0

SRQdiff

Differential output slew rate (output impedance = 40Ω ± 30%)

Differential output slew rate (output impedance = 60Ω ± 30%)

V/ns

5.0

SRQdiff

Definitions:

SR = slew rate, Q = query output (similar to DQ = data-in, query-output), diff = differential signals

NOTE 1 Measured with output reference load.

NOTE 2 The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC).

NOTE 3 Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of

DQ signals per data byte driving logic-low.

Version 1.4

06/2016

37

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

AC Overshoot/Undershoot Specification

Parameter

1066

Unit

Maximum peak amplitude provided for overshoot area

Max

0.35

0.15

V

Maximum peak amplitude provided for undershoot area Max

V

Maximum area above VDD

Maximum area below VSS

Notes:

Max

V-ns

1. VDD stands for VDDCA for CA[9:0], CK, , , and CKE. VDD stands for VDDQ for DQ, DM, DQS, and .

2. VSS stands for VSSCA for CA[9:0], CK, , , and CKE. VSS stands for VSSQ for DQ, DM, DQS, and .

3. Values are referenced from actual VDDQ, VDDCA, VSSQ and VSSCA levels.

Overshoot and Undershoot Definition

Notes:

1. VDD stands for VDDCA for CA[9:0], CK, , , and CKE. VDD stands for VDDQ for DQ, DM, DQS, and .

2. VSS stands for VSSCA for CA[9:0], CK, , , and CKE. VSS stands for VSSQ for DQ, DM, DQS, and .

Version 1.4

06/2016

38

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

HSUL_12 Driver Output Timing Reference Load

The timing reference loads are not intended as a precise representation of any particular system environment or a depiction

of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate

the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally

with one or more coaxial transmission lines terminated at the tester electronics.

HSUL_12 Driver Output Reference Load for Timing and Slew Rate

Notes:

All output timing parameter values (tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported with respect to this reference load. This

reference load is also used to report slew rate.

Output Driver Impedance Definition

The output driver impedance is selected by a mode register during initialization. The selected value is able to maintain

the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver

unless specifically stated otherwise. A functional representation of the output buffer is shown in below. The output driver

impedance RON is defined by the value of the external reference resistor RZQ as follows:

VDDQ – Vout

RONPU=

RONPD=

when RONPD is turned off

when RONPU is turned off

ABS (Iout)

Vout

ABS (Iout)

Output Driver: Definition of Voltages and Currents

Version 1.4

06/2016

39

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Input / Output Capacitance

TOPER; VDDQ = 1.14-1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V

LPDDR2 1066

Symbol

C_CK

C_DCK

C_I

Parameter

Unit

pF

Min

Max

Input capacitance :

1

2

CK, 

Input capacitance delta :

CK, 

0

1

0.2

2

pF

Input capacitance:

all other input-only pins

pF

Input capacitance delta:

-0.4

1.25

0.4

2.5

pF

C_DI

all other input-only pins

Input/output capacitance :

DQ, DQS, , DM

pF

C_IO

0

-0.5

0

0.25

0.5

pF

Input/output capacitance delta : DQS, 

Input/output capacitance delta : DQ, DM

Input/output capacitance : ZQ

C_DDQS

C_DIO

C_ZQ

2.5

Notes:

1. This parameter applies to die devices only (does not include package capacitance).

2. This parameter is not subject to production testing. It is verified by design and characterization. The capacitance is measured

according to JEP147 (procedure for measuring input capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ,

VSS, VSSCA, and VSSQ applied; all other pins are left floating.

3. Absolute value of CCK - .

4. CI applies to , CKE, and CA[9:0].

5. CDI = CI – 0.5 × (CCK + )

6. DM loading matches DQ and DQS.

7. MR3 I/O configuration DS OP[3:0] = 0001B (34.3 ohm typical)

8. Absolute value of CDQS and .

9. CDIO = CIO – 0.5 × (CDQS + ) in byte-lane.

10. Maximum external load capacitance on ZQ pin, including packaging, board, pin, resistor, and other LPDDR2 devices: 5pf.

Version 1.4

06/2016

40

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

IDD Specification Parameters and Test Conditions

IDD Measurement Conditions

The following definitions and conditions are used in the IDD measurement tables unless stated otherwise:

• LOW: V_IN≤ V_IL(DC)max

• HIGH: V_IN≥ V_IH(DC)min

• STABLE: Inputs are stable at a HIGH or LOW level

• SWITCHING: See Tables bellow

Switching for CA Input Signal

CK (Rising) / CK (Falling) / CK (Rising) / CK (Falling) / CK (Rising) /

(Falling) (Rising) (Falling) (Rising) (Falling)

N+1 N+2

HIGH HIGH

CK (Falling) / CK (Rising) /

(Rising) (Falling)

N+3

HIGH

CK (Falling) /

(Rising)

Cycle



N

HIGH

H

L

H

L

H

L

H

L

H

L

H

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CA9

Notes:

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

1.  must always be driven HIGH.

2. For each clock cycle, 50% of the CA bus is changing between HIGH and LOW.

3. The noted pattern (N, N + 1, N + 2, N + 3...) is used continuously during IDD measurement for IDD values that require

switching on the CA bus.

Version 1.4

06/2016

41

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

IDD Measurement Conditions (Continued)

Switching for IDD4R

Clock Cycle

Clock

CKE



Command

CA[2:0]

CA[9:3]

All DQ

Number

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

H

L

N

Read_Rising

Read_Falling

NOP

HLH

LLL

HLH

LLL

HLH

LHLHLHL

LLLLLLL

L

N

H

L

N+1

N+2

N+3

LLLLLLL

H

L

NOP

HLHLLHL

HHHHHHH

LHLHLHL

Read_Rising

Read_Falling

NOP

H

L

H

NOP

Notes:

1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle.

2. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R.

Switching for IDD4W

Clock Cycle

Clock

CKE



Command

CA[2:0]

CA[9:3]

All DQ

Number

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

H

L

N

Write_Rising

Write_Falling

NOP

HLL

LLL

HLH

HLL

LLL

HLH

LHLHLHL

LLLLLLL

L

N

H

L

N+1

N+2

N+3

LLLLLLL

H

L

NOP

HLHLLHL

HHHHHHH

LHLHLHL

Write_Rising

Write_Falling

NOP

H

L

H

NOP

Notes:

1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle.

2. Data masking (DM) must always be driven LOW.

3. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4W

Version 1.4

06/2016

42

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

IDD Specifications

LPDDR2 IDD Specification Parameters and Operating Conditions

Parameter/Condition

Symbol

Power Supply

VDD1

Notes

Operating one bank active-precharge current:

tCK = tCK(avg)min; tRC = tRCmin;

CKE is HIGH;

IDD01

IDD02

1

VDD2

 is HIGH between valid commands;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD0in

VDDCA,VDDQ

VDD1

1,4

1

Idle power-down standby current:

tCK = tCK(avg)min;

IDD2P1

IDD2P2

IDD2P,in

IDD2PS1

IDD2PS2

IDD2PS,in

IDD2N1

IDD2N2

IDD2N,in

IDD2NS1

IDD2NS2

IDD2NSIN

IDD3P1

IDD3P2

CKE is LOW;

VDD2

1

 is HIGH;

All banks/RBs idle;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

Idle power-down standby current with clock stop:

CK =LOW,  =HIGH;

VDDCA,VDDQ

VDD1

1,4

1

CKE is LOW;

VDD2

1

 is HIGH;

All banks/RBs idle;

CA bus inputs are STABLE;

Data bus inputs are STABLE

Idle non power-down standby current:

tCK = tCK(avg)min;

VDDCA,VDDQ

VDD1

1,4

1

CKE is HIGH;

VDD2

1

 is HIGH;

All banks/RBs idle;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

Idle non power-down standby current with clock stop:

CK =LOW,  =HIGH;

VDDCA,VDDQ

VDD1

1,4

1

CKE is HIGH;

VDD2

1

 is HIGH;

All banks/RBs idle;

CA bus inputs are STABLE;

Data bus inputs are STABLE

VDDCA,VDDQ

VDD1

1

Active power-down standby current:

tCK = tCK(avg)min;

CKE is LOW;

1

VDD2

1

 is HIGH;

Version 1.4

06/2016

43

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

One bank/RB active;

IDD3P,in

VDDCA,VDDQ

1,4

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

Active power-down standby current with clock stop:

CK=LOW,  =HIGH;

IDD3PS1

IDD3PS2

IDD3PS,in

IDD3N1

VDD1

VDD2

1

CKE is LOW;

 is HIGH;

One bank/RB active;

CA bus inputs are STABLE;

Data bus inputs are STABLE

Active non power-down standby current:

tCK = tCK(avg)min;

VDDCA,VDDQ

VDD1

1,4

1

CKE is HIGH;

IDD3N2

VDD2

1

 is HIGH;

One bank/RB active;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

Active non power-down standby current with clock stop:

CK=LOW,  =HIGH;

IDD3N,in

IDD3NS1

IDD3NS2

IDD3NS,in

IDD4R1

VDDCA,VDDQ

VDD1

1,4

1

CKE is HIGH;

VDD2

1

 is HIGH;

One bank/RB active;

CA bus inputs are STABLE;

Data bus inputs are STABLE

VDDCA,VDDQ

VDD1

1,4

1

Operating burst read current:

tCK = tCK(avg)min;

IDD4R2

VDD2

1

 is HIGH between valid commands;

One bank/RB active;

BL = 4; RL = RLmin;

IDD4R,in

VDDCA

1

CA bus inputs are SWITCHING;

50% data change each burst transf

IDD4RQ

IDD4W1

IDD4W2

IDD4W,in

IDD51

VDDQ

VDD1

1,4

1

Operating burst write current:

tCK = tCK(avg)min;

 is HIGH between valid commands;

One bank/RB active;

VDD2

1

BL = 4; WL = WLmin;

CA bus inputs are SWITCHING;

50% data change each burst transfer

All Bank Refresh Burst current:

tCK = tCK(avg)min;

VDDCA,VDDQ

VDD1

1,4

1

CKE is HIGH between valid commands;

tRC = tRFCabmin;

IDD52

VDD2

1

Burst refresh;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE;

IDD5IN

VDDCA,VDDQ

1,4

Version 1.4

06/2016

44

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

All Bank Refresh Average current:

tCK = tCK(avg)min;

IDD5AB1

IDD5AB2

IDD5AB,in

IDD5PB1

IDD5PB2

IDD5PB,in

VDD1

VDD2

1

CKE is HIGH between valid commands;

tRC = tREFI;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE;

VDDCA,VDDQ

VDD1

1,4

1,6

1,4,6

Per Bank Refresh Average current:

tCK = tCK(avg)min;

CKE is HIGH between valid commands;

tRC = tREFI/8;

VDD2

CA bus inputs are SWITCHING;

Data bus inputs are STABLE;

VDDCA,VDDQ

Version 1.4

06/2016

45

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

IDD Specifications (Continued)

LPDDR2 IDD Specification Parameters and Operating Conditions

Parameter/Condition

Symbol

IDD61

Power Supply Notes

Self refresh current (Standard Temperature Range):

CK=LOW, =HIGH;

VDD1

VDD2

1,7

1,4,7

8

CKE is LOW;

IDD62

CA bus inputs are STABLE;

Data bus inputs are STABLE;

Maximum 1x Self-Refresh Rate;

IDD6IN

IDD81

VDDCA,VDDQ

VDD1

Deep Power-Down current:

CK=LOW, =HIGH;

IDD82

VDD2

8

CKE is LOW;

CA bus inputs are STABLE;

Data bus inputs are STABLE;

IDD8IN

VDDCA,VDDQ

4,8

Notes:

1. Published IDD values are the maximum of the distribution of the arithmetic mean and are measured at 85℃.

2. IDD current specifications are tested after the device is properly initialized.

3. The 1x self refresh rate is the rate at which the device is refreshed internally during self refresh, before going into the extended temperature

range.

4. Measured currents are the summation of VDDQ and VDDCA.

5. Guaranteed by design with output load of 5pf and RON = 40Ohm.

6. Per Bank Refresh only applicable for LPDDR2-S4 devices of 1Gb or higher densities

7. This is the general definition that applies to full-array SELF REFRESH.

8. IDD8 are typical values. IDD8 is measured at 25℃.

Version 1.4

06/2016

46

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

IDD Specifications and Measurement Conditions

VDD2/VDDQ/VDDCA = 1.14~1.30V; VDD1 = 1.70~1.95V

1066

Symbol

Supply

Unit

SDP

DDP

10

40

20

80

I_DD01

I_DD02

V_DD1

V_DD2

mA

uA

IDD0

6

12

I_DD0IN

I_DD2P1

I_DD2P2

I_DD2PIN

V_DDCA, V_DDQ,

V_DD1

450

600

50

900

1200

100

IDD2P

V_DD2

uA

V_DDCA, V_DDQ,

uA

450

900

I_DD2PS1

V_DD1

uA

IDD2PS

600

50

1

1200

100

2

I_DD2PS2

I_DD2PSIN

I_DD2N1

V_DD2

V_DDCA, V_DDQ,

V_DD1

uA

mA

uA

15

6

30

IDD2N

IDD2NS

IDD3P

I_DD2N2

V_DD2

12

I_DD2NIN

I_DD2NS1

I_DD2NS2

I_DD2NSIN

I_DD3P1

V_DDCA, V_DDQ,

V_DD1

1

2

5

10

V_DD2

6

12

V_DDCA, V_DDQ,

V_DD1

1200

4

2400

8

I_DD3P2

V_DD2

mA

uA

100

200

I_DD3PIN

V_DDCA, V_DDQ,

1200

2400

I_DD3PS1

V_DD1

uA

IDD3PS

4

100

1.2

20

6

8

I_DD3PS2

I_DD3PSIN

I_DD3N1

V_DD2

V_DDCA, V_DDQ,

V_DD1

mA

uA

200

2.4

40

mA

IDD3N

I_DD3N2

V_DD2

12

I_DD3NIN

I_DD3NS1

I_DD3NS2

I_DD3NSIN

V_DDCA, V_DDQ,

V_DD1

1.2

7

2.4

14

IDD3NS

V_DD2

6

12

V_DDCA, V_DDQ,

Version 1.4

06/2016

47

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

1066

Symbol

Supply

Unit

SDP

DDP

2

200

6

4

400

12

480

4

I_DD4R1

I_DD4R2

V_DD1

V_DD2

mA

uA

IDD4R

I_DD4RIN

I_DD4RQ

I_DD4W1

I_DD4W2

I_DD4WIN

I_DD51

V_DDCA

240

2

V_DDQ

V_DD1

150

25

15

110

6

300

50

30

220

12

6

V_DD2

IDD4W

IDD5

V_DDCA, V_DDQ,

V_DD1

I_DD52

V_DD2

I_DD5IN

V_DDCA, V_DDQ,

V_DD1

3

I_DD5AB1

I_DD5AB2

I_DD5ABIN

I_DD5PB1

I_DD5PB2

I_DD5PBIN

I_DD81

20

6

40

12

6

IDD5AB

IDD5PB

IDD8

V_DD2

V_DDCA, V_DDQ,

V_DD1

3

20

6

40

12

15

80

20

V_DD2

V_DDCA, V_DDQ,

V_DD1

7.5

40

10

I_DD82

V_DD2

uA

I_DD8IN

V_DDCA, V_DDQ,

uA

Version 1.4

06/2016

48

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

IDD Specifications and Measurement Conditions

VDD2/VDDQ = 1.14~1.30V; VDD1 = 1.70~1.95V

IDD6 Partial Array Self-refresh current;

1066

PASR

Supply

Unit

SDP

DDP

700

2000

50

1400

4000

100

uA

V_DD1

V_DD2

V_DDQ

V_DD1

V_DD2

V_DDQ

V_DD1

V_DD2

V_DDQ

V_DD1

V_DD2

V_DDQ

Full Array

650

1600

50

1300

3200

100

1/2 Array

1/4 Array

1/8 Array

600

1400

50

1200

2800

100

550

1300

50

1100

2600

100

Version 1.4

06/2016

49

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Electrical Characteristic and AC Timing

Clock Specification

The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating minimum or maximum values may

result in device malfunction.

Definitions and Calculations

Symbol

Description

Calculation

Notes

The average clock period across any consecutive

200-cycle window. Each clock period is calculated

from rising clock edge to rising clock edge.

Unit tCK(avg) represents the actual clock average

tCK(avg) of the input clock under operation. Unit nCK

represents one clock cycle of the input clock,

tCK(avg) and nCK

counting from actual clock edge to actual clock edge.

tCK(avg) can change no more than ±1% within a

100-clock-cycle window, provided that all jitter and

timing specifications are met.

The absolute clock period, as measured from one

rising clock edge to the next consecutive rising clock

edge.

tCK(abs)

tCH(avg)

The average HIGH pulse width, as calculated across

any 200 consecutive HIGH pulses.

The average LOW pulse width, as calculated across

any 200 consecutive LOW pulses.

tCL(avg)

The single-period jitter defined as the largest

tJIT(per)

deviation of any signal tCK from tCK(avg).

tJIT(per),act

The actual clock jitter for a given system.

The specified clock period jitter allowance.

tJIT(per),allowed

The absolute difference in clock periods between two

consecutive clock cycles. tJIT(cc) defines the

cycle-to-cycle jitter.

tJIT(cc)

Version 1.4

06/2016

50

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Symbol

Description

Calculation

Notes

The cumulative error across n multiple consecutive

cycles from tCK(avg).

tERR(nper)

The actual cumulative error over n cycles for a given

tERR(nper),act

system.

The specified cumulative error allowance over n

tERR(nper),allowed

tERR(nper),min

tERR(nper),max

cycles.

The minimum tERR(nper).

The maximum tERR(nper).

Defined with tCH jitter and tCL jitter. tCH jitter is the

largest deviation of any single tCH from tCH(avg).

tCL jitter is the largest deviation of any single tCL

from tCL(avg).

tJIT(duty)

Definition for tCK(abs), tCH(abs) and tCL(abs)

These parameters are specified per their average values, however, it is understood that the following relationship between

the average timing and the absolute instantaneous timing holds at all times.

Symbol

Parameter

Minimum

Unit

ps

tCK(abs)

Absolute clock period

tCK(avg),min + tJIT(per),min

tCH(abs)

Absolute clock HIGH pulse width

Absolute clock LOW pulse width

tCH(avg),min + tJIT(duty),min/ tCK(avg)min

tCL(avg),min + tJIT(duty),min / tCK(avg)min

tCK(avg)

tCL(abs)

Notes:

1. tCK(avg),min is expressed in ps for this table.

2. tJIT(duty),min is a negative value.

Version 1.4

06/2016

51

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Period Clock Jitter

LPDDR2 devices can tolerate some clock period jitter without core timing parameter derating. This section describes device

timing requirements with clock period jitter (tJIT(per)) in excess of the values found in the AC timing table. Calculating cycle

time derating and clock cycle derating are also described.

Clock Period Jitter Effects on Core Timing Parameters

Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) extend across multiple clock

cycles. Period clock jitter impacts these parameters when measured in numbers of clock cycles. Within the specification

limits, the device is characterized and verified to support tnPARAM = RU[tPARAM / tCK(avg)]. During device operation

where clock jitter is outside specification limits, the number of clocks or tCK(avg), may need to be increased based on the

values for each core timing parameter.

Cycle Time Derating for Core Timing Parameters

For a given number of clocks (tnPARAM), for each core timing parameter, average clock period( tCK(avg) ) and actual

cumulative period error (tERR(tnPARAM), act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed) ,

the equation below calculates the amount of cycle time de-rating(in ns) required if the equation results in a positive value for

a core timing parameter(tCORE). A cycle time de-rating analysis should be conducted for each core timing parameter. The

amount of cycle time de-rating required is the maximum of the cycle time de-rating determined for each individual core

timing parameter.

Clock Cycle Derating for Core Timing Parameters

For each core timing parameter and a given number of clocks (tnPARAM), clock cycle derating should be specified with

tJIT(per). For a given number of clocks (tnPARAM), for each core parameter, average clock period( tCK(avg)) and actual

cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed),

the equation below calculates the clock cycle derating (in clocks) required if the equation results in a positive value for a

core timing parameter (tCORE), A clock cycle de-rating analysis should be conducted for each core timing parameter.

Version 1.4

06/2016

52

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Clock Jitter Effects on Command/Address Timing Parameters

Command/address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb, tIHCKEb) are measured from a

command/address signal (CKE, CS, or CA[9:0]) transition edge to its respective clock signal (CK, ) crossing. The

specification values are not affected by the tJIT(per) applied, as the setup and hold times are relative to the clock signal

crossing that latches the command/address. Regardless of clock jitter values, these values must be met.

Clock Jitter Effects on READ Timing Parameters

tRPRE

When the device is operated with input clock jitter, tRPRE must be derated by the actual period jitter( tJIT(per),act,max) of the

input clock that exceeds the allowed period jitter( tJIT(per),allowed,max.). Output de-ratings are relative to the input clock.

For example,

if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500ps, tJIT(per),act,min = –172ps, and JIT(per),act,max =

+193ps,

then tRPRE,min, derated = 0.9 - (tJIT(per), act,max - tJIT(per),

allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500 = 0.8628 tCK(avg).

tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)

These parameters are measured from a specific clock edge to a data signal transition (DMn or DQm, where: n = 0, 1, 2, or 3;

and m = DQ[31:0]), and specified timings must be met with respect to that clock edge. Therefore, they are not affected by

tJIT(per).

tQSH, tQSL

These parameters are affected by duty cycle jitter, represented by tCH(abs)min and tCL(abs)min. Therefore tQSH(abs)min and

tQSL(abs)min can be specified with tCH(abs)min and tCL(abs)min. tQSH(abs)min = tCH(abs)min - 0.05, tQSL(abs)min =

tCL(abs)min - 0.05. These parameters determine the absolute data-valid window at the device pin. The absolute minimum

data-valid window @ the device pin = min [(tQSH(abs)min × tCK(avg)min - tDQSQmax - tQHSmax), (tQSL(abs)min ×

tCK(avg)min - tDQSQmax - tQHSmax)]. This minimum data-valid window must be met at the target frequency regardless of

clock jitter.

Version 1.4

06/2016

53

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

tRPST

tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min can be specified by tCL(abs)min.

tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min.

Clock Jitter Effects on WRITE Timing Parameters

tDS, tDH

These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3; and m = DQ[31:0]) transition edge to

its respective data strobe signal (DQSn, n = 0,1,2,3) crossing. The specification values are not affected by the amount of

tJIT(per) applied, as the setup and hold times are relative to the clock signal crossing that latches the command/address.

Regardless of clock jitter values, these values must be met.

tDSS, tDSH

These parameters are measured from a data strobe signal (DQSx, x) crossing to its respective clock signal (CK, )

crossing. The specification values are not affected by the amount of tJIT(per)) applied, as the setup and hold times are relative

to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met.

Version 1.4

06/2016

54

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

REFRESH Requirements by Device Density

LPDDR2-S4 Refresh Requirement Parameters

Symbol

Parameter

2Gb(SDP)

4Gb(DDP)

Unit

8

Number of banks

32

tREFW

R

ms

Refresh window: TCASE ≤ 85°

8192

3.9

8192

3.9

Required number of REFRESH commands (MIN)

tREFI

us

ns

us

Average time between REFRESH commands

TCASE ≤ 85°C

0.4875

130

0.4875

130

tREFIpb

tRFCab

tRFCpb

tREFBW

Refresh cycle time

60

Per-bank REFRESH cycle time

Burst REFRESH window = 4 × 8 × tRFCab

4.16

Version 1.4

06/2016

55

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Electrical Characteristics and Recommended AC Timing

V_DD2,V_DDQ,V_DDCA= 1.14~1.30V; V_DD1= 1.70~1.95V

min/

Parameter

1066

Unit

Symbol

max

Clock Timing

533

MHz

ns

Max. Frequency

~

1.875

min

max

min

max

min

max

min

max

min

max

Average Clock Period

tCK(avg)

tCH(avg)

100

ns

0.45

tCK(avg)

ps

Average high pulse width

0.55

0.45

Average low pulse width

Absolute Clock Period

tCL(avg)

tCK(abs)

0.55

tCK(avg)min + tJIT(per),min

0.43

0.57

0.43

0.57

tCK(avg)

Absolute clock HIGH pulse width

(with allowed jitter)

tCH(abs),

allowed

Absolute clock LOW pulse width

(with allowed jitter)

tCL(abs),

allowed

min/

max

Parameter

1066

Unit

Symbol

-90

90

ps

min

Clock Period Jitter

(with allowed jitter)

tJIT(per),

allowed

max

Maximum Clock Jitter between

two consecutive clock cycles

(with allowed jitter)

tJIT(cc),

allowed

180

ps

max

min

min((tCH(abs),min - tCH(avg),min),

(tCL(abs),min - tCL(avg),min)) * tCK(avg)

max((tCH(abs),max - tCH(avg),max),

Duty cycle Jitter

tJIT(duty),

allowed

(with allowed jitter)

max

(tCL(abs),max - tCL(avg),max)) * tCK(avg)

-132

132

-157

157

-175

175

ps

tERR(2per),

allowed

min

max

min

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

tERR(3per),

allowed

max

min

tERR(4per),

allowed

max

Version 1.4

06/2016

56

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

min/

Parameter

1066

Unit

Symbol

max

-188

ps

tERR(5per),

allowed

min

max

min

max

min

max

min

max

min

max

min

max

min

max

min

max

min

max

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

188

-200

tERR(6per),

allowed

200

-209

tERR(7per),

allowed

209

-217

tERR(8per),

allowed

217

-224

tERR(9per),

allowed

224

-231

tERR(10per),

allowed

Cumulative error across 10

cycles

231

-237

tERR(11per),

allowed

Cumulative error across 11

cycles

237

-242

tERR(12per),

allowed

Cumulative error across 12

cycles

242

tERR(nper), allowed, min = (1 + 0.68ln(n)) * tJIT(per), allowed, min

tERR(nper), allowed, max = (1 + 0.68ln(n)) * tJIT(per), allowed, max

tERR(nper),

allowed

Cumulative error across n = 13,

14 . . . 49, 50 cycles

Version 1.4

06/2016

57

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Electrical Characteristics and Recommended AC Timing

V_DD2,V_DDQ,V_DDCA= 1.14~1.30V; V_DD1= 1.70~1.95V

Speed Grade

1066

min/ min

Symbol

Parameter

Unit

max ^tCK

ZQ calibration parameters

min

tZQINIT

tZQCL

Calibration initialization Time

1

us

ns

Long (Full) Calibration Time

Short Calibration Time

Calibration Reset Time

min

6

3

360

90

tZQCS

tZQRESET

50

Read parameters

min

max

2500

5500

330

ps

DQS output access time from CK, 

tDQSCK

tDQSCKDS DQSCK Delta Short

tDQSCKDM DQSCK Delta Medium

tDQSCKDL DQSCK Delta Long

680

920

DQS-DQ skew, DQS to last DQ valid, per group,

tDQSQ

max

200

ps

per access

tQHS

tQSH

tQSL

tQHP

tQH

Data Hold Skew Factor

max

min

230

ps

tCK(avg)

DQS output HIGH pulse width

DQS output LOW pulse width

Data half period

tCH(abs) - 0.05

tCL(abs) - 0.05

min(tQSH, tQSL)

tQHP - tQHS

Speed Grade

1066

tCK(avg)

DQ / DQS output hold time from DQS

ps

min/ min

max ^tCK

Symbol

Parameter

Unit

Read parameters

tCK(avg)

tRPRE

tRPST

READ Preamble

min

max

0.9

tCL(abs) - 0.05

READ Postamble

DQS Low-Z from CK

DQ Low-Z from CK

DQS High-Z from CK

tLZ(DQS)

tLZ(DQ)

tHZ(DQS)

tDQSCK_min– 300

ps

tDQSCK(MIN) – (1.4 × tQHS(MAX))

tDQSCK_max– 100

tDQSCK(MAX) +

(1.4 × tDQSQ(MAX))

tHZ(DQ)

DQ High-Z from CK

max

ps

Version 1.4

06/2016

58

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Speed Grade

1066

min/ min

Symbol

Parameter

Unit

max ^tCK

Write parameters

tDH

tDS

DQ and DM input hold time (V_REFbased)

DQ and DM input setup time (V_REFbased)

DQ and DM input pulse width

min

210

0.35

0.75

1.25

0.4

ps

tDIPW

tCK(avg)

Write command to 1^stDQS latching transition

tDQSS

tCK(avg)

max

min

tDQSH

tDQSL

tDSS

DQS input high-level width

min

DQS input low-level width

0.4

DQS falling edge to CK setup time

DQS falling edge hold time from CK

0.2

tDSH

min

0.2

tWPST

tWPRE

Write postamble

Write preamble

0.4

0.35

Speed Grade

1066

min/ min

max ^tCK

Symbol

Parameter

Unit

CKE input parameters

tCKE

CKE min. pulse width (high and low)

CKE input setup time

min

3

tCK(avg)

tISCKE

tIHCKE

0.25

CKE input hold time

Command / Address Input parameters

tIH

tIS

Address and Control input hold time

min

220

0.4

ps

Address and Control input setup time

Address and Control input pulse width

tIPW

tCK(avg)

Mode register parameters

tCK(avg)

tMRR

tMRW

MODE Register Read command period

MODE Register Write command period

min

2

5

2

5

SDRAM core parameters

tCK(avg)

RL

Read Latency

min

3

1

8

4

WL

Write Latency

CKE minimum pulse width during SELF REFRESH

(low pulse width during SELF REFRESH)

tCKESR

tXSR

min

3

2

15

ns

Exit SELF REFRESH to first valid command (min)

tRFC_AB+10

Version 1.4

06/2016

59

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Speed Grade

1066

min/ min

Symbol

Parameter

Unit

max ^tCK

SDRAM core parameters

tXP

Exit power-down mode to first valid command

Minimum Deep Power-Down time

min

2

-

7.5

500

50

ns

us

ns

tDPD

tFAW

tWTR

Four-Bank Activate Window

8

2

Internal WRITE to READ command delay

7.5

tRAS + tRP_AB(with all-bank Precharge)

tRAS + tRP_PB(with per-bank Precharge)

tRC

ACTIVE to ACTIVE command period

min

ns

tCCD

tRTP

tRCD

CAS-to-CAS delay

min

max

min

2

3

-

2

tCK(avg)

ns

Internal READ to PRECHARGE command delay

RAS-to-CAS delay

7.5

18

42

70

15

ns

tRAS

Row Active Time

us

tWR

Write recovery time

3

ns

tRPpb

PRECHARGE command period (single bank)

ns

PRECHARGE command period

tRPab

tRRD

min

3

2

18

ns

(all banks – 8bank)

ACTIVE bank-a to ACTIVE bank-b command

10

Speed Grade

1066

min/ min

max ^tCK

Symbol

Parameter

Unit

Boot parameters (10MHz ~ 55MHz)

min

18

100

2.5

ns

ps

tCKb

Clock cycle time

max

tISCKEb

tIHCKEb

tISb

CKE input setup time

CKE input hold time

Input setup time

min

2.5

min

1150

min/ min

Speed Grade

1066

Symbol

Parameter

Unit

max ^tCK

Boot parameters (10MHz ~ 55MHz)

tIHb

Input hold time

min

1150

2.0

ps

ns

tDQSCKb

Access window of DQS from CK, 

max

10.0

1.2

tDQSQb

tQHSb

DQS-DQ skew

Data hold skew factor

1.2

Version 1.4

06/2016

60

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Notes for Electrical Characteristics and Recommended AC Timing

1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities.

2. All AC timings assume an input slew rate of 1 V/ns.

3. READ, WRITE, and input setup and hold values are referenced to VREF.

4. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a contiguous

sequence of bursts in a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is <

10°C/s. Values do not include clock jitter.

5. tDQSCKdm is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 1.6μs rolling window.

tDQSCKdm is not tested and is guaranteed by design. Temperature drift in the system is < 10 °C/s. Values do not include clock jitter.

6. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 32ms rolling window.

tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10 °C/s. Values do not include clock jitter.

7. For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses the transition threshold

(VTT). tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not

referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or

begins driving (for tRPRE, tLZ(DQS), tLZ(DQ)). Figure shows a method to calculate the point when device is no longer driving tHZ (DQS)

and tHZ (DQ), or begins driving tLZ (DQS), tLZ (DQ) by measuring the signal at two different voltages. The actual voltage measurement

points are not critical as long as the calculation is consistent.

Data Out measurement reference points

The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are

determined from the differential signal DQS, .

8. Measured from the point when DQS,  begins driving the signal to the point when DQS,  begins driving the first rising strobe edge.

9. Measured from the last falling strobe edge of DQS,  to the point when DQS,  finishes driving the signal.

Version 1.4

06/2016

61

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Notes for Electrical Characteristics and Recommended AC Timing

10. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to CK,  crossing.

11. CKE input hold time is measured from CK,  crossing to CKE reaching a HIGH/LOW voltage level.

12. Input set-up/hold time for signal (CA[9:0], ).

13. To ensure device operation before the device is configured, a number of AC boot-timing parameters are defined in this table. Boot

parameter symbols have the letter b appended (for example, tCK during boot is tCKb).

14. The LPDDR device will set some mode register default values upon receiving a RESET command as specified in “Mode Register

Definition”.

15. The output skew parameters are measured with default output impedance settings using the reference load.

16. The minimum tCK column applies only when tCK is greater than 6ns.

Version 1.4

06/2016

62

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

CA and  Setup, Hold, and Derating

The For all input signals (CA and ), the total required setup time (tIS) and hold time (tIH) is calculated by adding the data

sheet tIS (base) and tIH (base) values to the ΔtIS and ΔtIH derating values, respectively. Example: tIS (total setup time) =

tIS(base) + ΔtIS.

Setup (tIS) typical slew rate for a rising signal is defined as the slew rate between the last crossing of V_REF(DC)and the first

crossing of VIH(AC)min. The setup (tIS) typical slew rate for a falling signal is defined as the slew rate between the last

crossing of V_REF(DC)and the first crossing of VIL(AC)max. If the actual signal is always earlier than the typical slew rate line

between the shaded VREF(DC)-to-(AC) region, use the typical slew rate for the derating value. If the actual signal is later than

the typical slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a tangent line to the actual

signal from the AC level to the DC level is used for the derating value.

The hold (tIH) typical slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the

first crossing of VREF(DC). The hold (tIH) typical slew rate for a falling signal is defined as the slew rate between the last

crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the typical slew rate line

between the shaded DC-to-VREF(DC) region, use the typical slew rate for the derating value. If the actual signal is earlier

than the typical slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the

actual signal from the DC level to VREF(DC) level is used for the derating value.

For a valid transition, the input signal must remain above or below VIH/VIL(AC) for a specified time, Tvac. For slow slew rates

the total setup time could be a negative value (that is, a valid input signal will not have reached VIH/VIL(AC) at the time of the

rising clock transition). A valid input signal is still required to complete the transition and reach VIH/VIL(AC).

For slew rates between the values listed, the derating values are obtained using linear interpolation. Slew rate values are not

typically subject to production testing. They are verified by design and characterization.

CA and  Setup and Hold Base Values

Data Rate

Parameter

Reference

1066

0

VIH/VIL(AC) = VREF(DC) ± 220 mV

VIH/VIL(DC) = VREF(DC) ± 130 mV

tIS (base)

tIH (base)

90

Notes: AC/DC referenced for 1 V/ns CA and  slew rate and 2 V/ns differential CK,  slew rate.

Version 1.4

06/2016

63

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

CA and  Setup, Hold, and Derating (Continued)

Derating Values for AC/DC-based tIS/tIH (AC220, DC130)

AC220 DC130 Threshold

CK,  Differential Slew Rate

2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns

4.0 V/ns

3.0 V/ns

1.2 V/ns

1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH

110

74

65

43

110

74

65

43

110

74

65

43

2

89

16

59

16

1.5

0

32

1

CA,

Slew rate

V/ns

-3

-5

-3

-8

-5

13

8

11

3

29

24

18

10

27

19

10

-3

45

40

34

26

4

43

35

26

13

-4

0.9

0.8

0.7

0.6

0.5

0.4

-13

56

50

42

20

-7

55

46

33

16

2

-6

66

58

36

17

78

65

48

34

Notes: Cell contents shaded in yellow are defined as “not supported.”

Version 1.4

06/2016

64

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition

tVAC @ 220mV [ps]

Slew Rate (V/ns)

Min

175

170

167

163

162

161

159

155

150

Max

>2.0

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

<0.5

–

Version 1.4

06/2016

65

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

CA and  Setup, Hold, and Derating (Continued)

Illustration of nominal slew rate and tVAC for setup time tIS for CA and  with respect to clock

Version 1.4

06/2016

66

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

CA and  Setup Hold, and Derating (Continued)

Illustration of nominal slew rate for hold time tIH for CA and  with respect to clock

Version 1.4

06/2016

67

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

CA and  Setup Hold, and Derating (Continued)

Tangent Line: tIS for CA and  Relative to Clock

Version 1.4

06/2016

68

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

CA and  Setup Hold, and Derating (Continued)

Tangent Line: tIH for CA and  Relative to Clock

Version 1.4

06/2016

69

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Data Setup, Hold, and Slew Rate Derating

For all input signals (DQ, DM) calculate the total required setup time (tDS) and hold time (tDH) by adding the data sheet

tDS(base) and tDH(base) values to the ΔtDS and ΔtDH derating values, respectively. Example: tDS = tDS(base) + ΔtDS.

The typical tDS slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first

crossing of VIH(AC)min. The typical tDS slew rate for a falling signal is defined as the slew rate between the last crossing of

VREF(DC) and the first crossing of VIL(AC)max.

If the actual signal is consistently earlier than the typical slew rate, the area shaded gray between the VREF(DC) region and

the AC region, use the typical slew rate for the derating value. If the actual signal is later than the typical slew rate line

anywhere between the shaded VREF(DC) region and the AC region, the slew rate of a tangent line to the actual signal from

the AC level to the DC level is used for the derating value.

The typical tDH slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first

crossing of VREF(DC). The typical tDH slew rate for a falling signal is defined as the slew rate between the last crossing of

VIH(DC)min and the first crossing of VREF(DC).

If the actual signal is consistently later than the typical slew rate line between the shaded DC-level-to-VREF(DC) region, use

the typical slew rate for the derating value. If the actual signal is earlier than the typical slew rate line anywhere between

shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the DC level to VREF(DC) level is

used for the derating value.

For a valid transition, the input signal must remain above or below VIH/VIL(AC) for the specified time, Tvac. The total setup

time for slow slew rates could be negative (that is, a valid input signal may not have reached VIH/VIL(AC) at the time of the

rising clock transition). A valid input signal is still required to complete the transition and reach VIH/VIL(AC).

For slew rates between the values listed in derating Tables, the derating values can be obtained using linear interpolation.

Slew rate values are not typically subject to production testing. They are verified by design and characterization.

Data Setup and Hold Base Values

Data Rate

Parameter

Reference

1066

-10

80

VIH/VIL(AC) = VREF(DC) ± 220 mV

VIH/VIL(DC) = VREF(DC) ± 130 mV

tDS (base)

tDH (base)

Notes: AC/DC referenced for 1 V/ns DQ, DM slew rate, and 2 V/ns differential DQS,  slew rate.

Version 1.4

06/2016

70

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Derating Values for AC/DC-based tDS/tDH (AC220, DC130)

AC220 DC130 Threshold

DQS,  Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH

110

74

65

43

110

74

65

43

110

74

65

43

2

89

16

59

16

1.5

0

32

1

DQ,DM

Slew rate

V/ns

-3

-5

-3

-8

-5

13

8

11

3

29

24

18

10

27

19

10

-3

45

40

34

26

4

43

35

26

13

-4

0.9

0.8

0.7

0.6

0.5

0.4

-13

56

50

42

20

-7

55

46

33

16

2

-6

66

58

36

17

78

65

48

34

Notes: Cell contents shaded in light purple are defined as “not supported.”

Version 1.4

06/2016

71

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition

tVAC @ 220mV [ps]

Slew Rate (V/ns)

Min

175

170

167

163

162

161

159

155

150

Max

>2.0

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

<0.5

–

Version 1.4

06/2016

72

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Data Setup, Hold, and Slew Rate Derating (Continued)

Typical Slew Rate and tVAC: tDS for DQ Relative to Strobe

Version 1.4

06/2016

73

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Data Setup, Hold, and Slew Rate Derating (Continued)

Typical Slew Rate: tDH for DQ Relative to Strobe

Version 1.4

06/2016

74

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Data Setup, Hold, and Slew Rate Derating (Continued)

Tangent Line: tDS for DQ with Respect to Strobe

Version 1.4

06/2016

75

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Data Setup, Hold, and Slew Rate Derating (Continued)

Tangent Line: tDH for DQ with Respect to Strobe

Version 1.4

06/2016

76

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Basic Functionality

LPDDR2-S4 uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of

input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each

command uses one clock cycle, during which command information is transferred on both the positive and

negative edge of the clock.

To achieve high-speed operation, our LPDDR2-S4 SDRAM uses the double data rate architecture and adopt

4n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access

for the LPDDR2-S4 effectively consists of a single 4n-bit wide, one clock cycle data transfer at the internal

SDRAM core and four corresponding n-bit wide, one-half-clock-cycle data transfer at the I/O pins. Read and write

accesses to the LPDDR2-S4 are burst oriented; accesses start at a selected location and continue for a

programmed number of locations in a programmed sequence.

For LPDDR2-S4 devices, accesses begin with the registration of an Active command, which is then followed by a

Read or Write command. The address and BA bits registered coincident with the Active command are used to

select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write

command are used to select the Bank and the starting column location for the burst access.

An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of

the burst access. As with standard DDR SDRAMs, the pipelined, multibank architecture of the LPDDR2-S4

SDRAMs supports concurrent operation, thereby providing high effective bandwidth by hiding row precharge and

activation time.

An auto refresh mode is provided, along with a power saving power-down mode. Deep power-down mode is

offered to achieve maximum power reduction by eliminating the power of the memory array. Data will not be

retained after device enters deep power-down mode. Two self refresh features, temperature-compensated self

refresh (TCSR) and partial array self refresh (PASR), offer additional power saving. TCSR is controlled by the

automatic on-chip temperature sensor. The PASR can be customized using the extended mode register settings.

The two features may be combined to achieve even greater power saving. The DLL that is typically used on

standard DDR devices is not necessary on the LPDDR2-S4 SDRAM. It has been omitted to save power.

Prior to normal operation, the LPDDR2-S4 SDRAM must be initialized. The following sections provide detailed

information covering device initialization, register definition, command descriptions and device operation.

Version 1.4

06/2016

77

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power-Up, Initialization, and Power-Off

LPDDR2 devices must be powered up and initialized in a predefined manner. Power-up and initialization by means other than

those specified will result in undefined operation.

Voltage Ramp and Device Initialization

The following sequence must be used to power up the device. Unless specified otherwise, this procedure is mandatory and

applies to devices.

1) Voltage Ramp:

While applying power (after Ta), CKE must be held LOW (≤ 0.2 × VDDCA), and all other inputs must be between VILmin and

VIHmax. The device outputs remain at High-Z while CKE is held LOW. Following the completion of the voltage ramp (Tb),

CKE must be maintained LOW. DQ, DM, DQS and  voltage levels must be between VSSQ and VDDQ during voltage

ramp to avoid latch up. CK, , , and CA input levels must be between VSSCA and VDDCA during voltage ramp to avoid

latch-up. Voltage ramp power supply requirements are provided bellow.

Voltage Ramp Conditions

After…

Applicable Conditions

VDD1 must be greater than VDD2 (200 mV)

VDD1 and VDD2 must be greater than VDDCA (200 mV)

VDD1 and VDD2 must be greater than VDDQ (200 mV)

VREF must always be less than all other supply voltages

Ta is reached

Notes:

1. Ta is the point when any power supply first reaches 300 mV.

2. Noted conditions apply between Ta and power-down (controlled or uncontrolled).

3. Tb is the point at which all supply and reference voltages are within their defined operating ranges. Reference voltages shall be

within their respective min/max operating conditions a minimum of 5 clocks before CKE goes high.

4. Power ramp duration tINIT0 (Tb – Ta) must not exceed 20ms.

5. For supply and reference voltage operating conditions, see DC power table.

6. The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed 100 mV.

Beginning at Tb, CKE must remain LOW for at least tINIT1 = 100 ns, after which CKE can be asserted HIGH. The clock must

be stable at least tINIT2 = 5 × tCK prior to the first CKE LOW-to-HIGH transition (Tc). CKE, , and CA inputs must observe

setup and hold requirements (tIS, tIH) with respect to the first rising clock edge (as well as to subsequent falling and rising

edges).

If any MRRs are issued, the clock period must be within the range defined for tCKb (18ns to 100ns). MRWs can be issued at

normal clock frequencies as long as all AC timings are met. Some AC parameters (for example, tDQSCK) could have relaxed

timings (such as tDQSCKb) before the system is appropriately configured. While keeping CKE HIGH, NOP commands must

be issued for at least tINIT3 = 200μs (Td).

Version 1.4

06/2016

78

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

2) RESET Command:

After tINIT3 is satisfied, the MRW RESET command must be issued (Td). An optional PRECHARGE ALL command can be

issued prior to the MRW RESET command. Wait at least tINIT4=1us while keeping CKE asserted and issuing NOP

commands.

3) MRRs and Device Auto Initialization (DAI) Polling:

After tINIT4 is satisfied (Te), only MRR commands and power-down entry/exit commands are supported. After Te, CKE can

go LOW in alignment with power-down entry and exit specifications. Use the MRR command to poll the DAI bit and report

when device auto initialization is complete; otherwise, the controller must wait a minimum of tINIT5, or until the DAI bit is set

before proceeding. As the memory output buffers are not properly configured by Te, some AC parameters must have relaxed

timings before the system is appropriately configured. After the DAI bit (MR0, DAI) is set to zero by the memory device (DAI

complete), the device is in the idle state (Tf ). DAI status can be determined by issuing the MRR command to MR0. The

device sets the DAI bit no later than tINIT5 after the RESET command. The controller must wait at least tINIT5 or until the DAI

bit is set before proceeding.

4) ZQ Calibration:

After tINIT5 (Tf ), the MRW initialization calibration (ZQ_CAL) command can be issued to the memory (MR10). For LPDDR2

devices that do not support ZQ calibration, this command will be ignored. This command is used to calibrate output

impedance over process, voltage, and temperature. In systems where more than one LPDDR2 device exists on the same bus,

the controller must not overlap MRW ZQ_CAL commands. The device is ready for normal operation after tZQinit.

5) Normal Operation:

After tZQinit (Tg), MRW commands must be used to properly configure the memory (for example the output buffer drive

strength, latencies, etc.). Specifically, MR1, MR2, and MR3 must be set to configure the memory for the target frequency and

memory configuration After the initialization sequence is complete, the device is ready for any valid command. After Tg, the

clock frequency can be changed using the procedure described in “Input Clock Frequency Changes and Clock Stop Events”.

Version 1.4

06/2016

79

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power Ramp and Initialization Sequence

Notes:

1. High-Z on the CA bus indicates valid NOP.

2. For tINIT values, see bellow.

Initialization Timing Parameters

Symbol

Parameter

Value

Unit

min

-

max

^tINIT0

^tINIT1

^tINIT2

^tINIT3

^tINIT4

Maximum Power Ramp Time

Minimum CKE low time after completion of power ramp

Minimum stable clock before first CKE high

Minimum idle time after first CKE assertion

Minimum idle time after Reset command,

this time will be about 2 x ^tRFCab + ^tRPab

Maximum duration of Device Auto-Initialization

ZQ Initial Calibration

20

-

ms

ns

100

5

-

^tCK

us

200

-

1

-

us

^tINIT5

^tZQINIT

^tCKb

-

10

-

us

ns

1

Clock cycle time during boot

18

100

Version 1.4

06/2016

80

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Initialization after RESET (without voltage ramp):

If the RESET command is issued before or after the power-up initialization sequence, the re-initialization procedure must begin at Td.

Power-Off Sequence

Use the following sequence to power off the device. Unless specified otherwise, this procedure is mandatory and applies to

devices. While powering off, CKE must be held LOW (≤ 0.2 × VDDCA); all other inputs must be between VILmin and VIHmax.

The device outputs remain at High-Z while CKE is held LOW.

DQ, DM, DQS, and  voltage levels must be between VSSQ and VDDQ during the power-off sequence to avoid latch-up.

CK, , , and CA input levels must be between VSSCA and VDDCA during the power-off sequence to avoid latch-up.

Tx is the point where any power supply drops below the minimum value.

Tz is the point where all power supplies are below 300 mV. After Tz, the device is powered off.

Power Supply Conditions

Between…

Tx and Tz

Applicable Conditions

VDD1 must be greater than VDD2—200 mV

VDD1 must be greater than VDDCA—200 mV

VDD1 must be greater than VDDQ—200 mV

VREF must always be less than all other supply voltages

Notes:

1. The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed 100 mV.

Uncontrolled Power-Off Sequence

When an uncontrolled power-off occurs, the following conditions must be met:

At Tx, when the power supply drops below the minimum values specified, all power supplies must be turned off and all

power-supply current capacity must be at zero, except for any static charge remaining in the system.

After Tz (the point at which all power supplies first reach 300 mV), the device must power off. The time between Tx and Tz

must not exceed 2s. During this period, the relative voltage between power supplies is uncontrolled. VDD1 and VDD2 must

decrease with a slope lower than 0.5 V/μs between Tx and Tz. An uncontrolled power-off sequence can occur a maximum

of 400 times over the life of the device.

Power-Off Timing

Symbol

Parameter

Min

Max

Unit

tPOFF

Maximum power-off ramp time

-

2

s

Version 1.4

06/2016

81

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Mode Register Definition

LPDDR2 devices contain a set of mode registers used for programming device operating parameters, reading device

information and status, and for initiating special operations such as DQ calibration, ZQ calibration, and device reset.

Mode Register Assignment and Definition

Table below shows the mode registers for LPDDR2 SDRAM. Each register is denoted as “R”, if it can be read but not

written, “W” if it can be written but not read, and “R/W” if it can be read and written. Mode Register Read Command shall

be used to read a register. Mode Register Write Command shall be used to write a register.

Version 1.4

06/2016

82

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Mode Register Assignment

MR#

MA <7:0>

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

DAI

Device Info

Device Feature1

Device Feature2

I/O Config-1

R

W

R

0

1

00_H

01_H

(RFU)

WC

DI

BL

nWR (for AP)

(RFU)

BT

2

02_H

RL & WL

DS

3

03_H

(RFU)

Refresh Rate

Basic Config-1

Basic Config-2

Basic Config-3

Basic Config-4

Test Mode

4

04_H

TUF

(RFU)

Refresh Rate

R

5

05_H

Manufacturer ID

Revision ID1

Revision ID2

Density

R

6

06_H

R

7

07_H

R

8

08_H

I/O width

Type

W

9

09_H

Specific Test Mode

Calibration Code

(RFU)

IO Calibration

(reserved)

10

0A_H

11~15

16

0B_H~0F_H

10_H

PASR_BANK

PASR_Seg

W

Bank Mask (4-Bank or 8-Bank)

Segment Mask

17

11_H

(Reserved)

18-19

20-31

32

12_H-13_H

18_H-1F_H

20_H

(RFU)

Reserved for NVM

DQ calibration pattern A

(Do Not Use)

DQ calibration pattern B

(Do Not Use)

(Reserved)

R

See “Data Calibration Pattern Description”

33-39

40

21_H-27_H

28_H

See “Data Calibration Pattern Description”

41-47

48-62

63

29_H-2F_H

30_H-3E_H

3F_H

(DNU)

(RFU)

X

Reset

W

(Reserved)

64-126

127

128-190

191

192-254

255

Notes:

40_H-7E_H

7F_H

(RFU)

(DNU)

(RFU)

(DNU)

(RFU)

(DNU)

(Do Not Use)

(Reserved)

80_H-BE_H

BF_H

(Do Not Use)

(Reserved)

C0_H-FE_H

FF_H

(Do Not Use)

1. RFU bits shall be set to “0” during Mode Register writes. RFU bits shall be read as “0” during Mode Register reads. All Mode Registers

that are specified as RFU shall not be written. Writes to read-only registers shall have no impact on the functionality of the device.

2. All Mode Registers from that are specified as RFU or write-only shall return undefined data when read and DQS shall be toggled.

Version 1.4

06/2016

83

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR0_Device Information (MA<7:0> = 00H)

MR#

0

MA <7:0>

00_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

DAI

Device Info

R

(RFU)

DI

0_B: S2 or S4 SDRAM

1_B: Do Not Use

OP1

DI (Device Information)

Read-only

DAI (Device Auto-Initialization

Status)

0_B: DAI complete

OP0

Read-only

1_B: DAI still in progress

Version 1.4

06/2016

84

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR1_Device Feature 1 (MA<7:0> = 01_H)

MR#

1

MA <7:0>

01_H

Function

Access

OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Device Feature1

W

nWR (for AP)

WC

BT

BL

010_B: BL4 (default)

011_B: BL8

OP<2:0>

BL (Burst Length)

Write-only

100_B: BL16

All others: reserved

0_B: Sequential (default)

1_B: Interleaved

OP3

OP4

BT¹(Burst Type)

WC (Wrap)

Write-only

0_B: Wrap (default)

1_B: No wrap (allowed for SDRAM BL4 only)

001_B: nWR=3 (default)

010_B: nWR =4

011_B: nWR =5

OP<7:5>

nWR²(for AP)

Write-only

100_B: nWR =6

101_B: nWR =7

110_B: nWR =8

All others: reserved

Notes:

1. BL16, interleaved is not an official combination to be supported.

2. Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge

operation for a write burst with AP enabled. It is determined by RU(^tWR/^tCK).

Version 1.4

06/2016

85

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Sequence by BL, BT, WC and column address

Burst Cycle Number and Burst Address Sequence

C3 C2 C1 C0 WC BT BL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

BL4

x

0_B

1_B

x

0_B

0

2

y

1

3

2

0

3

1

wrap any

nw any

4

y+1 y+2 y+3

BL8

x

0_B

1_B

0_B

1_B

x

0_B

1_B

0_B

1_B

0_B

1_B

0_B

1_B

x

0_B

0

2

4

6

0

2

4

6

1

3

5

7

1

3

5

7

2

4

6

0

2

0

6

4

3

5

7

1

3

1

7

5

4

6

0

2

4

6

0

2

5

7

1

3

5

7

1

3

6

0

2

4

6

4

2

0

7

1

3

5

7

5

3

1

seq

wrap

8

int

nw any

illegal (not allowed)

Burst Cycle Number and Burst Address Sequence

C3 C2 C1 C0 WC BT BL

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

BL16

0_B

1_B

x

0_B

1_B

0_B

1_B

0_B

1_B

0_B

1_B

0_B

0

2

1

3

5

7

9

B

D

F

2

4

3

5

7

9

B

D

F

1

4

6

5

7

9

B

D

F

1

3

6

8

7

9

B

D

F

1

3

5

8

A

C

E

0

9

B

D

F

1

3

5

7

A

C

E

0

2

4

6

8

B

D

F

1

3

5

7

9

C

E

0

2

4

6

8

A

D

F

1

3

5

7

9

B

E

0

2

4

6

8

A

C

F

1

3

5

7

9

B

D

4

6

8

A

C

E

0

6

8

A

C

E

0

seq

wrap

8

A

C

E

0

16

A

C

E

2

1_B

x

0_B

1_B

x

0_B

2

4

2

4

6

int

nw any

illegal (not allowed)

x

Notes:

1. C0 input is not present on CA bus. It is implied zero.

2. For BL=4, the burst address represents C1~C0.

3. For BL=8, the burst address represents C2~C0.

4. For BL=16, the burst address represents C3~C0.

5. For no-wrap, BL4, the burst must not cross the page boundary or the sub-page boundary. The variable y can start at any address with C0 equal to 0,

but must not start at any address shown bellow.

Version 1.4

06/2016

86

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Non-Wrap Restrictions

Width

64Mb

128Mb/256Mb

512Mb/1Gb/2Gb

4Gb/8Gb

Cannot cross full page boundary

X16

X32

FE, FF, 00, 01

7E, 7F, 00, 01

1FE, 1FF, 000, 001

FE, FF, 00, 01

3FE, 3FF, 000, 001

1FE, 1FF, 000, 001

7FE, 7FF, 000, 001

3FE, 3FF, 000, 001

Cannot cross sub-page boundary

X16

X32

7E, 7F, 80, 81

none

0FE, 0FF, 100, 101

none

1FE, 1FF, 200, 201

None

3FE, 3FF, 400, 401

none

Notes: Non-wrap BL= 4 data orders shown are prohibited.

Version 1.4

06/2016

87

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR2_Device Feature 2 (MA<7:0> = 02H)

MR#

2

MA <7:0>

02_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Device Feature2

W

(RFU)

RL & WL

0001_B: RL3 / WL1 (default)

0010_B: RL4 / WL2

0011_B: RL5 / WL2

0100_B: RL6 / WL3

0101_B: RL7 / WL4

0110_B: RL8 / WL4

All others: reserved

RL & WL

OP<3:0>

(Read Latency &

Write Latency)

Write-only

Version 1.4

06/2016

88

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR3_I/O Configuration 1 (MA<7:0> = 03H)

MR#

3

MA <7:0>

03_H

Function

Access

OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

I/O Config-1

W

(RFU)

DS

0000_B: reserved

0001_B: 34.3 ohm typical

0010_B: 40.0 ohm typical (default)

0011_B: 48.0 ohm typical

0100_B: 60.0 ohm typical

0101_B: reserved

OP<3:0>

DS (Drive Strength)

Write-only

0110_B: 80.0 ohm typical

0111_B: 120.0 ohm typical

All others: reserved

Version 1.4

06/2016

89

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR4_Device Temperature (MA<7:0> = 04H)

MR#

4

MA <7:0>

04_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Refresh Rate

R

TUF

(RFU)

Refresh Rate

000_B: SDRAM Low temperature operating limit exceeded

001_B: 4x tREFI, 4x tREFIpb, 4x tREFW

010_B: 2x tREFI, 2x tREFIpb, 2x tREFW

011_B: 1x tREFI, 1x tREFIpb, 1x tREFW (<=85C)

100_B: RFU

OP<2:0>

Refresh Rate

Read-only

101_B: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW,

do not de-rate SDRAM AC timing

110_B: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW,

de-rate SDRAM AC timing

111_B: SDRAM High temperature operating limit exceeded

0_B: OP<2:0> value has not changed since last read of MR4.

1_B: OP<2:0> value has changed since last read of MR4.

TUF

(Temperature Update Flag)

OP7

Read-only

Notes:

1. A Mode Register Read from MR4 will reset OP7 to “0”.

2. OP7 is reset to “0” at power-up.

3. If OP2 equals “1”, the device temperature is greater than 85C.

4. OP7 is set to “1”, if OP2~OP0 has changed at any time since the last read of MR4.

5. LPDDR2 might not operate properly when OP<2:0> = 000_Bor 111_B.

6. For specified operating temperature range and maximum operating temperature.

7. LPDDR2 devices must be derated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP and tRRD. The

tDQSCK parameter must be derated. Prevailing clock frequency specifications and related setup and hold timings remain

unchanged.

8. The recommended frequency for reading MR4 is provided in “Temperature Sensor”.

Version 1.4

06/2016

90

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR5_Basic Configuration-1 (MA<7:0> = 05H)

MR#

5

MA <7:0>

05_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Basic Config-1

R

Manufacturer ID

0000 0000_B: Reserved

0000 0001_B: Samsung

0000 0010_B: Qimonda

0000 0011_B: Elpida

0000 0100_B: Etron

0000 0101_B: Nanya

0000 0110_B: Hynix

0000 0111_B: Mosel

0000 1000_B: Winbond

0000 1001_B: ESMT

0000 1010_B: Reserved

0000 1011_B: Spansion

0000 1100_B: SST

OP<7:0>

Manufacturer ID

Read-only

0000 1101_B: ZMOS

0000 1110_B: Intel

1111 1110_B: Numonyx

1111 1111_B: Micron

All Others : Reserved

Version 1.4

06/2016

91

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR6_Basic Configuration-2 (MA<7:0> = 06H)

MR#

6

MA <7:0>

06_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Basic Config-2

R

Revision ID1

OP<7:0>

Revision ID1

Read-only

Reserved ¹

Notes:

1. Please contact with NTC for details

MR7_Basic Configuration-3 (MA<7:0> = 07H)

MR#

7

MA <7:0>

07_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Basic Config-3

R

Revision ID2

OP<7:0>

Revision ID2

Read-only

Reserved ¹

Notes:

1. Please contact with NTC for details

Version 1.4

06/2016

92

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR8_Basic Configuration-4 (MA<7:0> = 08H)

MR#

8

MA <7:0>

08_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Basic Config-4

R

I/O width

Density

Type

00_B: S4 SDRAM

01_B: S2 SDRAM

10_B: N NVM

11_B: Reserved

0000_B: 64Mb

0001_B: 128Mb

0010_B: 256Mb

0011_B: 512Mb

0100_B: 1Gb

OP<1:0>

OP<5:2>

OP<7:6>

Type

Read-only

Density

0101_B: 2Gb

0110_B: 4Gb

0111_B: 8Gb

1000_B: 16Gb

1001_B: 32Gb

All others: reserved

00_B: x32

01_B: x16

I/O width

10_B: x8

11_B: not used

Version 1.4

06/2016

93

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR9_Test Mode (MA<7:0> = 09H)

MR#

9

MA <7:0>

09_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Test Mode

W

Specific Test Mode

OP<7:0>

Specific Test Mode

Reserved ¹

Notes:

1. Please contact with NTC for details

Version 1.4

06/2016

94

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR10_Calibration (MA<7:0> = 0AH)

MR#

10

MA <7:0>

0A_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

IO Calibration

W

Calibration Code

0Xff: Calibration command after initialization

0Xab: Long calibration

OP<7:0>

Calibration Code

Write-only

0x56: Short calibration

0Xc3: ZQ Reset

All others: Reserved

Notes:

1. Host processor shall not write MR10 with “Reserved” values.

2. LPDDR2 devices shall ignore calibration command, when a “Reserved” values is written into MR10.

3. See AC timing table for the calibration latency.

4. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see “MRW ZQ Calibration Command”) or

default calibration (through the ZQ RESET command) is supported. If ZQ is connected to VDDCA, the device operates with

default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection must not change after

power is supplied to the device. Devices that do not support calibration ignore the ZQ calibration command.

Version 1.4

06/2016

95

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR11:15_(Reserved) (MA<7:0> = 0BH- 0FH)

MR#

MA <7:0>

0B_H~0F_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

11~15

(reserved)

(RFU)

OP<7:0>

RFU

Reserved for Future Use

Version 1.4

06/2016

96

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR16_PASR_Bank Mask (MA<7:0> = 010H)

MR#

16

MA <7:0>

10_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

PASR_BANK

W

Bank Mask (4-Bank or 8-Bank)

0_B: refresh enable to the bank (=unmasked, default)

1_B: refresh blocked (=masked)

OP<7:0>

Bank Mask (4-Bank or 8-Bank)

Write-only

For 4-bank S4 SDRAM, only OP<3:0> are used.

OP

Bank Mask

4 Bank

8 Bank

0

1

2

3

4

5

6

7

XXXXXXX1

XXXXXX1X

XXXXX1XX

XXXX1XXX

XXX1XXXX

XX1XXXXX

X1XXXXXX

1XXXXXXX

Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 1

Bank 2

Bank 3

-

Version 1.4

06/2016

97

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR17_PASR_Segment Mask (MA<7:0> = 011_H)

MR#

17

MA <7:0>

11_H

Function

Access OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

PASR_Seg

W

Segment Mask

0_B: refresh enable to the segment (=unmasked, default)

1_B: refresh blocked (=masked)

OP<7:0>

Segment Mask

Write-only

This table indicates the range of row addresses in each masked segment. X is don’t care for a particular segment.

2Gb, 4Gb

R13:11

000_B

1Gb

8Gb

Segment

OP

Bank Mask

R12:10

R14:12

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

XXXXXXX1

XXXXXX1X

XXXXX1XX

XXXX1XXX

XXX1XXXX

XX1XXXXX

X1XXXXXX

1XXXXXXX

001_B

010_B

011_B

100_B

101_B

110_B

111_B

Version 1.4

06/2016

98

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR18:19_(Reserved) (MA<7:0> = 012H- 013H)

MR#

MA <7:0>

12_H-13_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

18-19

(Reserved)

(RFU)

OP<7:0>

RFU

Reserved for Future Use

MR20:31_(Do Not Use) (MA<7:0> = 014H- 01FH)

MR#

MA <7:0>

18_H-1F_H

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

20-31

Reserved for NVM

OP<7:0>

Reserved for NVM

N/A

MR32_ DQ calibration pattern A (MA<7:0> = 020H)

MR40_ DQ calibration pattern B (MA<7:0> = 028H)

MR#

MA <7:0>

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

DQ calibration pattern A

DQ calibration pattern B

32

40

20_H

28_H

R

See “Data Calibration Pattern Description”

OP<7:0>

DQ calibration pattern A

DQ calibration pattern B

See “Data Calibration Pattern Description”

Version 1.4

06/2016

99

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

MR63_Reset (MA<7:0> = 03FH): MRW only

MR#

63

MA <7:0>

3FH

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Reset

W

X

OP<7:0>

Reset

(For additional information on MRW RESET, see “Mode Register Write Command”

on Timing Spec)

Do Not Use and Reserved functions

MR#

MA <7:0>

Function

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

17

33-39

41-47

48-62

64-126

127

11H

21_H-27_H

29H-2FH

30H-3EH

40H-7EH

7FH

(reserved)

(Do Not Use)

(Reserved)

(Do Not Use)

(Reserved)

(Do Not Use)

(Reserved)

(Do Not Use)

(RFU)

(DNU)

(RFU)

(DNU)

(RFU)

(DNU)

(RFU)

(DNU)

128-190

191

80H-BEH

BFH

192-254

255

C0H-FEH

FFH

Version 1.4

06/2016

100

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

LPDDR2-S4 SDRAM Truth Table

Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the

LPDDR2 device must be powered down and then restarted through the specified initialization sequence before normal

operation can continue.

Version 1.4

06/2016

101

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Command Truth Table

SDR Command Pins

DDR CA pins (10)

CKE

SDRAM



CA0

CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CK EDGE

command

CK

(n)

(n-1)

L

MA6

L

MA7

L

OP0

L

OP1

H

MA0

OP2

MA0

MA1

OP3

MA1

MA2

OP4

MA2

MA3

OP5

MA3

MA4

OP6

MA4

MA5

OP7

MA5

MRW

MRR

H

L

H

L

H

MA6

L

MA7

L

X

H

L

Refresh

(per bank)¹⁰

L

H

Refresh

(all bank)

Enter

Self Refresh

L

R0

H

R1

L

R8

R2

L

R9

R3

R10

R4

R11

R5

C1

C7

C1

C7

X

R12

R6

C2

C8

C2

C8

X

BA0

R7

BA1

R13

BA1

C10

BA1

C10

BA1

BA2

R14

BA2

C11

BA2

C11

BA2

Activate

(bank)

H

L

RFU

C5

RFU

C6

BA0

C9

Write

AP³

H

C3

L

C4

H

(bank)

Read

RFU

C5

RFU

C6

BA0

C9

AP³

H

C3

H

C4

L

(bank)

H

AB

BA0

Precharge

(bank)

X

H

L

BST

X

Enter

Deep Power Down

X

H

NOP

H

L

X

Maintain PD,

SREF, DPD (NOP)

X

NOP

H

L

H

L

X

Maintain PD,

SREF, DPD (NOP)

X

Enter

H

L

Power Down

X

Exit

H

PD, SREF, DPD

X

Version 1.4

06/2016

102

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Notes:

1. All LPDDR2 commands are defined by states of , CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock.

2. For LPDDR2 SDRAM, Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon.

3. AP “high” during a READ or WRITE command indicates that an auto-precharge will occur to the bank associated with the READ

or WRITE command.

4. “X” means “H or L (but a defined logic level)”.

5. Self refresh exit and Deep Power Down exit are asynchronous.

6. V_REFmust be between 0 and V_DDQduring Self Refresh and Deep Down operation.

7. CAxr refers to command/address bit “X” on the rising edge of clock.

8. CAxf refers to command/address bit “X” on the rising edge of clock.

9.  and CKE are sampled at the rising edge of clock.

10. Per Bank Refresh is only allowed in devices with 8 banks.

11. The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.

Version 1.4

06/2016

103

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

CKE Truth Table

Device

*1

CKE_n-1CKE_n

^*2Command n^*4

Operation n^*4

Device Next State Notes

Current State^*3

Active

L

H

L

H

L

x

H

x

Maintain Active Power Down

Exit Active Power Down

Maintain Idle Power Down

Exit Idle Power Down

Active Power Down

Power Down

Idle

NOP

x

Active

Idle Power Down

Idle

6,9

Power Down

Resetting

Power Down

Deep

H

L

H

x

NOP

x

Maintain Resetting Power Down

Exit Resetting Power Down

Maintain Deep Power Down

Exit Deep Power Down

Maintain Self Refresh

Resetting Power Down

Idle or Resetting

Deep Power Down

Power On

H

L

H

x

NOP

x

6,9,12

8

Power Down

H

L

H

x

NOP

x

Self Refresh

H

L

H

NOP

Exit Self Refresh

Idle

7,10

Enter Active Power Down

Active Power Down

Bank(s) Active

H

L

H

L

NOP

Enter Idle Power Down

Enter Self Refresh

Idle Power Down

Self Refresh

Enter

Self-Refresh

Enter

All Banks Idle

H

L

Enter Deep Power Down

Deep Power Down

DPD

Enter Resetting Power Down

Resetting Power Down

Resetting

Other states

Notes:

H

L

H

NOP

H

Refer to the Command Truth Table

1. “CKE_n” is the logic state of CKE at clock edge n; “CKE_n-1” was the logic state of CKE at previous clock edge.

2. “” is the logic state of  at the clock rising edge n;

3. “Current state” is the state of the LPDDR2 device immediately prior to clock edge n.

4. “Command n” is the command registered at clock edge N, and “Operation n” is a result of “Command n”.

5. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

6. Power Down exit time (^tXP) should elapse before a command other than NOP is issued.

7. Self-Refresh exit time (^tXSR) should elapse before a command other than NOP is issued.

8. The Deep Power-Down exit procedure must be followed as discussed in the DPD section of the Functional Description.

9. The clock must toggle at least once during the ^tXP period.

10. The clock must toggle at least once during the ^tXSR period.

11. “X” means “Don’t care”.

12. Upon exiting Resetting Power Down, the device will return to the idle state if ^tINIT5 has expired.

Version 1.4

06/2016

104

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Current State Bank n – Command to Bank n

Current State

Command

Operation

Next State

Notes

Continue previous operation

Select and activate row

Current State

Active

Any

NOP

ACTIVATE

Refresh (Per Bank)

Refresh (All Bank)

MRW

Begin to refresh

Refreshing (Per Bank)

Refreshing (All Bank)

MR Writing

6

7

Begin to refresh

Load value to Mode Register

Read value from Mode Register

Begin Device Auto-initialization

Deactivate row in bank or banks

Select column, and start read burst

Select column, and start write burst

Read value from Mode Register

Deactivate row in bank or banks

Idle

Idle / MR Reading

Resetting

MRR

7,8

Reset

Precharging

9,15

Precharge

Read

Reading

Writing

Write

Row Active

Active / MR Reading

Precharging

MRR

9

Precharge

Read

Select column, and start new read burst

Select column, and start write burst

Reading

Writing

10,11

10,11,12

Write

Reading

Writing

Read burst terminate

Active

Writing

13

10,11

10,11,14

13

BST

Select column, and start new write burst

Select column, and start read burst

Write burst terminate

Write

Reading

Read

Active

BST

Begin Device Auto-initialization

Read value from Mode Register

Resetting

7,9

Power On

Resetting

Reset

Resetting MR Reading

MRR

Notes:

1. The table applies when both CKE_n-1and CKE_nare HIGH, and after ^tXSR or ^tXP has been met, if the previous state was Power

Down.

2. All states and sequences not shown are illegal or reserved.

3. Current State definitions:

State

Definition

Idle

The bank or banks have been precharged, and tRP has been met.

A row in the bank has been activated, and tRCD has been met. No data bursts or accesses and no register accesses

are in progress.

Active

Reading

Writing

A READ burst has been initiated with auto precharge disabled, and has not yet terminated or been terminated.

A WRITE burst has been initiated with auto precharge disabled, and has not yet terminated or been terminated.

Version 1.4

06/2016

105

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

4. The following states must not be interrupted by a command issued to the same bank. NOP commands or allowable

commands to the other bank should been issued on any clock edge occurring during these states.

Ends when

Starts with

Notes

State

It’s met

Refreshing

(per bank)

Registration of a REFRESH

(per bank) command

tRFCpb

After tRFCpb is met, the bank is in the idle state.

Refreshing

(all banks)

Registration of a REFRESH

(all bank) command

tRFCab

tMRR

tMRW

tRP

After tRFCab is met, the device is in the all-banks idle state.

After tMRR is met, the device is in the all-banks idle state..

After tMRR is met, the device is in the all-banks idle state.

After tMRR is met, the bank is in the active state.

Idle MR

reading

Registration of the MRR

command

Resetting MR

reading

Registration of the MRR

command

Active MR

reading

Registration of the MRR

command

Registration of the MRW

command

After tMRW is met, the device is in the all-banks idle state.

After tRP is met, the device is in the all-banks idle state.

MR writing

Registration of a PRECHARGE

ALL command

Precharge all

5. The states listed below must not be interrupted by any executable command. NOP commands must be applied to each

positive clock edge during these states.

Ends when

State

Starts with

Notes

It’s met

Registration of a

Precharging

Row Active

tRP

After tRP is met, the bank is in the idle state.

After tRCD is met, the bank is in the active state.

After tRP is met, the bank is in the idle state.

PRECHARGE command

Registration of an ACTIVATE

command

tRCD

tRP

Registration of a READ

command with auto precharge

enabled

READ with

AP enable

Registration of a WRITE

command with auto precharge

enabled

WRITE with

AP enable

tRP

After tRP is met, the bank is in the idle state.

6. Bank-specific; requires that the bank is idle and no bursts are in progress.

7. Not bank-specific; requires that all banks are idle and no bursts are in progress.

8. Not bank-specific reset command is achieved through Mode Register Write command.

9. This command may or may not be bank specific. If all banks are being precharged, the must be in a valid state for precharging.

10. A command other than NOP should not be issued to the same bank while a READ or WRITE burst with auto precharge is enabled.

11. The new READ or WRITE command could be auto precharge enabled or auto precharge disabled.

12. A WRITE command can be issued after the completion of the READ burst; otherwise, a BST must be issued to end the READ prior

to asserting a WRITE command.

13. Not bank-specific. The BST command affects the most recent READ/WRITE burst started by the most recent READ/WRITE

command, regardless of bank.

14. A READ command can be issued after completion of the WRITE burst; otherwise, a BST must be used to end the WRITE prior to

asserting another READ command.

15. If a PRECHARGE command is issued to a bank in the idle state, tRP still applies.

Version 1.4

06/2016

106

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Current State Bank n – Command to Bank m

Current State

of Bank n

Any

Command

for Bank m

NOP

Next State

for Bank m

Operation

Continue previous operation

Notes

Current State of Bank m

Idle

Any

Activate

Read

Any command allowed to Bank m

-

18

7

Select and activate row in Bank m

Active

Select column, and start read burst from Bank m

Select column, and start write burst to Bank m

Deactivate row in bank or banks

Reading

Writing

8

Write

Row Activating,

Active, or

8

Precharge

Precharging

9

Idle MR Reading or Active

MR Reading

Precharging

MRR

BST

Read value from Mode Register

10,11,13

18

Read or Write burst terminate an ongoing Read/Write

from/to Bank m

Active

Read

Write

Select column, and start read burst from Bank m

Select column, and start write burst to Bank m

Select and activate row in Bank m

Reading

Writing

8

Reading

8,14

(AP disabled)

Activate

Precharge

Read

Active

Deactivate row in bank or banks

Precharging

Reading

9

8,16

8

Select column, and start read burst from Bank m

Select column, and start write burst to Bank m

Select and activate row in Bank m

Writing

Write

Writing

(AP disabled)

Activate

Precharge

Read

Active

Deactivate row in bank or banks

Precharging

Reading

9

Select column, and start read burst from Bank m

Select column, and start write burst to Bank m

Select and activate row in Bank m

8,15

Reading with

Write

Writing

8,14,15

Auto-Precharge

Activate

Precharge

Read

Active

Deactivate row in bank or banks

Precharging

Reading

9

Select column, and start read burst from Bank m

Select column, and start write burst to Bank m

Select and activate row in Bank m

8,15,16

8,15

Writing with

Write

Writing

Auto-Precharge

Activate

Precharge

Reset

Active

Deactivate row in bank or banks

Precharging

Resetting

Resetting MR Reading

9

Power On

Resetting

Notes:

Begin Device Auto-initialization

12,17

MRR

Read value from Mode Register

1. The table applies when both CKE_n-1and CKE_nare HIGH, and after ^tXSR or ^tXP has been met, if the previous state was Self

Refresh or Power Down.

2. All states and sequences not shown are illegal or reserved.

3. Current State definitions:

3.1) Idle: the bank has been precharged, and tRP has been met

3.2) Active: a row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses

are in progress.

Version 1.4

06/2016

107

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

3.3) Reading: a Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

3.4) Writing: a Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. Refresh, Self-Refresh, and Mode Register Write commands may only be issued when all bank are idle.

5. A Burst Terminate (BST) command can not be issued to another bank; it applies to the bank represented by the current state

only.

6. The following states must not be interrupted by any executable command; NOP commands must be applied during each clock

cycle while in these states:

6.1) Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has

been met,The bank will be in the Idle state.

6.2) Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once

tMRR has been met, the bank will be in the Resetting state.

6.3) Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR

has been met, the bank will be in the Active state.

6.4) MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has

been met, the bank will be in the Idle state.

7. tRRD must be met between the ACTIVATE command to bank n and any subsequent ACTIVATE command to bank m.

8. READs or WRITEs listed in the command column include READs and WRITEs with or without auto precharge enabled.

9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging.

10. MRR is supported in the row-activating state.

11. MRR is supported in the precharging state.

12. Not bank-specific; requires that all banks are idle and no bursts are in progress.

13. The next state for bank m depends on the current state of bank m (idle, row-activating, precharging, or active).

14. A WRITE command can be issued after the completion of the READ burst; otherwise a BST must be issued to end the READ

prior to asserting a WRITE command.

15. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be followed by any valid command to other

banks with timing restriction.

16. A READ command can be issued after the completion of the WRITE burst; otherwise, a BST must be issued to end the WRITE

prior to asserting another READ command.

17. RESET command is achieved through MODE REGISTER WRITE command.

18. BST is supported only if a READ or WRITE burst is ongoing.

Version 1.4

06/2016

108

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

DM Operation Truth Table

Function

Write Enable

Write Inhibit

DM

L

DQ

Valid

X

Notes

1

H

Notes:

1. Used to mask write data, provided coincident with the corresponding data.

Version 1.4

06/2016

109

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

COMMAND Definitions and Timing Diagrams

ACTIVE

The Active command is issued by holding  LOW, CA0 LOW, and CA1 HIGH at the rising edge of the clock. The bank

addresses BA0-BA2 are used to select the desired bank. The row addresses R0-R14 is used to determine which row in

the selected bank. The Active command must be applied before any Read or Write operation can be executed. The

LPDDR2 SDRAM can accept a read or write command at time ^tRCD after the active command is sent. Once a bank has

been active, it must be precharged before another Active command can be applied to the same bank. The bank active

t

and precharge times are defined as RAS and RP, respectively. The minimum time interval between two successive

ACTIVE commands on the same bank is determined by the RAS cycle time of the device (^tRC). The minimum time

interval between two successive ACTIVE commands on different banks is defined by ^tRRD.

Certain restriction on operation of the 8 bank devices must be observed. One for restricting the number of sequential

Active commands that can be issued and another for allowing more time for RAS precharge for a Precharge All

command. The rules are as follows:

8 bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated (or refreshed, in the

case of REF_pb) in a rolling ^tFAW window. Converting to clocks is done by diving ^tFAW [ns] by ^tCK[ns], and rounding up to

the next integer value. A an example of the rolling window, if RU{(^tFAW / ^tCK)} is 10 clocks, and an activate command is

issued in clock N, no more than three further activate commands may be issued at or between clock N+1 and N+9.

REF_pbalso counts as bank-activation for the purposes of ^tFAW.

t

8 bank device Precharge All allowance: ^tRP for a Precharge All command for an 8 Bank device shall equal to RP_ab,

which is greater than ^tRP_pb.

Activate command cycle: tRCD=3, tRP=3, Trrd=2

Notes:

1. A Precharge-All command uses tRPab timing, while a Single Bank Precharge command uses tRPpb timing. In this figure, tRP is

used to denote either an All-bank Precharge or a Single Bank Precharge.

Version 1.4

06/2016

110

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Tfaw timing

Notes:

1. Exclusively for 8-bank devices. No more than 4 banks may be activated in a rolling tFAW window.

Version 1.4

06/2016

111

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Command Input Signal Timing Definition

NOTE1: Setup and hold conditions also apply to the CKE pin. See section related to power down for timing diagrams related to the CKE pin.

CKE Input Signal Timing Definition

NOTE 1: After CKE is registered LOW, CKE signal level shall be maintained below VILCKE for tCKE specification (LOW pulse width).

NOTE 2: After CKE is registered HIGH, CKE signal level shall be maintained above VIHCKE for tCKE specification (HIGH pulse width).

Version 1.4

06/2016

112

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Read and Write access modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting  LOW, CA0

HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine whether the

access cycle is a read operation (CA2 HIGH) or a write operation (CA2 LOW).

The LPDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a burst read

or write operation on successive clock cycles.

For LPDDR2-S4 devices, a new burst access must not interrupt the previous 4-bit burst operation, in case of BL=4 setting.

In case of BL=8 and BL=16 settings, Reads may be interrupted by Reads, and Writes may be interrupted by Writes

provided that this occurs on even clock cycles after the Read or Write command and that ^tCCD is met. The minimum CAS

to CAS delay is defined by ^tCCD.

Version 1.4

06/2016

113

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Read

The Burst Read command is initiated by having  LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising edge of the

clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst.

The Read Latency (RL) is defined from the rising edge of the clock on which the Read Command is issued to the rising

t

edge of the clock from which the DQSCK delay is measured. The first valid datum is available RL * CK + DQSCK +

^tDQSQ after the rising edge of the clock where the Read Command is issued. The data strobe output is driven LOW

^tRPRE before the first rising valid strobe edge. The first bit of the burst is synchronized with the first rising edge of the data

strobe. Each subsequent data-out appears on each DQ pin edge aligned with the data strobe. The RL is programmed in

the mode registers. Timings for the data strobe are measured relative to the crosspoint of DQS and its complement, .

Data output (Read) timing (tDQSCKmax)

Notes:

1. tDQSCK can span multiple clock periods.

2. An effective Burst Length of 4 is shown.

Version 1.4

06/2016

114

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Read (Continued)

Data output (Read) timing (tDQSCKmin), BL=4

Burst Read: RL=5, BL=4, tDQSCK > tCK

Burst Read: RL=3, BL=8, tDQSCK < tCK

Version 1.4

06/2016

115

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Read (Continued)

tDQSCKdl timing : tDQSCKdl = |tDQSCKn – tDQSCKm| within any 32ms rolling window

Notes:

1. tDQSCKDLmax is defined as the maximum of ABS(tDQSCKn – tDQSCKm) for any { tDQSCKn – tDQSCKm} pair within any 32ms rolling window.

Version 1.4

06/2016

116

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Read (Continued)

tDQSCKdm timing : tDQSCKdm= |tDQSCKn – tDQSCKm| within any 1.6us rolling window

Notes:

1.tDQSCKDMmax is defined as the maximum of ABS(tDQSCKn – tDQSCKm) for any { tDQSCKn – tDQSCKm} pair within any 1.6us

rolling window.

Version 1.4

06/2016

117

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Read (Continued)

tDQSCKds timing : tDQSCKDS = |tDQSCKn – tDQSCKm| within a consecutive burst within any 160ns rolling window

Notes:

1. tDQSCKDSmax is defined as the maximum of ABS(tDQSCKn – tDQSCKm) for any { tDQSCKn – tDQSCKm} pair for reads within a

consecutive burst within any 160ns rolling window.

Version 1.4

06/2016

118

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Read (Continued)

Burst Read followed by burst write: RL=3, WL=1, BL=4

The minimum time from the burst READ command to the burst WRITE command is defined by the read latency (RL) and the

burst length (BL). Minimum READ-to-WRITE latency is RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 – WL clock cycles. Note that

if a READ burst is truncated with a burst TERMINATE (BST) command, the effective burst length of the truncated READ burst

should be used as “BL” to calculate the minimum READ-to-WRITE delay.

Seamless Burst Read: RL=3, BL=4, Tccd=2

The seamless burst READ operation is supported by enabling a READ command at every other clock cycle for BL = 4

operation, every fourth clock cycle for BL = 8 operation, and every eighth clock cycle for BL=16 operation. This operation is

supported as long as the banks are activated, whether the accesses read the same or different banks.

Version 1.4

06/2016

119

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Read (Continued)

For LPDDR2-S4 devices, burst read can be interrupted by another read on even clock cycles after the Read command,

provided that ^tCCD is met. For LPDDR2-S2 devices, burst reads may be interrupted by other reads on any subsequent clock,

provided that ^tCCD is met.

Read burst interrupt example: RL=3, BL=8, ^tCCD=2

Notes:

1. Reads can only be interrupted by other reads or the BST command.

2. The effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting read.

Version 1.4

06/2016

120

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Write

The burst WRITE command is initiated with  LOW, CA0 HIGH, CA1 LOW, and CA2 LOW at the rising edge of the clock.

The command address bus inputs, CA5r–CA6r and CA1f–CA9f, determine the starting column address for the burst. Write

latency (WL) is defined from the rising edge of the clock on which the WRITE command is issued to the rising edge of the

clock from which the Tdqss delay is measured. The first valid data must be driven WL × tCK + Tdqss from the rising edge of

the clock from which the WRITE command is issued. The data strobe signal (DQS) must be driven LOW Twpre prior to data

input. The burst cycle data bits must be applied to the DQ pins Tds prior to the associated edge of the DQS and held valid

until Tdh after that edge. Burst data is sampled on successive edges of the DQS until the 4-, 8-, or 16-bit burst length is

completed. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank can

be issued.Pin input timings are measured relative to the cross point of DQS and its complement, .

Data input (Write) timing

Burst write: WL=1, BL=4

Version 1.4

06/2016

121

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Write (Continued)

Burst write followed by burst read: RL=3, WL=1, BL=4

Notes:

1. The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 +

BL/2 + RU (tWTR / tCK) ].

2. tWTR starts at the rising edge of the clock after the last valid input datum.

3. If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write burst

should be used as “BL” to calculate the minimum write to read delay.

Seamless Burst write: WL=1, BL=4, Tccd=2

Notes:

1. The seamless burst write operation is supported by enabling a write command every other clock for BL=4 operation, every

four clocks for BL=8 operation, or every eight clocks for BL=16 operation. This operation is allowed regardless of same or

different banks as long as the banks are activated.

Version 1.4

06/2016

122

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Write (Continued)

Write burst interrupt timing: WL=1, BL=8, Tccd=2

Notes:

1. WRITEs can only be interrupted by other WRITEs or the BST command.

2. For LPDDR2-S4 devices, write burst interrupt function is only allowed on burst of 8 and burst of 16.

3. For LPDDR2-S4 devices, write burst interrupt may only occur on even clock cycles after the previous write commands, provided

that Tccd(min) is met.

4. Write burst interruption is allowed to any bank inside DRAM.

5. Write burst with Auto-Precharge is not allowed to be interrupted.

6. The effective burst length of the first WRITE equals two times the number of clock cycles between the first WRITE and the

interrupting WRITE.

Version 1.4

06/2016

123

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Terminate [BST]

The BST command is initiated with  LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 LOW at the rising edge of

the clock. A BST command can only be issued to terminate an active READ or WRITE burst. Therefore, a BST

command can only be issued up to and including BL/2 – 1 clock cycles after a READ or WRITE command. The

effective burst length of a READ or WRITE command truncated by a BST command is as follows:

• Effective burst length = 2 × (number of clock cycles from the READ or WRITE command to the BST command).

• If a READ or WRITE burst is truncated with a BST command, to calculate the minimum READ-to-WRITE or

WRITE-to-READ delay, the effective burst length of the truncated burst should be used as the value for BL.

• The BST command only affects the most recent READ or WRITE command. The BST command truncates an

ongoing READ burst RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock where the BST command is

issued. The BST command truncates an on-going write burst WL × tCK + Tdqss after the rising edge of the clock

where the BST command is issued.

• For LPDDR2-S4 devices, the 4-bit prefetch architecture enables BST command assertion on even clock cycles

following a WRITE or READ command. The effective burst length of a READ or WRITE command truncated by a

BST command is thus an integer multiple of 4.

Burst Write truncated by BST: WL=1, BL=16

Notes:

1. The BST command truncates an ongoing write burst WL * ^tCK + ^tDQSS after the rising edge of the clock where the Burst

Terminate command is issued.

2. For LPDDR2-S4 devices, BST can only be issued an even number of clock cycles after the Write command.

3. Additional BST commands are not allowed after T4, and may not be issued until after the next Read or Write command.

Version 1.4

06/2016

124

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Terminate [BST] (Continued)

Burst Read truncated by BST: RL=3, BL=16

Notes:

1. The BST command truncates an ongoing read burst RL * ^tCK + ^tDQSCK + ^tDQSQ after the rising edge of the clock where the Burst

Terminate command is issued.

2. For LPDDR2-S4 devices, BST can only be issued an even number of clock cycles after the Read command.

3. Additional BST commands are not allowed after T4, and may not be issued until after the next Read or Write command.

Version 1.4

06/2016

125

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Write data Mask

One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices, consistent with the

implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data byte (DQ) for any given cycle of the

burst. Data mask has identical timings on write operations as the data bits, though used as input only, is internally loaded

identically to data bits to insure matched system timing.

Data Mask Timing

Write data mask: WL=2, BL=4, second DQ masked

Notes: For the data mask function, WL=2, BL=4 is shown; the second data bit is masked.

Version 1.4

06/2016

126

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Precharge

The Precharge command is used to precharge or close a bank that has been activated. The Precharge command is initiated

by having  LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The Precharge

Command can be used to precharge each bank independently or all banks simultaneously. For 4-bank devices, the AB flag,

and the bank address bits, BA0 and BA1, are used to determine which bank(s) to precharge. For 8-bank devices, the AB flag,

and the bank address bits, BA0, BA1, and BA2, are used to determine which bank(s) to precharge. The bank(s) will be

available for a subsequent row access ^tRP_abafter an All-Bank Precharge command is issued and ^tRP_pbafter a Single-Bank

Precharge command is issued.

In order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank devices, the

Row Precharge time (^tRP) for an All-Bank Precharge for 8-bank devices (^tRP_ab) will be longer than the Row Precharge time

for a Single-Bank Precharge (^tRP_pb). For 4-bank devices, the Row Precharge time (^tRP) for an All-Bank Precharge (^tRP_ab) is

equal to the Row Precharge time for a Single-Bank Precharge (^tRP_pb).

Precharged Bank(s) Precharged Bank(s)

AB (CA4r)

BA2 (CA9r)

BA1 (CA8r)

BA0 (CA7r)

4-bank device

8-bank device

0

1

0

Bank 0 only

Bank 1 only

Bank 2 only

Bank 3 only

Bank 0 only

Bank 1 only

Bank 2 only

Bank 3 only

All Banks

Bank 0 only

Bank 1 only

Bank 2 only

Bank 3 only

Bank 4 only

Bank 5 only

Bank 6 only

Bank 7 only

All Banks

0

1

0

1

0

1

0

1

0

1

0

1

Don't care

Bank selection for Precharge by address bits

Version 1.4

06/2016

127

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Read followed by precharge

For the earliest possible precharge, the precharge command may be issued BL/2 clock cycles after a Read command. A new

bank active (command) may be issued to the same bank after the Row Precharge time (^tRP). A precharge command can not

be issued until after ^tRAS is satisfied.

For LPDDR2-S4 devices, the minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising

cloak edge that initiates the last 4-bit precharge of a Read command. This time is called ^tRTP (Read to Precharge). For

LPDDR2-S4 devices, ^tRTP begins BL/2 – 2 clock cycles after the Read command. If the burst is truncated by a BST

command, the effective “BL” shall be used to calculate when ^tRTP begins.

Burst Read followed by Precharge: RL=3, BL=8, RU(^tRTP(min)/^tCK)=2

Burst Read followed by Precharge: RL=3, BL=4, RU( ^tRTP(min)/^tCK) = 3

Version 1.4

06/2016

128

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Write followed by precharge

For write cycles, a delay must be satisfied from the time of the last valid burst input data until the Precharge command may be

issued. This delay is known as the write recovery time (^tWR) referenced from the completion of the burst write to the

t

Precharge command. No Precharge command to the same bank should be issued prior to the WR delay.

LPDDR2-S2 devices write data to the array in prefetch pairs (prefetch = 2) and LPDDR2-S4 devices write data to the array in

prefetch quadruples (prefetch = 4). The beginning of an internal write operation may only begin after a prefetch group has

been completely. Therefore, the write recovery time (^tWR) starts different boundaries for LPDDR2-S2 and LPDDR2-S4

devices.

For LPDDR2-S2 devices, minimum Write to Precharge command spacing to the same bank is WL + RU(BL/2) + 1 +

RU(^tWR/^tCK) clock cycles. For LPDDR2-S4 devices, minimum Write to Precharge command spacing to the same bank is WL

+ BL/2 + 1+ RU (^tWR/^tCK) clock cycles. For an untruncated burst, BL is the value from the Mode Register. For a truncated

burst, BL is the effective burst length.

Burst Write followed by Precharge: WL=1, BL=4

Version 1.4

06/2016

129

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Auto Precharge

Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command

or the auto-precharge function. When a Read or a Write command is given to the LPDDR2 SDRAM, the AP bit (CA0f) may be

set to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write

cycle. If AP is LOW when the Read or Write command is issued, the normal Read or Write burst operation is executed and

the bank remains active at the completion of the burst. If AP is HIGH when the Read or Write command is issued, then the

auto-precharge function is engaged. This feature allows the precharge operation to be partially or completely hidden during

burst read cycles (dependent upon Read or Write latency) thus improving system performance for random data access.

Burst Read with Auto Precharge

If AP (CA0f) is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. LPDDR2-S4

devices start an Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 – 2 + RU(^tRTP/^tCK) clock cycles later

than the Read with AP command, whichever is greater.

A new bank Activate command may be issued to the same bank if both of the following two conditions are satisfied

simultaneously:

- The RAS precharge time (^tRP) has been satisfied from the clock at which the auto-precharge begins.

- The RAS cycle time (^tRC) from the previous bank activation has been satisfied.

Burst Read with Auto-Precharge: RL=3, BL=4, RU(^tRTP(min)/^tCK)=2

Version 1.4

06/2016

130

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Burst Write with Auto Precharge

If AP (CA0f) is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The LPDDR2

SDRAM starts an Auto-precharge operation on the rising edge which is tWR cycles after the completion of the burst write.

A new bank Activate command may be issued to the same bank if both of the following two conditions are satisfied:

- The RAS precharge time (tRP) has been satisfied from the clock at which the auto-precharge begins.

- The RAS cycle time (Trc) from the previous bank activation has been satisfied.

Burst Write with Auto-Precharge: WL=1, BL=4

Version 1.4

06/2016

131

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

LPDDR2-S4: Precharge & Auto Precharge clarification

From

Minimum Delay between "From Command" to

To Command

Unit Notes

Command

"To Command"

Precharge (to same Bank as Read)

Precharge All

BL/2 + max(2, RU(^tRTP/^tCK)) - 2

tCK

1

1,2

1

3

1

3

1

Read

BL/2 + max(2, RU(^tRTP/^tCK)) - 2

Precharge (to same Bank as Read)

Precharge All

1

BST

(for Reads)

1

Precharge (to same Bank as Read w/AP)

Precharge All

BL/2 + max(2, RU(^tRTP/^tCK)) - 2

Activate (to same Bank as Read w/AP)

Write or Write w/AP (same bank)

Write or Write w/AP (different bank)

Read or Read w/AP (same bank)

Read or Read w/AP (different bank)

Precharge (to same Bank as Write)

Precharge All

BL/2 + max(2, RU(^tRTP/^tCK)) - 2 + RU(^tRP_pb/^tCK)

illegal

Read w/AP

RL + BL/2 + RU(^tDQSCKmax/^tCK) - WL + 1

illegal

BL/2

WL + BL/2 + RU(^tWR/^tCK) + 1

Write

WL + BL/2 + RU(^tWR/^tCK) + 1

Precharge (to same Bank as Write)

Precharge All

WL + RU(^tWR/^tCK) + 1

BST

(for Writes)

WL + RU(^tWR/^tCK) + 1

Precharge (to same Bank as Write w/AP)

Precharge All

WL + BL/2 + RU(^tWR/^tCK) + 1

Activate (to same Bank as Write w/AP)

Write or Write w/AP (same bank)

Write or Write w/AP (different bank)

Read or Read w/AP (same bank)

Read or Read w/AP (different bank)

Precharge (to same Bank as Precharge)

Precharge All

WL + BL/2 + RU(^tWR/^tCK) + 1 + RU(^tRP_pb/^tCK)

illegal

Write w/AP

Precharge

BL/2

illegal

WL + BL/2 + RU(^tWTR/^tCK) + 1

1

Precharge

All

Precharge All

Notes:

1. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge

or precharge all, issued to that bank. The precharge period is satisfied after ^tRP depending on the latest precharge command

issued to that bank.

2. Any command issued during the minimum delay time as specified above table is illegal.

3. After Read with AP, seamless read operations to different banks are supported. After Write with AP, seamless write

operations to different banks are supported. Read w/AP and Write a/AP may not be interrupted or truncated.

Version 1.4

06/2016

132

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Refresh Command

The Refresh Command is initiated by having  LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of clock. Per

Bank Refresh is initiated by having CA3 LOW at the rising edge of the clock and All Bank Refresh is initiated by having CA3

HIGH at the rising edge of clock. Per Bank Refresh is only allowed in devices with 8 banks.

A Per Bank Refresh Command, REFpb performs a refresh operation to the bank which is scheduled by the bank counter in

the memory device. The bank sequence of Per Bank Refresh is fixed to be a sequential round-robin: “0-1-2-3-4-5-6-7-0-1-…”.

The bank count is synchronized between the controller and the SDRAM upon issuing a RESET command or at every exit

from self refresh, by resetting bank count to zero. The bank addressing for the Per Bank Refresh count is the same as

established in the single-bank Precharge command.

A bank must be idle before it can be refreshed. It is the responsibility of the controller to track the bank being refreshed by the

Per Bank Refresh command. The REFpb command may not be issued to the memory until the following conditions are met:

- tRFCab has been satisfied after the prior REFab command.

- tRFCpb has been satisfied after the prior REFpb command.

- tRP has been satisfied after the prior Precharge command to that given bank.

tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a different

bank than affected by the REFpb command. The target bank is inaccessible during the Per Bank Refresh cycle (tRFCpb),

however other banks within the device are accessible and may be addressed during the Per Bank Refresh cycle. During the

REFpb operation, any of the banks other than the one being refreshed can be maintained in active state or accessed by a

read or a write command.

When the Per Bank Refresh cycle has completed, the affected bank will be in the idle state. As shown in the table, after

issuing REFpb:

- tRFCpb must be satisfied before issuing a REFab command.

- tRFCpb must be satisfied before issuing an ACTIVE command to a same bank.

- tRRD must be satisfied before issuing an ACTIVE command to a different bank.

- tRFCpb must be satisfied before issuing another REFpb command.

An All Bank Refresh command, REFab performs a refresh operation to all banks. All banks have to be in idle state when

REFab is issued (for instance, by Precharge All Bank command). REFab also synchronizes the bank count between the

controller and the SDRAM to zero. As shown in the table, the REFab command may not be issued to the memory until the

following conditions have been met:

- tRFCab has been satisfied after the prior REFab command.

- tRFCpb has been satisfied after the prior REFpb command.

- tRP has been satisfied after the prior Precharge commands.

When the All Bank Refresh cycle has completed, all banks will be in the idle state. As shown in the table, after issuing REFab:

- the tRFCab latency must be satisfied before issuing an ACTIVATE command.

- the tRFCab latency must be satisfied before issuing a REFab or REFpb command.

Version 1.4

06/2016

133

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Command Scheduling Separations related to Refresh

Symbol

minimum delay from

to

Notes

REF_ab

Activate cmd to any bank

^tRFC_ab

REF_ab

REF_pb

REF_ab

^tRFC_pb

^tRRD

REF_pb

Activate cmd to same bank as REF_pb

REF_pb

Activate cmd to different bank than REF_pb

REF_pbaffecting an idle bank (different bank than Activate)

Activate cmd to different bank than prior Activate

1

Activate

Notes:

1. A bank must be in the idle state before it is refreshed. Therefore, after Activate, REFab is not allowed and REFpb is

allowed only if it affects a bank which is in the idle state.

Refresh Requirement

(1) Minimum number of Refresh commands:

LPDDR2 requires a minimum number, R, of REFRESH (REFab) commands within any rolling refresh window

(tREFW = 32 ms @ MR4[2:0] = 011 or TC ≤ 85°C).

Symbol

Parameter

2Gb(SDP)

4Gb(DDP)

Unit

Number of banks

8

Refresh window: TCASE ≤ 85°

32

ms

tREFW

Required number of REFRESH commands (MIN)

8192

3.9

8192

3.9

R

us

tREFI

Average time between REFRESH commands

(for reference only)

Refresh cycle time

TCASE ≤ 85°C

0.4875

130

0.4875

130

us

ns

us

tREFIpb

tRFCab

tRFCpb

tREFBW

Per-bank REFRESH cycle time

60

4.16

Burst REFRESH window = 4 × 8 ×tRFCab

For devices supporting per-bank REFRESH, a REFab command can be replaced by a full cycle of eight REFpb

commands.

Version 1.4

06/2016

134

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Refresh Requirement (Continued)

(2) Burst Refresh limitation:

To limit maximum current consumption, a maximum of 8 REFab commands may be issued in any rolling tREFBW

(tREFBW = 4 x 8 x tRFCab).. This condition does not apply if REFpb commands are used.

(3) Refresh Requirements and Self-Refresh:

If any time within a refresh window is spent in Self-Refresh Mode, the number of required Refresh commands in this

particular window is reduced to:

R* = R - RU{tSRF / tREFI} = R - RU{R * tSRF / tREFW}; where RU stands for the round-up function.

LPDDR2 S4: Definition of Tsrf

NOTE: Above examples are several cases on how to Tsrf is calculated

1. (Example A): Time in self refresh mode is fully enclosed in the refresh window (tREFW)

2. (Example B): At self refresh entry.

3. (Example C): At self refresh exit.

4. (Example D): Several intervals in self refresh during one tREFW interval. In this example, Tsrf = Tsrf1 + Tsrf2.

Version 1.4

06/2016

135

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Refresh Requirement (Continued)

The LPDDR2 devices provide significant flexibility in scheduling REFRESH commands as long as the boundary conditions

are met. In the most straightforward implementations, a REFRESH command should be scheduled every Trefi. In this case,

self refresh can be entered at any time.

Users may choose to deviate from this regular refresh pattern, for example, to enable a period where no refreshes are

required. In the extreme (e.g., LPDDR2-S4 1Gb), the user can choose to issue a refresh burst of 4096 REFRESH commands

at the maximum supported rate (limited by tREFBW), followed by an extended period without issuing any REFRESH

commands, until the refresh window is complete. The maximum supported time without REFRESH commands is calculated

as follows: tREFW – (R/8) × tREFBW = tREFW – R × 4 × tRFCab.

For example, a 1Gb LPDDR2-S4 device at TC ≤ 85°C can be operated without REFRESH commands up to 32ms – 4096 × 4

× 130ns ≈ 30 ms. Both the regular and the burst/pause patterns can satisfy refresh requirements if they are repeated in every

32ms window. It is critical to satisfy the refresh requirement in every rolling refresh window during refresh pattern transitions.

The supported transition from a burst pattern to a regular distributed pattern. If this transition occurs immediately after the

burst refresh phase, all rolling tREFW intervals will meet the minimum required number of refreshes.

A non-supported transition –In this example, the regular refresh pattern starts after the completion of the pause phase of the

burst/pause refresh pattern. For several rolling tREFW intervals, the minimum number of REFRESH commands is not

satisfied.

Understanding this pattern transition is extremely important, even when only one pattern is employed. In self refresh mode, a

regular distributed-refresh pattern must be assumed. It is recommended entering self refresh mode immediately following the

burst phase of a burst/pause refresh pattern; upon exiting self refresh, begin with the burst phase.

Version 1.4

06/2016

136

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Refresh Requirement (Continued)

Regular, Distributed REFRESH Pattern

Notes:

1. Compared to repetitive burst REFRESH with subsequent REFRESH pause.

2. As an example, in a 1Gb LPDDR2-S4 device at TC ≤ 85°C, the distributed refresh pattern has one REFRESH command per

7.8μs; the burst refresh pattern has one refresh command per 0.52μs, followed by ≈ 30ms without any REFRESH command.

Version 1.4

06/2016

137

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Refresh Requirement (Continued)

Supported Transition from Repetitive Burst REFRESH

Notes:

1. Shown with subsequent REFRESH pause to regular, distributed-refresh pattern.

2. As an example, in a 1Gb LPDDR2-S4 device at TC ≤ 85°C, the distributed refresh pattern has one REFRESH command per 7.8μs;

the burst refresh pattern has one refresh command per 0.52μs, followed by ≈ 30ms without any REFRESH command.

Version 1.4

06/2016

138

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Refresh Requirement (Continued)

Recommended Self Refresh Entry and Exit

Notes:

1. In conjunction with a burst/pause refresh pattern.

Version 1.4

06/2016

139

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Refresh Requirement (Continued)

All Bank Refresh Operation

Per-Bank Refresh Operation

Notes:

1. In the beginning of this example, the REFpb bank is pointing to Bank 0.

2. Operations to other banks than the bank being refreshed are allowed during the tREFpb period.

Version 1.4

06/2016

140

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Self Refresh Operation

The Self Refresh command can be used to retain data in the LPDDR2 SDRAM, even if the rest of the system is powered

down. When in the Self Refresh mode, the LPDDR2 SDRAM retains data without external clocking. The LPDDR2 SDRAM

device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CKE

LOW,  LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE must be HIGH during the previous

clock cycle. A NOP command must be driven in the clock cycle following the power-down command. Once the command is

registered, CKE must be held LOW to keep the device in Self Refresh mode.

LPDDR2-S4 devices can operate in Self Refresh in both the Standard or Extended Temperature Ranges. LPDDR2-S4

devices will also manage Self Refresh power consumption when the operating temperature changes, lower at low

temperature and higher at high temperature.

Once the LPDDR2 SDRAM has entered Self Refresh mode, all of the external signals except CKE, are “don’t care”. For

proper self refresh operation, power supply pins (VDD1, VDD2, and VDDCA) must be at valid levels. VDDQ may be turned off

during Self-Refresh. Prior to exiting Self-Refresh, VDDQ must be within specified limits. VrefDQ and VrefCA may be at any

level within minimum and maximum levels. However prior to exiting Self-Refresh, VrefDQ and VrefCA must be within

specified limits. The SDRAM initiates a minimum of one all-bank refresh command internally within tCKESR period, once it

enters Self Refresh mode. The clock is internally disabled during Self Refresh Operation to save power. The minimum time

that the LPDDR2 SDRAM must remain in Self Refresh mode is tCKESR. The user may change the external clock frequency

or halt the external clock one clock after Self Refresh entry is registered; however, the clock must be restarted and stable

before the device can exit Self Refresh operation.

The procedure for exiting Self Refresh requires a sequence of commands. First, the clock shall be stable and within specified

limits for a minimum of 2 clock cycles prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least

tXSR must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE

must remain HIGH for the entire Self Refresh exit period tXSR for proper operation except for self refresh re-entry. NOP

commands must be registered on each positive clock edge during the Self Refresh exit interval tXSR.

The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is

raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one Refresh command (8

per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh.

Version 1.4

06/2016

141

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Self Refresh Operation (Continued)

Self Refresh Operation

Notes:

1. Input clock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a minimum of 2 clocks

(Tinit2) of stable clock are provided and the clock frequency is between the minimum and maximum frequency for the particular

speed grade.

2. Device must be in the “All banks idle” state prior to entering Self Refresh mode.

3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.

4. A valid command may be issued only after tXSR is satisfied. NOPs shall be issued during tXSR.

Version 1.4

06/2016

142

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Partial Array Self-Refresh: Bank Masking

LPDDR2-S4 SDRAM has 4 or 8 banks. For LPDDR2-S4 devices, 64Mb to 512Mb LPDDR2 SDRAM has 4 banks, while 1Gb

and higher density has 8. Each bank of LPDDR2 SDRAM can be independently configured whether a self refresh operation is

taking place. One mode register unit of 8 bits accessible via MRW command is assigned to program the bank masking status

of each bank up to 8 banks. For bank masking bit assignments, see Mode Register 16.

The mask bit to the bank controls a refresh operation of entire memory within the bank. If a bank is masked via MRW, a

refresh operation to entire bank is not blocked and data retention by a bank is not guaranteed in self refresh mode. To enable

a refresh operation to a bank, a coupled mask bit has to be programmed, “unmasked”. When a bank mask bit is unmasked,

the array space being refreshed within that bank is determinate by the programmed status of the segment mask bit.

Partial Array Self-Refresh: Segment Masking

Segment Programming segment mask bits is similar to programming bank mask bits. For densities 1Gb and higher, 8

segments are used for masking. Mode register 17 is used for programming segment mask bits up to 8 bits.

When the mask bit to an address range (represented as a segment) is programmed as“masked,” a REFRESH operation to

that segment is blocked. Conversely, when a segment mask bit to an address range is unmasked, refresh to that segment is

enabled. A segment-masking scheme can be used in place of or in combination with a bank masking scheme in LPDDR2-S4

SDRAM. Each segment-mask bit setting is applied across all banks.

Segment Mask

Bank 0

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

(MR17)

Bank Mask

(MR16)

0

1

0

1

Segment 0

Segment 1

Segment 2

Segment 3

Segment 4

Segment 5

Segment 6

Segment 7

0

1

0

1

M

Example of Bank and Segment Masking use in LPDDR2-S4 devices

Notes:

1. This table illustrates an example of an 8-bank LPDDR2-S4 device, when a refresh operation to bank 1 and bank 7, as well as segment

2 and segment 7 are masked.

Version 1.4

06/2016

143

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Mode Register Read Command

The Mode Register Read command is used to read configuration and status data from mode registers for LPDDR SDRAM.

The Mode Register Read (MRR) command is initiated by having  LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 HIGH

at the rising edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r-CA4r}. The mode register contents are

available on the first data beat of DQ0-DQ7, RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Mode

Register Read Command is issued. Subsequent data beats contain valid, but undefined content, except in the case of the DQ

Calibration function DQC, where subsequent data beats contain valid content as described in “DQ Calibration”. All DQS shall

be toggled for the duration of the Mode Register Read burst. The MRR command has a burst length of four. The Mode

Register Read operation (consisting of the MRR command and the corresponding data traffic) shall not be interrupted. The

MRR command period (tMRR) is 2 clock cycles. Mode Register Reads to reserved and write-only registers shall return valid,

but undefined content on all data beats and DQS shall be toggled.

Version 1.4

06/2016

144

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Mode Register Read Command (Continued)

Mode Register Read timing example: RL=3, tMRR=2

Notes:

1. Mode Register Read has a burst length of four

2. Mode Register Read operation shall not be interrupted

3. MRRs to DQ calibration registers MR32 and MR40 are described in “DQ Calibration”.

4. Only the NOP command is supported during tMRR.

5. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain valid but undefined data. DQ[MAX:8]

contain valid but undefined data for the duration of the MRR burst.

6. Minimum Mode Register Read to write latency is RL+RU(tDQSCK,max/tCK)+4/2+1-WL clock cycles

7. Minimum Mode Register Read to Mode Register Write Latency is RL+RU(tDQSCK,max/tCK)+4/2+1 clock cycles

After a prior READ command, the MRR command must not be issued earlier than BL/2 clock cycles, or WL + 1 + BL/2 +

RU(tWTR/tCK) clock cycles after a prior WRITE command, as READ bursts and WRITE bursts must not be truncated by

MRR. Note that if a READ or WRITE burst is truncated with a BST command, the effective burst length of the truncated

burst should be used for the value BL.

Version 1.4

06/2016

145

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Mode Register Read Command (Continued)

Read to MRR timing example: RL=3, tMRR=2

Notes:

1. The minimum number of clocks from the burst read command to the Mode Register Read command is BL/2.

2. Only the NOP command is supported during tMRR.

Burst Write Followed by MRR: RL=3, WL=1, BL=4

Notes:

1. The minimum number of clock cycles from the burst write command to the Mode Register Read command is [WL + 1 + BL/2 +

RU( tWTR/tCK)].

2. Only the NOP command is supported during tMRR.

Version 1.4

06/2016

146

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Temperature Sensor

LPDDR2 devices feature a temperature sensor whose status can be read from MR4. This sensor can be used to determine

an appropriate refresh rate, determine whether AC timing derating is required in the extended temperature range, and/or

monitor the operating temperature. Either the temperature sensor or the device operating temperature can be used to

determine if operating temperature requirements are being met.

Temperature sensor data may be read from MR4 using the Mode Register Read protocol.

When using the temperature sensor, the actual device case temperature may be higher than the operating temperature

specification that applies for the standard or extended temperature ranges. For example, TCASE could be above 85°C when

MR4[2:0] equals 011B.

To assure proper operation using the temperature sensor, applications must accommodate the specifications shown in bellow.

Temperature Sensor Definitions and Operating Considerations

Edge

Parameter

Symbol

Value

Unit

Notes

Maximum temperature gradient experienced by the

memory device at the temperature of interest over a

range of 2°C.

System Temperature Gradient

Max

System Dependent

C/s

TempGradient

MR4 Read Interval

Max

System Dependent

32

ms

ReadInterval

^tTSI

Time period between MR4 READs from the system.

Maximum delay between internal updates of MR4.

Temperature Sensor Interval

Maximum response time from an MR4 READ to the

system response.

System Response Delay

Max

System Dependent

ms

C

SysRespDelay

TempMargin

Margin above maximum temperature to support

controller response.

Device Temperature Margin

2

These devices accommodate the 2 degree Celsius temperature margin between the point at which the device

temperature enters the extended temperature range and point at which the controller re-configures the system

accordingly. To determine the required MR4 polling frequency, the system must use the maximum TempGradient and

the maximum response time of the system using the following equation:

For example, if TempGradient is 10°C/s and the SysRespDelay is 1ms:

In this case, ReadInterval must not exceed 183ms

Version 1.4

06/2016

147

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Temperature Sensor (Continued)

Temp Sensor Timing

Version 1.4

06/2016

148

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

DQ Calibration

LPDDR2 devices feature a DQ calibration function that outputs one of two predefined system-timing calibration patterns.

MRR to MR32 (pattern A) or MRR to MR40 (pattern B) will return the specified pattern on DQ0 and DQ8 for x16 devices

and DQ0, DQ8, DQ16, and DQ24 for x32 devices. For x16 devices, DQ[7:1] and DQ[15:9] drive the same information as

DQ0 during the MRR burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] drive the same information as

DQ0 during the MRR burst. MRR DQ calibration commands can occur only in the idle state.

DQ MR32 and MR40 DQ Calibration timing, example: RL=3, ^tMRR=2

Notes: Only the NOP command is supported during tMRR. Mode Register Read has BL4 and shall not be interrupted

Data Calibration Pattern Description

Pattern

MR# Bit Time 0 Bit Time 1 Bit Time 2 Bit Time 3

Notes

Pattern A

Pattern B

MR32

MR40

1

0

1

0

1

Reads to MR32 return DQ calibration pattern A.

Reads to MR32 return DQ calibration pattern B.

Version 1.4

06/2016

149

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Mode Register Write (MRW)

The MRW command is used to write configuration data to mode registers. The MRW command is initiated with  LOW, CA0

LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising edge of the clock. The mode register is selected by CA1f-CA0f,

CA9r-CA4r. The data to be written to the mode register is contained in CA9f-CA2f. The MRW command period is defined by

tMRW. Mode register WRITEs to read-only registers have no impact on the functionality of the device.

Mode Register Write timing, example: RL=3, tMRW=5

Notes:

1. Only the NOP command is supported during tMRW.

2. At time Ty, the device is in the idle state.

The MRW can only be issued when all banks are in the idle precharge state. One method of ensuring that the banks are in

this state is to issue a PRECHARGE-ALL command.

Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW)

Current State

Command

MRR

Intermediate State

Mode Register Reading (All Banks idle)

Mode Register Writing (All Banks idle)

Restting (Device Auto-Init)

Mode Register Reading (Bank(s) idle)

Not Allowed

Next State

All Banks idle

Bank(s) Active

Not Allowed

All Banks idle

MRW

MRW (Reset)

MRR

Bank(s) Active

MRW

MRW (Reset)

Not Allowed

Mode Register Write Reset (MRW Reset)

The MRW RESET command brings the device to the device auto-initialization (resetting) state in the power-on initialization

sequence. The MRW RESET command can be issued from the idle state. This command resets all mode registers to their

default values. Only the NOP command is supported during Tinit4. After MRW RESET, boot timings must be observed until

the device initialization sequence is complete and the device is in the idle state. Array data is undefined after the MRW

RESET command.

Version 1.4

06/2016

150

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Mode Register Write ZQ Calibration command

The MRW command is used to initiate the ZQ calibration command. This command is used to calibrate the output driver

impedance across process, temperature, and voltage. LPDDR2-S4 devices support ZQ calibration.

There are four ZQ calibration commands and related timings: tZQinit, tZQreset, tZQCL, and tZQCS. tZQinit is for initialization

calibration; tZQreset is for resetting ZQ to the default output impedance; tZQCL is for long calibration(s); and tZQCS is for

short calibration(s).

The initialization ZQ calibration (ZQINIT) must be performed for LPDDR2-S4. ZQINIT provides an output impedance

accuracy of ±15 percent. After initialization, the ZQ calibration long (ZQCL) can be used to recalibrate the system to an output

impedance accuracy of ±15 percent. A ZQ calibration short (ZQCS) can be used periodically to compensate for temperature

and voltage drift in the system.

The ZQ reset command (ZQRESET) resets the output impedance calibration to a default accuracy of ±30% across process,

voltage, and temperature. This command is used to ensure output impedance accuracy to ±30% when ZQCS and ZQCL

commands are not used.

One ZQCS command can effectively correct at least 1.5% (ZQ correction) of output impedance errors within tZQCS for all

speed bins, assuming the maximum sensitivities specified are met. The appropriate interval between ZQCS commands can

be determined from using these tables and system-specific parameters.

LPDDR2 devices are subject to temperature drift rate (Tdriftrate) and voltage drift rate (Vdriftrate) in various applications. To

accommodate drift rates and calculate the necessary interval between ZQCS commands, apply the following formula:

where Tsens = max(dRONdT) and Vsens = max(dRONdV), define the LPDDR2 temperature and voltage sensitivities.

For example, if Tsens = 0.75% / C, Vsens = 0.20% / mV, Tdriftrate = 1 C / sec and Vdriftrate = 15 mV / sec, then the interval

between ZQCS commands is calculated as:

For LPDDR2-S4 devices, a ZQ Calibration command may only be issued when the device is in Idle state with all banks

precharged. No other activities can be performed on the LPDDR2 data bus during the calibration period (tZQinit, tZQCL,

tZQCS). The quiet time on the LPDDR2 data bus helps to accurately calibrate RON. There is no required quiet time after the

ZQ Reset command. If multiple devices share a single ZQ Resistor, only one device may be calibrating at any given time.

After calibration is achieved, the LPDDR2 device shall disable the ZQ ball’s current consumption path to reduce power.

In systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQinit, tZQCS, or tZQCL

between the devices. ZQ Reset overlap is allowed. If the ZQ resistor is absent from the system, ZQ shall be connected

permanently to VDDCA. In this case, the LPDDR2 shall ignore ZQ calibration commands and the device will use the default

calibration settings.

Version 1.4

06/2016

151

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Mode Register Write ZQ Calibration command (Continued)

ZQ Calibration Initialization timing example

Notes:

1. Only the NOP command is supported during ZQ calibration.

2. CKE must be registered HIGH continuously during the calibration period.

3. All devices connected to the DQ bus should be High-Z during the calibration process.

ZQ External Resistor Value, Tolerance and Capacitive Loading

To use the ZQ Calibration function, a 240 Ohm +/- 1% tolerance external resistor must be connected between the ZQ pin and

ground. A single resistor can be used for each LPDDR2 device or one resistor can be shared between multiple LPDDR2

devices if the ZQ calibration timings for each LPDDR2 device do not overlap. The total capacitive loading on the ZQ pin must

be limited.

Version 1.4

06/2016

152

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power Down

Power-down is entered synchronously when CKE is registered LOW and  is HIGH at the rising edge of clock. CKE must be

registered HIGH in the previous clock cycle. A NOP command must be driven in the clock cycle following the power-down

command. CKE must not go LOW while MRR, MRW, READ, or WRITE operations are in progress. CKE can go LOW while

any other operations such as row activation, PRECHARGE, auto precharge, or REFRESH are in progress, but the

power-down IDD specification will not be applied until such operations are complete. Power-down entry and exit are shown in

below timing diagram.

If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when

there is a row active in any bank, this mode is referred to as active power-down.

Entering power-down deactivates the input and output buffers, excluding CK, , and CKE. In power-down mode, CKE must

be held LOW; all other input signals are “Don’t Care.” CKE LOW must be maintained until tCKe is satisfied. VREFCA must be

maintained at a valid level during power-down.

VDDQ can be turned off during power-down. If VDDQ is turned off, VREFDQ must also be turned off. Prior to exiting

power-down, both VDDQ and VREFDQ must be within their respective minimum/maximum operating ranges.

No refresh operations are performed in power-down mode. The maximum duration in power-down mode is only limited by the

refresh requirements outlined in section “REFRESH Command”.

The power-down state is excited when CKE is registered HIGH. The controller must drive  HIGH in conjunction with CKE

HIGH when exiting the power-down state. CKE HIGH must be maintained until tCKe is satisfied. A valid, executable command

can be applied with power-down exit latency tXP after CKE goes HIGH.

Basic Power-Down entry and exit timing

Notes: Input clock frequency can be changed or the input clock stopped during power-down, provided that the clock frequency is

between the minimum and maximum specified frequencies for the speed grade in use, and that prior to power-down exit, a

minimum of 2 stable clocks complete.

Version 1.4

06/2016

153

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power Down (Continued)

CKE intensive environment

REF to REF timing in CKE intensive environment

Notes:

1. The pattern shown above can repeat over a long period of time. With this pattern, LPDDR2 SDRAM guarantees all AC and DC

timing & voltage specifications with temperature and voltage drift ensured.

Version 1.4

06/2016

154

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power Down (Continued)

Read to Power-Down entry

Notes:

1.CKE must be held HIGH until the end of the burst operation

2.CKE may be registered LOW RL + RU(^tDQSCK(MAX)/^tCK) + BL/2 + 1 clock cycles after the clock on which the Read command is registered.

Version 1.4

06/2016

155

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power Down (Continued)

Read with Auto-precharge to Power-Down entry

Notes:

1. CKE must be held HIGH until the end of the burst operation.

2. CKE can be registered LOW at RL + RU(tDQSCK/tCK)+ BL/2 + 1 clock cycles after the clock on which the READ command is registered.

3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied.

4. Start internal PRECHARGE.

Version 1.4

06/2016

156

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power Down (Continued)

Write to Power-Down entry

Notes:

1. CKE can be registered LOW at WL + 1 + BL/2 + RU(tWR/tCK) clock cycles after the clock on which the WRITE command is registered

Version 1.4

06/2016

157

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power Down (Continued)

Write with Auto-precharge to Power-Down entry

Notes:

1. CKE may be registered LOW WL + 1 + BL/2 + RU(^tWR/^tCK) +1 clock cycles after the Write command is registered.

2. Start internal PRECHARGE.

Version 1.4

06/2016

158

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power Down (Continued)

Refresh command to Power-Down entry

Notes:

1. CKE may go LOW ^tIHCKE after the clock on which the Refresh command is registered.

Activate command to Power-Down entry

Notes:

1. CKE may go LOW tIHCKE after the clock on which the Activate command is registered.

Precharge command to Power-Down entry

Notes:

1. CKE may go LOW tIHCKE after the clock on which the Precharge command is registered.

Version 1.4

06/2016

159

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Power Down (Continued)

Mode Register Read to Power-Down entry

Notes:

1. CKE may be registered LOW RL + RU(tDQSCK/tCK)+ BL/2 + 1 clock cycles after the clock on which the Mode Register Read command

is registered.

Mode Register Write to Power-Down entry

Notes:

1. CKE may be registered LOW tMRW after the clock on which the Mode Register Write command is registered.

Version 1.4

06/2016

160

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Deep Power Down (DPD)

Deep Power-Down is entered when CKE is registered LOW with  LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW at the rising

edge of clock. A NOP command must be driven in the clock cycle following the power-down command. CKE is not allowed to

go LOW while mode register, read, or write operations are in progress. All banks must be in idle state with no activity on the

data bus prior to entering the Deep Power Down mode. During Deep Power-Down, CKE must be held LOW.

In Deep Power-Down mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry may be

disabled within the SDRAM. All power supplies must be within specified limits prior to exiting Deep Power-Down. VrefDQ and

VrefCA may be at any level within minimum and maximum levels. However prior to exiting Deep Power-Down, Vref must be

within specified limits.

The contents of the SDRAM may be lost upon entry into Deep Power-Down mode.

The Deep Power-Down state is exited when CKE is registered HIGH, while meeting Tiscke with a stable clock input. The

SDRAM must be fully re-initialized as described in the Power up initialization Sequence. The SDRAM is ready for normal

operation after the initialization sequence.

Deep Power-Down entry and exit timing diagram

Notes:

1. Initialization sequence may start at any time after Tx + 1.

2. Tinit3 and Tx + 1 and refer to timings in the initialization sequence.

3. The clock is stable and within specified limits for a minimum of 2 clock cycles prior to deep power down exit and the clock

frequency is between the minimum and maximum frequency for the particular speed grade.

Version 1.4

06/2016

161

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Input clock stop and frequency change

LPDDR2 devices support input clock frequency change during CKE LOW under the following conditions:

•

tCK(abs)min is met for each clock cycle

•

Refresh requirement apply during clock frequency change

During clock frequency change, only REFab or REFpb commands may be executing

Any ACTIVATE or PRECHARGE commands have completed prior to changing the frequency

Related timing conditions,tRCD and tRP, have been met prior to changing the frequency

The initial clock frequency must be maintained for a minimum of 2 clock cycles after CKE goes LOW

The clock satisfies tCH(abs) and tCL(abs) for a minimum of two clock cycles prior to CKE going HIGH.

•

After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set

the WR, RL, etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock

frequency.

LPDDR2 devices support clock stop during CKE LOW under the following conditions:

•

CK is held LOW and  is held HIGH during clock stop

Refresh requirements are met

Only REFab or REFpb commands can be in process

Any ACTIVATE or PRECHARGE commands have completed prior to changing the frequency

Related timing conditions, tRCD and tRP, have been met prior to changing the frequency

The initial clock frequency must be maintained for a minimum of 2 clock cycles after CKE goes LOW

The clock satisfies tCH(abs) and tCL(abs) for a minimum of two clock cycles prior to CKE going HIGH.

LPDDR2 devices support input clock frequency change during CKE HIGH under the following conditions:

•

tCK(abs)min is met for each clock cycle

Refresh requirement apply during clock frequency change

Any Activate, Read, Write, Precharge, Mode Register Write or Mode Register Read commands must have executed

to completion including any associated data bursts prior to changing the frequency

•

The related timing conditions (tRCD, tWR, tWRa, tRP,tMRW,tMRR etc) have been met prior to changing the

frequency

•

 shall be held HIGH during clock frequency change

During clock frequency change, only REFab or REFpb commands may be executing

The LPDDR2 device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of

2tCK+tXP.

•

After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set

the WR, RL, etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock

frequency.

Version 1.4

06/2016

162

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Input clock stop and frequency change (Continued)

LPDDR2 devices support clock stop during CKE HIGH under the following conditions:

•

CK is held LOW and  is held HIGH during clock stop

 shall be held HIGH during clock stop

Refresh requirements are met

Only REFab or REFpb commands can be in process

Any Activate, Read, Write, Precharge, Mode Register Write or Mode Register Read commands must have executed

to completion including any associated data bursts prior to stopping the clock

•

The related timing conditions (tRCD, tWR, tWRa, tRP, tMRW, tMRR etc) have been met prior to stopping the clock

The LPDDR2 device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for a

minimum of 2tCK+tXP.

No Operation Command

The purpose of the No Operation command (NOP) is to prevent the LPDDR2 device from registering any unwanted command

between operations. Only when the CKE level is constant for clock cycle N-1 and clock cycle N, a NOP command may be

issued at clock cycle N. A NOP command has two possible encodings:

1.  HIGH at the clock rising edge N.

2.  LOW and CA0, CA1, CA2 HIGH at the clock rising edge N.

The No Operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle.

Version 1.4

06/2016

163

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

Revision History

Rev

Page

Modified

Description

Released

1.1

-

Official Release

10/2015

P1-3,6,11,18

P1

Add part number: NT6TL128M16CQ-G0

1.2

01/2016

Modify 134b Ball pitch: 0.65mm (was:0.50mm)

1.3

1.4

P2,5,10,15

P1-16

Add part number and 134b information: NT6TL128M16CI-G0, NT6TL128M16CI-G0I

Add 134b (10.00 x 11.50 x 0.80(mm)) part number, ballout and POD.

02/2016

06/2017

Version 1.4

06/2016

164

Nanya Technology Corp.

LPDDR2-S4B 2Gb(SDP)/4Gb(DDP) SDRAM

NT6TL64M32CQ(I/A) / NT6TL128M16CQ(I/A) / NT6TL64T64CR(5)

http://www.nanya.com/

Version 1.4

06/2016

165

Nanya Technology Corp.


型号：	NT6TL64T64CI-G0I
厂家：	Nanya Technology Corporation.
描述：	Commercial and Industrial Mobile LPDDR2 2Gb / 4Gb(DDP) SDRAM 动态存储器双倍数据速率光电二极管
文件：	总165页 (文件大小：5113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NT6TL64T64CI-G0I [NANYA]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E