MC-454CA726LFA-A10 [NEC]
Synchronous DRAM Module, 4MX72, 6ns, MOS, DIMM-168;
| 型号： | MC-454CA726LFA-A10 |
| 厂家： | 
NEC |
| 描述： | Synchronous DRAM Module, 4MX72, 6ns, MOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-454CA726
4M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-454CA726 is a 4,194,304 words by 72 bits synchronous dynamic RAM module on which 5 pieces of 64M
SDRAM : µPD4564163 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 4,194,304 words by 72 bits organization
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
Power consumption (MAX.)
(MAX.)
6 ns
6 ns
6 ns
7 ns
6 ns
6 ns
6 ns
7 ns
Active
Standby
9.0 mW
MC-454CA726F-A80
MC-454CA726F-A10
MC-454CA726LFA-A80
MC-454CA726LFA-A10
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
125 MHz
100 MHz
100 MHz
77 MHz
3,510 mW
2,970 mW
2,970 mW
2,340 mW
3,510 mW
2,970 mW
2,970 mW
2,340 mW
(CMOS level input )
125 MHz
100 MHz
100 MHz
77 MHz
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length : 1, 2, 4, 8 and full page
• Programmable wrap sequence (sequential / interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ± 10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13500EJ3V0DS00 (3rd edition)
Date Published February 1999 NS CP (K)
Printed in Japan
The mark • shows major revised points.
1998
©
MC-454CA726
Ordering Information
Part number
Clock frequency
(MAX.)
Package
Mounted devices
MC-454CA726F-A80
MC-454CA726F-A10
MC-454CA726LFA-A80
MC-454CA726LFA-A10
125 MHz
100 MHz
125 MHz
100 MHz
168-pin Dual In-line Memory Module
(Socket Type)
5 pieces of µPD4564163G5 (Rev. E)
(400 mil TSOP (II))
Edge connector : Gold plated
34.93 mm (1.375 inch) height
168-pin Dual In-line Memory Module
(Socket Type)
5 pieces of µPD4564163G5 (Rev. L)
(400 mil TSOP (II))
Edge connector : Gold plated
25.4 mm (1.0 inch) height
2
Data Sheet M13500EJ3V0DS00
MC-454CA726
Pin Configuration
168-pin Dual In-line MemoryModule Socket Type (Edge connector: Gold plated)
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
V
SS
V
SS
/xxx indicates active low signal.
DQ32
DQ33
DQ34
DQ35
Vcc
DQ0
DQ1
DQ2
DQ3
Vcc
DQ36
DQ37
DQ38
DQ39
DQ4
DQ5
DQ6
DQ7
95
96
DQ40
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
V
SS
V
SS
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ46
DQ47
CB4
DQ14
DQ15
CB0
CB5
CB1
V
SS
V
SS
NC
NC
Vcc
NC
NC
Vcc
/WE
/CAS
DQMB4
DQMB5
NC
DQMB0
DQMB1
/CS0
NC
/RAS
V
SS
V
SS
A0
A2
A1
A3
A4
A5
A6
A7
A0 - A11
: Address Inputs
A8
A9
A10
BA0(A13)
A11
Vcc
BA1(A12)
Vcc
[Row: A0 - A11, Column: A0 - A7]
BA0 (A13), BA1 (A12)
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
: SDRAM Bank Select
DQ0 - DQ63, CB0 - CB7
: Data Inputs / Outputs
CLK0
VSS
VSS
CKE0
NC
NC
/CS2
DQMB2
DQMB3
NC
DQMB6
DQMB7
NC
CLK0 - CLK3
CKE0
: Clock Input
Vcc
Vcc
NC
NC
: Clock Enable Input
: Write Protect Note
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
NC
NC
CB6
CB7
CB2
WP
CB3
V
SS
VSS
/CS0, /CS2
/RAS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
/CAS
DQ52
NC
DQ20
NC
/WE
NC
NC
NC
NC
DQMB0 - DQMB7 : DQ Mask Enable
V
SS
VSS
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
SA0 - SA2
SDA
: Address Input for EEPROM
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
: Ground
V
SS
V
SS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
SCL
CC
V
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
SS
V
NC
: No Connection
V
SS
V
SS
CLK2
NC
CLK3
NC
WP
SA0
SA1
SA2
Vcc
Note WP is not used yet. It is connected to
SDA
SCL
Vcc
ground.
3
Data Sheet M13500EJ3V0DS00
MC-454CA726
Block Diagram
/WE
/CS0
/CS2
LDQM
/CS /WE
/CS /WE
/CS /WE
LDQM
/CS /WE
DQMB 6
DQMB 4
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 38
DQ 37
DQ 39
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D1
D4
UDQM
UDQM
DQMB 2
DQMB 0
DQ 8
DQ 8
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ 9
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
/CS /WE
DQMB 7
DQMB 5
LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D5
D2
DQMB 1
UDQM
DQMB 3
UDQM
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ 8
DQ 8
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ 9
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ8
LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
CLK0
CLK : U1 - U3
10 pF
SERIAL PD
SDA
WP
SCL
A0
A1
A2
CLK2
CLK : U4, U5
15 pF
47kΩ
SA0 SA1 SA2
D3
CLK1, CLK3
UDQM
10 pF
A0 - A11
BA0
A0 - A11: U1 - U5
A13: U1 - U5
DQ 8
CB7
CB6
CB4
CB5
CB3
CB2
CB1
CB0
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
/RAS
/CAS
/RAS: U1 - U5
/CAS: U1 - U5
BA1
A12: U1- U5
V
V
CC
SS
U1- U5
U1- U5
C
CKE0
CKE: U1 - U5
Remarks 1. The value of all resistors is 10 Ω except WP.
2. WP is not used yet. It is connected to ground.
3. U1 - U5 : µPD4564163 (1M words × 16 bits × 4 banks)
4
Data Sheet M13500EJ3V0DS00
MC-454CA726
Electrical Specifications
• All voltages are referenced to V (GND).
SS
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
4
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
Tstg
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
−0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
High level input voltage
VCC+0.3
+0.8
V
Low level input voltage
VIL
V
Operating ambient temperature
TA
70
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
Test condition
MIN.
25
TYP.
MAX.
44
Unit
pF
CI1
A0 - A11, BA0 (A13), BA1 (A12), /RAS,
/CAS, /WE
CI2
CI3
CI4
CI5
CLK0, CLK2
24
24
12
7
40
40
24
16
13
CKE0
/CS0, /CS2
DQMB0 - DQMB7
DQ0 - DQ63, CB0 - CB7
Data input / output capacitance
C
I/O
7
pF
5
Data Sheet M13500EJ3V0DS00
MC-454CA726
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
[MC-454CA726F]
Parameter
Symbol
ICC1
Test condition
Grade MIN. MAX. Unit Notes
Operating current
Burst length = 1,
/CAS latency = 2 -A80
450
400
575
450
5
mA
1
tRC ≥ tRC (MIN.), IO = 0 mA
-A10
/CAS latency = 3 -A80
-A10
Precharge standby current in
power down mode
ICC2P
CKE ≤ VIL (MAX.), tCK = 15 ns
mA
mA
ICC2PS CKE ≤ VIL (MAX.), tCK = ∞
ICC2N
2.5
100
Precharge standby current in
non power down mode
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞ , Input signals are stable.
ICC3P CKE ≤ VIL (MAX.), tCK = 15 ns
ICC3PS CKE ≤ VIL (MAX.), tCK = ∞
30
25
Active standby current in
power down mode
mA
mA
20
Active standby current in
non power down mode
ICC3N
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
125
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
50
Operating current
(Burst mode)
ICC4
tCK ≥ tCK (MIN.), IO = 0 mA
/CAS latency = 2 -A80
825
650
975
825
mA
mA
2
3
-A10
/CAS latency = 3 -A80
-A10
CBR (Auto) refresh current
ICC5
tRC ≥ tRC (MIN.)
/CAS latency = 2 -A80
-A10
650
/CAS latency = 3 -A80
-A10
675
Self refresh current
ICC6
II (L)
CKE ≤ 0.2 V
4
mA
µA
µA
V
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = –4.0 mA
−5
−1.5
2.4
+5
IO (L)
VOH
VOL
+1.5
IO = +4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6
Data Sheet M13500EJ3V0DS00
MC-454CA726
[MC-454CA726LFA]
Parameter
Symbol
ICC1
Test condition
Grade MIN. MAX. Unit Notes
Operating current
Burst length = 1,
/CAS latency = 2 -A80
450
400
575
450
5
mA
1
tRC ≥ tRC (MIN.), IO = 0 mA
-A10
/CAS latency = 3 -A80
-A10
Precharge standby current in
power down mode
ICC2P
CKE ≤ VIL (MAX.), tCK = 15 ns
mA
mA
ICC2PS CKE ≤ VIL (MAX.), tCK = ∞
ICC2N
2.5
100
Precharge standby current in
non power down mode
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞ , Input signals are stable.
ICC3P CKE ≤ VIL (MAX.), tCK = 15 ns
ICC3PS CKE ≤ VIL (MAX.), tCK = ∞
30
25
Active standby current in
power down mode
mA
mA
20
Active standby current in
non power down mode
ICC3N
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
125
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
75
★
Operating current
(Burst mode)
ICC4
tCK ≥ tCK (MIN.), IO = 0 mA
/CAS latency = 2 -A80
825
650
975
825
mA
mA
2
3
-A10
/CAS latency = 3 -A80
-A10
CBR (Auto) refresh current
ICC5
tRC ≥ tRC (MIN.)
/CAS latency = 2 -A80
-A10
650
/CAS latency = 3 -A80
-A10
675
Self refresh current
ICC6
II (L)
CKE ≤ 0.2 V
4
mA
µA
µA
V
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = –4.0 mA
−5
−1.5
2.4
+5
IO (L)
VOH
VOL
+1.5
IO = +4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
7
Data Sheet M13500EJ3V0DS00
MC-454CA726
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions
T
• AC measurements assume t = 1ns.
IH
IL
• Reference level for measuring timing of input signals is 1.4V. Transition times are measured between V and V .
T
IH (MIN.)
IL (MAX.)
and V
• If t is longer than 1ns, reference level for measuring timing of input signals is V
.
• An access time is measured at 1.4 V.
t
CK
t
CH
t
CL
2.0 V
1.4 V
0.8 V
CLK
t
SETUP
t
HOLD
2.0 V
1.4 V
0.8 V
Input
t
AC
t
OH
Output
8
Data Sheet M13500EJ3V0DS00
MC-454CA726
Synchronous Characteristics
Parameter
Symbol
-A80
-A10
Unit
Note
MIN.
8
MAX.
MIN.
10
MAX.
Clock cycle time
/CAS latency = 3
tCK3
tCK2
tAC3
tAC2
tCH
(125 MHz)
(100 MHz)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
10
(100 MHz)
13
(77 MHz)
Access time from CLK
6
6
6
7
1
1
CLK high level width
CLK low level width
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3
3
3
0
3
3
2
1
2
1
2
1
2
2
tCL
Data-out hold time
tOH
1
Data-out low-impedance time
tLZ
Data-out high-impedance time /CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
6
6
6
7
Data-in setup time
Data-in hold time
tDH
Address setup time
tAS
Address hold time
tAH
CKE setup time
tCKS
tCKH
tCKSP
tCMS
CKE hold time
CKE setup time (Power down exit)
Command (/CS0, /CS2, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0, /CS2, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
tCMH
1
1
ns
Note 1. Output load
1.4 V
50Ω
Z = 50Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
9
Data Sheet M13500EJ3V0DS00
MC-454CA726
Asynchronous Characteristics
Parameter
Symbol
-A80
-A10
Unit
Note
MIN.
70
48
20
20
16
8
MAX.
MIN.
MAX.
REF to REF/ACT command period
ACT to PRE command period
tRC
tRAS
tRP
70
ns
ns
120,000
50
120,000
PRE to ACT command period
20
ns
Delay time ACT to READ/WRITE command
ACT (0) to ACT (1) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
tDAL3
tDAL2
tRSC
tT
20
ns
20
ns
10
ns
Data-in to ACT (REF) command
period (Auto precharge)
/CAS latency = 3
/CAS latency = 2
1CLK+20
1CLK+20
2
1CLK+20
ns
1CLK+20
ns
Mode register set cycle time
Transition time
2
1
CLK
ns
0.5
30
64
30
64
Refresh time (4,096 refresh cycles)
tREF
ms
10
Data Sheet M13500EJ3V0DS00
MC-454CA726
Serial PD
(1/2)
Byte
No.
Function Described
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
128 bytes
256 bytes
0
Defines the number of bytes written
into serial PD memory
80H
08H
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
Total number of bytes of serial PD
memory
2
3
4
5
6
7
8
9
Fundamental memory type
04H
0CH
08H
01H
48H
00H
01H
80H
A0H
60H
60H
02H
80H
10H
10H
01H
8FH
04H
06H
01H
01H
00H
0EH
A0H
D0H
60H
70H
00H
14H
14H
10H
14H
14H
14H
30H
32H
08H
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDRAM
12 rows
8 columns
1 bank
72 bits
0
Number of rows
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
LVTTL
8 ns
CL = 3 cycle time
-A80
-A10
-A80
-A10
10 ns
6 ns
10
CL = 3 access time
6 ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate / type
ECC
Normal
x16
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
x16
1 clock
1, 2, 4, 8, F
4 banks
2, 3
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
0
/WE latency supported
0
SDRAM module attributes
SDRAM device attributes : General
CL = 2 cycle time
-A80
10 ns
13 ns
6 ns
-A10
-A80
-A10
24
CL = 2 access time
7 ns
25-26
27
tRP (MIN.)
-A80
-A10
-A80
-A10
-A80
-A10
-A80
-A10
20 ns
20 ns
10 ns
20 ns
20 ns
20 ns
48 ns
50 ns
32 bytes
28
29
30
31
tRRD (MIN.)
tRCD (MIN.)
tRAS (MIN.)
Module bank density
11
Data Sheet M13500EJ3V0DS00
MC-454CA726
(2/2)
Byte No.
32
Function Described
Hex
20H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
2 ns
Command and address signal input
setup time
0
0
1
0
0
0
0
0
33
Command and address signal input
hold time
10H
0
0
0
1
0
0
0
0
1 ns
34
35
Data signal input setup time
Data signal input hold time
20H
10H
00H
12H
F8H
5EH
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
2 ns
1 ns
36-61
62
SPD revision
1.2
-A80
63
Checksum for bytes 0 - 62
-A10
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
127
Intel specification frequency
Intel specification /CAS
latency support
64H
A7H
A5H
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
1
0
0
1
1
100 MHz
-A80
-A10
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348X).
12
Data Sheet M13500EJ3V0DS00
MC-454CA726
Package Drawings
[MC-454CA726F]
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Z1
Z2
N
Y1
Y2
F2
R2
F1
Q
M
R1
L
A
B
S
H
(OPTIONAL HOLES)
U1
U2
T
J
K
C
B
E
I
G
D
A1 (AREA A)
M2 (AREA A)
ITEM MILLIMETERS
A
133.35
133.35±0.13
11.43
A1
B
C
36.83
D
6.35
D1
D2
E
2.0
3.125
54.61
M1 (AREA B)
F1
F2
G
2.44
3.18
6.35
detail of A part
W
detail of B part
D2
H
1.27 (T.P.)
8.89
I
24.495
42.18
J
K
17.78
L
M
34.93±0.13
15.15
M1
M2
N
19.78
V
X
P
4.0 MAX.
1.0
P
D1
Q
R2.0
R1
R2
S
4.0±0.10
9.53
φ
3.0
T
1.27±0.1
4.0 MIN.
4.0 MIN.
0.2±0.15
1.0±0.05
2.54±0.10
3.0 MIN.
2.26
U1
U2
V
W
X
Y1
Y2
Z1
Z2
3.0 MIN.
2.26
M168S-50A95
13
Data Sheet M13500EJ3V0DS00
MC-454CA726
[MC-454CA726LFA]
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
N
Z1
Y1
Q
L
M
R
A
B
S
H
(OPTIONAL HOLES)
U
J
K
C
T
B
E
I
G
D
A1 (AREA A)
ITEM MILLIMETERS
A
A1
B
133.35
133.35±0.13
11.43±0.05
36.83±0.05
6.35±0.05
2.0±0.01
3.125±0.125
54.61±0.05
6.35±0.05
1.27 (TYP)
8.89
M2 (AREA A)
M1 (AREA B)
C
D
D1
D2
E
G
H
I
detail of A part
W
detail of B part
D2
24.495
J
K
42.18
17.78
L
M
25.4±0.13
5.62
M1
M2
N
19.78
2.8 MAX.
1.0±0.10
R2.0
P
Q
R
V
X
P
4.0±0.10
D1
φ
3.0
S
T
1.27±0.1
4.0 MIN.
0.2±0.15
1.0±0.05
2.54±0.10
3.0 MIN.
3.0 MIN.
U
V
W
X
Y1
Z1
14
Data Sheet M13500EJ3V0DS00
MC-454CA726
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
15
Data Sheet M13500EJ3V0DS00
MC-454CA726
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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