MC-454CB64LS-A10B [NEC]
Synchronous DRAM Module, 4MX64, 7ns, MOS, SODIMM-144;
| 型号： | MC-454CB64LS-A10B |
| 厂家： | 
NEC |
| 描述： | Synchronous DRAM Module, 4MX64, 7ns, MOS, SODIMM-144 动态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-454CB64S, 454CB64LS
4M-WORD BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Description
The MC-454CB64S and MC-454CB64LS are a 4,194,304 words by 64 bits synchronous dynamic RAM module
(Small Outline DIMM) on which 4 pieces of 64M SDRAM: µPD4564163 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 4,194,304 words by 64 bits organization
• Clock frequency and Access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
Power consumption (MAX.)
(MAX.)
6 ns
6 ns
6 ns
7 ns
7 ns
8 ns
7ns
Active
Standby
7.2 mW
MC-454CB64S-A80
MC-454CB64S-A10
MC-454CB64S-A10B
MC-454CB64S-A10BL
MC-454CB64LS-A10B
MC-454CB64LS-A10BL
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
125 MHz
100 MHz
100 MHz
77 MHz
2,808 mW
2,376 mW
2,376 mW
1,872 mW
2,376 mW
1,584 mW
2,376 mW
1,584 mW
2,376 mW
1,584 mW
2,376 mW
1,584 mW
(CMOS level input )
100 MHz
67 MHz
100 MHz
67 MHz
8ns
100 MHz
67 MHz
7 ns
8 ns
7ns
100 MHz
67 MHz
8ns
• Fully Synchronous Dynamic RAM, with all signals
referenced to a positive clock edge
• Pulsed interface
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3V ±0.3V power supply
• LVTTL compatible
• Possible to assert random column address in every
cycle
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge
command
• Dual internal banks controlled by BA0, BA1
(Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• 144-pin small outline dual in-line memory module
(Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark • shows major revised points.
Document No. M12386EJ9V0DS00 (9th edition)
Date Published February 1999 NS CP(K)
Printed in Japan
1997
©
MC-454CB64S, 454CB64LS
Ordering Information
Part number
Clock frequency
MHz (MAX.)
Package
Mounted devices
MC-454CB64S-A80
MC-454CB64S-A10
MC-454CB64S-A10B
125 MHz
100 MHz
100 MHz
144-pin Small Outline DIMM
(Socket Type)
4 pieces of µPD4564163G5 (Rev. E)
(400 mil TSOP (II))
Edge connector : Gold plated
25.4 mm (1 inch) height
MC-454CB64S-A10BL
MC-454CB64LS-A10B
MC-454CB64LS-A10BL
100 MHz
100 MHz
100 MHz
4 pieces of µPD4564163G5 (Rev. L)
(400 mil TSOP (II))
Data sheet M12386EJ9V0DS00
2
MC-454CB64S, 454CB64LS
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector : Gold plated)
2
4
Vss
Vss
DQ 0
DQ 1
DQ 2
DQ 3
1
/xxx indicates active low signal.
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
3
6
5
8
7
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
9
V
CC
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
DQ 36
DQ 37
DQ 38
DQ 39
Vss
DQ 4
DQ 5
DQ 6
DQ 7
Vss
DQMB4
DQMB5
Vcc
DQMB0
DQMB1
V
CC
A3
A0
A1
A4
A5
A2
Vss
Vss
DQ 40
DQ 41
DQ 42
DQ 43
Vcc
DQ 8
DQ 9
DQ 10
DQ 11
V
CC
DQ 44
DQ 45
DQ 46
DQ 47
Vss
NC
NC
DQ 12
DQ 13
DQ 14
DQ 15
Vss
NC
NC
62
64
CKE0
Vcc
CLK0
Vcc
/RAS
/WE
/CS0
NC
61
63
66
/CAS
NC
65
68
67
70
NC
NC
69
72
71
74
CLK1
Vss
NC
73
A0 - A11
: Address Inputs
76
Vss
NC
75
78
NC
77
80
NC
NC
79
[Row: A0 - A11, Column: A0 - A7 ]
BA0 (A13),
82
Vcc
V
CC
81
84
DQ 48
DQ 49
DQ 50
DQ 51
Vss
DQ 16
DQ 17
DQ 18
DQ 19
Vss
83
86
85
88
87
BA1 (A12)
DQ0 - DQ63
CLK0, CLK1
CKE0
: SDRAM Bank Select
: Data Inputs/Outputs
: Clock Input
90
89
92
91
94
DQ 52
DQ 53
DQ 54
DQ 55
Vcc
DQ 20
DQ 21
DQ 22
DQ 23
Vcc
93
96
95
98
97
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
: Clock Enable Input
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
A7
A6
BA0 (A13)
Vss
A8
/CS0
Vss
BA1 (A12)
A11
A9
A10
/RAS
Vcc
Vcc
DQMB6
DQMB7
Vss
DQMB2
DQMB3
Vss
/CAS
/WE
DQ 56
DQ 57
DQ 58
DQ 59
Vcc
DQ 60
DQ 61
DQ 62
DQ 63
Vss
SCL
Vcc
DQ 24
DQ 25
DQ 26
DQ 27
DQMB0 - DQMB7 : DQ Mask Enable
V
CC
SDA
SCL
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
: Ground
DQ 28
DQ 29
DQ 30
DQ 31
Vss
CC
V
SDA
V
CC
SS
V
NC
: No Connection
Data sheet M12386EJ9V0DS00
3
MC-454CB64S, 454CB64LS
Block Diagram
/WE
/CS0
/CS
/WE
/WE
/CS
LDQM
DQ 0
LDQM
DQ 0
DQMB0
DQMB4
DQ 32
DQ 0
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 1
DQ 1
DQ 2
DQ 2
DQ 3
DQ 3
DQ 4
DQ 4
DQ 5
DQ 5
DQ 6
DQ 6
D0
D2
DQ 7
DQ 7
UDQM
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
UDQM
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
DQMB1
DQMB5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 8
DQ 8
/CS
/WE
/WE
/CS
LDQM
DQ 7
LDQM
DQ 7
DQMB2
DQMB6
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQ 6
DQ 6
DQ 5
DQ 5
DQ 4
DQ 4
DQ 3
DQ 3
DQ 2
DQ 2
DQ 1
DQ 1
D1
D3
DQ 0
DQ 0
DQMB3
UDQM
DQ 8
DQMB7
UDQM
DQ 8
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 9
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
SERIAL PD
V
CC
D0 - D3
D0 - D3
C
V
SS
SCL
SDA
A0 A1 A2
CLK : D0, D2
CLK : D1, D3
CLK0
10 Ω
/RAS
/CAS
CKE0
/RAS : D0 - D3
/CAS : D0 - D3
CKE : D0 - D3
A0 - A11
BA0
A0 - A11 : D0 - D3
A13 : D0 - D3
BA1
A12 : D0 - D3
Remark D0 - D3 : µPD4564163 (1M words x 16 bits x 4 banks)
Data sheet M12386EJ9V0DS00
4
MC-454CB64S, 454CB64LS
Electrical Specifications
• All voltages are referenced to V (GND).
SS
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
4
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
–0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
Low level input voltage
VCC + 0.3
+ 0.8
70
V
VIL
V
Operating ambient temperature
TA
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
TYP.
MAX.
30
Unit
pF
Input capacitance
A0 - A11, BA0(A13), BA1(A12), /RAS, /CAS, /WE
CI2
CLK0, CLK1
CKE0
30
CI3
30
CI4
/CS0
30
CI5
DQMB0 - DQMB7
DQ0 - DQ63
10
Data input/output capacitance
CI/O
10
pF
Data sheet M12386EJ9V0DS00
5
MC-454CB64S, 454CB64LS
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
[MC-454CB64S]
Parameter
Symbol
ICC1
Test condition
Burst length = 1, tRC ≥ tRC(MIN.)
MIN. MAX. Unit Notes
Operating current
/CAS latency = 2
/CAS latency = 3
-A80
-A10
360
360
280
460
460
360
4
mA
1
-A10B
-A80
-A10
-A10B
Precharge standby current in
power down mode
ICC2P
CKE ≤ VIL(MAX.), tCK = 15 ns
mA
mA
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
ICC2N
2
Precharge standby current in
non power down mode
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
80
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞ , Input signals are stable.
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
ICC3N
24
20
Active standby current in
power down mode
mA
mA
16
Active standby current in
non power down mode
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
100
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞ , Input signals are stable.
tCK ≥ tCK(MIN.), IO = 0 mA
40
660
520
440
780
660
660
520
520
420
540
540
460
4
Operating current
(Burst mode)
ICC4
ICC5
ICC6
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
-A80
-A10
mA
mA
mA
2
-A10B
-A80
-A10
-A10B
-A80
CBR (Auto) refresh current
tRC ≥ tRC(MIN.)
3
-A10
-A10B
-A80
-A10
-A10B
-Axx
Self refresh current
CKE ≤ 0.2 V
-AxxL
2
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
II(L)
IO(L)
VOH
VOL
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = – 4.0 mA
– 4
–1.5
2.4
+4
µA
µA
V
+1.5
IO = + 4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
Data sheet M12386EJ9V0DS00
6
MC-454CB64S, 454CB64LS
[MC-454CB64LS]
Parameter
Symbol
ICC1
Test condition
Burst length = 1, tRC ≥ tRC(MIN.)
MIN. MAX. Unit Notes
Operating current
/CAS latency = 2 -A10B
/CAS latency = 3 -A10B
280
360
4
mA
mA
mA
1
Precharge standby current in
power down mode
ICC2P
CKE ≤ VIL(MAX.), tCK = 15 ns
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
ICC2N
2
Precharge standby current in
non power down mode
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
80
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞ , Input signals are stable.
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
ICC3N
24
20
Active standby current in
power down mode
mA
mA
16
Active standby current in
non power down mode
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
100
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞ , Input signals are stable.
•
60
440
660
420
460
4
Operating current
(Burst mode)
ICC4
ICC5
ICC6
tCK ≥ tCK(MIN.), IO = 0 mA
/CAS latency = 2 -A10B
/CAS latency = 3 -A10B
/CAS latency = 2 -A10B
/CAS latency = 3 -A10B
-Axx
mA
mA
mA
2
3
CBR (Auto) refresh current
tRC ≥ tRC(MIN.)
Self refresh current
CKE ≤ 0.2 V
-AxxL
2
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
II(L)
IO(L)
VOH
VOL
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = – 4.0 mA
– 4
–1.5
2.4
+4
µA
µA
V
+1.5
IO = + 4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
Data sheet M12386EJ9V0DS00
7
MC-454CB64S, 454CB64LS
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
T
• AC measurements assume t = 1ns.
IH
IL
• Reference level for measuring timing of input signals is 1.4V. Transition times are measured between V and V .
T
IH (MIN.)
IL (MAX.)
and V
• If t is longer than 1ns, reference level for measuring timing of input signals is V
.
• An access time is measured at 1.4 V.
t
CK
t
CH
t
CL
2.0 V
1.4 V
0.8 V
CLK
t
SETUP
t
HOLD
2.0 V
1.4 V
0.8 V
Input
t
AC
t
OH
Output
Data sheet M12386EJ9V0DS00
8
MC-454CB64S, 454CB64LS
Synchronous Characteristics
Parameter
Symbol
tCK3
-80
MAX.
-10
MAX.
-10B
MAX.
(100MHz) ns
Unit Note
MIN.
8
MIN.
10
MIN.
10
Clock cycle time
/CAS latency = 3
(125MHz)
(100MHz)
CK2
10
13
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
t
(100MHz)
(77MHz)
(67MHz)
Access time from CLK
tAC3
6
6
6
7
7
8
1
1
t
AC2
CLK high level width
CLK low level width
Data-out hold time
tCH
tCL
3
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3.5
3.5
3
OH3
OH2
tLZ
1
1
/CAS latency = 3
/CAS latency = 2
t
t
3
Data-out low-impedance time
Data-out high-impedance time
0
/CAS latency = 3
/CAS latency = 2
tHZ3
6
6
6
7
3
7
8
t
HZ2
3
Data-in setup time
Data-in hold time
tDS
tDH
2.5
1
Address setup time
Address hold time
CKE setup time
tAS
2.5
1
tAH
tCKS
tCKH
tCKSP
tCMS
2.5
1
CKE hold time
CKE setup time (Power down exit)
2.5
2.5
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
tCMH
1
1
1
ns
Note 1. Output load
1.4 V
50Ω
Z = 50Ω
Output
50 pF
Data sheet M12386EJ9V0DS00
9
MC-454CB64S, 454CB64LS
Asynchronous Characteristics
Parameter
Symbol
Unit Note
-80
MAX.
-10
MAX.
-10B
MAX.
MIN.
MIN.
MIN.
ACT to REF/ACT command period (Operation)
REF to REF/ACT command period (Refresh)
ACT to PRE command period
tRC
tRC1
tRAS
tRP
70
70
48
20
20
16
8
70
90
ns
ns
70
90
120,000
50
120,000
60
120,000 ns
PRE to ACT command period
20
30
ns
ns
Delay time ACT to READ/WRITE command
ACT(one) to ACT(another) command period
tRCD
tRRD
20
30
20
20
ns
Data-in to PRE command period
/CAS latency = 3 tDPL3
/CAS latency = 2
10
10
ns
t
DPL2
8
10
1CLK+20
1CLK+20
2
10
1CLK+30
1CLK+30
2
ns
Data-in to ACT(REF) command
period (Auto precharge)
/CAS latency = 3 tDAL3 1CLK+20
/CAS latency = 2
ns
t
DAL2 1CLK+20
ns
Mode register set cycle time
Transition time
tRSC
2
CLK
tT
0.5
30
64
1
30
64
1
30
64
ns
Refresh time (4,096 refresh cycles)
tREF
ms
Data sheet M12386EJ9V0DS00
10
MC-454CB64S, 454CB64LS
Serial PD
Byte No.
0
(1/2)
Function Described
Hex
80H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written into
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
3
4
5
6
7
8
9
Total number of bytes of serial PD memory
Fundamental memory type
Number of rows
08H
04H
0CH
08H
01H
40H
00H
01H
80H
A0H
A0H
60H
60H
70H
00H
80H
10H
00H
01H
8FH
04H
06H
01H
01H
00H
0EH
A0H
D0H
F0H
60H
70H
80H
00H
14H
14H
1EH
10H
14H
14H
14H
14H
1EH
30H
32H
3CH
08H
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
256 bytes
SDRAM
12 rows
8 columns
1 bank
64 bits
0
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
LVTTL
8 ns
CL = 3 Cycle time
-A80
-A10
10 ns
10 ns
6 ns
-A10B
-A80
10
CL =3 Access time
-A10
6 ns
-A10B
7 ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
None
Normal
×16
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
None
1 clock
1, 2, 4, 8, F
4 banks
2, 3
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
0
/WE latency supported
0
SDRAM module attributes
SDRAM device attributes : General
CL = 2 Cycle time
CL = 2 Access time
-A80
10 ns
13 ns
15 ns
6 ns
-A10
-A10B
-A80
24
-A10
7 ns
-A10B
8 ns
25-26
27
tRP(MIN.)
-A80
20 ns
20 ns
30 ns
16 ns
20 ns
20 ns
20 ns
20 ns
30 ns
48 ns
50 ns
60 ns
32M bytes
-A10
-A10B
-A80
28
29
30
31
tRRD(MIN.)
-A10
-A10B
-A80
tRCD(MIN.)
-A10
-A10B
-A80
tRAS(MIN.)
-A10
-A10B
Module bank density
Data sheet M12386EJ9V0DS00
11
MC-454CB64S, 454CB64LS
(2/2)
Byte No.
32
Function Described
Hex
20H
20H
00H
10H
10H
00H
20H
20H
00H
10H
10H
00H
00H
12H
12H
01H
DEH
44H
31H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Command and add
-A80
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
2 ns
2 ns
setup time
-A10
-A10B
-A80
33
34
35
Command and add
hold time
1 ns
1 ns
-A10
-A10B
Data signal input setup time -A80
2 ns
2 ns
-A10
-A10B
Data signal input hold time -A80
1 ns
1 ns
-A10
-A10B
36-61
62
SPD revision
-A80
1.2
1.2
1
-A10
-A10B
-A80
63
Checksum for bytes 0 - 62
-A10
-A10B
64-71
72
Manufacture’s JEDEC ID code
Manufacturing location
Manufacture’s P/N
73-90
91-92
93-94
95-98
Revision code
Manufacturing date
Assembly serial number
99-125 Mfg specific
126
Intel specification
-A80
64H
64H
66H
87H
85H
06H
0
0
0
1
1
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
0
0
1
1
0
100 MHz
100 MHz
66 MHz
frequency
-A10
-A10B
-A80
127
Intel specification /CAS
latency support
-A10
-A10B
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348X).
Data sheet M12386EJ9V0DS00
12
MC-454CB64S, 454CB64LS
Package Drawing
144 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Y
M1 (AREA B)
N
R
Q
M
L
M2 (AREA A)
S
A
H
(OPTIONAL HOLES)
U1
U2
C
T
I
B
E
D
A1 (AREA A)
F
ITEM MILLIMETERS
A
67.6
A1
B
67.6±0.15
23.2
C
29.0
D
4.6
detail of A part
D1
D2
E
1.5±0.10
4.0
D2
W
32.8
F
3.7
H
0.8(T.P.)
3.3
I
D1
L
20.0
X
M
M1
M2
N
25.4±0.15
3.4
V
22.0
3.8 MAX.
R2.0
Q
R
4.0±0.10
φ
S
1.8
T
1.0±0.1
U1
U2
V
3.2 MIN.
4.0 MIN.
0.25 MAX.
0.6±0.05
2.55 MIN.
W
X
Y
2.0 MIN.
Data sheet M12386EJ9V0DS00
13
MC-454CB64S, 454CB64LS
[MEMO]
Data sheet M12386EJ9V0DS00
14
MC-454CB64S, 454CB64LS
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data sheet M12386EJ9V0DS00
15
MC-454CB64S, 454CB64LS
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
相关型号：
©2020 ICPDF网 联系我们和版权申明