MC-4R64CEE6C-845 [NEC]
Direct Rambus DRAM RIMM Module 64M-BYTE 32M-WORD x 16-BIT; 直接Rambus DRAM RIMM模块64M - 32M字节，字×16位
| 型号： | MC-4R64CEE6C-845 |
| 厂家： | 
NEC |
| 描述： | Direct Rambus DRAM RIMM Module 64M-BYTE 32M-WORD x 16-BIT |
| 文件： | 总16页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4R64CEE6B, 4R64CEE6C
Direct RambusTM DRAM RIMMTM Module
64M-BYTE (32M-WORD x 16-BIT)
Description
The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for
use in a broad range of applications including computer memory, personal computers, workstations, and other
applications where high bandwidth and low latency are required.
MC-4R64CEE6B, 4R64CEE6C modules consists of four 128M Direct Rambus DRAM (Direct RDRAM™) devices
(µPD488448). These are extremely high-speed CMOS DRAMs organized as 8M words by 16 bits. The use of
Rambus Signaling Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using
conventional system and board design technologies.
Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The separate control and data buses with independent row and column
control yield over 95 % bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions
per device.
Features
• 184 edge connector pads with 1mm pad spacing
• 64 MB Direct RDRAM storage
• Each RDRAM has 32 banks, for 128 banks total on module
• Gold plated contacts
• RDRAMs use Chip Scale Package (CSP)
• Serial Presence Detect support
• Operates from a 2.5 V supply
• Low power and powerdown self refresh modes
• Separate Row and Column buses for higher efficiency
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14537EJ1V1DS00 (1st edition)
Date Published November 1999 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
1999
©
MC-4R64CEE6B, 4R64CEE6C
Order information
Part number
Organization I/O Freq. RAS access time
Package
Mounted devices
MHz
ns
MC-4R64CEE6B - 845
MC-4R64CEE6B - 745
MC-4R64CEE6B - 653
MC-4R64CEE6C - 845
MC-4R64CEE6C - 745
MC-4R64CEE6C - 653
32M x 16
800
711
600
800
711
600
45
45
53
45
45
53
184 edge connector pads RIMM 4 pieces of
with heat spreader
µPD488448FB
Edge connector : Gold plated
FBGA (D2BGATM) package
4 pieces of
µPD488448FF
FBGA (µBGA ) package
2
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
Module Pad Configuration
GND
LDQA8
GND
LDQA6
GND
LDQA4
GND
LDQA2
GND
LDQA0
GND
LCTMN
GND
LCTM
GND
NC
GND
LROW1
GND
LCOL4
GND
LCOL2
GND
LCOL0
GND
LDQB1
GND
LDQB3
GND
B1
B2
GND
LDQA7
GND
LDQA5
GND
LDQA3
GND
LDQA1
GND
LCFM
GND
LCFMN
GND
NC
GND
LROW2
GND
LROW0
GND
LCOL3
GND
LCOL1
GND
LDQB0
GND
LDQB2
GND
A1
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
B8
A8
B9
A9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
LDQB4
GND
LDQB6
GND
LDQB8
GND
LCMD
LDQB5
GND
LDQB7
GND
LSCK
V
CMOS
V
CMOS
SOUT
SIN
CMOS
VCMOS
V
NC
NC
GND
NC
GND
NC
V
DD
V
DD
VDD
VDD
NC
NC
NC
NC
NC
NC
NC
NC
LCFM, LCFMN,
Side B
Side A
RCFM, RCFMN : Clock from master
LCTM, LCTMN,
RCTM, RCTMN : Clock to master
LCMD, RCMD : Serial Command Pad
LROW2 - LROW0,
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
NC
NC
NC
NC
NC
NC
NC
NC
REF
GND
SCL
VDD
SDA
SVDD
SWP
VDD
RSCK
GND
RDQB7
GND
RDQB5
GND
RDQB3
GND
RDQB1
GND
RCOL0
GND
RCOL2
GND
RCOL4
GND
RROW1
GND
NC
GND
RCTM
GND
RCTMN
GND
RDQA0
GND
RDQA2
GND
RDQA4
GND
RDQA6
GND
RDQA8
GND
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
V
REF
V
RROW2 - RROW0 : Row bus
LCOL4 - LCOL0,
GND
SA0
VDD
SA1
SVDD
SA2
RCOL4 - RCOL0 : Column bus
LDQA8 - LDQA0,
VDD
RCMD
GND
RDQA8 - RDQA0 : Data bus A
LDQB8 - LDQB0,
RDQB8
GND
RDQB6
GND
RDQB4
GND
RDQB2
GND
RDQB0
GND
RCOL1
GND
RCOL3
GND
RROW0
GND
RROW2
GND
NC
GND
RCFMN
GND
RCFM
GND
RDQA1
GND
RDQA3
GND
RDQB8 - RDQB0 : Data bus B
LSCK, RSCK : Clock input
SA0 - SA2
SCL, SDA
: Serial Presence Detect Address
: Serial Presence Detect Clock
SIN, SOUT : Serial I/O
DD
SV
: SPD Voltage
SWP
: Serial Presence Detect Write Protect
: Supply voltage for serial pads
: Supply voltage
CMOS
V
DD
V
REF
V
: Logic threshold
GND
NC
: Ground reference
RDQA5
GND
RDQA7
GND
: These pads are not connected
3
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
Module Pad Names
Pad
A1
Signal Name
Pad
B1
Signal Name
GND
Pad
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
Signal Name
NC
Pad
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
Signal Name
NC
GND
LDQA8
GND
A2
B2
LDQA7
GND
NC
NC
A3
B3
NC
NC
A4
LDQA6
GND
B4
LDQA5
GND
NC
NC
A5
B5
VREF
VREF
A6
LDQA4
GND
B6
LDQA3
GND
GND
GND
A7
B7
SCL
SA0
A8
LDQA2
GND
B8
LDQA1
GND
VDD
VDD
A9
B9
SDA
SA1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
LDQA0
GND
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
LCFM
GND
SVDD
SVDD
SWP
SA2
LCTMN
GND
LCFMN
GND
VDD
VDD
RSCK
GND
RCMD
GND
LCTM
GND
NC
GND
RDQB7
GND
RDQB8
GND
NC
LROW2
GND
GND
RDQB5
GND
RDQB6
GND
LROW1
GND
LROW0
GND
RDQB3
GND
RDQB4
GND
LCOL4
GND
LCOL3
GND
RDQB1
GND
RDQB2
GND
LCOL2
GND
LCOL1
GND
RCOL0
GND
RDQB0
GND
LCOL0
GND
LDQB0
GND
RCOL2
GND
RCOL1
GND
LDQB1
GND
LDQB2
GND
RCOL4
GND
RCOL3
GND
LDQB3
GND
LDQB4
GND
RROW1
GND
RROW0
GND
LDQB5
GND
LDQB6
GND
NC
RROW2
GND
LDQB7
GND
LDQB8
GND
GND
RCTM
GND
NC
LSCK
VCMOS
SOUT
VCMOS
NC
LCMD
VCMOS
SIN
GND
RCTMN
GND
RCFMN
GND
VCMOS
NC
RDQA0
GND
RCFM
GND
GND
GND
RDQA2
GND
RDQA1
GND
NC
NC
VDD
VDD
RDQA4
GND
RDQA3
GND
VDD
VDD
NC
NC
RDQA6
GND
RDQA5
GND
NC
NC
NC
NC
RDQA8
GND
RDQA7
GND
NC
NC
4
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
Module Connector Pad Description
(1/2)
Signal
I/O
–
Type
–
Description
GND
Ground reference for RDRAM core and interface. 72 PCB connector pads.
LCFM
I
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
LCFMN
I
RSL
VCMOS
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
LCMD
I
Serial Command used to read from and write to the control registers. Also used
for power management.
LCOL4..LCOL0
LCTM
I
I
Column bus. 5-bit bus containing control and address information for column
accesses.
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
LCTMN
I
RSL
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
LDQA8..LDQA0
LDQB8..LDQB0
I/O
I/O
RSL
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information for row accesses.
RSL
LROW2..LROW0
LSCK
I
I
RSL
VCMOS
Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
NC
–
–
These pads are not connected. These 24 connector pads are reserved for future
use.
RCFM
I
RSL
RSL
VCMOS
RSL
RSL
RSL
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
RCFMN
I
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
RCMD
I
Serial Command Input used to read from and write to the control registers. Also
used for power management.
RCOL4..RCOL0
RCTM
I
Column bus. 5-bit bus containing control and address information for column
accesses.
I
I
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
RCTMN
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
RDQA8..RDQA0
I/O
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM
devices.
RDQB8..RDQB0
RROW2..RROW0
I/O
I
RSL
RSL
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM
devices.
Row bus. 3-bit bus containing control and address information for row accesses.
5
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
(2/2)
Signal
I/O
I
Type
Description
RSCK
VCMOS
Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
SA0
SA1
SA2
SCL
SDA
SIN
I
SVDD
SVDD
SVDD
SVDD
SVDD
VCMOS
Serial Presence Detect Address 0.
I
I
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
I
I/O
I/O
Serial Presence Detect Data (Open Collector I/O).
Serial I/O for reading from and writing to the control registers. Attaches to SIO0
of the first RDRAM on the module.
SOUT
I/O
VCMOS
Serial I/O for reading from and writing to the control registers. Attaches to SIO1
of the last RDRAM on the module.
SVDD
SWP
—
I
—
SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2.
SVDD
Serial Presence Detect Write Protect (active high). When low, the SPD can be
written as well as read.
VCMOS
VDD
—
—
—
—
—
—
CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.
Supply voltage for the RDRAM core and interface logic.
Logic threshold reference voltage for RSL signals.
VREF
6
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
Block Diagram
SIO 0
SIO 1
SCK
U1
CMD
V
REF
SIO 0
SIO 1
SCK
U2
CMD
VREF
SIO 0
SIO 1
SCK
U3
CMD
VREF
SIO 0
SIO 1
SCK
U4
CMD
V
REF
SERIAL PD
V
DD
2 per
RDRAM
0.1 µF
SVDD
SVDD
0.1 µF
V
CC
SCL
SCL
SDA
A2
SDA
U0
SWP
WP
A0
1 per
VREF
V
CMOS
1 per
2 RDRAMs
0.1 µF
A1
2 RDRAMs
Plus one
Near Connector
0.1 µF
47kΩ
SA0 SA1 SA2
Remarks 1. Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain.
2. See Serial Presence Detection Specification for information on the SPD device and its contents.
7
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
Electrical Specification
Absolute Maximum Ratings
Symbol
Parameter
MIN.
−0.3
−0.5
−50
MAX.
VDD + 0.3
VDD + 1.0
+100
Unit
V
VI,ABS
Voltage applied to any RSL or CMOS signal pad with respect to GND
Voltage on VDD with respect to GND
VDD,ABS
TSTORE
V
Storage temperature
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Recommended Electrical Conditions
Symbol
VDD
Parameter and conditions
Supply voltage
MIN.
MAX.
Unit
V
2.50 − 0.13
2.5 − 0.13
1.8 − 0.1
1.4 − 0.2
VREF − 0.5
VREF + 0.2
−0.3
2.50 + 0.13
2.5 + 0.25
1.8 + 0.2
1.4 + 0.2
VREF − 0.2
VREF + 0.5
0.5VCMOS − 0.25
VCMOS + 0.3
0.3
VCMOS
CMOS I/O power supply at pad
2.5V controllers
1.8V controllers
V
VREF
Reference voltage
V
V
VIL
RSL input low voltage
VIH
RSL input high voltage
V
VIL,CMOS
VIH,CMOS
VOL,CMOS
VOH,CMOS
IREF
CMOS input low voltage
V
CMOS input high voltage
0.5VCMOS+0.25
—
V
CMOS output low voltage, IOL,CMOS = 1 mA
CMOS output high voltage, IOH,CMOS = −0.25 mA
VREF current, VREF,MAX
V
—
VCMOS − 0.3
−40.0
V
+40.0
µA
µA
µA
ISCK,CMD
ISIN,SOUT
CMOS input leakage current, (0 ≤ VCMOS ≤ VDD)
CMOS input leakage current, (0 ≤ VCMOS ≤ VDD)
−40.0
+40.0
−10.0
+10.0
8
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
AC Electrical Specifications
Symbol
TYP.
28
MAX.
30.8
1.25
1.25
1.25
+21
Unit
Parameter and Conditions
MIN.
25.2
Z
Module Impedance
Ω
Average clock delay from finger to finger of all RSL clock nets
(CTM, CTMN,CFM, and CFMN)
-845
-745
-653
ns
TPD
∆TPD
Propagation delay variation of RSL signals with respect to TPD Note1,2
−21
ps
ps
∆TPD-CMOS Propagation delay variation of SCK and CMD signals with respect to
−100
+100
an average clock delay Note1
Attenuation Limit
-845
-745
-653
-845
-745
-653
-845
-745
-653
-845
-745
-653
12
12
8
%
%
%
Ω
Vα/VIN
VXF/VIN
VXB/VIN
RDC
Forward crosstalk coefficient
2
(300ps input rise time 20% - 80%)
2
2
crosstalk coefficient
1.5
1.5
1.5
0.6
0.6
0.6
Backward
(300ps input rise time 20% - 80%)
DC Resistance Limit
Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
PD
“Adjusted ∆T Specification” table.
Adjusted ∆TPD Specification
Symbol
Parameter and conditions
Adjusted MIN./MAX.
Absolute
Unit
ps
MIN.
−30
MAX.
+30
+/ [17+(18*N* Z0)] Note
∆TPD
Propagation delay variation of RSL signals with respect to TPD
−
∆
Note N = Number of RDRAM devices installed on the RIMM module.
%
∆Z0 = delta Z0 = (MAX. Z0 − MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
9
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
RIMM Module Current Profile
RIMM module power conditions
IDD
MAX.
TBD
TBD
TBD
TBD
TBD
TBD
Unit
mA
mA
mA
mA
mA
mA
One RDRAM in Read , balance in NAP mode
One RDRAM in Read , balance in Standby mode
One RDRAM in Read , balance in Active mode
One RDRAM in Write, balance in NAP mode
One RDRAM in Write, balance in Standby mode
One RDRAM in Write, balance in Active mode
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
10
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
Timing Parameters
The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM data sheet
(µPD488448, 488488) for detailed timing diagrams.
Para-
meter
Description
MIN.
-745
28
MAX.
—
Units
-845
28
-653
28
tRC
Row Cycle time of RDRAM banks - the interval between ROWA packets with
ACT commands to the same bank.
tCYCLE
tCYCLE
tCYCLE
Note 2
tRAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT
command and next ROWR packet with PRERNote 1 command to the same bank.
20
8
20
8
20
8
64 s
µ
tRP
Row Precharge time of RDRAM banks - the interval between ROWR packet with
PRERNote 1 command and next ROWA packet with ACT command to the same
bank.
—
tPP
Precharge-to-precharge time of RDRAM device - the interval between
successive ROWR packets with PRERNote 1 commands to any banks of the
same device.
8
8
8
—
tCYCLE
tRR
RAS-to-RAS time of RDRAM device - the interval between successive ROWA
packets with ACT commands to any banks of the same device.
8
9
8
7
8
7
—
—
tCYCLE
tRCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to
COLC packet with RD or WR command. Note - the RAS-to-CAS delay seen
by the RDRAM core (tRCD-C) is equal to tRCD-C = 1 + tRCD because of differences
in the row and column paths through the RDRAM interface.
tCYCLE
tCAC
CAS Access delay - the interval from RD command to Q read data. The
equation for tCAC is given in the TPARM register.
8
8
8
12
tCYCLE
tCWD
tCC
CAS Write Delay - interval from WR command to D write data.
6
4
6
4
6
4
6
tCYCLE
tCYCLE
CAS-to-CAS time of RDRAM bank – the interval between successive COLC
commands.
—
tPACKET
tRTR
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
8
4
8
4
8
4
tCYCLE
tCYCLE
Interval from COLC packet with WR command to COLC packet which causes
retire, and to COLM packet with bytemask.
—
tOFFP
The interval (offset) from COLC packet with RDA command, or from COLC
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
the equivalent ROWR packet with PRER. The equation for tOFFP is given in the
TPARM register.
4
4
4
4
tCYCLE
tRDP
Interval from last COLC packet with RD command to ROWR packet with
PRER.
4
4
4
4
4
4
—
—
tCYCLE
tRTP
Interval from last COLC packet with automatic retire command to ROWR
packet with PRER.
tCYCLE
Notes 1. Or equivalent PREC or PREX command.
2. This is a constraint imposed by the core, and is therefore in units of ms rather than tCYCLE.
11
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
Package Drawings
[MC-4R64CEE6B]
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE)
EEPROM
A (AREA B)
R
128 M Direct RDRAM
M1 (AREA B)
V
T
P
S
A
O N
M
Q
M2 (AREA A)
L
B
K
H
I
J
G
D
B
E
F
C
A1 (AREA A)
ITEM MILLIMETERS
A
133.35 TYP.
133.35±0.13
55.175
A1
B
B1
C
1.00±0.10
11.50
detail of A part
detail of B part
C1
C1
D
3.00±0.10
45.00
32.00
E
W
R1.00
R1.00
45.00
F
5.675
G
H
I
47.625
25.40
Y
B1
Z
47.625
J
X
6.35
K
1.00 TYP.
31.75±0.13
11.97
L
M
M1
M2
N
O
P
19.78
29.21
17.78
4.00±0.10
R 2.00
Q
R
S
3.00±0.10
φ
2.44
T
1.27±0.10
2.24 MAX.
0.80±0.10
2.99
V
W
X
Y
0.15
Z
2.00±0.10
12
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
[MC-4R64CEE6C]
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE)
EEPROM
A (AREA B)
R
128 M Direct RDRAM
M1 (AREA B)
V
T
P
S
A
O N
M
Q
M2 (AREA A)
L
B
K
H
I
J
G
D
B
E
F
C
A1 (AREA A)
ITEM MILLIMETERS
A
133.35 TYP.
133.35±0.13
55.175
A1
B
B1
C
1.00±0.10
11.50
detail of A part
detail of B part
C1
C1
D
3.00±0.10
45.00
32.00
E
W
R1.00
R1.00
45.00
F
5.675
G
H
I
47.625
25.40
Y
B1
Z
47.625
J
X
6.35
K
1.00 TYP.
31.75±0.13
11.97
L
M
M1
M2
N
O
P
19.78
29.21
17.78
4.00±0.10
R 2.00
Q
R
S
3.00±0.10
φ
2.44
T
1.27±0.10
2.43 MAX.
0.80±0.10
2.99
V
W
X
Y
0.15
Z
2.00±0.10
13
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
★
[MC-4R64CEE6B, MC-4R64CEE6C]
184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE)
A
B
E
F
G
H
C
D
C
Pad A1
Pad A92
DESCRIPTION
PCB length
ITEM
MIN.
TYP.
MAX.
UNIT
mm
A
B
C
D
E
F
133.22 133.35 133.48
PCB height for 1.25" RIMM Module
31.62
31.75
45.00
55.175
17.78
1.27
-
31.88
45.05
-
mm
mm
mm
mm
mm
mm
mm
Center-center pad width from pad A1 to A46,
A47 to A92, B1 to B46 or B47 to B92
44.95
Spacing from PCB left edge to connector key notch
-
Spacing from contact pad PCB edge
to side edge retainer notch
PCB thickness
-
-
1.17
1.37
3.09
4.46
Heat spreader thickness from PCB surface (one side) to
heat spreader top surface
G
H
-
-
RIMM thickness
-
14
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
15
Preliminary Data Sheet M14537EJ1V1DS00
MC-4R64CEE6B, 4R64CEE6C
Rambus, RDRAM and the Rambus Logo are registered trademarks of Rambus Inc.
DirectRambus, DirectRDRAM, RIMM, RModule and RSocket are trademarks of Rambus Inc.
µBGA is a registered trademark of Tessera Inc.
D2BGA is a trademark of NEC Corporation.
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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