NP32N055HDE [NEC]
Power Field-Effect Transistor, 32A I(D), 55V, 0.029ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, MP-3, 3 PIN;
| 型号： | NP32N055HDE |
| 厂家： | 
NEC |
| 描述： | Power Field-Effect Transistor, 32A I(D), 55V, 0.029ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, MP-3, 3 PIN 开关 脉冲 晶体管 |
| 文件： | 总7页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP32N055HDE, NP32N055IDE, NP32N055SDE
SWITCHING
N-CHANNEL POWER MOSFET
DESCRIPTION
ORDERING INFORMATION
These products are N-channel MOS Field Effect Transistor
designed for high current switching applications.
PART NUMBER
PACKAGE
NP32N055HDE
TO-251 (JEITA) / MP-3
TO-252 (JEITA) / MP-3Z
TO-252 (JEDEC) / MP-3ZK
Note
NP32N055IDE
NP32N055SDE
FEATURES
• Channel temperature 175 degree rated
• Super low on-state resistance
Note Not for new design.
RDS(on)1 = 24 mΩ MAX. (VGS = 10 V, ID = 16 A)
RDS(on)2 = 29 mΩ MAX. (VGS = 5.0 V, ID = 16 A)
• Low Ciss : Ciss = 1300 pF TYP.
(TO-251)
(TO-252)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
55
20
V
V
32
A
100
A
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
66
W
W
°C
°C
A
PT2
1.2
Tch
175
Storage Temperature
Tstg
–55 to +175
28 / 21 / 8
7.8 / 44 / 64
Single Avalanche Current Note2
Single Avalanche EnergyNote2
IAS
EAS
mJ
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, RG = 25 Ω , VGS = 20 → 0 V
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Rth(ch-C)
2.27
125
°C/W
°C/W
Channel to Ambient Thermal Resistance
Rth(ch-A)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No.
D15309EJ2V0DS00 (2nd edition)
The mark
shows major revised points.
Date Published July 2005 NS CP(K)
Printed in Japan
2001, 2005
NP32N055HDE, NP32N055IDE, NP32N055SDE
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
µA
nA
V
IDSS
VDS = 55 V, VGS = 0 V
10
100
2.5
IGSS
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 µA
VDS = 10 V, ID = 16 A
VGS = 10 V, ID = 16 A
VGS = 5.0 V, ID = 16 A
VGS = 4.5 V, ID = 16 A
VDS = 25 V
Gate to Source Threshold Voltage
VGS(th)
| yfs |
RDS(on)1
RDS(on)2
RDS(on)3
Ciss
1.5
8
2
Note
Forward Transfer Admittance
16
19
22
24
S
Note
mΩ
mΩ
mΩ
pF
pF
pF
ns
Drain to Source On-state Resistance
24
29
33
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
1300 2000
Coss
VGS = 0 V
180
90
14
8
270
160
31
Crss
f = 1 MHz
td(on)
tr
VDD = 28 V, ID = 16 A
VGS = 10 V
20
ns
RG = 1 Ω
Turn-off Delay Time
Fall Time
td(off)
tf
40
7.4
27
15
5
81
ns
19
ns
Total Gate Charge
QG1
VDD = 44 V, VGS = 10 V, ID = 32 A
VDD = 44 V
41
nC
nC
nC
nC
V
QG2
23
Gate to Source Charge
Gate to Drain Charge
QGS
VGS = 5.0 V
QGD
VF(S-D)
trr
ID = 32 A
9
Note
Body Diode Forward Voltage
IF = 32 A, VGS = 0 V
IF = 32 A, VGS = 0 V
di/dt = 100 A/µs
1.0
41
58
Reverse Recovery Time
Reverse Recovery Charge
ns
Qrr
nC
Note Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
D.U.T.
V
GS
R
L
RG
= 25 Ω
90%
V
GS
Wave Form
V
GS
10%
0
R
G
PG.
GS = 20 → 0 V
PG.
50 Ω
V
DD
VDD
V
VDS
90%
90%
V
DS
V
0
GS
BVDSS
10% 10%
V
DS
Wave Form
0
IAS
VDS
τ
ID
t
d(on)
t
r
t
d(off)
tf
VDD
t
on
toff
τ = 1 µs
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
= 2 mA
IG
RL
PG.
50 Ω
VDD
2
Data Sheet D15309EJ2V0DS
NP32N055HDE, NP32N055IDE, NP32N055SDE
TYPICAL CHARACTERISTICS (TA = 25°C)
Figure2. TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
Figure1. DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
70
60
50
40
30
20
10
0
100
80
60
40
20
0
0
25 50 75 100 125 150 175 200
0
25 50 75 100 125 150 175 200
- Case Temperature - ˚C
TC - Case Temperature - ˚C
TC
Figure4. SINGLE AVALANCHE ENERGY
DERATING FACTOR
Figure3. FORWARD BIAS SAFE OPERATING AREA
1000
70
60
50
40
64 mJ
ID(pulse)
100
1 ms
I
D(DC)
44 mJ
PowerDDiCssipation
Limited
I
AS = 8 A
21 A
10
28 A
30
20
10
0
1
7.8 mJ
TC
= 25˚C
Single Pulse
0.1
0.1
1
10
100
25
50
75
100
125
150
175
V
DS
-
Drain to Source Voltage - V
Starting Tch - Starting Channel Temperature - ˚C
Figure5. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
R
th(ch-A) = 125˚C/W
th(ch-C) = 2.27˚C/W
100
10
R
1
0.1
0.01
Single Pulse
T
C
= 25˚C
µ
10
1 m
10 m
100 m
1
10
100
1000
100
µ
PW - Pulse Width - s
3
Data Sheet D15309EJ2V0DS
NP32N055HDE, NP32N055IDE, NP32N055SDE
Figure7. DRAIN CURRENT vs.
Figure6. FORWARD TRANSFER CHARACTERISTICS
DRAIN TO SOURCE VOLTAGE
120
100
80
100
Pulsed
Pulsed
V
GS = 10 V
10
TA
= −55˚C
25˚C
75˚C
150˚C
175˚C
5.0 V
60
1
0.1
4.5 V
40
20
V
DS = 10 V
0
0.01
1
2
3
4
5
6
7
8
0
1.0
2.0
3.0
4.0
5.0 6.0
VGS - Gate to Source Voltage - V
VDS - Drain to Source Voltage - V
Figure9. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
Figure8. FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
40
100
Pulsed
DS = 10 V
Pulsed
V
30
10
T
A
= 175˚C
75˚C
I = 16 A
D
20
10
0
1
0.1
25˚C
−55˚C
0.01
0.01
0
0.1
1
10
100
2
4
6
8
10 12 14 16 18 20
VGS - Gate to Source Voltage - V
ID - Drain Current - A
Figure10. DRAIN TO SOURCE ON-STATE
Figure11. GATE TO SOURCE THRESHOLD VOLTAGE vs.
CHANNEL TEMPERATURE
RESISTANCE vs. DRAIN CURRENT
80
70
60
50
40
30
20
10
0
3.0
Pulsed
V
GµS
I
D
D=S =25V0
A
2.0
V
GS = 10 V
5.0 V
4.5 V
1.0
0
0.1
1
10
100
−50
0
50
100
150
ID - Drain Current - A
Tch - Channel Temperature - ˚C
4
Data Sheet D15309EJ2V0DS
NP32N055HDE, NP32N055IDE, NP32N055SDE
Figure13. SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
Figure12. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
60
1000
100
Pulsed
50
V
GS = 4.5 V
5.0 V
40
30
20
VGS = 10 V
10 V
10
VGS = 0 V
1
10
0
I
D
= 16 A
0.1
100
150
0
50
−50
0
0.5
1.0
1.5
Tch - Channel Temperature - ˚C
VSD
- Source to Drain Voltage - V
Figure14. CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
Figure15. SWITCHING CHARACTERISTICS
1000
100
10000
V
GS = 0 V
f = 1 MHz
Ciss
tf
1000
td(off)
td(on)
Coss
10
1
100
10
tr
C
rss
0.1
1
10
100
0.1
1
10
100
ID
- Drain Current - A
VDS - Drain to Source Voltage - V
Figure16. REVERSE RECOVERY TIME vs.
DRAIN CURRENT
Figure17. DYNAMIC INPUT/OUTPUT CHARACTERISTICS
80
16
14
12
10
8
1000
100
di/dt = 100 A/µs
GS = 0 V
V
60
V
GS
V
DD = 44 V
28 V
11 V
40
20
6
10
1
4
VDS
2
I
D
= 32 A
28 32
0
0
4
8
12 16 20 24
- Gate Charge - nC
0.1
1.0
10
100
Q
G
IF
- Drain Current - A
5
Data Sheet D15309EJ2V0DS
NP32N055HDE, NP32N055IDE, NP32N055SDE
PACKAGE DRAWINGS (Unit: mm)
1) TO-251 (JEITA) / MP-3
2) TO-252 (JEITA) / MP-3Z
2.3 0.2
6.5 0.2
2.3 0.2
6.5 0.2
5.0 0.2
4
0.5 0.1
5.0 0.2
0.5 0.1
4
1
2
3
DESIGN
1
2
3
1.1 0.2
NEW
1.1 0.2
0.9 MAX.
0.8 MAX.
+0.2
−0.1
+0.2
0.5
0.5
−0.1
2.3 TYP.
2.3 TYP.
0.8 TYP.
2.3 TYP.
2.3 TYP.
FOR
1. Gate
2. Drain
3. Source
1. Gate
2. Drain
3. Source
4. Fin (Drain)
NOT
4. Fin (Drain)
3) TO-252 (JEDEC) / MP-3ZK
2.3 0.1
6.5 0.2
5.1 TYP.
4.3 MIN.
0.5 0.1
No Plating
4
EQUIVALENT CIRCUIT
Drain
1
2
3
Body
Diode
Gate
No Plating
0.76 0.12
1.14 MAX.
0 to 0.25
0.5 0.1
2.3 2.3
1.0
Source
1. Gate
2. Drain
3. Source
4. Fin (Drain)
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade
the device operation. Steps must be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred.
6
Data Sheet D15309EJ2V0DS
NP32N055HDE, NP32N055IDE, NP32N055SDE
•
The information in this document is current as of July, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
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appear in this document.
•
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•
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