NP50N055SUG [NEC]
Power Field-Effect Transistor, 50A I(D), 55V, 0.015ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, TO-252, MP-3ZK, 3 PIN;
| 型号： | NP50N055SUG |
| 厂家： | 
NEC |
| 描述： | Power Field-Effect Transistor, 50A I(D), 55V, 0.015ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, TO-252, MP-3ZK, 3 PIN 开关 脉冲 晶体管 |
| 文件： | 总4页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT INFORMATION
MOS FIELD EFFECT TRANSISTOR
NP50N055SUG
SWITCHING
N-CHANNEL POWER MOS FET
ORDERING INFORMATION
PART NUMBER
DESCRIPTION
The NP50N055SUG is N-channel MOS Field Effect
Transistor designed for high current switching applications.
PACKAGE
NP50N055SUG
TO-252(MP-3ZK)
FEATURES
• Channel temperature 175 degree rating
• Super low on-state resistance:
RDS(on) = 15 mΩ MAX. (VGS = 10 V, ID = 25 A)
• Low Ciss: Ciss = 2000 pF TYP.
(TO-252)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
55
±20
±50
±200
63
V
V
A
A
W
W
°C
PT2
Tch
1.2
175
Storage Temperature
Tstg
IAR
EAR
–55 to +175
T.B.D.
°C
A
mJ
Repetitive Avalanche Current Note2
Repetitive Avalanche Energy Note2
T.B.D.
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1%
2. Starting Tch = 25°C, VDD = 28 V, RG = 25 Ω, VGS = 20 → 0 V
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
2.4
125
°C/W
°C/W
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are availabe in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No.
D16865EJ1V0PM00
Date Published January 2004 CP(K)
Printed in Japan
2004
NP50N055SUG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
SYMBOL
TEST CONDITIONS
DS = 55 V, VGS = 0 V
GS = ±20 V, VDS = 0 V
MIN. TYP. MAX. UNIT
10 µA
±100 nA
I
DSS
GSS
GS(off)
V
V
V
V
V
V
V
I
V
DS = VGS, I
D
= 250µA
= 25 A
2.0
3.0
4.0
V
S
Forward Transfer Admittance
Drain to Source On-state Resistance
Input Capacitance
| yfs
|
DS = 10V, I
D
T.B.D.
R
DS(on)
GS = 10 V, I
DS = 25 V
GS = 0 V
D
= 25 A
12
15
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
C
iss
2000
250
Output Capacitance
Coss
Reverse Transfer Capacitance
Turn-on Delay Time
C
rss
f = 1 MHz
DD = 28 V
155
t
d(on)
V
T.B.D.
T.B.D.
T.B.D.
T.B.D.
Rise Time
t
r
I
D
= 25 A
Turn-off Delay Time
t
d(off)
V
GS = 10 V
Fall Time
t
f
RG = 0 Ω
Total Gate Charge
QG
V
V
DD = 44 V
GS = 10 V
T.B.D.
T.B.D.
T.B.D.
1.0
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Q
GS
GD
Q
I
I
I
D
= 50 A
V
F(S-D)
rr
rr
F
F
= 50 A, VGS = 0 V
= 50 A, VGS = 0 V
1.5
t
T.B.D.
T.B.D.
ns
nC
Q
di/dt = 100 A/µs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
D.U.T.
V
V
GS
R
L
RG
= 25 Ω
90%
V
GS
Wave Form
V
GS
10%
0
R
G
PG.
GS = 20 → 0 V
PG.
50 Ω
V
DD
V
DD
V
DS
90%
90%
V
DS
V
0
GS
BVDSS
10% 10%
V
DS
Wave Form
0
I
AS
V
DS
τ
I
D
t
d(on)
t
r
t
d(off)
tf
V
DD
t
on
toff
τ = 1 µs
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
= 2 mA
I
G
RL
PG.
50 Ω
V
DD
2
Preliminary Product Information D16865EJ1V0PM00
NP50N055SUG
PACKAGE DRAWINGS (Unit: mm)
TO-252(MP-3ZK)
2.3±0.1
6.5±0.2
5.1±0.3
4.3 MIN.
0.5±0.1
No Plating
4
1
2
3
No Plating
1.14 MAX.
0.77±0.1
0.03 to 0.25
2.3 2.3
0.5±0.1
1.0
1.Gate
2.Drain
3.Source
4.Fin (Drain)
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Source
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it once, when it has occurred.
3
Preliminary Product Information D16865EJ1V0PM00
NP50N055SUG
•
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
•
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
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rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
•
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(1)
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defined above).
M5 02. 11-1
相关型号：
NP50P04SDG-E1-AY
Power Field-Effect Transistor, 50A I(D), 40V, 0.015ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, LEAD FREE, MP-3ZK, 3 PIN
NEC
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