NP50P04KDG-E1-AY [NEC]
MOS FIELD EFFECT TRANSISTOR; MOS场效应
| 型号： | NP50P04KDG-E1-AY |
| 厂家： | 
NEC |
| 描述： | MOS FIELD EFFECT TRANSISTOR |
| 文件： | 总7页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP50P04KDG
SWITCHING
P-CHANNEL POWER MOSFET
DESCRIPTION
The NP50P04KDG is P-channel MOS Field Effect Transistor designed for high current switching applications.
<R> ORDERING INFORMATION
PART NUMBER
LEAD PLATING
Pure Sn (Tin)
PACKING
PACKAGE
NP50P04KDG-E1-AY Note
NP50P04KDG-E2-AY Note
Tape 800 p/reel
TO-263 (MP-25ZK)
Note Pb-free (This product does not contain Pb in external electrode.)
FEATURES
(TO-263)
• Super low on-state resistance
RDS(on)1 = 10 mΩ MAX. (VGS = −10 V, ID = −25 A)
RDS(on)2 = 15 mΩ MAX. (VGS = −4.5 V, ID = −25 A)
• Low input capacitance
Ciss = 5100 pF TYP.
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
−40
m20
V
V
m50
A
m150
90
A
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
W
W
°C
°C
A
PT2
1.8
Tch
175
Storage Temperature
Tstg
−55 to +175
37
Single Avalanche Current Note2
Single Avalanche Energy Note2
IAS
EAS
136
mJ
Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, VDD = −30 V, RG = 25 Ω, VGS = −20 → 0 V
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
1.67
83.3
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D18688EJ3V0DS00 (3rd edition)
Date Published May 2007 NS CP(K)
Printed in Japan
2007
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
NP50P04KDG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
−10
UNIT
μA
nA
V
IDSS
VDS = −40 V, VGS = 0 V
IGSS
VGS = m20 V, VDS = 0 V
VDS = −10 V, ID = −1 mA
VDS = −10 V, ID = −25 A
VGS = −10 V, ID = −25 A
VGS = −4.5 V, ID = −25 A
VDS = −10 V,
m100
−2.5
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(th)
| yfs |
RDS(on)1
RDS(on)2
Ciss
−1.0
−1.6
30
15
S
7.9
9.8
5100
790
440
20
10
15
mΩ
mΩ
pF
pF
pF
ns
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
VGS = 0 V,
f = 1 MHz
td(on)
tr
VDD = −20 V, ID = −25 A,
VGS = −10 V,
45
ns
Turn-off Delay Time
Fall Time
td(off)
tf
RG = 0 Ω
405
230
100
13
ns
ns
Total Gate Charge
QG
VDD = −32 V,
nC
nC
nC
V
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage Note
Reverse Recovery Time
Reverse Recovery Charge
QGS
QGD
VF(S-D)
trr
VGS = −10 V,
ID = −50 A
42
IF = −50 A, VGS = 0 V
IF = −50 A, VGS = 0 V,
di/dt = −100 A/μs
0.95
48
1.5
ns
Qrr
66
nC
Note Pulsed test PW ≤ 350 μs, Duty Cycle ≤ 2%
TEST CIRCUIT 2 SWITCHING TIME
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
D.U.T.
L
RG
= 25 Ω
50 Ω
V
V
GS(−)
R
L
90%
V
GS
V
GS
10%
0
V
DD
PG.
GS = −20 → 0 V
Wave Form
RG
V
PG.
V
DD
DS(−)
90%
90%
−
BVDSS
I
AS
V
DS
V
0
GS(−)
V
DS
10% 10%
V
DS
0
Wave Form
I
D
t
d(on)
t
r
t
d(off)
t
f
V
DD
τ
t
on
t
off
τ = 1
μ
s
Starting Tch
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= −2 mA
RL
PG.
V
DD
50 Ω
2
Data Sheet D18688EJ3V0DS
NP50P04KDG
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
120
100
80
60
40
20
0
120
100
80
60
40
20
0
0
25 50 75 100 125 150 175 200
0
25 50 75 100 125 150 175 200
Tch - Channel Temperature - °C
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
-1000
-100
-10
I
D(pulse)
I
D(DC)
DC
R
DS(on) Limited
(VGS = −10 V)
-1
-0.1
-0.01
T
C
= 25°C
Single Pulse
-0.1
-1
-10
-100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
10
Rth(ch-A) = 83.3°C/Wi
1
Rth(ch-C) = 1.67°C/Wi
0.1
0.01
Single Pulse
100 1000
100 μ
1 m
10 m
100 m
1
10
PW - Pulse Width - s
3
Data Sheet D18688EJ3V0DS
NP50P04KDG
DRAIN CURRENT vs.
FORWARD TRANSFER CHARACTERISTICS
DRAIN TO SOURCE VOLTAGE
-150
-100
-50
0
-1000
-100
-10
V
DS = −10 V
VGS = −10 V
Pulsed
−4.5 V
T
ch = −55°C
−25°C
25°C
-1
-0.1
75°C
125°C
150°C
175°C
-0.01
-0.001
Pulsed
0
-1
-2
-3
-4
-5
0
-1
-2
-3
VGS - Gate to Source Voltage - V
VDS - Drain to Source Voltage - V
GATE TO SOURCE THRESHOLD VOLTAGE vs.
CHANNEL TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
-3
100
10
1
T
ch = −55°C
−25°C
-2.5
-2
25°C
75°C
125°C
150°C
175°C
-1.5
-1
-0.5
0
V
DS = −10 V
= −1 mA
V
DS = −10 V
I
D
Pulsed
0.1
-75
-25
25
75
125
175
225
-0.1
-1
-10
-100
Tch - Channel Temperature - °C
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
40
30
20
30
I
D
= −50 A
−25 A
−10 A
20
10
0
V
GS = −4.5 V
−10 V
10
0
Pulsed
-1000
Pulsed
-1
-10
-100
0
-5
-10
-15
-20
ID - Drain Current - A
VGS - Gate to Source Voltage - V
4
Data Sheet D18688EJ3V0DS
NP50P04KDG
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
20
10000
1000
100
C
iss
V
GS = −4.5 V
15
10
5
C
oss
C
rss
−10 V
I = −25 A
Pulsed
D
V
GS = 0 V
f = 1 MHz
0
10
-75
-25
25
75
125
175
225
-0.1
-1
-10
-100
Tch - Channel Temperature - °C
VDS - Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
td(off)
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
-40
1000
100
10
-12
-9
-6
-3
0
V
DD
=
−
−
−
32 V
20 V
8 V
-30
-20
-10
0
t
t
f
d(on)
VGS
t
r
V
V
DD = −20 V
GS = −10 V
RG = 0 Ω
V
DS
D
I = −50 A
1
0
20
40
60
80
100
120
-0.1
-1
-10
-100
QG - Gate Charge - nC
ID - Drain Current - A
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
-1000
-100
-10
1000
100
10
1
0 V
V
GS = −10 V
-1
-0.1
-0.01
di/dt = −100 A/μs
V
GS = 0 V
Pulsed
1.5
-0.1
-1
-10
-100
0
0.5
1
IF - Diode Forward Current - A
VF(S-D) - Source to Drain Voltage - V
5
Data Sheet D18688EJ3V0DS
NP50P04KDG
PACKAGE DRAWING (Unit: mm)
TO-263 (MP-25ZK)
10.0±0.3
4.45±0.2
1.3±0.2
No plating
7.88 MIN.
4
0.025 to
0.25
0.75±0.2
2.54
0.25
1
2
3
1.Gate
2.Drain
3.Source
4.Fin (Drain)
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Source
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as
possible, and quickly dissipate it once, when it has occurred.
6
Data Sheet D18688EJ3V0DS
NP50P04KDG
•
The information in this document is current as of May, 2007. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
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•
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M8E 02. 11-1
相关型号：
NP50P04SDG-E1-AY
Power Field-Effect Transistor, 50A I(D), 40V, 0.015ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, LEAD FREE, MP-3ZK, 3 PIN
NEC
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