UPA1819 [NEC]

P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING; P沟道MOS场效应晶体管切换


型号：	UPA1819
厂家：	NEC
描述：	P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING P沟道MOS场效应晶体管切换晶体晶体管场效应晶体管开关
文件：	总8页 (文件大小：78K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

µPA1819

P-CHANNEL MOS FIELD EFFECT TRANSISTOR

FOR SWITCHING

DESCRIPTION

PACKAGE DRAWING (Unit: mm)

The µ PA1819 is a switching device that can be driven

directly by a 4.0 V power source.

This device features a low on-state resistance and

excellent switching characteristics, and is suitable for

applications such as power management of notebook

computers and so on.

:Drain1

1, 2, 3: Source

1.2 MAX.

1.0±0.05

2, 3 :Source1

:G tete

a 1

6, 7

:Gate2

:Source2

:Drain2

5, 6, 7, 8: Drain

0.25

FEATURES

+5°

–3°

3°

0.5

• 4.0 V drive available

0.1±0.05

+0.15

–0.1

0.6

• Low on-state resistance

R^DS(on)1= 12 mΩ MAX. (V^GS= −10 V, I^D= −6.0 A)

R^DS(on)2= 18.5 mΩ MAX. (V^GS= −4.5 V, I^D= −6.0 A)

R^DS(on)3= 22 mΩ MAX. (V^GS= −4.0 V, I^D= −6.0 A)

• Built-in G-S protection diode against ESD

6.4 ±0.2

4.4 ±0.1

3.15 ±0.15

3.0 ±0.1

1.0 ±0.2

ORDERING INFORMATION

PART NUMBER

PACKAGE

0.65

0.8 MAX.

0.1

µPA1819GR-9JG

Power TSSOP8

+0.03

–0.08

0.27

0.10 M

ABSOLUTE MAXIMUM RATINGS (T^A= 25°C)

EQUIVALENT CIRCUIT

Drain to Source Voltage (V^GS= 0 V)

Gate to Source Voltage (V^DS= 0 V)

Drain Current (DC) (T^A= 25°C)

Drain Current (pulse) ^Note1

V^DSS

V^GSS

I^D(DC)

I^D(pulse)

P^T

−30

m20

m12

m48

2.0

Drain

Body

Diode

Gate

Total Power Dissipation ^Note2

°C

Channel Temperature

T^ch

150

Gate

Protection

Diode

Storage Temperature

T^stg

−55 to +150

°C

Source

Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%

2. Mounted on ceramic substrate of 5000 mm²x 1.1 mm

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When

this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated

voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. G16267EJ1V0DS00 (1st edition)

Date Published September 2002 NS CP(K)

Printed in Japan

2002

µPA1819

ELECTRICAL CHARACTERISTICS (T^A= 25°C)

CHARACTERISTICS

Zero Gate Voltage Drain Current

Gate Leakage Current

SYMBOL

I^DSS

TEST CONDITIONS

V^DS= −30 V, V^GS= 0 V

MIN. TYP. MAX. UNIT

−1.0

m10

µA

I^GSS

V^GS= m20 V, V^DS= 0 V

V^DS= −10 V, I^D= −1.0 mA

V^DS= −10 V, I^D= −6.0 A

V^GS= −10 V, I^D= −6.0 A

V^GS= −4.5 V, I^D= −6.0 A

V^GS= −4.0 V, I^D= −6.0 A

V^DS= −10 V

Gate Cut-off Voltage

V^GS(off)

| y^fs|

R^DS(on)1

R^DS(on)2

R^DS(on)3

C^iss

−1.0

−2.0

−2.5

Forward Transfer Admittance

Drain to Source On-state Resistance

9.8

13.9

16.4

2430

690

420

18.5

mΩ

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Turn-on Delay Time

Rise Time

C^oss

V^GS= 0 V

C^rss

f = 1.0 MHz

t^d(on)

t^r

t^d(off)

t^f

V^DD= −15 V, I^D= −6.0 A

V^GS= −10 V

Turn-off Delay Time

Fall Time

R^G= 10 Ω

160

Total Gate Charge

Q^G

V^DD= −24 V

Gate to Source Charge

Gate to Drain Charge

Body Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

Q^GS

V^GS= −10 V

5.5

Q^GD

V^F(S-D)

t^rr

I^D= −12 A

I^F= 12 A, V^GS= 0 V

di/dt = 100 A/µs

0.83

Q^rr

TEST CIRCUIT 1 SWITCHING TIME

TEST CIRCUIT 2 GATE CHARGE

D.U.T.

= −2 mA

GS(−)

90%

Wave Form

10%

PG.

50 Ω

PG.

DS(−)

90%

GS(−)

10% 10%

Wave Form

d(on)

d(off)

τ = 1

µs

toff

Duty Cycle ≤ 1%

Data Sheet G16267EJ1V0DS

µPA1819

TYPICAL CHARACTERISTICS (T^A= 25°C)

DERATING FACTOR OF FORWARD BIAS

SAFE OPERATING AREA

TOTAL POWER DISSIPATION vs.

AMBIENT TEMPERATURE

120

100

2.5

Mounted on ceramic

1.5

Substrate of 5000 mm²x 1.1 mm

0.5

Mounted on FR-4 board

of 2500 mm²x 1.6 mm

100

125

150

175

100

125

150

175

T^A- Ambient Temperature - °C

FORWARD BIAS SAFE OPERATING AREA

- 100

- 10

I^D(pulse)

PW = 1 ms

I^D(DC)

10 ms

- 1

R^DS(on)Limited

−

(V^GS= 10 V)

100 ms

- 0.1

Single pulse

Mounted on ceramic

Substrate of 5000 mm²x 1.1 mm

- 0.01

- 0.1

- 1

- 10

- 100

V^DS- Drain to Source Voltage - V

TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH

1000

100

Mounted on FR-4 board

Single pulse

of 2500 mm²x 1.6 mm

125°C/W

Mounted on ceramic

Substrate of 5000 mm²x 1.1 mm

62.5°C/W

0.1

1 m

10 m

100 m

100

1000

PW - Pulse Width - s

Data Sheet G16267EJ1V0DS

µPA1819

DRAIN CURRENT vs.

DRAIN TO SOURCE VOLTAGE

FORWARD TRANSFER CHARACTERISTICS

- 50

- 40

- 30

- 20

- 10

- 100

- 10

Pulsed

= −10 V

−

4.5 V

Pulsed

−

10 V

−

4.0 V

- 1

T = 125°C

75°C

25°C

−25°C

- 0.1

- 0.01

- 0.001

- 0.0001

- 0.2

- 0.4

- 0.6

- 0.8

- 1

- 1.5

- 2

- 2.5

- 3

- 3.5

- 4

V^DS- Drain to Source Voltage - V

V^GS- Gate to Source Voltage - V

GATE CUT-OFF VOLTAGE vs.

CHANNEL TEMPERATURE

FORWARD TRANSFER ADMITTANCE vs.

DRAIN CURRENT

100

- 2.4

- 2.2

- 2.0

- 1.8

- 1.6

- 1.4

V^DS= −10 V

Pulsed

−

10 V

−

1.0 mA

T^A= −25°C

25°C

75°C

125°C

0.1

- 0.01

- 0.1

- 1

- 10

- 100

-50

100

150

T^ch- Channel Temperature - °C

I^D- Drain Current - A

DRAIN TO SOURCE ON-STATE RESISTANCE

vs. CHANNEL TEMPERATURE

DRAIN TO SOURCE ON-STATE RESISTANCE

vs.GATE TO SOURCE VOLTAGE

−

6.0 A

Pulsed

−

4.0 V

−

4.5 V

−

10 V

-50

100

150

- 5

- 10

- 15

- 20

T^ch– Channel Temperrature - °C

V^GS- Gate to Source Voltage - V

Data Sheet G16267EJ1V0DS

µPA1819

DRAIN TO SOURCE ON-STATE RESISTANCE

vs. DRAIN CURRENT

DRAIN TO SOURCE ON-STATE RESISTANCE

vs. DRAIN CURRENT

−

= 4.5 V

10 V

Pulsed

= 125 C

75 C

25°C

= 125 C

−

25°C

75 C

25 C

−

25 C

- 0.01

- 0.1

- 1

- 10

- 100

- 0.01

- 0.1

- 1

- 10

- 100

I^D- Drain Current - A

DRAIN TO SOURCE ON-STATE RESISTANCE

vs. DRAIN CURRENT

CAPACITANCE vs.

DRAIN TO SOURCE VOLTAGE

10000

1000

100

−

4.0 V

V^GS= 0 V

f = 1.0 MHz

Pulsed

C^iss

= 125 C

75 C

C^oss

C^rss

25 C

−

25 C

- 0.01

- 0.1

- 1

- 10

- 100

- 0.1

- 1

- 10

- 100

I^D- Drain Current - A

V^DS- Drain to Source Voltage - V

SWITCHING CHARACTERISTICS

SOURCE TO DRAIN DIODE FORWARD VOLTAGE

10000

1000

100

−

15 V

10 V

Ω

= 0 V

Pulsed

= 10

d(off)

0.1

0.01

d(on)

- 0.01

- 0.1

- 1

- 10

- 100

0.4

0.6

0.8

1.2

I^D- Drain Current - A

V^F(S-D)- Source to Drain Voltage - V

Data Sheet G16267EJ1V0DS

µPA1819

DYNAMIC INPUT/OUTPUT CHARACTERISTICS

- 10

- 8

- 6

- 4

- 2

−

12 A

−

6.0 V

−

15 V

−

24 V

Q^G- Gate Charge - nC

Data Sheet G16267EJ1V0DS

µPA1819

[MEMO]

Data Sheet G16267EJ1V0DS

µPA1819

•

The information in this document is current as of September, 2002. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or

data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all

products and/or types are available in every country. Please check with an NEC sales representative

for availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

liability arising from the use of such products. No license, express, implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

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"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

application.

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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

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(Note)

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(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4

UPA1819 [NEC]

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