UPD16770N-XXX [NEC]
Liquid Crystal Driver, 420-Segment, MOS, TCP;
| 型号： | UPD16770N-XXX |
| 厂家： | 
NEC |
| 描述： | Liquid Crystal Driver, 420-Segment, MOS, TCP 驱动 接口集成电路 |
| 文件： | 总20页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16770B
420-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µ PD16770B is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input
is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000
colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules.
Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s
common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and
column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter
circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.
Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to SXGA + standard TFT-LCD
panels.
FEATURES
•
•
•
•
CMOS level input (2.3 to 3.6 V)
420 Outputs
Input of 6 bits (gray-scale data) by 6 dots
Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and
a D/A converter
•
•
•
•
•
•
•
•
•
Logic power supply voltage (VDD1): 2.3 to 3.6 V
Driver power supply voltage (VDD2): 8.5 ± 0.5 V
Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V
High-speed data transfer: fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V)
Apply for dot-line inversion, n-line inversion and column line inversion
Output voltage polarity inversion function (POL)
Display data inversion function (capable of controlling by each input port) (POL21, POL22)
Current consumption control function (LPC, HPC, Bcont)
Slim chip
ORDERING INFORMATION
Part Number
Package
µ PD16770BN -×××
TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14773EJ1V0DS00 (1st edition)
Date Published May 2001 NS CP(K)
Printed in Japan
2000
©
The mark ★ shows major revised points.
µ PD16770B
★
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
STHL
VDD1
70-bit bidirectional shift register
VSS1
C1
C2
C69
C70
D
D
D
D
D
D
00 -
D
D
D
D
D
D
05
10 -
15
20 -
25
Data register
30 -
40 -
50 -
35
45
55
POL21,
POL22
Latch
POL
V
DD2
SS2
Level shifter
V
V0 -
V9
D/A converter
HPC
LPC
Voltage follower output
Bcont
S1
S2
S3
S420
Remark /xxx indicates active low signal.
★
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
419
S
420
5
5
V
0
V
4
Multi-
plexer
6-bit D/A converter
V
5
V
9
POL
Data Sheet S14773EJ1V0DS
2
µ PD16770B
3. PIN CONFIGURATION (µPD16770BN-xxx: Copper foil surface, Face-up)
S420
S419
S418
S417
STHL
D55
D54
D53
D52
D51
D50
D45
D44
D43
D42
D41
D40
D35
D34
D33
D32
D31
D30
VDD1
R,/L
V9
V8
V7
V6
V5
VDD2
Copper foil
surface
VSS2
Bcont
V4
V3
V2
V1
V0
HPC
VSS1
LPC
CLK
STB
POL
POL21
POL22
D25
D24
D23
D22
D21
D20
D15
D14
D13
D12
D11
D10
D05
D04
D03
S4
S3
S2
S1
D02
D01
D00
STHR
Remark This figure does not specify the TCP package.
Data Sheet S14773EJ1V0DS
3
µ PD16770B
4. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
Description
S1 to S420
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L
Driver output
The D/A converted 64-gray-scale analog voltage is output.
Display data input
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits)
by 6 dots (2 pixels).
DX0: LSB, DX5: MSB
Shift direction control
input
These refer to the start pulse input/output pins when driver ICs are connected in
cascade. The shift directions of the shift registers are as follows.
R,/L = H: STHR input, S1 → S420, STHL output
R,/L = L: STHL input, S420 → S1, STHR output
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Fetching of display data starts when H is read at the rising edge of CLK.
R,/L = H (right shift): STHR input, STHL output
STHR
STHL
CLK
Right shift start pulse
input/output
Left shift start pulse
input/output
R,/L = L (left shift): STHL input, STHR output
The start pulse width (H level) for next-level drivers is 1 CLK.
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge. At the rising edge of the 70 th clock after the
start pulse input, the start pulse output reaches the high level, thus becoming the
start pulse of the next-level driver. If 72 clock pulses are input after input of the start
pulse, input of display data is halted automatically. The contents of the shift register
are cleared at the STB’s rising edge.
Shift clock input
STB
POL
Latch input
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It
is necessary to ensure input of one pulse per horizontal period.
Polarity input
POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output
uses V5 to V9 as the reference supply.
POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output
uses V0 to V4 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL
signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
POL21,
POL22
Data inversion
Data inversion can invert when display data is loaded.
POL21, POL22 = H: Data inversion loads display data after inverting it.
POL21, POL22 = L: Data inversion does not invert input data.
POL21: D00 to D05, D10 to D15, D20to D25
POL22: D30 to D35, D40 to D45, D50 to D55
Controls the write function of the driver section by digitally controlling the bypass
current of the output amplifier.
LPC
HPC
Low power control input
High power control input
This pin is pulled up to the VDD1 power supply inside the IC.
Refer to 9. CURRENT CONSUMPTION CONTROL FUNCTION.
Data Sheet S14773EJ1V0DS
4
µ PD16770B
(2/2)
Pin Symbol
Bcont
Pin Name
Bias control
Description
This pin can be used to finely control the bias current inside the output amplifier.
When this fine-control function is not required, leave this pin open.
Refer to 9. CURRENT CONSUMPTION CONTROL FUNCTION.
Input the γ -corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V
2.3 to 3.6 V
V0 to V9
γ -corrected power
supplies
VDD1
VDD2
VSS1
VSS2
Logic power supply
Driver power supply
Logic ground
8.5 V ± 0.5 V
Grounding
Driver ground
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order.
Reverse this sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
V
DD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a
bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power supply
terminals (V , V , V , ···, V ) and VSS2.
0
1
2
9
Data Sheet S14773EJ1V0DS
5
µ PD16770B
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The µ PD16770B incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The
D/A converter consists of ladder resistors and switches.
The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’
and V0” to V63” is almost equivalent. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9,
respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine gray scale
voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated power
supplies V1 to V3 and V6 to V8.
Figure 5−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2,
common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data.
Be sure to maintain the voltage relationships as follows.
VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V.
Figures 5−2 and 5−3 show the relationship between the input data and the output data and the resistance values of
the resistor strings.
Figure 5−1. Relationship between Input Data and γ - corrected Power Supplies
VDD2
Split interval
0.1 V
V0
16
V
V
V
1
16
16
2
3
15
V4
VCOM
0.5 VDD2
15
16
V5
V6
V
7
8
16
16
V
V9
0.1 V
VSS2
00
10
20
30
3F
Input Data (HEX)
Data Sheet S14773EJ1V0DS
6
µ PD16770B
Figure 5−2. Relationship between Input Data and Output Voltage
VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > 0.5 VDD2, POL21, POL22 = L
DX5
DX4
DX3
DX2
DX1
DX0
rn
(Ω)
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Output Voltage
V0' V0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
r0
r1
r2
r3
r4
r5
r6
r7
1766
736
566
509
396
340
283
283
226
226
170
170
170
170
170
170
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
175
175
175
175
175
232
232
232
232
289
345
402
402
459
872
V1' V1+(V0-V1)×
V2' V1+(V0-V1)×
V3' V1+(V0-V1)×
V4' V1+(V0-V1)×
V5' V1+(V0-V1)×
V6' V1+(V0-V1)×
V7' V1+(V0-V1)×
V8' V1+(V0-V1)×
V9' V1+(V0-V1)×
V10' V1+(V0-V1)×
V11' V1+(V0-V1)×
V12' V1+(V0-V1)×
V13' V1+(V0-V1)×
V14' V1+(V0-V1)×
V15' V1+(V0-V1)×
V16' V1
4585 /
3849 /
3283 /
2774 /
2378 /
2038 /
1755 /
1472 /
1246 /
1020 /
850 /
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
V0
V0'
r0
r1
r2
r3
V
V
V
1
'
'
'
2
3
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
680 /
510 /
340 /
170 /
r
14
15
V
15
'
'
r
V17' V2+(V1-V2)×
V18' V2+(V1-V2)×
V19' V2+(V1-V2)×
V20' V2+(V1-V2)×
V21' V2+(V1-V2)×
V22' V2+(V1-V2)×
V23' V2+(V1-V2)×
V24' V2+(V1-V2)×
V25' V2+(V1-V2)×
V26' V2+(V1-V2)×
V27' V2+(V1-V2)×
V28' V2+(V1-V2)×
V29' V2+(V1-V2)×
V30' V2+(V1-V2)×
V31' V2+(V1-V2)×
V32' V2
2280 /
2128 /
1976 /
1824 /
1672 /
1520 /
1368 /
1216 /
1064 /
912 /
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
V1
V16
r
16
17
V17'
r
760 /
608 /
456 /
304 /
152 /
V33' V3+(V2-V3)×
V34' V3+(V2-V3)×
V35' V3+(V2-V3)×
V36' V3+(V2-V3)×
V37' V3+(V2-V3)×
V38' V3+(V2-V3)×
V39' V3+(V2-V3)×
V40' V3+(V2-V3)×
V41' V3+(V2-V3)×
V42' V3+(V2-V3)×
V43' V3+(V2-V3)×
V44' V3+(V2-V3)×
V45' V3+(V2-V3)×
V46' V3+(V2-V3)×
V47' V3+(V2-V3)×
V48' V3
2340 /
2184 /
2028 /
1872 /
1716 /
1560 /
1404 /
1248 /
1092 /
936 /
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
r46
r47
r48
780 /
624 /
468 /
312 /
V
V
V
47
'
'
'
V3
48
49
156 /
r49
V49' V4+(V3-V4)×
V50' V4+(V3-V4)×
V51' V4+(V3-V4)×
V52' V4+(V3-V4)×
V53' V4+(V3-V4)×
V54' V4+(V3-V4)×
V55' V4+(V3-V4)×
V56' V4+(V3-V4)×
V57' V4+(V3-V4)×
V58' V4+(V3-V4)×
V59' V4+(V3-V4)×
V60' V4+(V3-V4)×
V61' V4+(V3-V4)×
V62' V4+(V3-V4)×
V63' V4
4397 /
4222 /
4047 /
3872 /
3697 /
3465 /
3233 /
3001 /
2769 /
2480 /
2135 /
1733 /
1331 /
872 /
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
r
60
61
V61'
r
V62'
r62
V4
V63'
rtotal 15851
Caution There is no connection between V4 and V5 terminal in the chip.
Data Sheet S14773EJ1V0DS
7
µ PD16770B
Figure 5−3. Relationship between Input Data and Output Voltage
0.5 VDD2 > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V, POL21, POL22 = L
DX5
DX4
DX3
DX2
DX1
DX0
rn
Ω
(
)
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
Output Voltage
V0'' V9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
r0
r1
r2
r3
r4
r5
r6
r7
1766
736
566
509
396
340
283
283
226
226
170
170
170
170
170
170
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
152
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
156
175
175
175
175
175
232
232
232
232
289
345
402
402
459
872
V
63''
62''
V5
V1'' V9+(V8-V9)×
V2'' V9+(V8-V9)×
V3'' V9+(V8-V9)×
V4'' V9+(V8-V9)×
V5'' V9+(V8-V9)×
V6'' V9+(V8-V9)×
V7'' V9+(V8-V9)×
V8'' V9+(V8-V9)×
V9'' V9+(V8-V9)×
V10'' V9+(V8-V9)×
V11'' V9+(V8-V9)×
V12'' V9+(V8-V9)×
V13'' V9+(V8-V9)×
V14'' V9+(V8-V9)×
V15'' V9+(V8-V9)×
V16'' V8
1766 /
2502 /
3068 /
3577 /
3973 /
4313 /
4596 /
4879 /
5105 /
5331 /
5501 /
5671 /
5841 /
6011 /
6181 /
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
6351
r
62
61
V
r
V
61''
60''
r
60
59
V
r
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
r49
V49''
V48''
V47''
r
48
47
V6
r
V17'' V8+(V7-V8)×
V18'' V8+(V7-V8)×
V19'' V8+(V7-V8)×
V20'' V8+(V7-V8)×
V21'' V8+(V7-V8)×
V22'' V8+(V7-V8)×
V23'' V8+(V7-V8)×
V24'' V8+(V7-V8)×
V25'' V8+(V7-V8)×
V26'' V8+(V7-V8)×
V27'' V8+(V7-V8)×
V28'' V8+(V7-V8)×
V29'' V8+(V7-V8)×
V30'' V8+(V7-V8)×
V31'' V8+(V7-V8)×
V32'' V7
152 /
304 /
456 /
608 /
760 /
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
2432
r46
912 /
1064 /
1216 /
1368 /
1520 /
1672 /
1824 /
1976 /
2128 /
2280 /
V33'' V7+(V6-V7)×
V34'' V7+(V6-V7)×
V35'' V7+(V6-V7)×
V36'' V7+(V6-V7)×
V37'' V7+(V6-V7)×
V38'' V7+(V6-V7)×
V39'' V7+(V6-V7)×
V40'' V7+(V6-V7)×
V41'' V7+(V6-V7)×
V42'' V7+(V6-V7)×
V43'' V7+(V6-V7)×
V44'' V7+(V6-V7)×
V45'' V7+(V6-V7)×
V46'' V7+(V6-V7)×
V47'' V7+(V6-V7)×
V48'' V6
156 /
312 /
468 /
624 /
780 /
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
2496
r17
r16
r15
r14
V
17''
16''
936 /
V
V8
1092 /
1248 /
1404 /
1560 /
1716 /
1872 /
2028 /
2184 /
2340 /
V15''
V49'' V6+(V5-V6)×
V50'' V6+(V5-V6)×
V51'' V6+(V5-V6)×
V52'' V6+(V5-V6)×
V53'' V6+(V5-V6)×
V54'' V6+(V5-V6)×
V55'' V6+(V5-V6)×
V56'' V6+(V5-V6)×
V57'' V6+(V5-V6)×
V58'' V6+(V5-V6)×
V59'' V6+(V5-V6)×
V60'' V6+(V5-V6)×
V61'' V6+(V5-V6)×
V62'' V6+(V5-V6)×
V63'' V5
175 /
350 /
525 /
700 /
875 /
1107 /
1339 /
1571 /
1803 /
2092 /
2437 /
2839 /
3241 /
3700 /
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
4572
r2
V2''
r
1
0
V1''
r
V0''
V9
3FH
1
1
1
1
1
1
rtotal 15851
Caution There is no connection between V4 and V5 terminal in the chip.
Data Sheet S14773EJ1V0DS
8
µ PD16770B
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format: 6 bits × 2 RGBs (6 dots)
Input width: 36 bits (2-pixel data)
R,/L = H (Right shift)
Output
Data
S1
S2
S3
S4
xxx
xxx
S419
S420
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
R,/L = L (Left shift)
Output
Data
S1
S2
S3
S4
xxx
xxx
S419
S420
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
Note
Note
S2n–1
S2n
POL
L
V0 to V4
V5 to V9
V5 to V9
V0 to V4
H
Note S2n-1 (Odd output), S2n (Even output)
7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
STB
POL
S
2n-1
Selected voltage V
0
toV
4
Selected voltage V
5
toV
9
Selected voltage V
0
toV
4
S
2n
Selected voltage V
0
toV
4
Selected voltage V
5
toV
9
Selected voltage V
5
toV
9
Hi-Z
Hi-Z
Hi-Z
Data Sheet S14773EJ1V0DS
9
µ PD16770B
8. RELATIONSHIP BETWEEN STB, CLK, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
Figure8−1. Output Circuit Block Diagram
Output Amp
DAC
+
SW1
Sn (VOUT)
VAMP(IN)
Figure8−2. Output Circuit Timing Waveform
[1] [2]
CLK
(External Input)
STB
(External Input)
SW1 : ON
SW1 : OFF
SW1 : ON
VAMP(IN)
S
n
(VOUT: External Output)
Output
Output
Hi-Z
Remarks 1. STB = L: SW1 = ON, STB = H: SW1 = OFF
2. STB = “H” is acknowledged at timing [1].
3. The display data latch is completed at timing [2] and the input voltage
(VAMP(IN): gray-scale level voltage) of the output amplifier changes.
Data Sheet S14773EJ1V0DS
10
µ PD16770B
9. CURRENT CONSUMPTION CONTROL FUNCTION
The µ PD16770B has a power control function which can switch the bias current of the output amplifier between
four levels and a bias control function (Bcont) which can be used to finely control the bias current.
<Power control function (LPC, HPC)>
The bias current of the output amplifier can be switched between four levels using LPC (Low Power Control) pins
and HPC (High Power Control) pins.
Power mode
LPC
HPC
High
L
L
Middle
Normal
Low
H or Open
L
L
H or Open
H or Open
H or Open
Following graph shows the relationship between each power modes and bias current.
HIGH
MID
NOMAL
LOW
6.00
7.00
8.00
9.00
V
DD2
Remark This relationship is founded on results of simulation and don’t assuring a characteristics of this
product.
Data Sheet S14773EJ1V0DS
11
µ PD16770B
<Bias Current Control Function (Bcont)>
It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When
using this function, connect this pin to the stabilized ground potential (VSS2) via an external resistor (REXT). When not
using this function, leave this pin open.
Figure9−1. Bias Current Control Function (Bcont)
H/L
H/L
HPC
LPC
PD16770B
µ
B
cont
REXT
Refer to the table below for the percentage of current regulation when using the bias current control function.
Table9−1. Current Consumption Regulation Percentage Compared to Normal Mode
Current Consumption Regulation Percentage
REXT
LPC = L, HPC = H/open
LPC = H/open, HPC = H/open
VDD1 = 3.3 V
VDD2 = 8.7 V
∞ (Open)
50 kΩ
100%
110%
115%
120%
65%
70%
80%
85%
20 kΩ
10 kΩ
Remark The above current consumption regulation percentages are founded on results of
simulation and don’t assuring a characteristics of this product.
Caution Because the power and bias-current control functions control the bias current in the output
amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the
characteristics of the output amplifier will simultaneously change. Therefore, when using these
functions, be sure to sufficiently evaluate the picture quality.
Data Sheet S14773EJ1V0DS
12
µ PD16770B
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V)
Parameter
Logic Part Supply Voltage
Driver Part Supply Voltage
Logic Part Input Voltage
Driver Part Input Voltage
Logic Part Output Voltage
Driver Part Output Voltage
Operating Ambient Temperature
Storage Temperature
Symbol
VDD1
VDD2
VI1
Rating
Unit
V
–0.5 to +4.0
–0.5 to +10.0
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–0.5 to VDD1 + 0.5
–0.5 to VDD2 + 0.5
–10 to +75
V
V
VI2
V
VO1
V
VO2
V
TA
°C
°C
Tstg
–55 to +125
Caution Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter/ That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
VDD1
VDD2
VIH
Conditions
MIN.
2.3
TYP.
8.5
MAX.
3.6
Unit
V
Logic Part Supply Voltage
Driver Part Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
γ -Corrected Voltage
8.0
9.0
V
0.7 VDD1
0
VDD1
V
VIL
0.3 VDD1
VDD2 − 0.1
VDD2 − 0.1
45
V
V0 to V9
VO
VSS2 + 0.1
VSS2 + 0.1
V
Driver Part Output Voltage
Maximum Clock Frequency
V
fCLK
VDD1 = 2.3 V
MHz
Data Sheet S14773EJ1V0DS
13
µ PD16770B
Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.5 V ± 0.5 V, VSS1 = VSS2 = 0 V,
unless otherwise specified, power mode: normal, Bcont = open)
Parameter
Symbol
IIL
Conditions
MIN.
TYP.
MAX.
Unit
µA
V
Input Leak Current
±1.0
High-Level Output Voltage
Low-Level Output Voltage
γ -Corrected Supply Current
VOH
VOL
Iγ
STHR (STHL), IOH = 0 mA
STHR (STHL), IOL = 0 mA
VDD1 − 0.1
0.1
V
VDD2 = 8.5 V
V0 to V4 =
V0 pin, V5 pin
126
252
504
µA
V4 pin, V9 pin
−504
−252
−126
−30
µA
V5 to V9 = 4.0 V
VX = 7.0 V, VOUT = 6.5 VNote
VX = 1.0 V, VOUT = 1.5 VNote
TA = 25°C
Driver Output Current
IVOH
IVOL
∆VO
µA
µA
30
Output Voltage Deviation
±7
±2
±20
±15
mV
VDD1 = 3.3 V, VDD2 = 8.5 V,
VOUT = 2.0 V, 4.25 V, 6.5 V
Output swing difference
deviation
∆VP–P
mV
mA
mA
Logic Part Dynamic Current
Consumption
IDD1
VDD1
1.0
3.0
6.5
6.5
Driver Part Dynamic
Current Consumption
IDD2
VDD2, with no load
Note VX refers to the output voltage of analog output pins S1 to S420. VOUT refers to the voltage applied to analog
output pins S1 to S420.
★
Cautions 1. fSTB = 64 kHz, fCLK = 40 MHz.
2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the
measured values in the dot checkerboard input pattern.
3. Refers to the current consumption per driver when cascades are connected under the
assumption of SXGA+ single-sided mounting (10 units).
Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.5 V ± 0.5 V, VSS1 = VSS2 = 0 V,
unless otherwise specified, power mode: normal, Bcont = open)
Parameter
Symbol
tPLH1
tPHL1
tPLH2
tPLH3
tPHL2
tPHL3
CI1
Conditions
CL = 10 pF
MIN.
TYP.
10
10
2.5
5
MAX.
20
20
5
Unit
ns
ns
µs
µs
µs
µs
pF
Start Pulse Delay Time
Driver Output Delay Time
CL = 75 pF, RL = 5 kΩ
8
2.5
5
5
8
Input Capacitance
STHR (STHL) excluded,
TA = 25°C
10
CI2
STHR (STHL),TA = 25°C
10
pF
Data Sheet S14773EJ1V0DS
14
µ PD16770B
Timing Requirement (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Clock Pulse Width
Symbol
PWCLK
PWCLK(H)
PWCLK(L)
tSETUP1
tHOLD1
Conditions
MIN.
22
4
TYP.
MAX.
Unit
ns
Clock Pulse High Period
Clock Pulse Low Period
Data Setup Time
ns
4
ns
4
ns
Data Hold Time
0
ns
Start Pulse Setup Time
Start Pulse Hold Time
POL21, POL22 Setup Time
POL21, POL22 Hold Time
Start Pulse Low Period
STB Pulse Width
tSETUP2
tHOLD2
tSETUP3
tHOLD3
4
ns
0
ns
4
ns
0
ns
tSPL
1
CLK
CLK
CLK
ns
PWSTB
tLDT
2
Last Data Timing
2
CLK-STB Time
tCLK-STB
tSTB-CLK
tSTB-STH
tPOL-STB
tSTB-POL
CLK ↑ → STB ↑
6
STB-CLK Time
STB ↑ → CLK ↑
9
ns
Time Between STB and Start Pulse
POL-STB Time
STB ↑ → STHR(STHL) ↑
POL ↑ or ↓ → STB ↑
STB ↓ → POL ↓ or ↑
2
CLK
ns
–5
6
STB-POL Time
ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
Data Sheet S14773EJ1V0DS
15
PWCLK(L) PWCLK
PWCLK(H)
t
r
t
f
1
2
V
DD1
SS1
90%
1
2
3
70
71
72
701
702
CLK
V
10%
t
SETUP2
t
HOLD2
t
STB-CLK
t
SPL
t
CLK-STB
V
DD1
SS1
STHR
(1st Dr.)
V
t
SETUP1
t
HOLD1
t
STB-STH
V
DD1
SS1
D
D
409 to
D
D
415 to
D
D
421 to
D
D
4195 to
D
n0 to Dn5
INVALID
INVALID
D1
to D
6
D
7
to D12
INVALID
D1
to D
6
D7 to D12
414
420
426
4200
V
t
SETUP3
t
HOLD3
V
DD1
SS1
POL21,
POL22
INVALID
V
t
PLH1
t
PHL1
V
DD1
SS1
STHL
(1st Dr.)
V
t
LDT
PWSTB
V
DD1
SS1
STB
POL
V
t
POL-STB
t
STB-POL
V
DD1
SS1
V
t
t
PLH3
Hi-Z
PLH2
Target Voltage +0.1 VDD2
6-bit accuracy
µ
µ
S
n
(VOUT
)
t
t
PHL2
PHL3
µ PD16770B
11. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the µ PD16770B.
For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.
µPD16770BN-×××: TCP (TAB package)
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C: heating for 2 to 3 seconds: pressure 100g (per
solder)
ACF
Temporary bonding 70 to 100°C: pressure 3 to 8 kg/cm2 : time 3 to 5
seconds.
Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2 : time 30 to 40
seconds. (When using the anisotropy conductive film SUMIZAC1003 of
Sumitomo Bakelite, Ltd.)
(Adhesive
Conductive Film)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more packaging methods at a time.
Data Sheet S14773EJ1V0DS
17
µ PD16770B
[MEMO]
Data Sheet S14773EJ1V0DS
18
µ PD16770B
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14773EJ1V0DS
19
µ PD16770B
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Semiconductor Device Mounting Technology (C10535E)
•
The information in this document is current as of May, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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