UPD44164082AF5-E40-EQ2-A [NEC]
DDR SRAM, 2MX8, CMOS, PBGA165, 13 X 5 MM, LEAD FREE, PLASTIC, BGA-165;型号: | UPD44164082AF5-E40-EQ2-A |
厂家: | NEC |
描述: | DDR SRAM, 2MX8, CMOS, PBGA165, 13 X 5 MM, LEAD FREE, PLASTIC, BGA-165 双倍数据速率 静态存储器 内存集成电路 |
文件: | 总40页 (文件大小:374K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD44164082A, 44164092A, 44164182A, 44164362A
18M-BIT DDRII SRAM
2-WORD BURST OPERATION
Description
The μPD44164082A is a 2,097,152-word by 8-bit, the μPD44164092A is a 2,097,152-word by 9-bit, the μPD44164182A
is a 1,048,576-word by 18-bit and the μPD44164362A is a 524,288-word by 36-bit synchronous double data rate static
RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The μPD44164082A, μPD44164092A, μPD44164182A and μPD44164362A integrate unique synchronous peripheral
circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive
edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA package (13 x 15)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Pipelined double data rate operation
• Common data input/output bus
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
• User programmable impedance output
<R>
<R>
• Fast clock cycle time : 3.3 ns (300 MHz), 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scan
• Operating ambient temperature: Commercial TA = 0 to +70°C
(-E33, -E37, -E40, -E50)
Industrial TA = –40 to +85°C (-E37Y, -E40Y, -E50Y)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M17767EJ3V0DS00 (3rd edition)
Date Published February 2007 NS CP(N)
Printed in Japan
2006
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
μPD44164082A, 44164092A, 44164182A, 44164362A
Ordering Information
(1) Operating Ambient Temperature TA = 0 to +70°C
Part number
Cycle
Time
ns
Clock
Frequency
MHz
Organization
(word x bit)
Package
Operating
Ambient
Temperature
μPD44164082AF5-E33-EQ2
μPD44164082AF5-E40-EQ2
μPD44164082AF5-E50-EQ2
μPD44164092AF5-E33-EQ2
μPD44164092AF5-E40-EQ2
μPD44164092AF5-E50-EQ2
μPD44164182AF5-E33-EQ2
μPD44164182AF5-E37-EQ2
μPD44164182AF5-E40-EQ2
μPD44164182AF5-E50-EQ2
μPD44164362AF5-E33-EQ2
μPD44164362AF5-E40-EQ2
μPD44164362AF5-E50-EQ2
μPD44164082AF5-E33-EQ2-A
μPD44164082AF5-E40-EQ2-A
μPD44164082AF5-E50-EQ2-A
μPD44164092AF5-E33-EQ2-A
μPD44164092AF5-E40-EQ2-A
μPD44164092AF5-E50-EQ2-A
μPD44164182AF5-E33-EQ2-A
μPD44164182AF5-E37-EQ2-A
μPD44164182AF5-E40-EQ2-A
μPD44164182AF5-E50-EQ2-A
μPD44164362AF5-E33-EQ2-A
μPD44164362AF5-E40-EQ2-A
μPD44164362AF5-E50-EQ2-A
3.3
4.0
5.0
3.3
4.0
5.0
3.3
3.7
4.0
5.0
3.3
4.0
5.0
3.3
4.0
5.0
3.3
4.0
5.0
3.3
3.7
4.0
5.0
3.3
4.0
5.0
300
250
200
300
250
200
300
270
250
200
300
250
200
300
250
200
300
250
200
300
270
250
200
300
250
200
2M x 8-bit
2M x 9-bit
1M x 18-bit
165-pin PLASTIC
BGA (13 x 15)
Commercial
(TA = 0 to +70°C)
<R>
512K x 36-bit
2M x 8-bit
165-pin PLASTIC
BGA (13 x 15)
2M x 9-bit
Lead-free
1M x 18-bit
<R>
512K x 36-bit
Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.
The footprint is commonly used.
2. Products with -A at the end of the part number are lead-free products.
Data Sheet M17767EJ3V0DS
2
μPD44164082A, 44164092A, 44164182A, 44164362A
(2) Operating Ambient Temperature TA = –40 to +85°C
<R>
Part number
Cycle
Time
ns
Clock
Frequency
MHz
Organization
(word x bit)
Package
Operating
Ambient
Temperature
μPD44164082AF5-E37Y-EQ2
μPD44164082AF5-E40Y-EQ2
μPD44164082AF5-E50Y-EQ2
μPD44164092AF5-E37Y-EQ2
μPD44164092AF5-E40Y-EQ2
μPD44164092AF5-E50Y-EQ2
μPD44164182AF5-E37Y-EQ2
μPD44164182AF5-E40Y-EQ2
μPD44164182AF5-E50Y-EQ2
μPD44164082AF5-E37Y-EQ2-A
μPD44164082AF5-E40Y-EQ2-A
μPD44164082AF5-E50Y-EQ2-A
μPD44164092AF5-E37Y-EQ2-A
μPD44164092AF5-E40Y-EQ2-A
μPD44164092AF5-E50Y-EQ2-A
μPD44164182AF5-E37Y-EQ2-A
μPD44164182AF5-E40Y-EQ2-A
μPD44164182AF5-E50Y-EQ2-A
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
270
250
200
270
250
200
270
250
200
270
250
200
270
250
200
270
250
200
2M x 8-bit
2M x 9-bit
1M x 18-bit
2M x 8-bit
2M x 9-bit
1M x 18-bit
165-pin PLASTIC
BGA (13 x 15)
Industrial
(TA = –40 to +85°C)
165-pin PLASTIC
BGA (13 x 15)
Lead-free
Remarks 1. QDR Consortium standard package size is 13 x 15 and 15 x 17.
The footprint is commonly used.
2. Products with -A at the end of the part number are lead-free products.
Data Sheet M17767EJ3V0DS
3
μPD44164082A, 44164092A, 44164182A, 44164362A
Pin Configurations
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164082A]
2M x 8-bit
1
CQ#
NC
2
3
A
4
5
6
7
NC
NW0#
A
8
9
A
10
VSS
NC
NC
NC
NC
NC
NC
VREF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
A
B
C
D
E
F
VSS
NC
NC
NC
NC
NC
NC
VREF
NC
NC
DQ6
NC
NC
NC
TCK
R, W# NW1#
K#
K
LD#
A
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
A
A
NC
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
VSS
A
VSS
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
G
H
J
NC
DLL#
NC
NC
NC
DQ0
NC
NC
NC
TDI
K
L
NC
NC
M
N
P
R
NC
NC
VSS
VSS
NC
A
A
C
A
A
TDO
A
A
C#
A
A
A
: Address inputs
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
DQ0 to DQ7
LD#
: Data inputs / outputs
: Synchronous load
: Read Write input
: Nibble Write data select
: Input clock
TDI
TCK
TDO
VREF
VDD
R, W#
NW0#, NW1#
K, K#
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
C, C#
: Output clock
VDDQ
VSS
CQ, CQ#
ZQ
: Echo clock
: Output impedance matching
: DLL/PLL disable
NC
: No connection
DLL#
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.
2A and 10A of this product can also be used as NC.
Data Sheet M17767EJ3V0DS
4
μPD44164082A, 44164092A, 44164182A, 44164362A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164092A]
2M x 9-bit
1
CQ#
NC
2
3
A
4
5
6
7
NC
BW0#
A
8
9
A
10
VSS
NC
NC
NC
NC
NC
NC
VREF
DQ2
NC
NC
NC
NC
NC
TMS
11
CQ
DQ4
NC
A
B
C
D
E
F
VSS
NC
NC
NC
NC
NC
NC
VREF
NC
NC
DQ7
NC
NC
NC
TCK
R, W#
A
NC
NC
A
K#
K
LD#
A
NC
NC
NC
DQ5
NC
DQ6
VDDQ
NC
NC
NC
NC
NC
DQ8
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
VSS
A
VSS
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ3
NC
NC
G
H
J
NC
NC
DLL#
NC
ZQ
NC
K
L
NC
NC
NC
DQ1
NC
M
N
P
R
NC
NC
VSS
VSS
NC
NC
A
A
C
A
A
DQ0
TDI
TDO
A
A
C#
A
A
A
: Address inputs
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
DQ0 to DQ8
LD#
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
TDI
TCK
TDO
VREF
VDD
R, W#
BW0#
K, K#
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
C, C#
: Output clock
VDDQ
VSS
CQ, CQ#
ZQ
: Echo clock
: Output impedance matching
: DLL/PLL disable
NC
: No connection
DLL#
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.
2A and 10A of this product can also be used as NC.
Data Sheet M17767EJ3V0DS
5
μPD44164082A, 44164092A, 44164182A, 44164362A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164182A]
1M x 18-bit
1
CQ#
NC
2
VSS
3
4
5
6
7
NC
BW0#
A
8
9
A
10
VSS
NC
11
CQ
A
B
C
D
E
F
A
R, W# BW1#
K#
K
LD#
A
DQ9
NC
NC
A
NC
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
DQ8
NC
NC
NC
VSS
A0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
DQ7
NC
NC
NC
DQ10
DQ11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
DQ6
DQ5
NC
NC
DQ12
NC
NC
G
H
J
NC
DQ13
VDDQ
NC
NC
DLL#
NC
VREF
NC
VREF
DQ4
NC
ZQ
NC
K
L
NC
NC
DQ14
NC
DQ3
DQ2
NC
NC
DQ15
NC
NC
M
N
P
R
NC
NC
DQ1
NC
NC
NC
DQ16
DQ17
A
VSS
VSS
NC
NC
NC
A
A
C
A
A
NC
DQ0
TDI
TDO
TCK
A
A
C#
A
A
TMS
A0, A
: Address inputs
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
DQ0 to DQ17
LD#
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
TDI
TCK
TDO
VREF
VDD
R, W#
BW0#, BW1#
K, K#
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
C, C#
: Output clock
VDDQ
VSS
CQ, CQ#
ZQ
: Echo clock
: Output impedance matching
: DLL/PLL disable
NC
: No connection
DLL#
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 7A and 10A are expansion addresses: 10A for 36Mb, 2A for 72Mb and 7A for 144Mb.
2A and 10A of this product can also be used as NC.
Data Sheet M17767EJ3V0DS
6
μPD44164082A, 44164092A, 44164182A, 44164362A
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164362A]
512K x 36-bit
1
CQ#
NC
2
3
4
5
6
7
BW1#
BW0#
A
8
9
A
10
VSS
11
CQ
A
B
C
D
E
F
VSS
NC
R, W# BW2#
K#
K
LD#
A
DQ27
NC
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
A
BW3#
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
NC
VSS
A0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
DQ17
NC
NC
DQ29
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ15
NC
NC
DQ30
DQ31
VREF
NC
G
H
J
NC
NC
DLL#
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
NC
NC
DQ33
NC
M
N
P
R
NC
DQ11
NC
NC
DQ35
NC
VSS
VSS
NC
A
A
C
A
A
DQ9
TMS
TDO
TCK
A
A
C#
A
A
A0, A
: Address inputs
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
DQ0 to DQ35
LD#
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
TDI
TCK
TDO
VREF
VDD
R, W#
BW0# to BW3#
K, K#
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
C, C#
: Output clock
VDDQ
VSS
CQ, CQ#
ZQ
: Echo clock
: Output impedance matching
: DLL/PLL disable
NC
: No connection
DLL#
Remarks 1. ×××# indicates active LOW signal.
2. Refer to Package Drawing for the index mark.
3. 2A, 3A and 10A are expansion addresses: 3A for 36Mb, 10A for 72Mb and 2A for 144Mb.
2A and 10A of this product can also be used as NC.
Data Sheet M17767EJ3V0DS
7
μPD44164082A, 44164092A, 44164182A, 44164362A
Pin Identification
(1/2)
Symbol
Description
A0
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). A0 is used
as the lowest order address bit permitting a random starting address within the burst operation on x18 and x36
devices. These inputs are ignored when device is deselected, i.e., NOP (LD# = HIGH).
DQ0 to DQxx Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and K#. Output
data is synchronized to the respective C and C# data clocks or to K and K# if C and C# are tied to HIGH.
x8 device uses DQ0 to DQ7.
x9 device uses DQ0 to DQ8.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
LD#
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus
activity).
R, W#
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R, W#
is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must meet the setup and hold times
around the rising edge of K.
BWx#
NWx#
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin
Configurations for signal to data relationships.
x8 device uses NW0#, NW1#.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx#, NWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
C# is used as the output timing reference for first output data. The rising edge of C is used as the output
reference for second output data. Ideally, C# is 180 degrees out of phase with C. When use of K and K# as the
reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and
C# are fixed to HIGH (i.e. toggle of C and C#).
K, K#
C, C#
Data Sheet M17767EJ3V0DS
8
μPD44164082A, 44164092A, 44164182A, 44164362A
(2/2)
Symbol
Description
CQ, CQ#
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ
tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also
stop.
<R>
<R>
ZQ
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. The output impedance can be minimized by directly connect ZQ to VDDQ. This pin cannot be
connected directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon
power-up to account for drifts in supply voltage and temperature. After replacement for a resistor, the new
output impedance is reset by implementing power-on sequence.
DLL#
DLL/PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency
slower than TKHKH (MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. The AC/DC characteristics
cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a
10 kΩ or less resistor.
TMS
TDI
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
TCK
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO
VREF
VDD
IEEE 1149.1 Test Output: 1.8 V I/O level.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for
range.
VDDQ
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended
DC Operating Conditions and DC Characteristics for range.
Power Supply: Ground
VSS
<R>
NC
No Connect: These signals are not connected internally.
Data Sheet M17767EJ3V0DS
9
μPD44164082A, 44164092A, 44164182A, 44164362A
Block Diagram
CLK
Burst
Logic
A0'
A0
D0
Q0
R
Address
Register
Address
LD#
W#
E
Compare
C#
C
A0''
A0'''
Output control
Logic
Write address
Register
K
E
E
A0'
Input
Register
/A0'
A0'
ZQ
0
2 :1
MUX
Memory
Array
CLK
/A0'
K
1
A0'
Output Buffer
E
DQ
0
1
K#
Input
Register
E
A0'''
Output Enable
Register
C
R, W#
R, W#`
Register
E
Data Sheet M17767EJ3V0DS
10
μPD44164082A, 44164092A, 44164182A, 44164362A
Power-on Sequence
The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after
VDD/VDDQ stable and when starting the clock before VDD/VDDQ stable.
1. Clock starts after VDD/VDDQ stable
The clock is supplied from a controller.
(a)
VDD/VDDQ
VDD/VDDQ Stable (< 0.1 V DC per 50 ns)
DLL#
Clock
Fix HIGH (or tied to VDDQ)
20 ns (MIN.)
Clock Start Note
1,024 cycles or more
Stable Clock
Normal Operation
Start
Note Input a stable clock from the start.
(b)
V
DD/VDD
Q
DLL#
Clock
VDD/VDDQ Stable (< 0.1 V DC per 50 ns)
Switched to HIGH after Clock is stable.
Unstable Clock
(level, frequency)
1,024 cycles or more
Stable Clock
Normal Operation
Start
Clock Start
(c)
VDD/VDD
Q
VDD/VDDQ Stable (< 0.1 V DC per 50 ns)
DLL#
Clock
Fix HIGH (or tied to VDDQ)
30 ns. (MIN.)
Clock Stop
Unstable Clock
(level, frequency)
1,024 cycles or more
Stable Clock
Normal Operation
Start
Clock Start
Data Sheet M17767EJ3V0DS
11
μPD44164082A, 44164092A, 44164182A, 44164362A
2. Clock starts before VDD/VDDQ stable
The clock is supplied from a clock generator.
(a)
VDD/VDDQ
VDD/VDDQ Stable (< 0.1 V DC per 50 ns)
DLL#
Clock
Fix HIGH (or tied to VDDQ)
Unstable Clock
(level, frequency)
1,024 cycles or more
Stable Clock
Normal Operation Start
30 ns. (MIN.)
Clock Stop
Clock Start
(b)
VDD/VDD
Q
VDD/VDDQ Stable (< 0.1 V DC per 50 ns)
30 ns (MIN.)
DLL# LOW
HIGH or LOW
DLL#
Clock
Switched to HIGH after Clock is stable.
Unstable Clock
(level, frequency)
1,024 cycles or more Normal
Stable Clock
Operation
Start
Clock keep running
Clock Start
Data Sheet M17767EJ3V0DS
12
μPD44164082A, 44164092A, 44164182A, 44164362A
Burst Sequence
Linear Burst Sequence Table
[μPD44164182A, μPD44164362A]
A0
0
A0
1
External Address
1st Internal Burst Address
1
0
Truth Table
Operation
LD# R, W#
CLK
DQ
WRITE cycle
L
L
L → H
Data in
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Input data
Input clock
D(A1)
D(A2)
K(t+1) ↑
K#(t+1) ↑
L
H
L → H
Data out
Output data
Output clock
High-Z
Previous state
Load address, read data on two
consecutive C and C# rising edge
NOP (No operation)
Clock stop
Q(A1)
Q(A2)
C#(t+1) ↑
C(t+2) ↑
H
X
X
X
L → H
Stopped
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst
address in accordance with the linear burst sequence.
7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
Data Sheet M17767EJ3V0DS
13
μPD44164082A, 44164092A, 44164182A, 44164362A
Byte Write Operation
[μPD44164082A]
Operation
K
K#
–
NW0#
NW1#
Write DQ0 to DQ7
L → H
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
–
L → H
–
L → H
–
Write DQ0 to DQ3
Write DQ4 to DQ7
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
<R>
2. Assumes a WRITE cycle was initiated. NW0# and NW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD44164092A]
Operation
K
L → H
–
K#
–
BW0#
Write DQ0 to DQ8
Write nothing
0
0
1
1
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
<R>
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD44164182A]
Operation
K
L → H
–
K#
–
BW0#
BW1#
Write DQ0 to DQ17
Write DQ0 to DQ8
Write DQ9 to DQ17
Write nothing
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
<R>
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Data Sheet M17767EJ3V0DS
14
μPD44164082A, 44164092A, 44164182A, 44164362A
[μPD44164362A]
Operation
K
L → H
–
K#
–
BW0#
BW1#
BW2#
BW3#
Write DQ0 to DQ35
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
L → H
–
Write DQ0 to DQ8
Write DQ9 to DQ17
Write DQ18 to DQ26
Write DQ27 to DQ35
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
<R>
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Data Sheet M17767EJ3V0DS
15
μPD44164082A, 44164092A, 44164182A, 44164362A
Bus Cycle State Diagram
LOAD NEW
ADDRESS
Count = 0
Load, Count = 2
Load, Count = 2
Write
Read
READ DOUBLE
Count = Count + 2
WRITE DOUBLE
Count = Count + 2
Load
NOP,
NOP,
Count = 2
Count = 2
NOP
NOP
Supply voltage provided
Power UP
Remarks 1. A0 is internally advanced in accordance with the burst order table.
Bus cycle is terminated after burst count = 2.
2. State machine control timing sequence is controlled by K.
Data Sheet M17767EJ3V0DS
16
μPD44164082A, 44164092A, 44164182A, 44164362A
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VDD
Conditions
MIN.
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
Unit
V
Supply voltage
+2.5
Output supply voltage
Input voltage
VDDQ
VIN
VDD
V
VDD + 0.5 (2.5 V MAX.)
V
Input / Output voltage
Operating ambient temperature
VI/O
VDDQ + 0.5 (2.5 V MAX.)
V
TA
Commercial
Industrial
+70
+85
°C
<R>
–40
–55
Storage temperature
Tstg
+125
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
1.7
TYP.
MAX.
1.9
Unit
V
Note
Output supply voltage
Input HIGH voltage
Input LOW voltage
Clock input voltage
Reference voltage
VDDQ
VIH (DC)
VIL (DC)
VIN
1.4
VDD
V
1
VREF + 0.1
–0.3
VDDQ + 0.3
VREF – 0.1
VDDQ + 0.3
0.95
V
1, 2
1, 2
1, 2
V
–0.3
V
VREF
0.68
V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions
Parameter
Input HIGH voltage
Input LOW voltage
Symbol
VIH (AC)
VIL (AC)
Conditions
MIN.
VREF + 0.2
–
TYP.
MAX.
–
Unit
V
Note
1
1
VREF – 0.2
V
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
Data Sheet M17767EJ3V0DS
17
μPD44164082A, 44164092A, 44164182A, 44164362A
DC Characteristics (VDD = 1.8 ± 0.1 V)
<R>
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
x8, x9 x18 x36
+2
Unit Note
Input leakage current
I/O leakage current
Operating supply
current
ILI
–2
–2
–
–
μA
μA
ILO
IDD
+2
Note1
Commercial
-E33
-E37
-E40
-E50
-E37Y
480 520 610
mA
(TA = 0 to +70°C)
–
490
–
(Read cycle/
440 470 540
400 420 470
Write cycle)
Industrial
470 510
460 490
420 440
–
–
–
(TA = –40 to +85°C) -E40Y
-E50Y
Standby supply
current
ISB1
Note1
Commercial
-E33
-E37
-E40
-E50
-E37Y
300 300 300
290
mA
(TA = 0 to +70°C)
–
–
(NOP)
280 280 280
260 260 260
Industrial
310 310
300 300
280 280
VDDQ
–
–
–
(TA = –40 to +85°C) -E40Y
-E50Y
Output HIGH voltage VOH(Low) |IOH| ≤ 0.1 mA
VOH Note2
VDDQ – 0.2
VDDQ/2–0.12
VSS
–
–
–
–
V
V
V
V
4, 5
4, 5
4, 5
4, 5
VDDQ/2+0.12
0.2
Output LOW voltage VOL(Low) IOL ≤ 0.1 mA
VOL Note3
VDDQ/2–0.12
VDDQ/2+0.12
Notes 1. VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA, Cycle = MAX.
2. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) ±15 % for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) ±15 % for values of 175 Ω ≤ RQ ≤ 350 Ω.
4. AC load current is higher than the shown DC values.
5. HSTL outputs meet JEDEC HSTL Class I and standards.
Capacitance (TA = 25°C, f = 1MHz)
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
MIN.
TYP.
MAX.
Unit
pF
Input capacitance (Address, Control)
Input / Output capacitance
(DQ, CQ, CQ#)
4
6
5
7
CI/O
VI/O = 0 V
pF
Clock Input capacitance
Cclk
Vclk = 0 V
5
6
pF
Remark These parameters are periodically sampled and not 100% tested.
Thermal Resistance
Parameter
Thermal resistance
Symbol
Test conditions
MIN.
TYP.
25.1
MAX.
Unit
θ j-a
°C/W
(junction – ambient)
Thermal resistance
(junction – case)
θ j-c
2.8
°C/W
Remark These parameters are simulated under the condition of air flow velocity = 1 m/s.
Data Sheet M17767EJ3V0DS
18
μPD44164082A, 44164092A, 44164182A, 44164362A
AC Characteristics (VDD = 1.8 ± 0.1 V)
AC Test Conditions (VDD = 1.8 ± 0.1 V, VDDQ = 1.4 V to VDD)
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
0.75 V
Test Points
0.25 V
Output waveform
V
DDQ / 2
Test Points
VDDQ / 2
Output load condition
Figure 1. External load at test
VDDQ / 2
0.75 V
50 Ω
V
REF
ZO = 50 Ω
SRAM
250 Ω
ZQ
Data Sheet M17767EJ3V0DS
19
μPD44164082A, 44164092A, 44164182A, 44164362A
<R>
Read and Write Cycle
-E33
Parameter
Symbol
-E37, -E37Y -E40, -E40Y -E50, -E50Y Unit Note
(270 MHz) (250 MHz) (200 MHz)
(300 MHz)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock
Average Clock cycle time (K, K#, C, C#)
Clock phase jitter (K, K#, C, C#)
Clock HIGH time (K, K#, C, C#)
Clock LOW time (K, K#, C, C#)
Clock HIGH to Clock# HIGH
(K→K#, C→C#)
TKHKH
TKC var
TKHKL
TKLKH
TKHK#H
3.3
–
8.4
0.2
–
3.7
−
8.4
0.2
−
4.0
–
8.4
0.2
–
5.0
–
8.4
0.2
–
ns
ns
ns
ns
ns
1
2
1.32
1.32
1.49
1.5
1.5
1.7
1.6
1.6
1.8
2.0
2.0
2.2
–
−
–
–
–
−
–
–
Clock# HIGH to Clock HIGH
(K#→K, C#→C)
TK#HKH
1.49
–
1.7
−
1.8
–
2.2
–
ns
ns
Clock to data clock
270 to 300 MHz TKHCH
250 to 270 MHz
200 to 250 MHz
167 to 200 MHz
133 to 167 MHz
< 133 MHz
0
1.45
1.65
1.8
2.3
2.8
3.55
–
–
–
1.65
1.8
2.3
2.8
3.55
–
–
–
–
–
–
–
(K→C, K#→C#)
0
0
–
–
0
0
0
0
0
0
1.8
2.3
2.8
3.55
–
–
0
–
2.3
2.8
3.55
–
0
0
0
0
0
0
0
0
DLL/PLL lock time (K, C)
K static to DLL/PLL reset
TKC lock
1,024
30
1,024
30
1,024
30
1,024
30
Cycle
ns
3
4
TKC reset
–
–
–
–
Output Times
C, C# HIGH to output valid
C, C# HIGH to output hold
TCHQV
TCHQX
–
– 0.45
–
0.45
–
−
−0.45
−
0.45
−
–
– 0.45
–
0.45
–
–
– 0.45
–
0.45
–
ns
ns
ns
ns
ns
ns
ns
ns
C, C# HIGH to echo clock valid
C, C# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
C HIGH to output High-Z
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
0.45
–
0.45
−
0.45
–
0.45
–
– 0.45
–
−0.45
−
– 0.45
–
– 0.45
–
0.27
–
0.3
−
0.3
–
0.35
–
5
5
– 0.27
–
−0.3
−
– 0.3
–
– 0.35
–
0.45
–
0.45
−
0.45
–
0.45
–
C HIGH to output Low-Z
TCHQX1
– 0.45
−0.45
– 0.45
– 0.45
Setup Times
Address valid to K rising edge
Synchronous load input (LD#),
read write input (R, W#) valid to
K rising edge
TAVKH
TIVKH
0.4
0.4
–
–
0.5
0.5
−
−
0.5
0.5
–
–
0.6
0.6
–
–
ns
ns
6
6
Data inputs and write data select
inputs (BWx#, NWx#) valid to
K, K# rising edge
TDVKH
0.3
–
0.35
−
0.35
–
0.4
–
ns
6
Hold Times
K rising edge to address hold
K rising edge to
TKHAX
TKHIX
0.4
0.4
–
–
0.5
0.5
−
−
0.5
0.5
–
–
0.6
0.6
–
–
ns
ns
6
6
synchronous load input (LD#),
read write input (R, W#) hold
K, K# rising edge to data inputs and
write data select inputs (BWx#, NWx#)
hold
TKHDX
0.3
–
0.35
−
0.35
–
0.4
–
ns
6
Data Sheet M17767EJ3V0DS
20
μPD44164082A, 44164092A, 44164182A, 44164362A
<R>
Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.5 clock in
this operation. The AC/DC characteristics cannot be guaranteed, however.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.
DLL/PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
<R>
K
TKC reset
or
K
TKC reset
5. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
6. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
Data Sheet M17767EJ3V0DS
21
μPD44164082A, 44164092A, 44164182A, 44164362A
Read and Write Timing
READ
NOP
READ
NOP
NOP
WRITE
WRITE
READ
(burst of 2)
(burst of 2)
(burst of 2) (burst of 2)
(burst of 2)
1
2
3
4
5
6
7
8
9
10
TKHKH
K
TKHKL TKLKH
TKLKH
TKHK#H
TK#HKH
K#
LD#
TIVKH
TKHIX
R, W#
TAVKH TKHAX
A0
Address
DQ
A1
A2
A3
A4
TKHDX
TKHDX
TDVKH
TDVKH
D21
D22
D31
D32
Q01 Q02 Q11
TCHQX
Q12
Qx2
Q41 Q42
TCQHQX
TCQHQV
TCHQX1
TCHQV
TCHQZ
TCHQX
TKHCH
TKHCH
TCHQV
CQ
TCHCQX
TCHCQV
CQ#
C
TCHCQX
TCHCQV
TKHKL TKLKH TKHKH TKHK#H TK#HKH
C#
Remarks 1. Q01 refers to output from address A0.
Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled (high impedance) 2.5 clocks after the last READ (LD# = LOW, R, W# = HIGH) is
input in the sequences of [READ]-[NOP].
3. The second NOP cycle at the cycle “5” is not necessary for correct device operation;
however, at high clock frequencies it may be required to prevent bus contention.
Data Sheet M17767EJ3V0DS
22
μPD44164082A, 44164092A, 44164182A, 44164362A
Application Example
R =
250 Ω
R =
250 Ω
ZQ
CQ#
CQ
ZQ
CQ#
CQ
. . .
SRAM#1
SRAM#4
DQ
A
DQ
A
LD# R, W# BWx# C/C# K/K#
LD# R, W# BWx# C/C# K/K#
V
t
SRAM
Controller
R
Data IO
V
t
Address
LD#
R
R, W#
BW#
SRAM#1 CQ/CQ#
V
t
R
R
SRAM#4 CQ/CQ#
V
t
Source CLK/CLK#
Return CLK/CLK#
V
t
R
R = 50 Ω
Vt = Vref
Remark AC specifications are defined at the condition of SRAM outputs, CQ, CQ# and DQ with termination.
Data Sheet M17767EJ3V0DS
23
μPD44164082A, 44164092A, 44164182A, 44164362A
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
TCK
Pin assignments
2R
Description
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
Test Mode Select. This is the command input for the TAP controller state machine.
TMS
TDI
10R
11R
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
TDO
1R
Test Data Output. This is the output side of the serial registers placed between TDI and
TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
ILI
Conditions
MIN.
–5.0
–5.0
TYP.
MAX.
+5.0
+5.0
Unit
μA
JTAG Input leakage current
JTAG I/O leakage current
0 V ≤ VIN ≤ VDD
–
–
ILO
0 V ≤ VIN ≤ VDDQ,
μA
Outputs disabled
JTAG input HIGH voltage
JTAG input LOW voltage
JTAG output HIGH voltage
VIH
VIL
1.3
–0.3
1.6
1.4
–
–
–
–
–
–
–
VDD+0.3
V
V
V
V
V
V
+0.5
–
VOH1
VOH2
VOL1
VOL2
| IOHC | = 100 μA
| IOHT | = 2 mA
IOLC = 100 μA
IOLT = 2 mA
–
JTAG output LOW voltage
0.2
0.4
–
Data Sheet M17767EJ3V0DS
24
μPD44164082A, 44164092A, 44164182A, 44164362A
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
0 V
0.9 V
Test Points
Output waveform
0.9 V
Test Points
0.9 V
Output load
Figure 2. External load at test
V
TT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
Data Sheet M17767EJ3V0DS
25
μPD44164082A, 44164092A, 44164182A, 44164362A
<R>
JTAG AC Characteristics
Parameter
Clock
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
tTHTH
fTF
50
–
–
–
–
–
–
20
–
ns
MHz
ns
tTHTL
tTLTH
20
20
–
ns
Output time
TCK LOW to TDO unknown
TCK LOW to TDO valid
tTLOX
tTLOV
0
–
–
–
–
ns
ns
10
Setup time
TMS setup time
TDI valid to TCK HIGH
Capture setup time
tMVTH
tDVTH
tCS
5
5
5
–
–
–
–
–
–
ns
ns
ns
Hold time
TMS hold time
tTHMX
tTHDX
tCH
5
5
5
–
–
–
–
–
–
ns
ns
ns
TCK HIGH to TDI invalid
Capture hold time
JTAG Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
tTLTH
TMS
TDI
tTHMX
tDVTH
tTHDX
tTLOV
tTLOX
TDO
Data Sheet M17767EJ3V0DS
26
μPD44164082A, 44164092A, 44164182A, 44164362A
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
ID register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Instruction register
Bypass register
ID register
Bit size
Unit
bit
3
1
bit
32
107
bit
Boundary register
bit
ID Register Definition
Part number
μPD44164082A
μPD44164092A
μPD44164182A
μPD44164362A
Organization ID [31:28] vendor revision no.
ID [27:12] part no.
0000 0000 0001 0010
0000 0000 0101 0011
0000 0000 0001 0011
0000 0000 0001 0100
ID [11:1] vendor ID no.
00000010000
ID [0] fix bit
2M x 8
2M x 9
XXXX
XXXX
XXXX
XXXX
1
1
1
1
00000010000
1M x 18
512K x 36
00000010000
00000010000
Data Sheet M17767EJ3V0DS
27
μPD44164082A, 44164092A, 44164182A, 44164362A
SCAN Exit Order
Bit
no.
1
Signal name
x9 x18 x36
Bump
ID
Bit
no.
37
38
39
40
41
42
Signal name
Bump
ID
Bit
no.
73
Signal name
x9 x18 x36
NC NC NC NC
Bump
ID
x8
x8
x9
NC
NC
x18 x36
x8
C#
C
A
6R
6P
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
10D
9E
2C
2
74 DQ4 DQ5 DQ11 DQ20 3E
3
6N
7P
NC DQ7 DQ17 10C
75
76
77
78
79
80
81
NC NC NC DQ29 2D
4
A
NC
NC
NC
NC DQ16 11D
NC NC NC NC
NC NC NC NC
2E
1E
5
A
7N
7R
8R
8P
NC
NC
NC
NC
9C
9D
6
A
NC NC DQ12 DQ30 2F
NC NC NC DQ21 3F
7
A
43 DQ3 DQ4 DQ8 DQ8 11B
8
A
44
45
46
47
48
49
50
51
52
53
54
NC
NC
NC
NC
NC
NC
NC DQ7 11C
NC NC NC NC
NC NC NC NC
1G
1F
9
A
9R
NC
NC
NC
NC
9B
10B
11A
Internal
9A
10 NC DQ0 DQ0 DQ0 11P
11 NC NC NC DQ9 10P
12 NC NC NC NC 10N
82 DQ5 DQ6 DQ13 DQ22 3G
CQ
–
83
84
85
86
87
88
89
NC NC NC DQ31 2G
NC NC NC NC
NC NC NC NC
1J
2J
13 NC NC NC NC
9P
A
14 NC NC DQ1 DQ11 10M
15 NC NC NC DQ10 11N
A
8B
NC NC DQ14 DQ23 3K
NC NC NC DQ32 3J
A
7C
16 NC NC NC NC
17 NC NC NC NC
9M
9N
A
A
A0
A0
6C
NC NC NC NC
NC NC NC NC
2K
1K
LD#
NC
8A
18 DQ0 DQ1 DQ2 DQ2 11L
19 NC NC NC DQ1 11M
NC
NC BW1# 7A
90 DQ6 DQ7 DQ15 DQ33 2L
55 NW0# BW0# BW0# BW0# 7B
91
92
93
94
95
96
97
NC NC NC DQ24 3L
NC NC NC NC 1M
20 NC NC NC NC
21 NC NC NC NC
9L
56
57
58
K
6B
6A
10L
K#
NC NC NC NC
1L
22 NC NC DQ3 DQ3 11K
23 NC NC NC DQ12 10K
NC
NC
NC BW3# 5B
NC NC DQ16 DQ25 3N
NC NC NC DQ34 3M
59 NW1# NC BW1# BW2# 5A
24 NC NC NC NC
25 NC NC NC NC
9J
60
61
62
63
64
65
66
67
68
69
70
71
72
R, W#
4A
5C
4B
3A
1H
1A
NC NC NC NC
1N
9K
A
A
NC NC NC NC 2M
26 DQ1 DQ2 DQ4 DQ13 10J
27 NC NC NC DQ4 11J
98 DQ7 DQ8 DQ17 DQ26 3P
99 NC NC NC DQ35 2N
A
A
A
NC
28
29 NC NC NC NC 10G
30 NC NC NC NC 9G
ZQ
11H
DLL#
CQ#
100 NC NC NC NC
101 NC NC NC NC
2P
1P
3R
4R
4P
5P
5N
5R
NC
NC
NC
NC
NC
NC
NC
NC DQ9 DQ27 2B
102
103
104
105
106
107
A
A
A
A
A
A
31 NC NC DQ5 DQ5 11F
32 NC NC NC DQ14 11G
NC
NC
NC
NC DQ18 3B
NC
NC
NC
NC
1C
1B
33 NC NC NC NC
34 NC NC NC NC
9F
10F
NC DQ10 DQ19 3D
35 DQ2 DQ3 DQ6 DQ6 11E
36 NC NC NC DQ15 10E
NC
NC
NC DQ28 3C
NC NC 1D
Data Sheet M17767EJ3V0DS
28
μPD44164082A, 44164092A, 44164182A, 44164362A
JTAG Instructions
Instructions
EXTEST
Description
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output drive is turned on and the PRELOAD data is driven onto the output pins.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is
placed in the test-logic-reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register, the bypass register is placed
between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This
allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE / PRELOAD
SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /
PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-
DR state loads the data in the RAMs input and DQ pins into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to
capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).
Although allowing the TAP to sample metastable input will not harm the device, repeatable results
cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input
data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any
other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving
the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are forced to an
inactive drive state (high impedance) and the boundary register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
Note
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
2
0
1
1
RESERVED
SAMPLE / PRELOAD
RESERVED
RESERVED
BYPASS
1
0
0
1
0
1
2
2
1
1
0
1
1
1
Notes 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
Data Sheet M17767EJ3V0DS
29
μPD44164082A, 44164092A, 44164182A, 44164362A
Output Pin States of CQ, CQ# and DQ
Instructions
Control-Register Status
Output Pin Status
CQ, CQ#
Update
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
DQ
EXTEST
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
0
1
0
1
0
1
0
1
0
1
High-Z
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
Boundary Scan
Register
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 48).
CAPTURE
Register
There are three statuses:
Update
Register
SRAM
Output
Update : Contents of the “Update Register” are output to
the output pin (QDR Pad).
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (QDR Pad).
High-Z : The output pin (QDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
Update
QDR
Pad
SRAM
SRAM
Output
Driver
High-Z
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
High-Z
JTAG ctrl
Data Sheet M17767EJ3V0DS
30
μPD44164082A, 44164092A, 44164182A, 44164362A
Boundary Scan Register Status of Output Pins CQ, CQ# and DQ
Instructions
SRAM Status
Boundary Scan Register Status
Note
CQ, CQ#
DQ
Pad
Pad
–
EXTEST
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
Pad
Pad
–
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
No definition
–
–
Pad
Pad
Internal
Internal
–
Pad
Pad
Internal
Pad
–
No definition
–
–
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
Boundary Scan
Register
CAPTURE
Register
There are two statuses:
Internal
Pad
: Contents of the output pin (QDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Register.
SRAM
Output
Update
Register
Pad
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
QDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
Data Sheet M17767EJ3V0DS
31
μPD44164082A, 44164092A, 44164182A, 44164362A
TAP Controller State Diagram
1
0
Test-Logic-Reset
0
1
1
1
Run-Test / Idle
Select-DR-Scan
0
Select-IR-Scan
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix
them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also
when the TAP controller is not used.
Data Sheet M17767EJ3V0DS
32
Test Logic Operation (Instruction Scan)
TCK
TMS
Controller
state
TDI
Instruction
Register state
IDCODE
New Instruction
Output Inactive
TDO
Test Logic (Data Scan)
TCK
TMS
Controller
state
TDI
Instruction
Register state
Instruction
IDCODE
Output Inactive
TDO
μPD44164082A, 44164092A, 44164182A, 44164362A
Package Drawing
165-PIN PLASTIC BGA (13x15)
B
E
w
S
B
ZD
ZE
11
10
9
8
A
7
6
D
5
4
3
2
1
R P N M L K J H G F E D C B A
w
S A
INDEX MARK
A
A2
y1
S
S
y
e
S
A1
(UNIT:mm)
ITEM DIMENSIONS
M
φ
φ
x
b
S A B
D
E
13.00 0.10
15.00 0.10
0.15
w
e
1.00
A
1.40 0.11
0.40 0.05
1.00
A1
A2
b
0.50 0.05
0.08
x
y
0.10
y1
ZD
ZE
0.20
1.50
0.50
P165F5-100-EQ2
Data Sheet M17767EJ3V0DS
35
μPD44164082A, 44164092A, 44164182A, 44164362A
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μPD44164082AF5-EQ2
μPD44164092AF5-EQ2
μPD44164182AF5-EQ2
μPD44164362AF5-EQ2
:
:
:
:
165-pin PLASTIC BGA (13 x 15)
165-pin PLASTIC BGA (13 x 15)
165-pin PLASTIC BGA (13 x 15)
165-pin PLASTIC BGA (13 x 15)
μPD44164082AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
μPD44164092AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
μPD44164182AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
μPD44164362AF5-EQ2-A : 165-pin PLASTIC BGA (13 x 15)
Data Sheet M17767EJ3V0DS
36
μPD44164082A, 44164092A, 44164182A, 44164362A
Revision History
Edition/
Page
Previous
edition
Type of
revision
Location
Description
Date
This
edition
(Previous edition → This edition)
3rd edition/ Throughout Throughout
Feb. 2007
Addition
⎯
-E37 (Commercial)
-E37Y, -E40Y, -E50Y (Industrial)
Text has been modified.
p.9
pp.14, 15
p.21
pp.7,8
p.13
Modification Pin Identification ZQ, DLL#, NC
Addition Byte Write Operation
Remark 2 has been added.
p.19
Modification Read and Write Cycle
Addition
Note 1 has been modified.
Note 4 has been added.
p.26
p.24
Modification JTAG AC Characteristics
JTAG AC Characteristics have been modified.
Data Sheet M17767EJ3V0DS
37
μPD44164082A, 44164092A, 44164182A, 44164362A
[ MEMO ]
Data Sheet M17767EJ3V0DS
38
μPD44164082A, 44164092A, 44164182A, 44164362A
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet M17767EJ3V0DS
39
μPD44164082A, 44164092A, 44164182A, 44164362A
•
The information in this document is current as of February, 2007. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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