UPD4616112-X [NEC]
16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION; 16M - BIT的CMOS移动指明RAM 1M - WORD 16位扩展的工作温度
| 型号： | UPD4616112-X |
| 厂家： | 
NEC |
| 描述： | 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| 文件： | 总32页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4616112-X
16M-BIT CMOS MOBILE SPECIFIED RAM
1M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
Description
The µPD4616112-X is a high speed, low power, 16,777,216 bits (1,048,576 words by 16 bits) CMOS mobile
specified RAM featuring low power static RAM compatible function and pin configuration.
The µPD4616112-X is fabricated with advanced CMOS technology using one-transistor memory cell.
The µPD4616112-X is packed in 48-pin TAPE FBGA.
Features
• 1,048,576 words by 16 bits organization
• Fast access time: 85, 95 ns (MAX.)
• Byte data control: /LB (I/O0 - I/O7), /UB (I/O8 - I/O15)
• Low voltage operation: VCC = 2.6 to 3.1 V
• Operating ambient temperature: TA = –25 to +85 °C
• Output Enable input for easy application
• Chip Enable input: /CS pin
• Standby Mode input: MODE pin
• Standby Mode1: Normal standby (Memory cell data hold valid)
• Standby Mode2: Memory cell data hold invalid
Product name
Access time
ns (MAX.)
Operating supply Operating ambient
Supply current
Voltage
temperature
°C
At operating
At standby
mA (MAX.)
35
µA (MAX.)
µPD4616112-BxxLX
85, 95
2.6 to 3.1
–25 to +85
70 / 10
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15794EJ2V0DS00 (2nd edition)
Date Published January 2002 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
2001
©
µPD4616112-X
Ordering Information
Part number
Package
Access time
ns (MAX.)
Operating
Operating
Remark
supply voltage temperature
V
°C
µPD4616112F9-B85LX-BC2
µPD4616112F9-B95LX-BC2
48-pin TAPE FBGA (8 x 6)
85
95
2.6 to 3.1
–25 to +85
B version
Marking Image
Part number
Marking (XX)
µPD4616112F9-B85LX-BC2
µPD4616112F9-B95LX-BC2
L1
L2
J
MS16M0-XX
Lot number
Index mark
2
Data Sheet M15794EJ2V0DS
µPD4616112-X
Pin Configuration
/xxx indicates active low signal.
48-pin TAPE FBGA (8 x 6)
Top View
Bottom View
A
B
C
D
E
F
G
H
1
2
3
4
5
6
6
5
4
3
2
1
6
5
4
3
2
1
1
2
3
4
5
6
A
B
C
D
E
F
MODE
I/O0
I/O2
VCC
A2
A1
A4
A0
A3
A5
/OE
/LB
A
B
C
D
E
F
/LB
/OE
A0
A3
A5
A1
A4
A6
A7
A2
MODE
I/O0
I/O2
VCC
/CS
I/O1
I/O3
I/O4
I/O5
/WE
/UB
I/O8
I/O9
GND
VCC
I/O8
I/O9
GND
VCC
/UB
/CS
I/O1
I/O3
I/O4
I/O5
/WE
A11
A6
I/O10
I/O11
I/O12
I/O13
A19
I/O10
I/O11
I/O12
I/O13
A19
A7
A17
GND
A14
A12
A9
A17
GND
A14
A12
A9
GND
I/O6
I/O7
A16
A15
A13
A16
A15
A13
A10
GND
I/O6
I/O7
GND
I/O14
I/O15
I/O14
I/O15
A18
G
G
H
A8
H
GND
A11
A10
A8
A18
A0 - A19
: Address inputs
/OE
: Output enable
: Byte data select
: Power supply
: Ground
I/O0 - I/O15 : Data inputs / outputs
/LB, /UB
VCC
/CS
: Chip Select
MODE
/WE
: Standby mode
: Write enable
GND
Remark Refer to Package Drawing for the index mark.
3
Data Sheet M15794EJ2V0DS
µPD4616112-X
Block Diagram
Standby mode control
V
CC
Refresh
control
GND
Memory cell array
16,777,216 bits
Refresh
counter
Row
decoder
A0
Address
buffer
A19
I/O0 - I/O7
Sense amplifier / Switching circuit
Column decoder
Input data
controller
Output data
controller
I/O8 - I/O15
Address buffer
/CS
MODE
/LB
/UB
/WE
/OE
4
Data Sheet M15794EJ2V0DS
µPD4616112-X
Truth Table
/CS MODE /OE
/WE
/LB
/UB
Mode
I/O
Supply current
I/O0 - I/O7
I/O8 - I/O15
H
H
L
H
L
×
×
H
L
×
×
×
×
×
×
Not selected (Standby Mode 1) High impedance High impedance
Not selected (Standby Mode 2) High impedance High impedance
ISB1
ISB2
ICCA
H
H
H
×
×
Output disable
Word read
High impedance High impedance
L
L
DOUT
DOUT
DOUT
High impedance
DOUT
L
H
L
Lower byte read
Upper byte read
Output disable
Word write
H
H
L
High impedance
H
L
High impedance High impedance
×
L
DIN
DIN
DIN
High impedance
DIN
L
H
L
Lower byte write
Upper byte write
Write abort
H
H
High impedance
H
High impedance High impedance
Caution MODE pin must be fixed to High except Standby Mode 2.
Remark ×: VIH or VIL
Initialization
The µPD4616112-X is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, before turning on the power, a 200 µs or longer wait time must precede any signal
toggling.
(2) After the wait time, read operation must be performed at least 3 times. After that, it can be normal operation.
Initialization Timing Chart
V
CC (MIN.)
V
CC
Address (Input)
V
IH (MIN.)
MODE (Input)
/CS (Input)
t
RC
t
CP
VIH (MIN.)
Wait Time
Power On
Read Operation 3 times
Normal
Operation
200 s
µ
Cautions 1. Following power application, make MODE and /CS high level during the wait time interval.
2. Following power application, make MODE high level during the wait time and three read
operations.
3. The read operation must satisfy the specs described on page 10 (Read Cycle (B Version)).
4. The address is don’t care (VIH or VIL) during read operation.
5. Read operation must be executed with toggled the /CS pin.
6. To prevent bus contention, it is recommended to set /OE to high level.
7. Do not input data to the I/O pins if /OE is low level during a read operation.
5
Data Sheet M15794EJ2V0DS
µPD4616112-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VT
Condition
Rating
Unit
V
–0.5 Note to +3.3
Input / Output voltage
Operating ambient temperature
Storage temperature
–0.5 Note to VCC + 0.4 (3.3 V MAX).
V
TA
–25 to +85
°C
°C
Tstg
–55 to +125
Note –1.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
µPD4616112-BxxLX
Unit
MIN.
MAX.
3.1
Supply voltage
VCC
VIH
VIL
TA
2.6
0.8 VCC
–0.3 Note
–25
V
V
High level input voltage
VCC+0.3
0.2 VCC
+85
Low level input voltage
V
Operating ambient temperature
°C
Note –0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Input capacitance
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
pF
CIN
VIN = 0 V
VI/O = 0 V
8
Input / Output capacitance
CI/O
10
pF
Remarks 1. VIN: Input voltage
VI/O: Input / Output voltage
2. These parameters are not 100% tested.
6
Data Sheet M15794EJ2V0DS
µPD4616112-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
µPD4616112-BxxLX
TYP.
Unit
MIN.
–1.0
–1.0
MAX.
+1.0
+1.0
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
µA
µA
ILO
VI/O = 0 V to VCC, /CS = VIH or
/WE = VIL or /OE = VIH
Operating supply current
Standby supply current
ICCA
ISB1
ISB2
VOH
VOL
/CS = VIL, Minimum cycle time, II/O = 0 mA
/CS ≥ VCC − 0.2 V, MODE ≥ VCC − 0.2 V
/CS ≥ VCC − 0.2 V, MODE ≤ 0.2 V
IOH = –0.5 mA
35
70
10
mA
µA
High level output voltage
Low level output voltage
0.8 VCC
V
V
IOL = 1 mA
0.2 VCC
Remarks 1. VIN: Input voltage
VI/O: Input / Output voltage
2. These DC characteristics are in common regardless of product classifications.
7
Data Sheet M15794EJ2V0DS
µPD4616112-X
Standby Mode State Machine
Power on
/CS = VIH
,
MODE = VIH
Wait 200
µ
s
Dummy read operation (3 times)
Initial State
/CS = VIL
/CS = VIH
MODE = VIH
,
MODE = VIH
Active
/CS = VIH
,
/CS = VIH
,
MODE = VIH
MODE = VIL
/CS = VIL
,
MODE = VIH
/CS = VIH, MODE = VIL
Standby
Mode2
Standby
Mode1
Standby Mode Characteristics
Standby Mode
Mode 1
Memory Cell Data Hold
Standby Supply Current (µA)
Valid
70 (ISB1)
10 (ISB2)
Mode 2
Invalid
8
Data Sheet M15794EJ2V0DS
µPD4616112-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ µPD4616112-B85LX, µPD4616112-B95LX ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
Vcc
0.8 Vcc
Vcc/2
Test points
Vcc/2
0.2 Vcc
GND
5ns
Output Waveform
Vcc/2
Test points
Vcc/2
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1.
Figure 1
CL: 50 pF
5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW)
ZO = 50 Ω
I/O (Output)
CL
50 Ω
V
CC/2
9
Data Sheet M15794EJ2V0DS
µPD4616112-X
Read Cycle (B version)
Parameter
Symbol
µPD4616112-B85LX
µPD4616112-B95LX
Unit
Note
MIN.
85
MAX.
10,000
10,000
10
MIN.
95
MAX.
10,000
10,000
20
Read cycle time
tRC
tRC1
tSKEW
tCP
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
Identical address read cycle time
Address skew time
85
95
/CS pulse width
10
10
Address access time
tAA
85
85
35
35
95
95
40
40
4
5
/CS access time
tACS
tOE
/OE to output valid
/LB, /UB to output valid
tBA
Output hold from address change
/CS to output in low impedance
/OE to output in low impedance
/LB, /UB to output in low impedance
/CS to output in high impedance
/OE to output in high impedance
/LB, /UB to output in high impedance
tOH
10
10
5
10
10
5
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
5
5
25
25
25
25
25
25
Notes 1. One read cycle (tRC) must satisfy the minimum value (tRC(MIN.)) and maximum value (tRC(MAX.) = 10 µs). tRC
indicates the time from the /CS low level input point or address change start point, whichever is later, to
the /CS high level input point or the next address change start point, whichever is earlier. As a result,
there are the following four conditions for tRC.
1) Time from address change start point to /CS high level input point
2) Time from address change start point to next address change start point
3) Time from /CS low level input point to next address change start point
4) Time from /CS low level input point to /CS high level input point
(address access)
(address access)
(/CS access)
(/CS access)
2. The identical address read cycle time (tRC1) is the cycle time of one read operation when performing
continuous read operations toggling /OE , /LB, and /UB with the address fixed and /CS low level. Perform
settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less.
3. tSKEW indicates the following three types of time depending on the condition.
1) When switching /CS from high level to low level, tSKEW is the time from the /CS low level input point until
the next address is determined.
2) When switching /CS from low level to high level, tSKEW is the time from the address change start point to
the /CS high level input point.
3) When /CS is fixed to low level, tSKEW is the time from the address change start point until the next address
is determined.
Since specs are defined for tSKEW only when /CS is active, tSKEW is not subject to limitations when /CS is
switched from high level to low level following address determination, or when the address is changed after
/CS is switched from low level to high level.
4. Regarding tAA and tACS, only tAA is satisfied during address access (refer to 1) and 2) of Note 1), and only
tACS is satisfied during /CS access (refer to 3) of Note 1).
5. Regarding tBA and tOE, only tBA is satisfied if /OE becomes active later than /UB and /LB, and only tOE is
satisfied if /UB and /LB become active before /OE.
10
Data Sheet M15794EJ2V0DS
µPD4616112-X
Read Cycle Timing Chart 1
t
SKEW
t
SKEW
Address (Input)
/CS (Input)
t
CP
t
RC
t
CP
t
ACS
t
CHZ
t
CLZ
/OE (Input)
t
OE
t
OHZ
t
OLZ
/LB, /UB (Input)
t
BA
t
BHZ
OH
t
BLZ
t
High impedance
Data out
I/O (Output)
t
RC
t
SKEW
t
SKEW
Address (Input)
/CS (Input)
t
CP
t
CP
t
ACS
t
CHZ
t
CLZ
/OE (Input)
t
OE
t
OHZ
t
OLZ
/LB, /UB (Input)
t
BA
t
BHZ
t
BLZ
High impedance
Data out
I/O (Output)
Caution If the address is changed using a value that is either lower than the minimum value or higher than
the maximum value for the read cycle time (tRC), none of the data can be guaranteed.
Remark In read cycle, /WE should be fixed to High.
11
Data Sheet M15794EJ2V0DS
Read Cycle Timing Chart 2
t
RC
t
RC
t
SKEW
t
SKEW
t
SKEW
t
SKEW
Address (Input)
/CS (Input)
t
CP
t
RC
t
RC
t
CP
t
RC
t
ACS
t
AA
t
AA
t
CLZ
t
CHZ
t
ACS
t
CHZ
t
ACS
t
CHZ
t
CLZ
t
CLZ
/OE (Input)
t
OE
t
t
OLZ
t
OHZ
/LB, /UB (Input)
I/O (Output)
t
BA
t
BHZ
t
BHZ
t
OH
t
BA
t
BHZ
t
BA
t
OH
BLZ
t
OH
t
BLZ
t
BLZ
High impedance
Data out
Data out
Data out
Data out
Data out
µ
µ
Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle
time (tRC), none of the data can be guaranteed.
Remark In read cycle, /WE should be fixed to High.
Read Cycle Timing Chart 3
t
RC
t
RC
t
RC
tRC
t
RC
t
SKEW
t
SKEW
t
SKEW
tSKEW
t
SKEW
Address (Input)
/CS (Input)
t
ACS
t
AA
t
AA
t
CLZ
t
OE
t
OE
tOE
/OE (Input)
t
t
OHZ
t
OHZ
t
t
OHZ
t
OLZ
t
OLZ
t
OLZ
t
BA
tBA
/LB (Input)
BHZ
BHZ
t
OH
t
OH
t
BLZ
tBLZ
Hi-Z
I/O0~7 (Output)
/UB (Input)
Data out
Data out
t
BA
t
BA
t
BHZ
t
BHZ
t
OH
t
OH
t
BLZ
tBLZ
High impedance
Data out
Data out
I/O8~15 (Output)
µ
µ
Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle
time (tRC), none of the data can be guaranteed.
Remark In read cycle, /WE should be fixed to High.
µPD4616112-X
Read Cycle Timing Chart 4
t
RC
t
SKEW
t
SKEW
Address (Input)
Note
Note
t
RC1
t
RC1
t
ACS
/CS (Input)
/OE (Input)
t
OE
t
OE
t
OLZ
t
OLZ
t
OHZ
t
OHZ
t
BA
t
BA
t
BLZ
t
BLZ
/LB, /UB (Input)
I/O (Output)
t
BHZ
t
BHZ
Data out
Data out
High impedance
High impedance
Caution If the address is changed using a value that is either lower than the minimum value or higher than
the maximum value for the read cycle time (tRC), none of the data can be guaranteed.
Note To perform a continuous read toggling /OE, /UB, and /LB with /CS low level at an identical address, make
settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less.
Remark In read cycle, /WE should be fixed to High.
14
Data Sheet M15794EJ2V0DS
µPD4616112-X
Write Cycle (B version)
Parameter
Symbol
µPD4616112-B85LX
µPD4616112-B95LX
Unit
Note
MIN.
85
MAX.
10,000
10,000
10
MIN.
95
MAX.
10,000
10,000
20
Write cycle time
tWC
tWC1
tSKEW
tCW
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
Identical address write cycle time
Address skew time
85
95
/CS to end of write
40
30
35
30
20
10
0
50
35
45
35
20
10
0
/LB, /UB to end of write
Address valid to end of write
Write pulse width
tBW
tAW
tWP
Write recovery time
tWR
tCP
5
/CS pulse width
Address setup time
tAS
Byte write hold time
tBWH
tDW
20
20
0
20
25
0
Data valid to end of write
Data hold time
tDH
/OE to output in low impedance
/WE to output in high impedance
/OE to output in high impedance
Output active from end of write
tOLZ
tWHZ
tOHZ
tOW
5
5
25
25
25
25
5
5
Notes 1. One write cycle (tWC) must satisfy the minimum value (tWC(MIN.)) and the maximum value (tWC(MAX.) = 10 µs).
tWC indicates the time from the /CS low level input point or address change start point, whichever is after,
to the /CS high level input point or the next address change start point, whichever is earlier. As a result,
there are the following four conditions for tWC.
1) Time from address change start point to /CS high level input point
2) Time from address change start point to next address change start point
3) Time from /CS low level input point to next address change start point
4) Time from /CS low level input point to /CS high level input point
2. The identical address read cycle time (tWC1) is the cycle time of one write cycle when performing continuous
write operations with the address fixed and /CS low level, changing /LB and /UB at the same time, and
toggling /WE, as well as when performing a continuous write toggling /LB and /UB. Make settings so that
the sum (tWC) of the identical address write cycle times (tWC1) is 10 µs or less.
3. tSKEW indicates the following three types of time depending on the condition.
1) When switching /CS from high level to low level, tSKEW is the time from the /CS low level input point until
the next address is determined.
2) When switching /CS from low level to high level, tSKEW is the time from the address change start point to
the /CS high level input point.
3) When /CS is fixed to low level, tSKEW is the time from the address change start point until the next address
is determined.
Since specs are defined for tSKEW only when /CS is active, tSKEW is not subject to limitations when /CS is
switched from high level to low level following address determination, or when the address is changed after
/CS is switched from low level to high level.
15
Data Sheet M15794EJ2V0DS
µPD4616112-X
4. Definition of write start and write end
/CS
/WE
L
/LB, /UB
L
Status
Write start pattern 1
Write start pattern 2
Write start pattern 3
Write end pattern 1
Write end pattern 2
H to L
If /WE, /LB, /UB are low level, time when /CS
changes from high level to low level
L
L
L
L
H to L
L
If /CS, /LB, /UB are low level, time when /WE
changes from high level to low level
L
L to H
L
H to L
L
If /CS, /WE are low level, time when /LB or
/UB changes from high level to low level
If /CS, /WE, /LB, /UB are low level, time when
/WE changes from low level to high level
When /CS, /WE, /LB, /UB are low level, time
when /LB or /UB changes from low level to
high level
L to H
5. Definition of write end recovery time (tWR)
1) Time from write end to address change start point, or from write end to /CS high level input point
2) When /CS, /LB, /UB are low level and continuously written to the identical address, time from /WE high
level input point to /WE low level input point
3) When /CS, /WE are low level and continuously written to the identical address, time from /LB or /UB
high level input point, whichever is later, to /LB or /UB low level input point, whichever is earlier.
4) When /CS is low level and continuously written to the identical address, time from write end to point at
which /WE , /LB, or /UB starts to change from high level to low level, whichever is earliest.
16
Data Sheet M15794EJ2V0DS
µPD4616112-X
Write Cycle Timing Chart 1
t
WC
tWC
t
SKEW
tSKEW
Address (Input)
t
CW
t
CW
t
CP
/CS (Input)
/WE (Input)
t
WP
t
AS
tWP
t
WR
tWR
t
AS
t
BW
t
BW
/LB, /UB (Input)
I/O (Input)
t
DW
tDH
t
DW
tDH
High impedance
High impedance
Data in
Data in
t
SKEW
t
SKEW
tSKEW
t
WC
t
WC
Address (Input)
t
CW
t
CW
t
CP
/CS (Input)
/WE (Input)
t
WP
tWP
t
WR
tWR
t
BW
t
BW
/LB, /UB (Input)
I/O (Input)
t
DW
tDH
t
DW
tDH
High impedance
High impedance
Data in
Data in
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
17
Data Sheet M15794EJ2V0DS
µPD4616112-X
Write Cycle Timing Chart 2 (/WE Controlled)
t
WC
t
WC
tWC
t
SKEW
t
SKEW
t
SKEW
t
SKEW
tSKEW
Address (Input)
t
CP
t
AW
t
AW
t
CW
/CS (Input)
/WE (Input)
t
AS
tAS
t
WR
tWR
t
WP
t
WP
t
WP
tWR
t
AS
t
AW
t
OW
t
t
WHZ
/OE (Input)
t
OLZ
OHZ
t
DW
t
DH
t
DW
t
DH
t
DW
tDH
Indefinite
data out
I/O (Input / Output)
Data in
Data in
Data in
High impedance
High impedance
High impedance
High
High
impedance
impedance
t
WC
t
SKEW
tSKEW
Address (Input)
/CS (Input)
Note
Note
t
WC1
t
WC1
t
AS
t
WP
t
WR
t
WP
tWR
/WE (Input)
t
BW
/LB, /UB (Input)
t
DW
t
DH
t
DW
tDH
I/O (Input)
Data in
Data in
High impedance
High impedance
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE
is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs or
less.
Remarks 1. Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
2. When /WE is at Low, the I/O pins are always high impedance. When /WE is at High, read operation is
executed. Therefore /OE should be at High to make the I/O pins high impedance.
18
Data Sheet M15794EJ2V0DS
µPD4616112-X
Write Cycle Timing Chart 3 (/CS Controlled)
Address (Input)
t
WC
t
WC
/CS (Input)
t
AS
t
WR
t
WR
t
CW
t
AS
t
CW
/WE (Input)
/LB, /UB (Input)
t
DW
t
DH
t
DW
t
DH
Data in
Data in
I/O (Input)
High impedance
High impedance
High impedance
Address (Input)
t
WC
t
WC
/CS (Input)
/WE (Input)
t
AS
t
WR
t
WR
t
CW
t
AS
t
CW
/LB, /UB (Input)
I/O (Input)
t
DW
t
DH
t
DW
t
DH
Data in
Data in
High impedance
High impedance
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
19
Data Sheet M15794EJ2V0DS
µPD4616112-X
Write Cycle Timing Chart 4 (/LB, /UB Controlled 1)
t
WC
t
WC
t
SKEW
t
SKEW
Address (Input)
/CS (Input)
t
CW
t
AW
t
WP
/WE (Input)
t
AS
t
BW
t
WR
t
AS
t
BW
t
WR
/LB, /UB (Input)
t
DW
t
DH
t
DW
t
DH
High impedance
High impedance
I/O (Input)
Data in
Data in
t
WC
t
SKEW
t
WC
t
SKEW
Address (Input)
/CS (Input)
t
AW
t
CW
t
WP
/WE (Input)
t
AS
t
BW
t
AS
t
BW
t
WR
t
WR
/LB, /UB (Input)
t
DW
t
DH
t
DW
t
DH
High impedance
High impedance
I/O (Input)
Data in
Data in
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
20
Data Sheet M15794EJ2V0DS
µPD4616112-X
Write Cycle Timing Chart 5 (/LB, /UB Controlled 2)
t
WC
t
SKEW
t
SKEW
Address (Input)
Note
WC1
Note
t
t
WC1
/CS (Input)
/WE (Input)
t
WP
t
AS
t
BW
t
WR
t
BW
t
WR
/LB, /UB (Input)
I/O (Input)
t
DW
t
DH
t
DW
t
DH
Data in
Data in
High impedance
High impedance
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE
is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs or
less.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
21
Data Sheet M15794EJ2V0DS
µPD4616112-X
Write Cycle Timing Chart 6 (/LB, /UB Independent Controlled 1)
t
WC
Address (Input)
Note
Note
WC1
t
WC1
t
/CS (Input)
/WE (Input)
t
CW
WP
t
/LB (Input)
t
AS
t
BW
t
WR
t
WR
t
BW
/UB (Input)
t
DW
t
DH
Data in
I/O0 - 7 (Input)
I/O8 - 15 (Input)
High impedance
High impedance
High impedance
t
DW
t
DH
Data in
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Note If /LB and /UB are changed at the same time with /CS low level and a continuous write operation toggling /WE
is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs or
less.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
22
Data Sheet M15794EJ2V0DS
µPD4616112-X
Write Cycle Timing Chart 7 (/LB, /UB Independent Controlled 2)
Address (Input)
t
WC
/CS (Input)
t
CW
t
CW
t
WP
t
WP
/WE (Input)
/LB (Input)
t
BW
t
WR
t
AS
t
BWH
t
WR
t
BW
/UB (Input)
I/O0 - 7 (Input)
I/O8 - 15 (Input)
t
AS
t
DW
t
DH
Data in
High impedance
High impedance
High impedance
t
DW
t
DH
Data in
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
23
Data Sheet M15794EJ2V0DS
µPD4616112-X
Read Write Cycle (B version)
Parameter
Read write cycle time
Byte write setup time
Byte read setup time
Symbol
tRWC
MIN.
MAX.
Unit
ns
Note
1, 2
10,000
tBWS
20
20
ns
tBRS
ns
Notes 1. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB
following a read using /LB with /CS low level, or when a write is performed using /LB following a read using
/UB.
2. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1) is 10 µs or less when a read is performed at the identical address using /UB
following a write using /LB with /CS low level, or when a read is performed using /LB following a write using
/UB.
24
Data Sheet M15794EJ2V0DS
µPD4616112-X
Read Write Cycle Timing Chart 1 (/LB, /UB Independent Controlled 1)
t
RWC
Address (Input)
Note
Note
WC1
t
RC1
t
t
AA
/CS (Input)
/WE (Input)
t
ACS
t
WP
t
BWS
/LB (Input)
t
WR
t
BW
/UB (Input)
t
CLZ
t
BLZ
t
BHZ
Data out
I/O0 - 7 (Output)
I/O8 - 15 (Input)
High impedance
High impedance
High impedance
t
DW
t
DH
Data in
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1), none of the data can be guaranteed.
Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address
write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a
read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
25
Data Sheet M15794EJ2V0DS
µPD4616112-X
Read Write Cycle Timing Chart 2 (/LB, /UB Independent Controlled 2)
tRWC
Address (Input)
Note
Note
tWC1
tRC1
tCW
/CS (Input)
tWR
tWP
/WE (Input)
tBW
/LB (Input)
tAS
tBRS
/UB (Input)
tDW
tDH
Data in
I/O0 - 7 (Input)
High impedance
High impedance
tBA
tBHZ
tBLZ
Data out
I/O8 - 15 (Output)
High impedance
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1), none of the data can be guaranteed.
Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address
write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a
read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
26
Data Sheet M15794EJ2V0DS
µPD4616112-X
Read Write Cycle Timing Chart 3 (/LB, /UB Independent Controlled 3)
t
RWC
Address (Input)
Note
WC1
Note
RC1
t
t
t
CW
/CS (Input)
/WE (Input)
t
WR
t
WP
t
AS
t
BW
/LB (Input)
/UB (Input)
t
DW
t
DH
Data in
I/O0 - 7 (Input)
I/O8 - 15 (Output)
High impedance
High impedance
t
BA
t
BHZ
t
BLZ
Data out
High impedance
High impedance
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1), none of the data can be guaranteed.
Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address
write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a
read using /LB with /CS low level, or when a write is performed using /LB following a read using /UB.
Remark Write operation is done during the overlap time of a Low /CS, /WE, /LB and/or /UB.
27
Data Sheet M15794EJ2V0DS
µPD4616112-X
Standby Mode 2 entry and recovery Timing Chart
Address (Input)
MODE (Input)
t
RC
t
CP
/CS (Input)
t
CM
Read Operation 3 times
Wait Time 200
µ
s
Standby
Mode 2
Normal
Operation
(Data invalid)
Parameter
/CS High to MODE Low
Symbol
tCM
MIN.
0
MAX.
Unit
ns
Note
Cautions 1. Make MODE and /CS high level during the wait time.
2. Make MODE high level during the wait time and three read operations.
3. The read operation must satisfy the specs described on page 10 (Read Cycle (B Version)).
4. The read operation address can be either VIH or VIL.
5. Perform reading by toggling /CS.
6. To prevent bus contention, it is recommended to set /OE to high level.
7. Do not input data to the I/O pins if /OE is low level during a read operation.
28
Data Sheet M15794EJ2V0DS
µPD4616112-X
Package Drawing
48-PIN TAPE FBGA (8x6)
ZE
E
ZD
B
w
S B
6
5
4
3
2
1
A
D
H G F E D C B A
INDEX MARK
INDEX MARK
w
S A
A
A2
y1
S
S
e
y
S
A1
A B
M
φ
φ
x
b
S
ITEM MILLIMETERS
6.0±0.1
8.0±0.1
0.2
D
E
w
e
0.75
A
0.94±0.10
0.24±0.05
0.70
A1
A2
b
0.40±0.05
0.08
x
y
0.1
y1
ZD
ZE
0.2
1.125
1.375
P48F9-75-BC2
29
Data Sheet M15794EJ2V0DS
µPD4616112-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD4616112-X.
Type of Surface Mount Device
µPD4616112F9-BxxLX-BC2: 48-pin TAPE FBGA (8 x 6)
30
Data Sheet M15794EJ2V0DS
µPD4616112-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
31
Data Sheet M15794EJ2V0DS
µPD4616112-X
•
The information in this document is current as of January, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
相关型号：
UPD4616112F9-B85LX-BC2
16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
NEC
UPD4616112F9-B95LX-BC2
16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
NEC
©2020 ICPDF网 联系我们和版权申明