UPD703040YGM [NEC]
V850/SV1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS; V850 / SV1TM 32位/ 16位单芯片微控制器
| 型号： | UPD703040YGM |
| 厂家： | 
NEC |
| 描述： | V850/SV1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| 文件： | 总44页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
V850/SV1TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703039, 703039Y, 703040, 703040Y, 703041, and 703041Y (collectively known as the V850/SV1) are
products in the low-power series of V850 FamilyTM products, which are NEC’s single-chip microcontrollers for real-
time control.
The V850/SV1 employs the CPU core of the V850 Family, and has on-chip peripheral functions such as large
capacity ROM/RAM, a multi-function timer/counter, serial interface, A/D converter, DMA controller, PWM, and a
Vsync/Hsync separation circuit.
The V850/SV1 not only realizes the low power consumption necessary for applications such as camcorders, but
also extremely high cost performance.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SV1 User’s Manual Hardware
: U14462E
V850 Family User’s Manual Architecture : U10243E
FEATURES
{ 10-bit resolution A/D converter: 16 channels
{ Number of instructions: 74
{ Timer/counter
{ Minimum instruction execution time:
62.5 ns (@ 16 MHz operation with main system clock)
24-bit: 2 channels, 16-bit: 2 channels
8-bit: 8 channels
30.5 µs (@ 32.768 kHz operation with subsystem clock) { Watch timer: 1 channel
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set (signed multiplication, saturation
{ Watchdog timer: 1 channel
{ DMA controller: 6 channels
operations, 32-bit shift instructions, bit manipulation { Interrupts and exceptions
instructions, load/store instructions)
{ Memory space:
Non-maskable interrupt: 2 sources
Maskable interrupt
16 MB linear address space
Memory block allocation function: 2 MB per block
{ External bus: 16-bit multiplexed bus
{ Internal memory:
: µPD703039, 703040, 703041 (51 sources)
: µPD703039Y, 703040Y, 703041Y (52 sources)
Software exception: 32 sources
Exception trap: 1 source
µPD703039, 703039Y
{ Serial interface (SIO)
(ROM: 256 KB, RAM: 8 KB)
µPD703040, 703040Y
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
(ROM: 256 KB, RAM: 16 KB)
µPD703041, 703041Y
3-wire variable length serial interface (CSI4)
I2C bus interface (I2C) (µPD703039Y, 703040Y,
703041Y)
(ROM: 192 KB, RAM: 8 KB)
{ I/O lines Total: 151
{ RTP: 8 bits × 2 channels or 4 bits × 4 channels
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U13953EJ1V0DS00 (1st edition)
Date Published March 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
2000
©
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
{ PWM output: 4 channels
{ Vsync/Hsync separation circuit
{ On-chip key return function
{ On-chip clock generator
{ Power saving function: HALT/IDLE/STOP modes
{ ROM correction: 4 points changeable
{ Package: 176-pin plastic LQFP (24 × 24 mm)
APPLICATIONS
{ System/servo/camera control of camcorders
{ Portable cameras such as digital still cameras
{ Cellular phones, portable information terminals, etc.
ORDERING INFORMATION
Part Number
Package
µPD703039GM-×××-UEU
µPD703039YGM-×××-UEU
µPD703040GM-×××-UEU
µPD703040YGM-×××-UEU
µPD703041GM-×××-UEU
µPD703041YGM-×××-UEU
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
Remark ××× indicates ROM code suffix.
DIFFERENCES BETWEEN V850/SV1 PRODUCTS
Internal ROM
Internal RAM
I2C
VPP Pin
None
µPD703039
µPD703039Y
µPD703040
µPD703040Y
µPD703041
µPD703041Y
µPD70F3040
µPD70F3040Y
256 KB (mask ROM)
8 KB
None
Provided
None
16 KB
8 KB
Provided
None
192 KB (mask ROM)
Provided
None
256 KB (flash memory)
16 KB
Provided
Provided
2
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
PIN CONFIGURATION
176-pin plastic LQFP (fine pitch) (24 × 24 mm)
µPD703039GM-×××-UEU
µPD703039YGM-×××-UEU
µPD703040GM-×××-UEU
µPD703040YGM-×××-UEU
µPD703041GM-×××-UEU
µPD703041YGM-×××-UEU
P12/SCK0/SCL0Note 2
P13/SI1/RXD0
P14/SO1/TXD0
P15/SCK1/ASCK0
P20/SI2/SDA1Note 2
P21/SO2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
2
3
4
5
6
P22/SCK2/SCL1Note 2
P23/SI3/RXD1
P24/SO3/TXD1
P25/SCK3/ASCK1
P26/TI2/TO2
P27/TI3/TO3
VDD
7
8
P80/ANI8
9
P77/ANI7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
VSS
P72/ANI2
P30/TI000
P31/TI001
P32/TI010
P33/TI011
P34/TO0
P71/ANI1
P70/ANI0
P147
P146
P145/RTPTRG1
P144/TI9/INTTI9
P143/INTCP93
P142/INTCP92
P141/INTCP91
P140/INTCP90
P137/TO81
P136/TO80
P135/TCLR8/INTTCLR8
P134/TI8/INTTI8
P133/INTCP83
P132/INTCP82
P131/INTCP81
P130/INTCP80
VSS
P35/TO1
P36/TI4/TO4
P37/TI5/TO5
P120/SI4
P121/SO4
P122/SCK4
P123/CLO
P124/TI6/TO6
P125/TI7/TO7
P126/TI10/TO10
P127/TI11/TO11
P180
P181
P182
P183
VDD
P184
98
P07/INTP6
P06/INTP5/RTPTRG0
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P185
97
P186
96
P187
95
VDD
94
VSS
93
P190
92
P191
91
P192
90
P157/RTP17
P156/RTP16
P193
89
Notes 1. Connect directly to VSS.
2. SCL0, SCL1, SDA0, and SDA1 are valid for the µPD703039Y, 703040Y, and 703041Y only.
3
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
PIN IDENTIFICATION
A16 to A21:
AD0 to AD15:
ADTRG:
ANI0 to ANI15:
ASCK0, ASCK1:
ASTB:
Address Bus
P110 to P113:
P120 to P127:
P130 to P137:
P140 to P147:
P150 to P157:
P160 to P167:
P170 to P177:
P180 to P187:
P190 to P197:
PWM0 to PWM3:
RD:
Port 11
Address/Data Bus
AD Trigger Input
Port 12
Port 13
Analog Input
Port 14
Asynchronous Serial Clock
Address Strobe
Port 15
Port 16
AVDD:
Analog Power Supply
Analog Reference Voltage
Analog Ground
Port 17
AVREF:
Port 18
AVSS:
Port 19
BVDD:
Bus Interface Power Supply
Bus Interface Ground
Clock Output
Pulse Width Modulation
Read
BVSS:
CLKOUT:
CLO:
RESET:
Reset
Clock Output (divided)
Csync Input
RTP00 to RTP07,:
RTP10 to RTP17
Real-time Output Port
CSYNCIN:
DSTB:
Data Strobe
RTPTRG0, RTPTRG1: RTP Trigger Input
HLDAK:
HLDRQ:
Hold Acknowledge
Hold Request
R/W:
Read/Write Status
Receive Data
Serial Clock
Serial Clock
Serial Data
RXD0, RXD1:
SCK0 to SCK4:
SCL0, SCL1:
SDA0, SDA1:
SI0 to SI4:
SO0 to SO4:
TCLR8:
HSOUT0, HSOUT1: Hsync Output
IC:
Internally Connected
INTCP80 to INTPC83,: Interrupt Request from Peripherals
INTCP90 to INTCP93,
INTP0 to INTP6,
INTTCLR8,
Serial Input
Serial Output
Timer Clear
INTTI8, INTTI9
TI000, TI001, TI010,: Timer Input
TI011, TI2 to TI11
KR0 to KR7:
LBEN:
Key Return
Lower Byte Enable
TO0 to TO7, TO80,: Timer Output
TO81, TO10, TO11
NMI:
Non-Maskable Interrupt Request
P00 to P07:
P10 to P15:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P65:
P70 to P77:
P80 to P87:
P90 to P96:
P100 to P107:
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
TXD0,TXD1:
UBEN:
VDD:
Transmit Data
Upper Byte Enable
Power Supply
VSOUT:
VSS:
Vsync Output
Ground
WAIT:
Wait
WRH:
Write Strobe High Level Data
Write Strobe Low Level Data
Crystal for Main System Clock
Crystal for Subsystem Clock
WRL:
X1, X2:
XT1, XT2:
4
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
INTERNAL BLOCK DIAGRAM
NMI
INTP0 to INTP6
ROM
CPU
INTC
HLDRQ
HLDAK
INTCP80 to INTCP83,
INTCP90 to INTCP93
INTTCLR8
Instruction
queue
ROM correction
PC
Note 1
ASTB
INTTI8, INTTI9
TI000, TI001,
32-bit barrel
shifter
Timer/counter
16-bit timers
: TM0, TM1
8-bit timers
: TM2 to TM7,
TM10, TM11
24-bit timers
: TM8, TM9
DSTB/RD
R/W/WRH
UBEN
LBEN/WRL
WAIT
A16 to A21
AD0 to AD15
Multiplier
16 × 16 → 32
TI010, TI011
TO0, TO1
System
register
BCU
RAM
TO80, TO81
TI8, TI9
ALU
General registers
32 bits × 32
TCLR8
Note 2
TI2/TO2, TI3/TO3
TI4/TO4, TI5/TO5
TI6/TO6, TI7/TO7
TI10/TO10, TI11/TO11
CSYNCIN
Vsync/Hsync
SIO
HSOUT0, HSOUT1,
VSOUT
SO0
SI0/SDA0Note 3
SCK0/SCL0Note 3
SO2
CSI0/I2C0Note 4
CSI2/I2C1Note 4
CSI1/UART0
CSI3/UART1
CLKOUT
CLO
X1
Ports
A/D
converter
SI2/SDA1Note 3
SCK2/SCL1Note 3
SO1/TXD0
SI1/RXD0
X2
CG
XT1
XT2
RESET
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
V
V
BVDD
BVSS
IC
DD
SS
Variable
length CSI4
SI4
SCK4
Watch timer
KR0 to KR7
Key return function
DMAC: 6 ch
PWM
Watchdog timer
RTP00 to RTP07,
RTP10 to RTP17
RTPTRG0,
RTP
PWM0 to PWM3
RTPTRG1
Notes 1. µPD703039, 703039Y, 703040, 703040Y: 256 KB
µPD703041, 703041Y: 192 KB
2. µPD703039, 703039Y, 703041, 703041Y: 8 KB
µPD703040, 703040Y: 16 KB
3. SDA0, SDA1, SCL0, and SCL1 are valid for the µPD703039Y, 703040Y, and 703041Y only.
4. The I2C function is valid for the µPD703039Y, 703040Y, and 703041Y only.
5
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
CONTENTS
1. PIN FUNCTIONS.................................................................................................................................. 7
1.1 Port Pins....................................................................................................................................................7
1.2 Non-Port Pins...........................................................................................................................................11
1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins .......................14
2. ELECTRICAL SPECIFICATIONS...................................................................................................... 18
3. PACKAGE DRAWING ....................................................................................................................... 37
4. RECOMMENDED SOLDERING CONDITIONS................................................................................ 38
6
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1. PIN FUNCTIONS
1.1 Port Pins
(1/4)
Pin Name
P00
I/O
I/O
PULL
Yes
Function
Alternate Function
NMI
Port 0
8-bit I/O port
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
INTP0
Input/output mode can be specified in 1-bit units.
INTP1
INTP2
INTP3
INTP4/ADTRG
INTP5/RTPTRG0
INTP6
I/O
Yes
Port 1
SI0/SDA0
SO0
6-bit I/O port
Input/output mode can be specified in 1-bit units.
SCK0/SCL0
SI1/RXD0
SO1/TXD0
SCK1/ASCK0
SI2/SDA1
SO2
I/O
Yes
Port 2
8-bit I/O port
Input/output mode can be specified in 1-bit units.
SCK2/SCL1
SI3/RXD1
SO3/TXD1
SCK3/ASCK1
TI2/TO2
TI3/TO3
TI000
I/O
Yes
Port 3
8-bit I/O port
TI001
Input/output mode can be specified in 1-bit units.
TI010
TI011
TO0
TO1
TI4/TO4
TI5/TO5
AD0
I/O
No
Port 4
8-bit I/O port
AD1
Input/output mode can be specified in 1-bit units.
AD2
AD3
AD4
Remark PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
7
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(2/4)
Pin Name
P45
I/O
I/O
PULL
No
Function
Alternate Function
AD5
Port 4
8-bit I/O port
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
P60
P61
P62
P63
P64
P65
P70
P71
P72
P73
P74
P75
P76
P77
P80
P81
P82
P83
P84
P85
P86
P87
P90
P91
P92
P93
AD6
Input/output mode can be specified in 1-bit units.
AD7
I/O
No
Port 5
AD8
8-bit I/O port
AD9
Input/output mode can be specified in 1-bit units.
AD10
AD11
AD12
AD13
AD14
AD15
A16
I/O
No
Port 6
6-bit I/O port
A17
Input/output mode can be specified in 1-bit units.
A18
A19
A20
A21
Input
No
Port 7
ANI0
8-bit input port
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Input
No
Port 8
ANI8
8-bit input port
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
LBEN/WRL
UBEN
R/W/WRH
DSTB/RD
I/O
No
Port 9
7-bit I/O port
Input/output mode can be specified in 1-bit units.
Remark PULL: on-chip pull-up resistor
8
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(3/4)
Pin Name
P94
I/O
I/O
PULL
No
Function
Alternate Function
ASTB
Port 9
7-bit I/O port
P95
HLDAK
HLDRQ
RTP00
RTP01
RTP02
RTP03
RTP04
RTP05
RTP06
RTP07
Input/output mode can be specified in 1-bit units.
P96
P100
P101
P102
P103
P104
P105
P106
P107
P110
P111
P112
P113
P120
P121
P122
P123
P124
P125
P126
P127
P130
P131
P132
P133
P134
P135
P136
P137
P140
P141
P142
P143
P144
P145
P146
P147
I/O
Yes
Port 10
8-bit I/O port
Input/output mode can be specified in 1-bit units.
I/O
I/O
No
No
Port 11
–
–
–
–
4-bit I/O port
Input/output mode can be specified in 1-bit units.
Port 12
SI4
8-bit I/O port
SO4
Input/output mode can be specified in 1-bit units.
SCK4
CLO
TI6/TO6
TI7/TO7
TI10/TO10
TI11/TO11
INTCP80
INTCP81
INTCP82
INTCP83
TI8/INTTI8
TCLR8/INTTCLR8
TO80
I/O
No
Port 13
8-bit I/O port
Input/output mode can be specified in 1-bit units.
TO81
I/O
No
Port 14
INTCP90
INTCP91
INTCP92
INTCP93
TI9/INTTI9
RTPTRG1
–
8-bit I/O port
Input/output mode can be specified in 1-bit units.
–
Remark PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
9
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(4/4)
Pin Name
P150
I/O
I/O
PULL
No
Function
Alternate Function
RTP10
Port 15
8-bit I/O port
P151
P152
P153
P154
P155
P156
P157
P160
P161
P162
P163
P164
P165
P166
P167
P170
P171
P172
P173
P174
P175
P176
P177
P180
P181
P182
P183
P184
P185
P186
P187
P190
P191
P192
P193
P194
P195
P196
P197
RTP11
RTP12
RTP13
RTP14
RTP15
RTP16
RTP17
PWM0
PWM1
PWM2
PWM3
CSYNCIN
VSOUT
HSOUT0
HSOUT1
KR0
Input/output mode can be specified in 1-bit units.
I/O
I/O
I/O
I/O
No
Yes
No
Port 16
8-bit I/O port
Input/output mode can be specified in 1-bit units.
Port 17
8-bit I/O port
KR1
Input/output mode can be specified in 1-bit units.
KR2
KR3
KR4
KR5
KR6
KR7
Port 18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
8-bit I/O port
Input/output mode can be specified in 1-bit units.
No
Port 19
8-bit I/O port
Input/output mode can be specified in 1-bit units.
Remark PULL: on-chip pull-up resistor
10
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1.2 Non-Port Pins
(1/3)
Pin Name
A16 to A21
AD0 to AD7
AD8 to AD15
ADTRG
I/O
PULL
No
Function
Alternate Function
P60 to P65
P40 to P47
P50 to P57
P05/INTP4
P70 to P77
P80 to P87
P15/SCK1
P25/SCK3
P94
Output
I/O
Address bus 16 to 21
No
Address/data multiplexed bus 0 to 15
Input
Input
Input
Input
Yes
No
A/D converter external trigger input
Analog input to A/D converter
ANI0 to ANI7
ANI8 to ANI15
ASCK0
No
Yes
Baud rate clock input for UART0 and UART1
External address strobe signal output
ASCK1
ASTB
Output
–
No
–
AVDD
Positive power supply for A/D converter and ports used for
alternate functions
–
AVREF
AVSS
Input
–
–
–
Reference voltage input for A/D converter
–
–
Ground potential for A/D converter and ports used for alternate
functions
BVDD
BVSS
–
–
–
–
Positive power supply for bus interface and ports used for
alternate functions
–
–
Ground potential for bus interface and ports used for alternate
functions
CLKOUT
CLO
Output
Output
Input
–
Internal system clock output
CLO output signal
–
P123
No
No
No
No
No
No
CSYNCIN
DSTB
Csync signal input
P164
Output
Output
Input
External data strobe signal output
Bus hold acknowledge output
Bus hold request input
P93/RD
P95
HLDAK
HLDRQ
HSOUT0
HSOUT1
IC
P96
Output
Hsync signal output before revision
Hsync signal output after revision
Internal connection (connect directly to VSS)
External capture input for CC80 to CC83
P166
P167
–
–
–
INTCP80 to
INTCP83
Input
No
P130 to P133
INTCP90 to
INTCP93
Input
Input
No
External capture input for CP90 to CP93
P140 to P143
INTP0 to INTP3
INTP4
Yes
External interrupt request input (digital noise elimination)
External interrupt request input (digital noise elimination)
P01 to P04
P05/ADTRG
P06/RTPTRG0
P07
INTP5
INTP6
External interrupt request input (digital noise elimination
supporting remote controller)
Remark PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
11
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(2/3)
Pin Name
INTTCLR8
INTTI8
I/O
PULL
No
Function
Alternate Function
P135/TCLR8
P134/TI8
P144/TI9
P170 to P177
P90/WRL
P00
Input
Input
External interrupt request input (digital noise elimination)
No
INTTI9
KR0 to KR7
LBEN
Input
Output
Input
Yes
No
Yes
No
No
–
Key return input
Lower byte enable signal output for external data bus
Non-maskable interrupt request input
Output of PWM channels 0 to 3
Bus read strobe signal output
System reset input
NMI
PWM0 to PWM3 Output
P160 to P163
P93/DSTB
–
RD
Output
Input
RESET
RTP00 to RTP07 Output
RTP10 to RTP17
Yes
Real-time output port
P100 to P107
P150 to P157
P06
RTPTRG0
RTPTRG1
R/W
Input
Yes
No
RTP external trigger input
P146
Output
Input
No
External read/write status output
P92/WRH
P13/SI1
RXD0
RXD1
SCK0
SCK1
SCK2
SCK3
SCK4
SCL0
SCL1
SDA0
SDA1
SI0
Yes
Serial receive data input for UART0 and UART1
P23/SI3
I/O
Yes
Serial clock I/O for CSI0 to CSI3 (3-wire mode)
P12/SCL0
P15/ASCK0
P22/SCL1
P25/ASCK1
P122
No
Variable-length CSI4 serial clock I/O
I/O
I/O
Yes
Serial clock I/O for I2C0 and I2C1
P12/SCK0
P22/SCK2
P10/SI0
(µPD703039Y, 703040Y and 703041Y)
Yes
Yes
Serial transmit/receive data I/O for I2C0 and I2C1
(µPD703039Y, 703040Y and 703041Y)
P20/SI2
Input
Serial receive data input for CSI0 to CSI3 (3-wire mode)
P10/SDA0
P13/RXD0
P20/SDA1
P23/RXD1
P120
SI1
SI2
SI3
SI4
No
Variable-length CSI4 serial receive data input (3-wire mode)
Serial transmit data output for CSI0 to CSI3
SO0
Output
Yes
P11
SO1
P14/TXD0
P21
SO2
SO3
P24/TXD1
P121
SO4
No
No
Variable-length CSI4 serial transmit data output
External clear input for TM8
TCLR8
TI000
Input
Input
P135/INTTCLR8
P30
Yes
External count clock input/external capture trigger input for TM0
Remark PULL: on-chip pull-up resistor
12
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(3/3)
Pin Name
TI001
I/O
PULL
Yes
Function
External capture trigger input for TM0
External count clock input/external capture trigger input for TM1
External capture trigger input for TM1
External count clock input for TM2
External count clock input for TM3
External count clock input for TM4
External count clock input for TM5
External count clock input for TM6
External count clock input for TM7
External count clock input for TM8
External count clock input for TM9
External count clock input for TM10
External count clock input for TM11
Pulse signal output for TM0
Alternate Function
P31
Input
TI010
TI011
TI2
P32
P33
P26/TO2
P27/TO3
P36/TO4/A15
P37/TO5
P124/TO6
P125/TO7
P134/INTTI8
P144/INTTI9
P126/TO10
P127/TO11
P34
TI3
TI4
TI5
TI6
No
TI7
TI8
TI9
TI10
TI11
TO0
TO1
TO2
TO3
TO4
TO5
TO6
TO7
TO80
TO81
TO10
TO11
TXD0
TXD1
UBEN
VDD
Output
Yes
Pulse signal output for TM1
P35
Pulse signal output for TM2
P26/TI2
P27/TI3
P36/TI4
P37/TI5
P124/TI6
P125/TI7
P136
Pulse signal output for TM3
Pulse signal output for TM4
Pulse signal output for TM5
No
Pulse signal output for TM6
Pulse signal output for TM7
Pulse signal output 0 for TM8
Pulse signal output 1 for TM8
P137
Pulse signal output for TM10
P126/TI10
P127/TI11
P14/SO1
P24/SO3
P91
Pulse signal output for TM11
Output
Yes
Serial transmit data output for UART0 and UART1
Output
–
No
–
Higher byte enable signal output for external data bus
Positive power supply pin
–
VSOUT
VSS
Output
–
No
–
Vsync signal output
P165
Ground potential
–
WAIT
WRH
WRL
X1
Input
Output
No
No
External WAIT signal input
–
Higher byte write strobe signal output for external data bus
Lower byte write strobe signal output for external data bus
Resonator connection for main system clock
P92/R/W
P90/LBEN
–
Input
–
No
No
X2
–
XT1
XT2
Input
–
Resonator connection for subsystem clock
–
–
Remark PULL: on-chip pull-up resistor
Preliminary Data Sheet U13953EJ1V0DS00
13
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins
Table 1-1 shows the I/O circuit type of each pin and the recommended connection of unused pins.
For the input/output configuration of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (1/2)
Pin
Alternate Function
I/O Circuit
Type
I/O Buffer
Recommended Connection Method
Power Supply
P00
NMI
5-W
VDD
Input:
Independently connect to VDD or VSS
via a resistor
P01 to P04
P05
INTP0 to INTP3
INTP4/ADTRG
INTP5/RTPTRG0
INTP6
Output: Leave open
P06
P07
P10
SI0/SDA0
SO0
10-F
10-E
10-F
5-W
10-E
10-F
10-F
10-E
10-F
5-W
10-E
10-F
5-W
5-W
VDD
P11
P12
SCK0/SCL0
SI1/RXD0
SO1/TXD0
SCK1/ASCK0
SI2/SDA1
SO2
P13
P14
P15
P20
VDD
P21
P22
SCK2/SCL1
SI3/RXD1
SO3/TXD1
SCK3/ASCK1
TI2/TO2, TI3/TO3
TI000, TI001
TI010, TI011
TO0, TO1
TI4/TO4
P23
P24
P25
P26, P27
P30, P31
P32, P33
P34, P35
P36
VDD
5-A
5-W
P37
TI5/TO5
P40 to P47
P50 to P57
P60 to P65
P70 to P77
P80 to P87
P90
AD0 to AD7
AD8 to AD15
A16 to A21
ANI0 to ANI7
ANI8 to ANI15
LBEN/WRL
UBEN
5
5
5
9
9
5
BVDD
BVDD
BVDD
AVDD
AVDD
BVDD
Input:
Independently connect to BVDD or BVSS
via a resistor
Output: Leave open
Connect to AVSS
Input:
Independently connect to BVDD or BVSS
via a resistor
Output: Leave open
P91
P92
R/W/WRH
DSTB/RD
ASTB
P93
P94
P95
HLDAK
P96
HLDRQ
P100 to P107
P110 to P113
P120
RTP00 to RTP07
–
10-E
5
VDD
VDD
VDD
Input:
Independently connect to VDD or VSS
via a resistor
Output: Leave open
SI4
5-K
14
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (2/2)
Pin
Alternate Function
I/O Circuit
Type
I/O Buffer
Recommended Connection Method
Power Supply
P121
P122
P123
P124
P125
P126
P127
SO4
10-G
10-H
5
VDD
Input:
Independently connect to VDD or VSS
via a resistor
SCK4
Output: Leave open
CLO
TI6/TO6
5-K
TI7/TO7
TI10/TO10
TI11/TO11
P130 to P133
P134
INTCP80 to INTCP83
5-K
VDD
TI8/INTTI8
P135
TCLR8/INTTCLR8
P136, P137
P140 to P143
P144
TO80, TO81
5
INTCP90 to INTCP93
5-K
VDD
TI9/INTTI9
P145
RTPTRG1
P146, P147
P150 to P157
P160 to P163
P164
–
5
RTP10 to RTP17
5
VDD
VDD
PWM0 to PWM3
5
CSYNCIN
5-K
5
P165
VSOUT
P166
HSOUT0
P167
HSOUT1
P170 to P177
P180 to P187
P190 to P197
CLKOUT
WAIT
KR0 to KR7
5-K
5
5
4
1
2
–
–
–
–
–
–
–
–
–
–
–
–
VDD
VDD
VDD
BVDD
BVDD
VDD
VDD
VDD
VDD
VDD
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Leave open
Connect to VDD via a resistor
–
RESET
X1
–
X2
Leave open
Connect to VSS
Leave open
Connect to AVSS
Connect directly to VSS
–
XT1
XT2
AVREF
IC
–
VDD
–
VSS
–
–
AVDD
–
Connect to VDD
Connect to VSS
Connect to VDD
Connect to VSS
AVSS
–
BVDD
–
BVSS
–
Preliminary Data Sheet U13953EJ1V0DS00
15
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Figure 1-1. Pin Input/Output Circuits (1/2)
Type 1
Type 5
V
DD
V
DD
Data
P-ch
P-ch
IN/OUT
IN
Output
disable
N-ch
N-ch
Input
enable
Type 2
Type 5-A
V
DD
Pullup
enable
P-ch
V
DD
Data
P-ch
N-ch
IN
IN/OUT
Output
disable
Input
Schmitt-triggered input with hysteresis characteristics
Type 4
enable
Type 5-K
V
DD
V
DD
Data
P-ch
N-ch
Data
P-ch
IN/OUT
OUT
Output
disable
Output
disable
N-ch
Input
enable
Push-pull output that can be set for high impedance output
(both P-ch and N-ch are off)
16
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Figure 1-1. Pin Input/Output Circuits (2/2)
Type 5-W
Type 10-F
V
DD
V
DD
Pullup
enable
Pullup
enable
P-ch
P-ch
V
DD
V
DD
Data
Data
P-ch
P-ch
IN/OUT
IN/OUT
Open
Output
disable
Output
disable
N-ch
N-ch
Input
Input
enable
enable
Type 9
Type 10-G
VDD
P-ch
N-ch
Data
P-ch
N-ch
Comparator
+
–
IN
IN/OUT
Open drain
V
REF (Threshold voltage)
Output
disable
Input enable
Input
enable
Type 10-E
Type 10-H
V
DD
V
DD
Pullup
enable
Data
P-ch
P-ch
N-ch
V
DD
IN/OUT
Data
P-ch
Open drain
Output
disable
IN/OUT
Open
Output
N-ch
disable
Input
enable
Input
enable
Preliminary Data Sheet U13953EJ1V0DS00
17
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
Unit
V
–0.5 to +4.6
AVDD
BVDD
AVSS
BVSS
VI1
–0.5 to +4.6
V
–0.5 to +4.6
V
–0.5 to +0.5
V
–0.5 to +0.5
V
Input voltage
Note 1 (V
DD)
–0.5 to VDD + 0.5Note 4
V
VI2
Note 2 (BVDD)
–0.5 to BVDD + 0.5Note 4
V
Clock input voltage
VK
X1, XT1, VDD = 2.7 to 3.6 V
Note 3 (AV
–0.5 to V
DD + 1.0Note 4
Analog input voltage
Analog reference input voltage
Output current, low
VIAN
AVREF
IOL
DD)
–0.5 to AVDD + 0.5Note 4
V
AVREF pin
–0.5 to AV
DD + 0.5Note 4
V
Per pin
4.0
25
25
25
25
25
25
mA
mA
mA
mA
mA
mA
mA
Total for P00 to P07, P150 to P157
Total for P100 to P107, P160 to P167
Total for P170 to P177, P190 to P197
Total for P124 to P127, P180 to P187
Total for P30 to P37, P120 to P123
Total for P12 to P15, P20 to P27, P110 to
P113
Total for P50 to P57, P60 to P65, CLKOUT
Total for P40 to P47, P90 to P96
Total for P130 to P137, P140 to P147
Per pin
25
25
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
25
Output current, high
IOH
–4.0
–25
–25
–25
–25
–25
–25
Total for P00 to P07, P150 to P157
Total for P100 to P107, P160 to P167
Total for P170 to P177, P190 to P197
Total for P124 to P127, P180 to P187
Total for P30 to P37, P120 to P123
Total for P12 to P15, P20 to P27, P110 to
P113
Total for P50 to P57, P60 to P65, CLKOUT
Total for P40 to P47, P90 to P96
–25
–25
–25
mA
mA
mA
V
Total for P130 to P137, P140 to P147
Output voltage
VO1
VO2
TA
Note 1 (V
DD)
–0.5 to V + 0.5
DD
Note 2 (BV
DD)
–0.5 to BV + 0.5
DD
V
Operating ambient temperature
Storage temperature
–40 to +85
°C
°C
Tstg
–65 to +150
Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, RESET (includes alternate function pins)
2. Ports 4, 5, 6, 9, CLKOUT, WAIT (includes alternate function pins)
18
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3. Ports 7, 8 (includes alternate function pins)
4. Be sure not to exceed each absolute maximum rating (MAX.).
Cautions 1. Do not directly connect to each other output pins (or I/O pins) of IC products, and do not
connect them directly to VDD, VCC, or GND. However, open-drain pins and open-connector
pins can be directly connected to each other. Moreover, external circuits that implement a
timing that avoids conflict with the output of pins that go into high-impedance can be
directly connected.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
fC = 1 MHz
Unmeasured pins returned to 0 V
I/O capacitance
CIO
15
pF
Output capacitance
CO
15
pF
Operating Conditions
(1) CPU Operation Frequency
Parameter
Symbol
fCPU
Conditions
@ main system clock operation
@ subsystem clock operation
MIN.
0.5
TYP.
MAX.
16
Unit
MHz
MHz
CPU operation frequency
32.768
(2) Supply Voltage
Parameter
Symbol
VDD
Conditions
MIN.
2.7
TYP.
MAX.
3.6
Unit
V
Supply voltage
AVDD
BVDD
2.7
3.6
V
2.7
3.6
V
(3) Operation Frequency for Each Supply Voltage
Internal Operation Clock Frequency
4 MHz ≤ fXX ≤ 16 MHz
Supply Voltage (VDD = AVDD = BVDD)
2.7 to 3.6 V
2.7 to 3.6 V
fXT = 32.768 kHz
Preliminary Data Sheet U13953EJ1V0DS00
19
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Recommended Oscillator
(1) Main System Clock Oscillator (TA = −40 to +85°C)
X2
X1
Parameter
Symbol
fXX
Conditions
MIN.
4
TYP.
MAX.
16
Unit
MHz
s
Oscillation frequency
Oscillation stabilization
time
After reset release
219/fXX
After STOP mode release
Note
s
Note Values vary depending on the settings of the oscillation stabilization time selection register (OSTS).
Remarks 1. Place the oscillator as close as possible to X1 and X2.
2. Do not wire other signal lines within the broken lines.
3. For resonator selection and oscillation constants, customers are advised to either evaluate the
oscillation themselves, or apply to the resonator manufacturer for evaluation.
(2) Subsystem Clock Oscillator (TA = −40 to +85°C)
XT1
XT2
Parameter
Symbol
fXT
Conditions
MIN.
32
TYP.
32.768
10
MAX.
35
Unit
kHz
s
Oscillation frequency
Oscillation stabilization time
Remarks 1. Place the oscillator as close as possible to XT1 and XT2.
2. Do not wire other signal lines within the broken lines.
3. For resonator selection and oscillation constants, customers are advised to either evaluate the
oscillation themselves, or apply to the resonator manufacturer for evaluation.
20
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
DC Characteristics (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
VIH1
VIH2
VIH3
VIH4
VIH5
VIL1
Conditions
Pins in Note 1 , WAIT
MIN.
0.7BVDD
0.7VDD
TYP.
MAX.
BVDD
Unit
V
Input voltage, high
Pins in Note 2
VDD
V
Pins in Note 3, RESET
Pins in Note 4
0.75VDD
0.7AVDD
0.8VDD
VDD
V
AVDD
V
X, XT1, XT2
VDD
V
Input voltage, low
Pins in Note 1 , WAIT
Pins in Note 2
BVSS – 0.5
VSS – 0.5
VSS – 0.5
AVSS – 0.5
VSS
0.3BVDD
0.3VDD
0.3VDD
0.3AVDD
0.2VDD
V
VIL2
V
VIL3
Pins in Note 3, RESET
Pins in Note 4
V
VIL4
V
VIL5
X, XT1, XT2
V
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VOL2
Note 1, CLKOUT
Notes 2, 3
IOH = –3 mA
0.8BVDD
0.8VDD
V
IOH = –1 mA
IOL = 1.6 mA
IOL = 1.6 mA
V
Note 1, CLKOUT
0.4
0.4
V
Notes 2, 3 (except
V
P10, 12, 20, 22)
VOL3
ILIH1
ILIH2
ILIL1
ILIL2
ILOH
ILOL
IDD1
IDD2
IDD3
IDD4
P10, 12, 20, 22
IOL = 3 mA
0.4
5
V
Input leakage current, high
Input leakage current, low
VI = VDD = AVDD =
BVDD
Other than X1, XT1, XT2
X1, XT1, XT2
µA
µA
µA
µA
µA
µA
mA
mA
mA
µA
20
–5
–20
5
VI = 0 V
Other than X1, XT1, XT2
X1, XT1, XT2
Output leakage current, high
Output leakage current, low
Supply currentNote 5
VO = VDD = AVDD = BVDD
VO = 0 V
–5
55
30
4
Normal operation mode (fXX = 16 MHz)
HALT mode (fXX = 16 MHz)
IDLE mode (fXX = 16 MHz)
25
14
1.2
10
STOP mode (subsystem clock operation: fXT
= 32.768 kHz, watch timer operation)
70
STOP mode (subsystem clock stopped)
1
60
µA
kΩ
Pull-up resistor
RL
10
30
100
Notes 1. Ports 4, 5, 6, 9 (includes alternate-function pins)
2. P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147,
P150 to P157, P160 to P163, P165 to P167, P180 to P187, P190 to P197 (includes alternate-function
pins)
3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124
to P127, P130 to P135, P140 to P145, P164, P170 to P177 (includes alternate-function pins)
4. Ports 7, 8 (includes alternate-function pins)
5. The typical values listed are those of at VDD = 3.3 V. The current that is consumed at output buffers is
not included.
Preliminary Data Sheet U13953EJ1V0DS00
21
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Data Retention Characteristics (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Data retention voltage
Data retention current
Symbol
VDDDR
IDDDR
tRVD
Conditions
STOP mode
MIN.
1.8
TYP.
MAX.
3.6
Unit
V
VDDDR [V]
1
60
µA
µs
Supply voltage rising time
Supply voltage falling time
200
200
0
tFVD
µs
Supply voltage hold time
(from STOP mode setting)
tHVD
ms
STOP release signal input time
tDREL
VIHDR
VILDR
0
VIHn
0
ms
V
Data retention high-level input voltage
Data retention low-level input voltage
All input port
All input port
VDDDR
VILn
V
Remark n = 1 to 5
Setting STOP mode
t
FVD
t
RVD
V
DD
V
DDDR
t
HVD
t
DREL
RESET
(input)
V
V
IHDR
NMI, INTP0 to INTP3
(input)
IHDR
STOP release interrupt (NMI, etc.)
(when STOP mode is released
at rising edge)
V
ILDR
Caution Be sure to shift to and return from STOP mode when VDD is 2.7 V or higher.
22
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
AC Characteristics
AC Test Input Waveforms (VDD, BVDD, AVDD)
V
DD
V
V
IH
IL
V
IH
Test points
V
IL
0 V
AC Test Output Test Point (BVDD)
V
V
OH
V
OH
Test points
OL
V
OL
Load Conditions
DUT
(Device under test)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load
capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Preliminary Data Sheet U13953EJ1V0DS00
23
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Clock Timing
Operating Conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
X1 input cycle
Symbol
tCYX
Condition
MIN.
62.5
28.6
31.2
14.3
31.2
14.3
MAX.
Unit
ns
µs
ns
µs
ns
µs
ns
ns
<1>
<2>
<3>
250
XT1 input cycle
31.2
125
X1 input high-level width
XT1 input high-level width
X1 input low-level width
XT1 input low-level width
X1 input rise time
tWXH
15.6
tWXL
125
15.6
tXR
tXF
<4>
<5>
<6>
<7>
<8>
<9>
<10>
(<1> – <2> – <3>)/2
(<1> – <2> – <3>)/2
31.2 µs
X1 input fall time
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
tCYK
tWKH
tWKL
tKR
62.5 ns
0.4(T – 20)
0.4(T – 20)
ns
ns
ns
ns
10
10
CLKOUT fall time
tKF
Remark T = tCYK
Clock Timing
<1>
<3>
<2>
X1, XT1 (input)
<4>
<5>
<6>
<7>
<8>
CLKOUT (output)
<9>
<10>
Timing of Pins Other Than X1 and CLKOUT Pins
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, Output Pin Load Capacitance: CL
= 50 pF)
Parameter
Symbol
tOR
Condition
MIN.
MAX.
20
Unit
ns
Output rise time
Output fall time
tOF
20
ns
24
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Bus Timing (CLKOUT Asynchronous)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Address float from DSTB↓
tSAST
tHSTA
tFDA
<11>
<12>
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
<29>
<30>
<31>
<32>
<33>
<34>
<35>
<36>
<37>
<38>
0.5T – 20
0.5T – 15
2
Data input setup time from address
Data input setup time from DSTB↓
DSTB↓ delay time from ASTB↓
Data input hold time (from DSTB↑)
Address output time from DSTB↑
ASTB↑ delay time from DSTB↑
ASTB↓ delay time from DSTB↑
DSTB low-level width
tDAID
(2 + n)T – 30
(1 + n)T – 30
tDDID
tDSTD
0.5T – 15
0
tHDID
tDDA
(1 + i)T – 15
0.5T – 15
(1.5 + i)T – 15
(1 + n)T – 15
T – 15
tDDST1
tDDST2
tWDL
ASTB high-level width
tWSTH
tDDOD
tSODD
tHDOD
tSAWT1
tSAWT2
tHAWT1
tHAWT2
tSSTWT1
tSSTWT2
tHSTWT1
tHSTWT2
tWHQH
tWHAL
tDHAC
Data output time from DSTB↓
Data output setup time (to DSTB↑)
Data output hold time (from DSTB↑)
WAIT setup time (to address)
15
(1 + n)T – 20
T – 15
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
1.5T – 30
(1.5 + n)T – 30
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
(0.5 + n)T
(1.5 + n)T
1.5T – 25
(1.5 + n)T – 25
nT + 5
(1 + n)T + 5
T + 10
T – 15
0
HLDRQ high-level width
HLDAK low-level width
Bus output delay time from HLDAK↑
HLDAK↓ delay time from HLDRQ↓
HLDAK↑ delay time from HLDRQ↑
tDHQHA1
tDHQHA2
1.5T
(2n + 7.5)T + 25
1.5T + 25
0.5T
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
Sampling timing changes when a programmable wait is inserted.
3. i: Number of idle states inserted after the read cycle (0 or 1).
4. The specifications described above are the values of when a clock of duty ratio 1:1 is input from X1.
Preliminary Data Sheet U13953EJ1V0DS00
25
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Bus Timing (CLKOUT Synchronous)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
tDKA
Condition
MIN.
0
MAX.
19
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address delay time from CLKOUT↑
Address float delay time from CLKOUT↑
ASTB↓ delay time from CLKOUT↓
DSTB↑ delay time from CLKOUT↑
Data input setup time (to CLKOUT↑)
Data input hold time (from CLKOUT↑)
Data output delay time from CLKOUT↑
WAIT setup time (to CLKOUT↓)
<39>
<40>
<41>
<42>
<43>
<44>
<45>
<46>
<47>
<48>
<49>
<50>
<51>
tFKA
tDKST
tDKD
–12
–12
–5
7
14
tSIDK
tHKID
tDKOD
tSWTK
tHKWT
tSHQK
tHKHQ
tDKF
15
5
19
15
5
WAIT hold time (from CLKOUT↓)
HLDRQ setup time (to CLKOUT↓)
HLDRQ hold time (from CLKOUT↓)
Address float delay time from CLKOUT↑
HLDAK delay time from CLKOUT↑
15
5
19
19
tDKHA
Remark The specifications described above are the values of when a clock of duty ratio 1:1 is input from X1.
26
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<39>
A16 to A21 (output), Note
<14>
<43> <44>
Data
<40>
Hi-Z
AD0 to AD15 (I/O)
ASTB (output)
Address
<41>
<41>
<12>
<11>
<17>
<22>
<42>
<16>
<19>
<13>
<15>
<18>
<20>
<42>
DSTB (output),
RD (output)
<21>
<46> <47>
<30> <46> <47>
<32>
<31>
<33>
WAIT (input)
<26>
<28>
<27>
<29>
Note R/W (output), UBEN (output), LBEN (output)
Remark WRL and WRH are high level.
Preliminary Data Sheet U13953EJ1V0DS00
27
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<39>
A16 to A21 (output), Note
<45>
AD0 to AD15 (I/O)
ASTB (output)
Address
Data
<41>
<11>
<41>
<12>
<22>
<19>
<42>
<16>
<42>
<23>
<24>
<25>
DSTB (output),
WRL (output),
WRH (output)
<21>
<46> <47>
<30> <46> <47>
<32>
<31>
<33>
WAIT (input)
<26>
<28>
<27>
<29>
Note R/W (output), UBEN (output), LBEN (output)
Remark RD is high level.
28
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Bus Hold
TH
TH
TH
TI
CLKOUT (output)
HLDRQ (input)
<48>
<48> <49>
<34>
<51>
<51>
<37>
<38>
HLDAK (output)
<50>
<35>
<36>
Hi-Z
A16 to A21 (output), Note
AD0 to AD15 (I/O)
ASTB (output)
Data
Hi-Z
Hi-Z
Hi-Z
DSTB (output), RD (output),
WRL (output), WRH (output)
Note R/W (output), UBEN (output), LBEN (output)
Preliminary Data Sheet U13953EJ1V0DS00
29
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Reset/Interrupt Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
RESET high-level width
RESET low-level width
NMI high-level width
NMI low-level width
Symbol
tWRSH
Condition
MIN.
500
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
<52>
<53>
<54>
<55>
<56>
tWRSL
tWNIH
tWNIL
tWITH
500
500
500
INTPn high-level width
n = 0 to 3, analog noise elimination
n = 4, 5, digital noise elimination
n = 6, digital noise elimination
n = 0 to 3, analog noise elimination
n = 4, 5, digital noise elimination
n = 6, digital noise elimination
500
3T + 20
3Tsmp + 20
500
INTPn low-level width
tWITL
<57>
3T + 20
3Tsmp + 20
Remarks 1. T = 1/fXX
2. Tsmp = Noise elimination sampling clock frequency
Reset
<52>
<53>
RESET (input)
Interrupt
<54>
<55>
<57>
NMI (input)
<56>
INTPn (input)
Remark n = 0 to 6
30
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
TIn Input Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ns
TIn0, TIn1 (n = 00, 01)
high-level width
t
TIH
<58>
2T
sam + 20Note
TIn (n = 2 to 7, 10, 11)
high-level width
3/fXX + 20
sam + 20Note
ns
ns
ns
TIn0, TIn1 (n = 00, 01)
low-level width
t
TIL
<59>
2T
TIn (n = 2 to 7, 10, 11)
low-level width
3/fXX + 20
Note Tsam can be selected by setting the PRMn1 and PRMn0 bits of prescaler mode registers n0, n1 (PRMn0,
PRMn1) (n = 0, 1).
TM0 (PRM00, PRM01 registers): Tsam = 2/fXX, 4/fXX, 16/fXX, 64/fXX, 256/fXX, 1/INTWTI period
TM1 (PRM10, PRM11 registers): Tsam = 2/fXX, 4/fXX, 16/fXX, 32/fXX, 128/fXX, 256/fXX
However, when the TIn0 valid edge is selected as the count clock, Tsam = 4/fXX (n = 0, 1).
<59>
<58>
TIn
Remark n = 000, 001, 010, 011, 10, 11, 2 to 7
Preliminary Data Sheet U13953EJ1V0DS00
31
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3-Wire SIO Timing
(1) Master Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
SCKn cycle time
Symbol
Condition
MIN.
400
140
140
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY1
tKH1
tKL1
<60>
<61>
<62>
<63>
<64>
<65>
SCKn high-level width
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↓)
SOn output delay time from SCKn↓
tSIK1
tKSI1
tKSO1
50
60
Remark n = 0 to 3
(2) Slave Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
SCKn cycle time
Symbol
Condition
MIN.
400
140
140
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY2
tKH2
tKL2
<60>
<61>
<62>
<63>
<64>
<65>
SCKn high-level width
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↓)
SOn output delay time from SCKn↓
tSIK2
tKSI2
tKSO2
50
60
Remark n = 0 to 3
<60>
<61>
<62>
SCKn (I/O)
SIn (input)
<63> <64>
<65>
SOn (output)
Remark n = 0 to 3
32
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3-Wire Variable-Length CSI Timing
(1) Master Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
SCK4 cycle time
Symbol
Condition
MIN.
400
140
140
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY1
tKH1
tKL1
<66>
<67>
<68>
<69>
<70>
<71>
SCK4 high-level width
SCK4 low-level width
SI4 setup time (to SCK4↑)
SI4 hold time (from SCK4↑)
SO4 output delay time from SCK4↓
tSIK1
tKSI1
tKSO1
50
60
(2) Slave Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
SCK4 cycle time
Symbol
Condition
MIN.
400
140
140
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY2
tKH2
tKL2
<66>
<67>
<68>
<69>
<70>
<71>
SCK4 high-level width
SCK4 low-level width
SI4 setup time (to SCK4↑)
SI4 hold time (from SCK4↑)
SO4 output delay time from SCK4↓
tSIK2
tKSI2
tKSO2
50
60
<66>
<67>
<68>
SCK4 (I/O)
SI4 (input)
<69> <70>
<71>
SO4 (output)
Preliminary Data Sheet U13953EJ1V0DS00
33
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
UART Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
ASCKn cycle time
Symbol
Condition
MIN.
200
80
MAX.
Unit
ns
tKCY13
tKH13
tKL13
<72>
<73>
<74>
ASCKn high-level width
ASCKn low-level width
ns
80
ns
Remark n = 0, 1
<72>
<73>
<74>
ASCKn (input)
Remark n = 0, 1
34
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
I2C Bus Mode (Only for µPD703039Y, 703040Y, and 703041Y)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter Symbol Standard Mode
High-Speed Mode
MIN. MAX.
Unit
MIN.
MAX.
100
–
SCLn clock frequency
fCLK
tBUF
0
0
400
kHz
Bus free time
<75>
4.7
1.3
–
µs
(between stop and start conditions)
Hold timeNote 1
tHD : STA
tLOW
<76>
<77>
<78>
<79>
<80>
4.0
4.7
4.0
4.7
5.0
0Note 2
250
–
–
–
0.6
–
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
SCLn clock low-level width
SCLn clock high-level width
Setup time of start/restart conditions
1.3
–
–
tHIGH
–
0.6
tSU : STA
–
0.6
–
Data hold
time
CBUS-compatible master tHD : DAT
–
–
0Note 2
–
I2C mode
–
0.9Note 3
Data setup time
tSU : DAT
tR
Falling time of SDAn and SCLn signals tF
<81>
<82>
<83>
<84>
<85>
–
100Note 4
20 + 0.1CbNote 5
20 + 0.1CbNote 5
0.6
–
Rising time of SDAn and SCLn signals
1000
300
–
300
300
–
–
Setup time of stop condition
tSU : STO
SP
4.0
–
Pulse width of spike suppressed by
input filter
t
–
0
50
Load capacitance of bus lines
Cb
–
400
–
400
pF
Notes 1. The first clock pulse in the start condition is generated after the hold time.
2. The system must internally provide at least 300 ns hold time for the SDAn signal (at VIHmin. of the SCLn
signal) in order to fill the undefined area that appears at the SCLn falling edge.
3. If the system does not extend the low hold time (tLOW), it is required to satisfy only the maximum data
hold time (tHD: DAT).
4. The high-speed I2C bus is available in the standard mode I2C bus system. In this case, following
conditions should be satisfied.
•
•
When the system does not extend the low-state hold time of the SCLn signal
tSU: DAT ≥ 250 ns
When the system extends the low-state hold time of the SCLn signal
Before the SCLn line is released (tRmax. + tSU: DAT = 1000 + 250 = 1250 ns: Standard mode I2C bus
specification), send the next data bit to the SDAn line.
5. Cb: Total capacitance of one bus line (Unit: pF)
Remark n = 0, 1
Preliminary Data Sheet U13953EJ1V0DS00
35
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
I2C Bus Mode (Only for µPD703039Y, 703040Y, and 703041Y)
<77>
<82>
<80>
SCLn
SDAn
<78>
<83>
<79>
<81>
<85>
<84>
<76>
<76>
<75>
Restart
condition
Stop
condition
Stop
Start
condition condition
Remark n = 0, 1
A/D Converter (TA = –40 to +85°C, VDD = AVDD = AVREF = 2.7 to 3.6 V, AVSS = VSS = 0 V, Output Pin Load
Capacitance: CL = 50 pF)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Overall errorNote 1
±0.8
100
±0.4
±0.4
±4.0
±4.0
3.6
%FSR
µs
Conversion time
tCONV
5
Zero-scale errorNote 1
Full-scale errorNote 1
Integral linearity errorNote 2
Differential linearity errorNote 2
Analog reference voltage
Analog input voltage
AVREF current
%FSR
%FSR
LSB
LSB
V
AVREF
VIAN
AVREF = AVDD
2.7
AVSS
AVREF
360
3
V
AIREF
AIDD
240
1
µA
Supply current
mA
Notes 1. Excluding quantization error (±0.05%FSR)
2. Excluding quantization error (±0.5LSB)
Remark LSB: Least Significant Bit
FSR: Full Scale Range
36
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3. PACKAGE DRAWING
176-PIN PLASTIC LQFP (FINE PITCH) (24x24)
A
B
132
133
89
88
detail of lead end
S
P
T
C
D
R
L
U
Q
176
1
45
44
F
M
J
G
H
I
K
S
S
M
N
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
26.0±0.2
24.0±0.2
24.0±0.2
26.0±0.2
1.25
1.25
0.22±0.05
0.08
J
0.5 (T.P.)
1.0±0.2
0.5
K
L
+0.03
M
0.17
−0.07
0.08
N
P
Q
1.4
0.1±0.05
+4°
3°
R
S
−3°
1.5±0.1
S176GM-50-UEU
Preliminary Data Sheet U13953EJ1V0DS00
37
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
4. RECOMMENDED SOLDERING CONDITIONS
The µPD703039, 703039Y, 703040, 703040Y, 703041, and 703041Y should be soldered and mounted under the
following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 4-1. Surface Mounting Type Soldering Conditions
µPD703039GM-×××-UEU: 176-pin plastic LQFP (fine pitch) (24 × 24 mm)
µPD703040GM-×××-UEU: 176-pin plastic LQFP (fine pitch) (24 × 24 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher),
Count: Twice or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for 10
hours)
IR35-103-2
VPS
Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher),
Count: Twice or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for 10
hours)
VP15-103-2
Partial heating
Pin temperature: 300°C Max., Time 3 sec. Max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Cautions 1. Do not use different soldering methods together (except for partial heating).
2. Soldering conditions for µPD703039Y, 703040Y, 703041, and 703041Y are undetermined.
38
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
[MEMO]
Preliminary Data Sheet U13953EJ1V0DS00
39
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
[MEMO]
40
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
[MEMO]
Preliminary Data Sheet U13953EJ1V0DS00
41
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Related document
µPD70F3040, 70F3040Y Data Sheet (U14622E)
Reference document Electrical Characteristics for Microcomputer (IEI-601) Note
Note This document number is that of the Japanese version.
The documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V850 Family and V850/SV1 are trademarks of NEC Corporation.
42
Preliminary Data Sheet U13953EJ1V0DS00
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Preliminary Data Sheet U13953EJ1V0DS00
43
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8
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