UPD703102GJ-33-XXX-UEN [NEC]
Microcontroller, 32-Bit, MROM, 33MHz, MOS, PQFP144, 20 X 20 MM, PLASTIC, LQFP-144;
| 型号： | UPD703102GJ-33-XXX-UEN |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 32-Bit, MROM, 33MHz, MOS, PQFP144, 20 X 20 MM, PLASTIC, LQFP-144 微控制器 |
| 文件： | 总126页 (文件大小：735K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD703100-33, 703100-40, 703101-33, 703102-33
V850E/MS1TM
32/16-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD703101-33 and µPD703102-33 are members of the V850 FamilyTM of 32-bit single-chip microcontrollers
designed for real-time control operations. These microcontrollers provide on-chip features, including a 32-bit CPU
core, ROM, RAM, interrupt controller, real-time pulse unit, serial interface, A/D converter, and DMA controller.
The µPD703100-33 and µPD703100-40 are ROM-less versions of the µPD703101-33 and µPD703102-33
products.
The µPD703100-A33, µPD703100-A40, µPD703101-A33, and µPD703102-A33 are also available as products
having a 3.3-V power supply for external pins.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850E/MS1 User’s Manual Hardware:
U12688E
V850E/MS1 User’s Manual Architecture: U12197E
FEATURES
•
•
Number of instructions: 81
Minimum instruction execution time 25 ns (@ 40-MHz operation) ····· µPD703100-40
30 ns (@ 33-MHz operation) ····· µPD703100-33, 703101-33, 703102-33
•
•
•
General registers 32 bits × 32
Instruction set optimized for control applications
Internal memory ROM: None (µPD703100-33, 703100-40),
96 Kbytes (µPD703101-33),
128 Kbytes (µPD703102-33)
RAM : 4 Kbytes
•
•
•
•
•
•
•
Advanced on-chip interrupt controller
Real-time pulse unit suitable for control operations
Powerful serial interface (on-chip dedicated baud rate generator)
On-chip clock generator
10-bit resolution A/D converter: 8 channels
DMA controller: 4 channels
Power saving functions
APPLICATIONS
•
•
•
•
Office automation equipment: printers, facsimile machines, PPCs, etc.
Multimedia equipment: digital still cameras, video printers, etc.
Consumer equipment: single-lens reflex cameras, etc.
Industrial equipment: motor controllers, NC machine tools, etc.
The information in this document is subject to change without notice.
Document No. U13995EJ1V0DS00 (1st edition)
Date Published April 1999 N CP(K)
Printed in Japan
©
1999
µPD703100-33, 703100-40, 703101-33, 703102-33
ORDERING INFORMATION
Maximum Operating
Frequency (MHz)
Internal ROM
(bytes)
Part Number
Package
µPD703100GJ-33-8EU
µPD703100GJ-40-8EU
µPD703101GJ-33-xxx-8EU
µPD703102GJ-33-xxx-8EU
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
33 MHz
40 MHz
33 MHz
33 MHz
None
None
96 Kbytes
128 Kbytes
Remark xxx indicates ROM code suffix.
PIN CONFIGURATION (Top view)
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
•
•
µPD703100GJ-33-8EU
µPD703100GJ-40-8EU
•
•
µPD703101GJ-33-xxx-8EU
µPD703102GJ-33-xxx-8EU
INTP103/DMARQ3/P07
INTP102/DMARQ2/P06
INTP101/DMARQ1/P05
INTP100/DMARQ0/P04
TI10/P03
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
TCLR10/P02
TO101/P01
TO100/P00
V
SS
9
HVDD
INTP113/DMAAK3/P17
INTP112/DMAAK2/P16
INTP111/DMAAK1/P15
INTP110/DMAAK0/P14
TI11/P13
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CS0/RAS0/P80
CS1/RAS1/P81
CS2/RAS2/P82
CS3/RAS3/P83
CS4/RAS4/IOWR/P84
CS5/RAS5/IORD/P85
CS6/RAS6/P86
CS7/RAS7/P87
LCAS/LWR/P90
UCAS/UWR/P91
RD/P92
WE/P93
BCYST/P94
OE/P95
HLDAK/P96
HLDRQ/P97
VSS
TCLR11/P12
TO111/P11
TO110/P10
INTP123/TC3/P107
INTP122/TC2/P106
INTP121/TC1/P105
INTP120/TC0/P104
TI12/P103
TCLR12/P102
TO121/P101
TO120/P100
ANI7/P77
ANI6/P76
ANI5/P75
ANI4/P74
ANI3/P73
ANI2/P72
ANI1/P71
ANI0/P70
AVDD
AVSS
AVREF
REFRO/PX5
WAIT/PX6
CLKOUT/PX7
TO150/P120
TO151/P121
TCLR15/P122
TI15/P123
INTP150/P124
INTP151/P125
INTP152/P126
74
73
2
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
PIN NAMES
A0 to A23
ADTRG
ANI0 to ANI7
AVDD
: Address Bus
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
P100 to P107
P110 to P117
P120 to P127
PA0 to PA7
PB0 to PB7
PX5 to PX7
RAS0 to RAS7
RD
: Port 5
: AD Trigger Input
: Port 6
: Analog Input
: Port 7
: Analog Power Supply
: Analog Reference Voltage
: Analog Ground
: Port 8
AVREF
: Port 9
AVSS
: Port 10
BCYST
CKSEL
CLKOUT
CS0 to CS7
CVDD
: Bus Cycle Start Timing
: Clock Generator Operating Mode Select
: Clock Output
: Port 11
: Port 12
: Port A
: Chip Select
: Port B
: Clock Generator Power Supply
: Clock Generator Ground
: Data Bus
: Port X
CVSS
: Row Address Strobe
: Read
D0 to D15
DMAAK0 to DMAAK3 : DMA Acknowledge
DMARQ0 to DMARQ3 : DMA Request
REFRQ
: Refresh Request
: Reset
RESET
HLDAK
HLDRQ
HVDD
: Hold Acknowledge
RXD0, RXD1
SCK0 to SCK3
SI0 to SI3
: Receive Data
: Serial Clock
: Serial Input
: Serial Output
: Terminal Count Signal
: Hold Request
: Power Supply for External Pins
INTP100 to INTP103, : Interrupt Request from Peripherals
INTP110 to INTP113,
SO0 to SO3
TC0 to TC3
INTP120 to INTP123,
TCLR10 to TCLR15: Timer Clear
INTP130 to INTP133,
TI10 to TI15
TO100, TO101,
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141,
TO150, TO151
TXD0, TXD1
UCAS
: Timer Input
INTP140 to INTP143,
: Timer Output
INTP150 to INTP153
IORD
IOWR
LCAS
LWR
: I/O Read Strobe
: I/O Write Strobe
: Lower Column Address Strobe
: Lower Write Strobe
MODE0 to MODE3 : Mode
: Transmit Data
: Upper Column Address Strobe
: Upper Write Strobe
: Power Supply for Internal Unit
: Ground
NMI
: Non-Maskable Interrupt Request
OE
: Output Enable
: Port 0
UWR
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
VDD
: Port 1
VSS
: Port 2
WAIT
: Wait
: Port 3
WE
: Write Enable
: Port 4
X1, X2
: Crystal
3
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
INTERNAL BLOCK DIAGRAM
NMI
HLDRQ
CPU
BCU
ROM
HLDAK
INTP100 to INTP103,
INTC
INTP110 to INTP113,
CS0 to CS7/RAS0 to RAS7
INTP120 to INTP123,
INTP130 to INTP133,
INTP140 to INTP143,
INTP150 to INTP153
IOWR
Instruction queue
PC
IORD
Multiplier
(32 × 32 → 64)
Note
DRAMC
REFRQ
BCYST
WE
TO100, TO101,
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141,
TO150, TO151
RD
Barrel
shifter
OE
Page ROM
controller
RPU
RAM
System registers
UWR/UCAS
LWR/LCAS
WAIT
TCLR10 to TCLR15
TI10 to TI15
ALU
General registers
(32 bits × 32)
A0 to A23
D0 to D15
DMARQ0 to DMARQ3
DMAAK0 to DMARQ3
TC0 to TC3
4 Kbytes
DMAC
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
BRG0
UART1/CSI1
BRG1
SO1/TXD1
SI1/RXD1
SCK1
CKSEL
CLKOUT
X1
Port
CG
X2
CVDD
CVSS
SO2
SI2
CSI2
SCK2
MODE0 to MODE3
RESET
BRG2
System
controller
SO3
SI3
CSI3
SCK3
VDD
VSS
ANI0 to ANI7
AVREF
AVSS
ADC
AVDD
ADTRG
Note µPD703100-33, 703100-40: None
µPD703101-33: 96 Kbytes (mask ROM)
µPD703102-33: 128 Kbytes (mask ROM)
4
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
CONTENTS
1. DIFFERENCES AMONG PRODUCTS...........................................................................................
2. PIN FUNCTIONS .............................................................................................................................
2.1 Port Pins .................................................................................................................................
7
8
8
2.2 Non-port Pins ......................................................................................................................... 11
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins..................................... 15
3. FUNCTION BLOCKS ...................................................................................................................... 18
3.1 Internal Units.......................................................................................................................... 18
3.1.1 CPU ........................................................................................................................................... 18
3.1.2 Bus control unit (BCU)............................................................................................................... 18
3.1.3 ROM .......................................................................................................................................... 18
3.1.4 RAM........................................................................................................................................... 19
3.1.5 Ports .......................................................................................................................................... 19
3.1.6 Interrupt controller (INTC).......................................................................................................... 19
3.1.7 Clock generator (CG)................................................................................................................. 19
3.1.8 Real-time pulse unit (RPU)........................................................................................................ 19
3.1.9 Serial interface (SIO) ................................................................................................................. 19
3.1.10 A/D converter (ADC).................................................................................................................. 19
4. CPU FUNCTIONS............................................................................................................................ 20
5. BUS CONTROL FUNCTIONS........................................................................................................ 20
6. MEMORY ACCESS CONTROL FUNCTIONS.............................................................................. 21
6.1 SRAM Connection.................................................................................................................. 21
6.2 Page ROM Controller (ROMC) .............................................................................................. 22
6.2.1 Features..................................................................................................................................... 22
6.2.2 Page ROM connection............................................................................................................... 22
6.3 DRAM Controller.................................................................................................................... 24
6.3.1 Features..................................................................................................................................... 24
6.3.2 DRAM Connections ................................................................................................................... 24
7. DMA FUNCTIONS (DMA CONTROLLER) ................................................................................... 26
8. INTERRUPT/EXCEPTION PROCESSING FUNCTIONS............................................................... 28
8.1 Features.................................................................................................................................. 28
9. CLOCK GENERATION FUNCTIONS ............................................................................................ 33
10. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)..................................................... 34
5
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
11. SERIAL INTERFACE FUNCTION.................................................................................................. 37
11.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)....................................................... 37
11.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3) ................................................................... 38
11.3 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2).................................................. 40
12. A/D CONVERTER............................................................................................................................ 41
13. PORT FUNCTIONS ......................................................................................................................... 42
14. RESET FUNCTION.......................................................................................................................... 53
15. INSTRUCTION SET......................................................................................................................... 54
16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES)...................................................... 64
17. PACKAGE DRAWING..................................................................................................................... 120
18. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 121
6
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
1. DIFFERENCES AMONG PRODUCTS
Product Name
µPD703100
–40 –A33
µPD703101
–33 –A33
µPD703102
–33 –A33
µPD70F3102
Item
–33
–A40
–33
–A33
Internal ROM
None
96 Kbytes
128 Kbytes
(mask ROM)
128 Kbytes
(mask ROM)
(flash memory)
Maximum operating
frequency
33 MHz 40 MHz 33 MHz 40 MHz
33 MHz
HVDD
4.5 to 5.5 V
3.0 to 3.6 V
4.5 to
5.5 V
3.0 to
3.6 V
4.5 to
5.5 V
3.0 to
4.5 to
5.5 V
3.0 to
3.6 V
3.6 V
Operation mode
Single-chip
mode 0, 1
None
None
Provided
Flash memory
programming
mode
Provided
Flash memory
None
Provided (VPP)
programming pin
Electrical
Power consumptions differ (refer to the data sheet of each product).
specifications
Package
144LQFP
144LQFP
157FBGA
144LQFP
144LQFP
157FBGA
144LQFP
144LQFP
157FBGA
144LQFP
144LQFP
157FBGA
Others
Noise tolerance and noise radiation will differ due to the differences in circuit scale and mask layout.
Remark 144LQFP: 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
157FBGA: 157-pin plastic FBGA (14 × 14 mm)
7
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
2. PIN FUNCTIONS
2.1 Port Pins
(1/3)
Pin Name
P00
I/O
I/O
Function
Alternate Function
TO100
Port 0
8-bit I/O port
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40 to P47
TO101
Input/output mode can be specified in 1-bit units
TCLR10
TI10
INTP100/DMARQ0
INTP101/DMARQ1
INTP102/DMARQ2
INTP103/DMARQ3
TO110
I/O
Port 1
8-bit I/O port
TO111
Input/output mode can be specified in 1-bit units
TCLR11
TI11
INTP110/DMAAK0
INTP111/DMAAK1
INTP112/DMAAK2
INTP113/DMAAK3
NMI
I
Port 2
P20 is an input only port.
I/O
–
When a valid edge is input, this pin operates as NMI input. Also, bit 0
of the P2 register indicates the NMI input status.
P21 to P27 are 7-bit I/O port.
TXD0/SO0
RXD0/SO0
SCK0
Input/output mode can be specified in 1-bit units
TXD1/SO1
RXD1/SI1
SCK1
I/O
Port 3
TO130
8-bit I/O port.
TO131
Input/output mode can be specified in 1-bit units
TCLR13
TI13
INTP130
INTP131/SO2
INTP132/SI2
INTP133/SCK2
D0 to D7
I/O
Port 4
8-bit I/O port
Input/output mode can be specified in 1-bit units
8
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(2/3)
Pin Name
I/O
I/O
Function
Alternate Function
D8 to D15
P50 to P57
Port 5
8-bit I/O port
Input/output mode can be specified in 1-bit units
P60 to P67
P70 to P77
I/O
Port 6
A16 to A23
8-bit I/O port
Input/output mode can be specified in 1-bit units
I
Port 7
ANI0 to ANI7
8-bit input only port
P80
I/O
Port 8
CS0/RAS0
CS1/RAS1
CS2/RAS2
CS3/RAS3
CS4/RAS4/IOWR
CS5/RAS5/IORD
CS6/RAS6
CS7/RAS7
LCAS/LWR
UCAS/UWR
RD
8-bit I/O port
P81
Input/output mode can be specified in 1-bit units
P82
P83
P84
P85
P86
P87
P90
I/O
I/O
I/O
Port 9
8-bit I/O port
P91
Input/output mode can be specified in 1-bit units
P92
P93
WE
P94
BCYST
P95
OE
P96
HLDAK
P97
HLDRQ
P100
P101
P102
P103
P104
P105
P106
P107
P110
P111
P112
P113
P114
P115
P116
P117
Port 10
TO120
8-bit I/O port
TO121
Input/output mode can be specified in 1-bit units
TCLR12
TI12
INTP120/TC0
INTP121/TC1
INTP122/TC2
INTP123/TC3
TO140
Port 11
8-bit I/O port
TO141
Input/output mode can be specified in 1-bit units
TCLR14
TI14
INTP140
INTP141/SO3
INTP142/SI3
INTP143/SCK3
9
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(3/3)
Pin Name
P120
I/O
I/O
Function
Alternate Function
Port 12
TO150
TO151
TCLR15
TI15
8-bit I/O port
P121
P122
P123
P124
P125
P126
P127
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PX5
PX6
PX7
Input/output mode can be specified in 1-bit units
INTP150
INTP151
INTP152
INTP153/ADTRG
A0
I/O
I/O
I/O
Port A
8-bit I/O port
A1
Input/output mode can be specified in 1-bit units
A2
A3
A4
A5
A6
A7
Port B
A8
8-bit I/O port
A9
Input/output mode can be specified in 1-bit units
A10
A11
A12
A13
A14
A15
Port X
REFRQ
WAIT
CLKOUT
3-bit I/O port
Input/output mode can be specified in 1-bit units
10
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
2.2 Non-port Pins
(1/4)
Pin Name
TO100
I/O
Function
Pulse signal output for timers 10 to 15
Alternate Function
P00
O
TO101
TO110
TO111
TO120
TO121
TO130
TO131
TO140
TO141
TO150
TO151
TCLR10
TCLR11
TCLR12
TCLR13
TCLR14
TCLR15
TI10
P01
P10
P11
P100
P101
P30
P31
P110
P111
P120
P121
I
External clear signal input for timers 10 to 15
P02
P12
P102
P32
P112
P122
I
External count clock input for timers 10 to 15
P03
TI11
P13
TI12
P103
TI13
P33
TI14
P113
TI15
P123
INTP100
INTP101
INTP102
INTP103
INTP110
INTP111
INTP112
INTP113
INTP120
INTP121
INTP122
INTP123
I
I
I
External maskable interrupt request input, shared as external capture
trigger input for timer 10
P04/DMARQ0
P05/DMARQ1
P06/DMARQ2
P07/DMARQ3
P14/DMAAK0
P15/DMAAK1
P16/DMAAK2
P17/DMAAK3
P104/TC0
P105/TC1
P106/TC2
P107/TC3
External maskable interrupt request input, shared as external capture
trigger input for timer 11
External maskable interrupt request input, shared as external capture
trigger input for timer 12
11
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(2/4)
Pin Name
INTP130
I/O
I
Function
Alternate Function
P34
External maskable interrupt request input, shared as external capture
trigger input for timer 13
INTP131
INTP132
INTP133
INTP140
INTP141
INTP142
INTP143
INTP150
INTP151
INTP152
INTP153
SO0
P35/SO2
P36/SI2
P37/SCK2
P114
I
I
External maskable interrupt request input, shared as external capture
trigger input for timer 14
P115/SO3
P116/SI3
P117/SCK3
P124
External maskable interrupt request input, shared as external capture
trigger input for timer 15
P125
P126
P127/ADTRG
P22/TXD0
P25/TXD1
P35/INTP131
P115/INTP141
P23/RXD0
P26/RXD1
P36/INTP132
P116/INTP142
P24
O
Serial transmit data output (3-wire) for CSI0 to CSI3
Serial receive data input (3-wire) for CSI0 to CSI3
Serial clock I/O (3-wire) for CSI0 to CSI3
SO1
SO2
SO3
SI0
I
SI1
SI2
SI3
SCK0
I/O
SCK1
P27
SCK2
P37/INTP133
P117/INTP143
P22/SO0
P25/SO1
P23/SI0
SCK3
TXD0
O
I
Serial transmit data output for UART0 and UART1
Serial receive data input for UART0 and UART1
16-bit data bus for external memory
TXD1
RXD0
RXD1
P26/SI1
D0 to D7
D8 to D15
A0 to A7
A8 to A15
A16 to A23
LWR
I/O
O
P40 to P47
P50 to P57
PA0 to PA7
PB0 to PB7
P60 to P67
P90/LCAS
P91/UCAS
P92
24-bit address bus for external memory
O
O
O
O
O
Lower byte write-enable signal output for external data bus
Higher byte write-enable signal output for external data bus
Read strobe signal output for external data bus
Write enable signal output for DRAM
UWR
RD
WE
P93
OE
Output enable signal output for DRAM
P95
12
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(3/4)
Pin Name
LCAS
I/O
O
Function
Alternate Function
P90/LWR
Column address strobe signal output for DRAM’s lower data
Column address strobe signal output for DRAM’s higher data
Low address strobe signal output for DRAM
UCAS
O
P91/UWR
RAS0 to RAS3
RAS4
O
P80/CS0 to P83/CS3
P84/CS4/IOWR
P85/CS5/IORD
P86/CS6
RAS5
RAS6
RAS7
P87/CS7
BCYST
CS0 to CS3
O
O
Strobe signal output indicating start of bus cycle
Chip select signal output
P94
P80/RAS0 to
P83/RAS3
CS4
P84/RAS4/IOWR
P85/RAS5/IORD
P86/RAS6
CS5
CS6
CS7
P87/RAS7
WAIT
REFRQ
IOWR
IORD
I
Control signal input for inserting waits in bus cycle
Refresh request signal output for DRAM
DMA write strobe signal output
PX6
O
O
O
I
PX5
P84/RAS4/CS4
P85/RAS5/CS5
DMA read strobe signal output
DMARQ0 to
DMARQ3
DMA request signal input
P04/INTP100 to
P07/INTP103
DMAAK0 to
DMAAK3
O
O
DMA acknowledge signal output
P14/INTP110 to
P17/INTP113
TC0 to TC3
DMA end (terminal count) signal output
P104/INTP120 to
P107/INTP123
HLDAK
HLDRQ
ANI0 to ANI7
NMI
O
I
Bus hold acknowledge output
Bus hold request input
P96
P97
I
Analog input to A/D converter
Non-maskable interrupt request input
System clock output
P70 to P77
I
P20
PX7
–
CLKOUT
CKSEL
O
I
Input for specifying clock generator’s operation mode
Specify operation modes
MODE0 to
MODE3
I
–
RESET
X1
I
I
System reset input
–
Oscillator connection for system clock. Input is via X1 when using an
external clock.
–
X2
–
I
–
ADTRG
AVREF
AVDD
AVSS
A/D converter external trigger input
Reference voltage input for A/D converter
Positive power supply for A/D converter
Ground potential for A/D converter
P127/INTP153
I
–
–
–
–
–
13
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(4/4)
Pin Name
CVDD
I/O
–
Function
Positive power supply for dedicated clock generator
Ground potential for dedicated clock generator
Positive power supply (power supply for internal units)
Positive power supply (power supply for external pins)
Ground potential
Alternate Function
–
–
–
–
–
CVSS
VDD
–
–
HVDD
VSS
–
–
14
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows
the various circuit types using partially abridged diagrams.
When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended.
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)
Pin
I/O Circuit Type
Recommended Connection of Unused Pins
P00/TO100, P01/TO101
P02/TCLR10, P03/TI10
5
Input : Independently connect to HVDD or VSS via a resistor
Output: Leave open
5-K
P04/INTP100/DMARQ0 to
P07/INTP103/DMARQ3
P10/TO110, P11/TO111
P12/TCLR11, P13/TI11
5
5-K
P14/INTP110/DMAAK0 to
P17/INTP113/DMAAK3
P20/NMI
2
5
Connect directly to VSS
P21
Input : Independently connect to HVDD or VSS via a resistor
Output: Leave open
P22/TXD0/SO0
P23/RXD0/SI0
5-K
P24/SCK0
P25/TXD1/SO1
P26/RXD1/SI1
5
5-K
P27/SCK1
P30/TO130, P31/TO131
P32/TCLR13,P33/TI13
P34/INTP130
5
5-K
P35/INTP131/SO2
P36/INTP132/SI2
P37/INTP133/SCK2
P40/D0 to P47/D7
P50/D8 to P57/D15
P60/A16 to P67/A23
P70/ANI0 to P77/ANI7
P80/CS0/RAS0 to P83/CS3/RAS3
5
9
5
Connect directly to VSS
Input : Independently connect to HVDD or VSS via a resistor
Output: Leave open
P84/CS4/RAS4/IOWR,
P85/CS5/RAS5/IORD
P86/CS6/RAS6, P87/CS7/RAS7
P90/LCAS/LWR
P91/UCAS/UWR
15
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2)
Pin
I/O Circuit Type
5
Recommended Connection of Unused Pins
P92/RD
Input : Independently connect to HVDD or VSS via a resistor
Output: Leave open
P93/WE
P94/BCYST
P95/OE
P96/HLDAK
P97/HLDRQ
P100/TO120, P101/TO121
P102/TCLR12, P103/TI12
5-K
P104/INTP120/TC0 to
P107/INTP123/TC3
P110/TO140, P111/TOI41
P112/TCLR14, P113/TI14
P114/INTP140
5
5-K
P115/INTP141/SO3
P116/INTP142/SI3
P117/INTP143/SCK3
P120/TO150, P121/TO151
P122/TCLR15, P123/TI15
P124/INTP150 to P126/INTP152
P127/INTP153/ADTRG
PA0/A0-PA7/A7
PB0/A8-PB7/A15
PX5/REFRQ
5
5-K
5
PX6/WAIT
PX7/CLKOUT
CKSEL
1
2
Connect directly to HVDD
–
RESET
MODE0 to MODE2
MODE3
Connect to VSS via a resistor (RVPP)
Connect directly to VSS
AVREF, AVSS
–
–
AVDD
Connect directly to HVDD
16
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 2-1. Pin I/O Circuits
Type 1
Type 5-K
V
DD
V
DD
data
P-ch
IN/OUT
P-ch
IN
output
N-ch
disable
N-ch
input
enable
Type 2
Type 9
P-ch
N-ch
Comparator
IN
+
–
IN
VREF (threshold voltage)
input enable
Schmitt trigger input with hysteresis characteristics
Type 5
V
DD
data
P-ch
IN/OUT
output
disable
N-ch
input
enable
Caution Replace VDD by HVDD when referencing the circuit diagrams shown above.
17
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
3. FUNCTION BLOCKS
3.1 Internal Units
3.1.1 CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits, or 32 bits × 32 bits → 64
bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
3.1.2 Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU
generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an
internal instruction queue of the CPU.
The BCU contains DRAM controller (DRAMC), page ROM controller, and DMA controller (DMAC).
(a) DRAM controller (DRAMC)
The DRAM controller generates the RAS, UCAS, and LCAS signals (2CAS control) and controls access to the
DRAM.
It supports high-speed page DRAM and EDO DRAM, and has two types of cycles for accessing DRAM.
These types of cycles are referred to as normal access (off-page) and page access (on-page).
The DRAM controller also has a refresh function that is associated with the CBR refresh cycle.
(b) Page ROM controller
The page ROM controller supports access to ROM that has the page access function.
It compares the address with that of the preceding bus cycle and controls the waits for normal access (off-
page) and page access (on-page). The page ROM controller can support page sizes of 8 to 64 bytes.
(c) DMA controller (DMAC)
The DMA controller transfers data between memory and an I/O device in place of the CPU.
The two address modes are flyby (one-cycle) transfer and two-cycle transfer. The three bus modes are single
transfer, single-step transfer, and block transfer.
3.1.3 ROM
The µPD703101-33 contains 96-Kbytes mask ROM, and the µPD703102-33 contains 128-Kbytes mask ROM.
The CPU can access ROM in one clock cycle when an instruction is fetched.
When single-chip mode 0 is set, ROM is mapped to the address space starting at 00000000H. When single-chip
mode 1 is set, ROM is mapped to the address space starting at 00100000H. When ROM-less mode 0 or 1 is set,
ROM cannot be accessed.
The µPD703100-33 and µPD703100-40 have no internal ROM.
18
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
3.1.4 RAM
RAM is mapped to the 4-Kbyte address space starting at FFFFE000H. The CPU can access RAM in one clock
cycle when an instruction is fetched or data is accessed.
3.1.5 Ports
In addition to the 123 pins (ports 0 to 12, A, B, and X) comprising I/O ports (of which nine pins comprise an input-
only port), various port pin and control pin functions can be selected for these pins.
3.1.6 Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP100 to INTP103, INTP110 to INTP113, INTP120 to
INTP123, INTP130 to INTP133, INTP140 to INTP143, and INTP150 to INTP153) from on-chip peripheral I/O and
external hardware. Eight interrupt priority levels can be specified for these interrupt requests, and multiplexed
servicing control can be performed for interrupt sources.
3.1.7 Clock generator (CG)
A frequency of five times (using an on-chip PLL) or one-half times (not using an on-chip PLL) that of the input
clock (fXX) is supplied as the internal system clock (φ). Either an external oscillator is connected to pins X1 and X2
(only when the on-chip PLL synthesizer is used) or an external clock is input from the X1 pin as the input clock.
3.1.8 Real-time pulse unit (RPU)
The RPU includes a six-channel 16-bit timer/event counter and a two-channel 16-bit interval timer, which enables
measurement of pulse intervals and frequency as well as programmable pulse output.
3.1.9 Serial interface (SIO)
Four channels are comprised of two kinds of serial interfaces: an asynchronous serial interface (UART) and a
clocked serial interface (CSI). Two of these four channels are switchable between the UART and CSI and the other
two channels are fixed as CSI.
For UART, data is transferred via the TXD and RXD pins. For CSI, data is transferred via the SO, SI, and SCK
pins.
The serial clock source can be selected from dedicated baud rate generator output or the internal system clock.
3.1.10 A/D converter (ADC)
This is a high-speed, high-resolution 10-bit A/D converter that includes eight analog input pins. It converts using
the successive approximation method.
19
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
4. CPU FUNCTIONS
{ RISC-based architecture
{ Uses five-stage pipeline control to enable single-clock execution of almost all instructions
{ Minimum instruction execution time
25 ns (@ 40-MHz operation) ... µPD703100-40
30 ns (@ 33-MHz operation) ... µPD703100-33, 703101-33, 703102-33
{ Memory space
Program space : 64-Mbyte linear
Data space : 4-Gbyte linear
{ General registers 32 bits × 32
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiply/divide instructions
{ Saturated operation instructions
{ 32-bit shift instruction: 1 clock
{ Long/short format
{ Four types of bit manipulation instructions
•
•
•
•
Set
Clear
Not
Test
5. BUS CONTROL FUNCTIONS
{ 16-bit/8-bit data bus sizing function
{ 8-space chip select output function
{ Wait functions
•
•
Programmable wait function for up to seven states for each memory block
External wait function using WAIT pin
{ Idle state insertion function
{ Bus mastering arbitration function
{ Bus hold function
{ Alternate function for port pins are connectable to external bus
20
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
6. MEMORY ACCESS CONTROL FUNCTIONS
6.1 SRAM Connection
The following figure shows an SRAM connection example.
Figure 6-1. SRAM Connection Example
A1 to A17
D0 to D7
D8 to D15
CSn
A0 to A16
I/O1 to I/O8
CS
UWR
LWR
WE
OE
RD
5 V
5 V
HVDD
VCC
V850E/MS1
1-Mbit (128 K × 8) SRAM
A0 to A16
I/O1 to I/O8
CS
WE
OE
5 V
VCC
1-Mbit (128 K × 8) SRAM
Remark n = 0 to 7
21
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
6.2 Page ROM Controller (ROMC)
The page ROM controller (ROMC) supports access to ROM (page ROM) that has the page access function.
It compares the address with that of the preceding bus cycle and performs wait control for normal access (off-
page) and page access (on-page). The page ROM controller can support page widths of 8 to 64 bytes.
6.2.1 Features
{ Can be connected directly to 8-bit or 16-bit page ROM
{ For 16-bit bus width, it supports 4-, 8-, 16-, or 32-word page access
For 8-bit bus width, it supports 8-, 16-, 32-, or 64-word page access
{ Enables waits to be set (0 to 7 waits) independently for off-page and on-page access
6.2.2 Page ROM connection
The following figure shows page ROM connection examples.
Figure 6-2. Page ROM Connection Examples (1/2)
(a) 16-Mbit (1 M × 16) page ROM
A1 to A20
D0 to D15
A0 to A19
O1 to O16
RD
OE
CE
CSn
V
DD
WORD/BYTE
16-Mbit (1 M × 16) page ROM
V850E/MS1
Remark n = 0 to 7
22
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 6-2. Page ROM Connection Examples (2/2)
(b) 16-Mbit (2 M × 8) page ROM
A1 to A20
D0 to D7
A0 to A19
O0 to O7
RD
OE
CE
CSn
WORD/BYTE
D8 to D15
16-Mbit (2 M × 8) page ROM
V850E/MS1
A0 to A19
O0 to O7
OE
CE
WORD/BYTE
16-Mbit (2 M × 8) page ROM
Remark n = 0 to 7
23
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
6.3 DRAM Controller
6.3.1 Features
{ Generates the RAS, UCAS, and LCAS signals
{ Can be connected directly to high-speed page DRAM and EDO DRAM
{ Supports RAS hold mode
{ Can assign 4 types of DRAM to 8 memory block spaces
{ Supports 2CAS type DRAM
{ Can be switched between row and column address multiplex widths
{ Can insert waits (0 to 3 waits) at each of the following timings
•
•
•
•
Row address pre-charge wait
Row address hold wait
Data access wait
Column address pre-charge wait
{ Supports CBR refresh and CBR self refresh
6.3.2 DRAM Connections
The following figure shows DRAM connection examples.
Figure 6-3. DRAM Connection Examples (1/2)
(a) 16-Mbit (1 M × 16) DRAM
A0 to A9
A1 to A10
D0 to D15
I/O1 to I/O16
RASn
LCAS
UCAS
WE
RASn
LCAS
UCAS
WE
OE
OE
V850E/MS1
16-Mbit (1 M × 16) DRAM
Remark n = 0 to 7
24
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 6-3. DRAM Connection Examples (2/2)
(b) 4-Mbit (1 M × 4) DRAM
A0 to A9
A0 to A9
A1 to A10
D0 to D7
D8 to D15
RASn
I/O1 to I/O4
I/O1 to I/O4
RAS
CAS
RAS
CAS
LCAS
UCAS
WE
WE
OE
WE
OE
OE
V850E/MS1
4-Mbit (1 M × 4) DRAM
4-Mbit (1 M × 4) DRAM
A0 to A9
A0 to A9
I/O1 to I/O4
I/O1 to I/O4
RAS
CAS
RAS
CAS
WE
OE
WE
OE
4-Mbit (1 M × 4) DRAM
4-Mbit (1 M × 4) DRAM
Remark n = 0 to 7
25
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
7. DMA FUNCTIONS (DMA CONTROLLER)
{ 4 independent DMA channels
{ Transfer units: 8 or 16 bits
{ Maximum transfer count: 65536 (216)
{ Two types of transfer
•
•
Flyby (one-cycle) transfer
Two-cycle transfer
{ Three transfer modes
•
•
•
Single transfer mode
Single-step transfer mode
Block transfer mode
{ Transfer requests
•
•
•
DMARQ0 to DMARQ3 pin (× 4)
Requests from on-chip peripheral I/O (serial interface and real-time pulse unit)
Requests by software
{ Transfer objects
•
•
Memory to I/O and vice versa
Memory to memory and vice versa
{ DMA transfer end output signal (TC0 to TC3)
26
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 7-1. DMA Function Block Diagram
Internal RAM
Internal peripheral I/O
Internal bus
Internal peripheral I/O bus
CPU
DMA source address
register (DSAnH/DSAnL)
Data control
Address control
DMA destination address
register (DDAnH/DDAnL)
DMA byte count register
(DBCn)
TCn
NMI
Count control
DMA addressing control
register (DADCn)
DMA channel control
register (DCHCn)
INTPmn
Request from on-chip
peripheral I/O
Channel control
DMA disable status
register (DDISn)
DMA restart register
(DRSTn)
DMARQn
DMAAKn
DMA trigger source
register (DTFRn)
DMAC
Bus interface
V850E/MS1
External bus
External ROM
External I/O
External RAM
Remark m = 10 to 15, n=0 to 3
27
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
8. INTERRUPT/EXCEPTION PROCESSING FUNCTIONS
8.1 Features
{ Interrupts
•
•
•
•
•
•
Non-maskable interrupt: 1 source
Maskable interrupt : 47 sources
8-level programmable priority control
Multiple interrupt control based on priority levels
Mask specification for each maskable interrupt request
Noise elimination, edge detection, and valid edge specification for external interrupt requests
{ Exceptions
•
•
Software exceptions: 32 sources
Exception trap
: 1 source (invalid instruction code exception)
28
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 8-1. Interrupt Control Function Block Diagram
Internal bus
ISPR register
xxICn register
xxMKn (interrupt mask flag)
INTOV10
INTOV11
INTOV12
Handler
address
generator
OVIF10
OVIF11
OVIF12
INTOV13
OVIF13
INTOV14
OVIF14
INTOV15
OVIF15
INTP100/INTCC100
CPU
P10IF0
P10IF1
P10IF2
P10IF3
P11IF0
P11IF1
P11IF2
P11IF3
P12IF0
P12IF1
P12IF2
P12IF3
P13IF0
P13IF1
P13IF2
P13IF3
P14IF0
P14IF1
P14IF2
P14IF3
P15IF0
P15IF1
P15IF2
P15IF3
CMIF40
CMIF41
DMAIF0
DMAIF1
DMAIF2
DMAIF3
CSIF0
INTP101/INTCC101
INTP102/INTCC102
INTP103/INTCC103
INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113
INTP120/INTCC120
INTP100
INTP101
INTP102
INTP103
INTM1
(edge detection)
Note
Note
Note
Note
Note
Note
PSW
ID
INTP110
INTP111
INTP112
INTP113
INTM2
(edge detection)
INTP121/INTCC121
INTP122/INTCC122
Interrupt request
INTP120
INTP121
INTP122
INTP123
RPU
INTM3
(edge detection)
Interrupt request
acknowledge
INTP123/INTCC123
INTP130/INTCC130
INTP131/INTCC131
INTP132/INTCC132
INTP133/INTCC133
INTP140/INTCC140
INTP141/INTCC141
INTP142/INTCC142
INTP143/INTCC143
HALT mode
release signal
INTP130
INTP131
INTP132
INTP133
INTM4
(edge detection)
INTP140
INTP141
INTP142
INTP143
INTM5
(edge detection)
INTP150/INTCC150
INTP151/INTCC151
INTP152/INTCC152
INTP150
INTP151
INTP152
INTP153
INTM6
(edge detection)
INTP153/INTCC153
INTCM40
INTCM41
INTDMA0
INTDMA1
INTDMA2
INTDMA3
INTCSI0
INTSER0
INTSR0
DMAC
CSI0
SEIF0
SRIF0
STIF0
CSIF1
SEIF1
SRIF1
UART0
CSI1
INTST0
INTCSI1
INTSER1
INTSR1
INTST1
SIO
UART1
CSI2
STIF1
CSIF2
CSIF3
ADIF
INTCSI2
INTCSI3
INTAD
CSI3
A/D converter
NMI
Note Noise elimination
Remark xx: OV, CM, P10 to P15, DMA, CS, SE, SR, ST, AD
n: None, or 10 to 15, 40, 41, 0 to 3
29
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 8-1. List of Interrupts (1/3)
Interrupt/Exception Source
Excep-
Default
Handler
Address
Restore
PC
Type
Category
tion
Control
Generat-
ing Unit
Priority
Name
Generation Source
RESET input
Code
Register
Reset
Interrupt
Interrupt
RESSET
–
Pin
–
–
0000H
0010H
00000000H
00000010H
Unde-
fined
Non-
NMI
–
NMI input
Pin
nextPC
maskable
Software
exception
Exception TRAP0nNote
Exception TRAP1nNote
–
–
–
TRAP instruction
TRAP instruction
–
–
–
–
–
–
004nNote
005nNote
0060H
H
00000040H
00000050H
00000060H
nextPC
nextPC
nextPC
H
Exception
trap
Exception
ILGOP
Illegal instruction
code
Maskable
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
INTOV10
INTOV11
INTOV12
INTOV13
INTOV14
INTOV15
OVIC10
OVIC11
OVIC12
OVIC13
OVIC14
OVIC15
P10IC0
Timer 10 overflow
Timer 11 overflow
Timer 12 overflow
Timer 13 overflow
Timer 14 overflow
Timer 15 overflow
RPU
RPU
0
1
2
3
4
5
6
0080H
0090H
00000080H
00000090H
000000A0H
000000B0H
000000C0H
000000D0H
00000100H
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
RPU
00A0H
00B0H
00C0H
00D0H
0100H
RPU
RPU
RPU
INTP100/
Match between
Pin/RPU
INTCC100
INTP100 and CC100
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
INTP101/
P10IC1
P10IC2
P10IC3
P11IC0
P11IC1
P11IC2
P11IC3
P12IC0
P12IC1
P12IC2
Match between
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
7
0110H
0120H
0130H
0140H
0150H
0160H
0170H
0180H
0190H
01A0H
00000110H
00000120H
00000130H
00000140H
00000150H
00000160H
00000170H
00000180H
00000190H
000001A0H
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
INTCC101
INTP101 and CC101
INTP102/
Match between
8
INTCC102
INTP102 and CC102
INTP103/
Match between
9
INTCC103
INTP103 and CC103
INTP110/
Match between
10
11
12
13
14
15
16
INTCC110
INTP110 and CC110
INTP111/
Match between
INTCC111
INTP111 and CC111
INTP112/
Match between
INTCC112
INTP112 and CC112
INTP113/
Match between
INTCC113
INTP113 and CC113
INTP120/
Match between
INTCC120
INTP120 and CC120
INTP121/
Match between
INTCC121
INTP121 and CC121
INTP122/
Match between
INTCC122
INTP122 and CC122
Note n = 0 to FH
30
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 8-1. List of Interrupts (2/3)
Interrupt/Exception Source
Excep-
Default
Handler
Address
Restore
PC
Type
Category
tion
Control
Generat-
ing Unit
Priority
Name
Generation Source
Code
Register
Maskable
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
INTP123/
P12IC3
P13IC0
P13IC1
P13IC2
P13IC3
P14IC0
P14IC1
P14IC2
P14IC3
P15IC0
P15IC1
P15IC2
P15IC3
Match between
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
17
18
19
20
21
22
23
24
25
26
27
28
29
01B0H
01C0H
01D0H
01E0H
01F0H
0200H
0210H
0220H
0230H
0240H
0250H
0260H
0270H
000001B0H
000001C0H
000001D0H
000001E0H
000001F0H
00000200H
00000210H
00000220H
00000230H
00000240H
00000250H
00000260H
00000270H
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
INTCC123
INTP123 and CC123
INTP130/
Match between
INTCC130
INTP130 and CC130
INTP131/
Match between
INTCC131
INTP131 and CC131
INTP132/
Match between
INTCC132
INTP132 and CC132
INTP133/
Match between
INTCC133
INTP133 and CC133
INTP140/
Match between
INTCC140
INTP140 and CC140
INTP141/
Match between
INTCC141
INTP141 and CC141
INTP142/
Match between
INTCC142
INTP142 and CC142
INTP143/
Match between
INTCC143
INTP143 and CC143
INTP150/
Match between
INTCC150
INTP150 and CC150
INTP151/
Match between
INTCC151
INTP151 and CC151
INTP152/
Match between
INTCC152
INTP152 and CC152
INTP153/
INTC153
Match between
INTP153 and CC153
Interrupt
Interrupt
Interrupt
INTCM40
INTCM41
INTDMA0
CMIC40
CMIC41
DMAIC0
CM40 match signal
CM41 match signal
RPU
RPU
30
31
32
0280H
0290H
02A0H
00000280H
00000290H
000002A0H
nextPC
nextPC
nextPC
DMA channel 0
DMAC
transfer completion
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
INTDMA1
INTDMA2
INTDMA3
INTCSI0
DMAIC1
DMAIC2
DMAIC3
CSIC0
DMA channel 1
DMAC
DMAC
DMAC
SIO
33
34
35
36
37
02B0H
02C0H
02D0H
0300H
0310H
000002B0H
000002C0H
000002D0H
000000300H
000000310H
nextPC
nextPC
nextPC
nextPC
nextPC
transfer completion
DMA channel 2
transfer completion
DMA channel 3
transfer completion
CSI0 send/receive
completion
INTSER0
SEIC0
UART0 receive error
SIO
Note n = 0 to FH
31
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 8-1. List of Interrupts (3/3)
Interrupt/Exception Source
Excep-
Default
Handler
Address
Restore
PC
Type
Category
tion
Control
Generat-
ing Unit
Priority
Name
Generation Source
Code
Register
Maskable
Interrupt
Interrupt
Interrupt
INTSR0
SRIC0
STIC0
CSIC1
UART0 receive
completion
SIO
SIO
SIO
38
39
40
0320H
0330H
0340H
00000320H
00000330H
00000340H
nextPC
nextPC
nextPC
INTST0
UART0 send
completion
INTCSI1
CSI1 send/receive
completion
Interrupt
Interrupt
INTSER1
INTSR1
SEIC1
SRIC1
UART1 receive error
SIO
SIO
41
42
0350H
0360H
00000350H
00000360H
nextPC
nextPC
UART1 receive
completion
Interrupt
Interrupt
Interrupt
Interrupt
INTST1
INTCSI2
INTCSI3
INTAD
STIC1
CSIC2
CSIC3
ADIC
UART1 send
completion
SIO
SIO
SIO
ADC
43
44
45
46
0370H
0380H
03C0H
0400H
00000370H
00000380H
000003C0H
00000400H
nextPC
nextPC
nextPC
nextPC
CSI2 send/receive
completion
CSI3 send/receive
completion
A/D conversion
completion
Remarks 1. Default priority: Priority that takes precedence when two or more maskable interrupt requests having
the same priority level are generated at the same time. The highest priority is 0.
Restore PC: The PC value that is saved in EIPC or FEPC when the interrupt or exception
processing is started. However, the restore PC value that is saved when an interrupt is
acknowledged during the execution of a division instruction (DIV, DIVH, DIVU, or
DIVHU), is the PC value of the current instruction (DIV, DIVH, DIVU, or DIVHU).
2. The execution address of the illegal instruction when an illegal opcode exception occurs is obtained
according to the calculation “restore PC - 4.”
32
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
9. CLOCK GENERATION FUNCTIONS
{ Multiplier function using a PLL (Phase locked loop) synthesizer
{ Clock sources
•
•
Oscillation by connecting an oscillator: fXX = φ/5
External clock: fXX = 2 × φ or φ/5
{ Power saving modes
•
•
•
•
HALT mode
IDLE mode
Software STOP mode
Clock output inhibit mode
{ Internal system clock output function
Figure 9-1. Block Diagram of Clock Generation Function
φ
X1
CPU, on-chip peripheral I/O
CLKOUT
(fXX
)
Clock generator
(CG)
X2
CKSEL
Time base counter (TBC)
Remark φ : internal system clock frequency
FXX: external oscillator or external clock frequency
33
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
10. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
{ Measures the pulse interval and frequency, and outputs a programmable pulse
•
•
16-bit measurements are possible
Can generate a variety of pulse patterns (interval pulse, one-shot pulse)
{ Timer 1
•
•
•
•
•
•
16-bit timer/event counter
Count clock sources: 2 types (division of internal system clock, and external pulse input)
Capture/compare common registers: 24
Count clear pins: TCLR10 to TCLR15
Interrupt sources: 30 types
External pulse outputs: 12
{ Timer 4
•
•
•
•
16-bit interval timer
Count clock can select division for internal system clock
Compare registers: 2
Interrupt sources: 2
34
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 10-1. Block Diagram of Timer 1 (16-bit Timer/Event Counter)
Internal system
TM10
φ
clock ( )
TCLR10
TI10
Edge detection
ETI10
Clear and
count control
Clear and
start
PRS100,
PRS101
Note 2
PRM
101
Edge detection
OVF10
φ
m
1/2
1/4
INTOV10
TM10 (16 bits)
Note 1
1/4
1/8
1/16
ALV101 ALV100
INTP100
INTP101
INTP102
INTP103
S
R
Q
CC100
CC101
CC102
CC103
TO100
TO101
Note 3 Q
Edge
detection
(INTM1)
Noise
elimination
S
RNote 3
Q
Q
IMS100 IMS101 IMS102 IMS103
INTP100/INTCC100
INTP101/INTCC101
INTP102/INTCC102
INTP103/INTCC103
Selector
Selector
Selector
Selector
TCLR11
TI11
INTP110
INTP111
INTP112
INTP113
INTOV11
TO110
TO111
TM11
INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113
TCLR15
TI15
INTP150
INTP151
INTP152
INTP153
INTOV15
TO150
TO151
TM15
INTP150/INTCC150
INTP151/INTCC151
INTP152/INTCC152
INTP153/INTCC153
Notes 1. Internal count clock
2. External count clock
3. Reset priority
35
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 10-2. Block Diagram of Timer 4 (16-bit Interval Timer)
Internal system
clock
φ
(
)
TM40
PRM400, PRM401
PRS400
Internal count
clock
1/2
1/4
1/8
1/16
1/32
φ
m
TM40 (16 bits)
CM40
Clear and
start
INTCM40
INTCM41
TM41
36
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
11. SERIAL INTERFACE FUNCTION
The serial interface function provides two 6-channel serial interfaces.
Up to four channels can be used at the same time.
(1) Asynchronous serial interface (UART0 and UART1): 2 channels
(2) Clocked serial interface (CSI0 to CSI3): 4 channels
Caution UART0 and CSI0 share a pin, as do UART1 and CSI1. One or the other of each pair can be
selected via a register (ASIM00, ASIM10).
11.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
{ Transfer rate
150 bps to 76800 bps (using the dedicated baud rate generator when the internal system clock is
33 MHz)
Maximum 4.125 Mbps (using the φ/2 clock when the internal system clock is 33 MHz)
{ Full duplex communications
On-chip receive buffer (RXBn)
{ 2-pin configuration
TXDn: Transmit data output pin
RXDn: Receive data input pin
{ Receive error detection functions
•
•
•
Parity error
Framing error
Overrun error
{ Interrupt sources: 3 types
•
•
•
Receive error interrupt (INTSERn)
Receive completion interrupt (INTSRn)
Transmission completion interrupt (INTSTn)
{ The character length of transmission/reception data is specified by the ASIMn0 and ASIMn1 registers.
{ Character length
7, 8 bits
9 bits (when adding an expansion bit)
{ Parity function: odd, even, 0, none
{ Transmission stop bit: 1, 2 bits
{ On-chip dedicated baud rate generator
{ Serial clock (SCKn) output function
Remark n = 0, 1
37
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 11-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
UART0
RXE0
RXB0/RXB0L
Receive buffer
Receive shift
register
RXD0
TXD0
TXS0/TXS0L
Transmit shift
register
Transmit
control
parity addition
INTST0
Receive
control
parity check
INTSER0
INTSR0
SCLS01, SCLS00
Internal system
clock (φ)
SCK0
1/16
1/16
BRG0
1/2
INTST1
INTSER1
INTSR1
RXD1
TXD1
SCK1
UART1
BRG1
11.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
{ High-speed transfer
Maximum 10 Mbps (when the internal system clock is operating at 40 MHz) ... µPD703100-40
Maximum 8.25 Mbps (when the internal system clock is operating at 33 MHz) ... µPD703100-33, µPD703101-33,
µPD703102-33
{ Half-duplex communications
{ Character length: 8 bits
{ Can switch between MSB first or LSB first for data
{ Either external serial clock input or internal serial clock output can be selected
{ 3-wire type
SOn: Serial data output
SIn:
Serial data input
SCKn: Serial clock input/output
{ Interrupt source: 1 type
•
Transmission/reception completion interrupt (INTCSIn)
Remark n = 0 to 3
38
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 11-2. Block Diagram of Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
CSI0
CTXE0
Internal system
clock (φ)
SO0
SI0
CRXE0
SO latch
Serial I/O shift register
(SIO0)
CLS00, CLS01
D
Q
1/2
1/4
Serial clock control
circuit
SCK0
BRG0
Interrupt
control circuit
Serial clock counter
INTCSI0
1/2
1/4
SO1
SI1
CSI1
BRG1
SCK1
INTCSI1
1/2
1/4
SO2
SI2
CSI2
BRG2
SCK2
INTCSI2
1/2
1/4
SO3
SI3
CSI3
SCK3
INTCSI3
39
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
11.3 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)
{ Serial clock can be selected via either dedicated baud rate generator output or internal system clock (φ)
{ Identical baud rates during transmission and reception
Figure 11-3. Block Diagram of Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)
BRG0
BRGC0
CSI0
BRCE0
BPR00 to BPR02
Prescaler
Match
Internal system
UART0
clock (φ)
Clear
TMBRG0
1/2
CSI1
BRG1
BRG2
UART1
CSI2
CSI3
40
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
12. A/D CONVERTER
{ Analog input: 8 channels
{ On-chip 10-bit A/D converter
{ On-chip A/D conversion result registers (ADCR0 to ADCR7)
10 bits × 8
{ A/D conversion trigger modes
A/D trigger mode
Timer trigger mode
External trigger mode
{ Successive approximation method
Figure 12-1. A/D Converter Block Diagram
Series resistor string
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
AVREF
Sample & hold circuit
R/2
R
R/2
AVSS
AVDD
Voltage comparator
9
9
0
SAR (10)
10
10
INTAD
0
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
INTCC110
INTCC111
INTCC112
INTCC113
Controller
Noise
Edge
ADTRG
elimination detection
7
0
7
0
ADM0 (8)
8
ADM1 (8)
10
8
Internal bus
41
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
13. PORT FUNCTIONS
{ Number of ports
Dedicated input ports: 9
Input/output ports
: 114
{ Shares pins with other peripheral function I/O
{ Input and output can be specified in 1-bit units
The block diagrams of the various ports are divided into 16 block types identified by A to P as shown in Table 13-
1. Figures 13-1 to 13-16 show the block diagrams of each type.
Table 13-1. List of Port Block Types
Port Name
Port 0
Pin Name
Port Function
Function in Control Mode
Block Type
A, B, M
P00 to P07
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, DMA controller (DMAC) input
Port 1
Port 2
Port 3
P10 to P17
P20 to P27
P30 to P37
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, DMA controller (DMAC) output
A, B, K
1-bit input,
NMI input, serial interface (UART0/CSI0, UART1/CSI1)
input/output
A, C, D, I, J
7-bit input/output
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, serial interface (CSI2) input/output
A, B, K, M,
N
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
8-bit input/output
8-bit input/output
8-bit input/output
8-bit input/output
8-bit input/output
8-bit input/output
8-bit input/output
External data bus (D0 to D7)
E
External data bus (D8 to D15)
E
External address bus (A16 to A23)
A/D converter (ADC) analog input
External bus interface control signal output
External bus interface control signal input/output
F
G
O, P
H, O
A, B, K
P100 to
P107
Input/output of real-time pulse unit (RPU), external
interrupt input, DMA controller (DMAC) output
Port 11
Port 12
P110 to
P117
8-bit input/output
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, serial interface (CSI3) input/output
A, B, K, M,
N
P120 to
P127
Input/output of real-time pulse unit (RPU), external
A, B
interrupt input, A/D converter (ADC) external trigger input
Port A
Port B
Port X
PA0 to PA7
PB0 to PB7
PX5 to PX7
8-bit input/output
8-bit input/output
3-bit input/output
External address bus (A0 to A7)
External address bus (A8 to A15)
F
F
Refresh request signal output, wait insertion signal input,
internal system clock output
A, L
42
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-1. Block Diagram of Type A
WRPMC
PMCmn
PMmn
WRPM
Output signal
in control mode
WRPORT
Pmn
Pmn
RDIN
Address
Remark m: port number
n : bit number
Figure 13-2. Block Diagram of Type B
WRPMC
PMCmn
PMmn
WRPM
WRPORT
Pmn
Pmn
Address
RDIN
Noise elimination
Edge detection
Input signal in
control mode
Remark m: port number
n : bit number
43
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-3. Block Diagram of Type C
WRPMC
WRPM
SCKx output
enable signal
PMCmn
PMmn
Output signal in
control mode
WRPORT
Pmn
Pmn
Address
RDIN
Input signal in
control mode
Remark mn: 24, 27
: 0 (when mn = 24), 1 (when mn = 27)
x
Figure 13-4. Block Diagram of Type D
WRPMC
WRPM
PMCmn
PMmn
WRPORT
Pmn
Pmn
Address
RDIN
Input signal in
control mode
Remark m: port number
n : bit number
44
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-5. Block Diagram of Type E
MODE0 to MODE3 MM0 to MM3
I/O control circuit
WRPM
PMmn
Output signal in
control mode
WRPORT
Pmn
Pmn
Address
RDIN
Input signal in
control mode
Remark m: port number
n : bit number
Figure 13-6. Block Diagram of Type F
MODE0 to MODE3 MM0 to MM3
I/O control circuit
WRPM
PMmn
Output signal in
control mode
WRPORT
Pmn
Pmn
Address
RDIN
Remark m: port number
n : bit number
45
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-7. Block Diagram of Type G
P7n
RDIN
ANIn
Input signal in
control mode
Sample & hold circuit
Remark n = 0 to 7
Figure 13-8. Block Diagram of Type H
MODE0 to MODE3 MM0 to MM3
I/O control circuit
WRPM
PMmn
Pmn
WRPORT
P97
Address
RDIN
Input signal in
control mode
46
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-9. Block Diagram of Type I
1
P20
Noise elimination
Address
RDIN
NMI
Edge detection
Figure 13-10. Block Diagram of Type J
WRPM
PMmn
Pmn
WRPORT
Pmn
Address
RDIN
Remark m: port number
n : bit number
47
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-11. Block Diagram of Type K
WRPCS
WRPMC
PCSmn
PMCmn
PMmn
WRPM
Output signal in
control mode
WRPORT
Pmn
Pmn
Address
RDIN
Input signal in
control mode
Noise elimination
Edge detection
Remark m: port number
n : bit number
48
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-12. Block Diagram of Type L
WRPMC
PMCmn
PMmn
WRPM
WRPORT
Pmn
Pmn
Address
RDIN
Input signal in
control mode
Remark m: port number
n : bit number
49
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-13. Block Diagram of Type M
WRPCS
WRPMC
PCSmnNote
PMCmn
PMmn
WRPM
WRPORT
Pmn
Pmn
Address
RDIN
INTP100 to INTP103,
INTP132, INTP142
Noise elimination
Edge detection
DMARQ0 to DMARQ3,
SI2, SI3
Note When mn = 36: PCS35
When mn = 116: PCS115
Remark mn: 04 to 07, 36, 116
50
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-14. Block Diagram of Type N
WRPCS
PCSm5
PMCmn
PMmn
SCKx output
enable signal
WRPMC
WRPM
Output signal in
control mode
WRPORT
Pmn
Pmn
Address
RDIN
Noise elimination
Edge detection
INTP133, INTP143
SCK2, SCK3
Remark mn: 37, 117
x: 2 (when mn = 37), 3 (when mn = 117)
51
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-15. Block Diagram of Type O
MODE0 to MODE3 MM0 to MM3
WRPMC
WRPM
PMCmn
I/O control circuit
PMmn
Output signal in
control mode
Pmn
WRPORT
Pmn
Address
RDIN
Remark m: port number
n : bit number
Figure 13-16. Block Diagram of Type P
WRPCS
PCSmn
MODE0 to MODE3 MM0 to MM3
WRPMC
WRPM
PMCmn
PMmn
I/O control circuit
Output signal in
control mode
WRPORT
Pmn
Pmn
Address
RDIN
Remark m: port number
n : bit number
52
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
14. RESET FUNCTION
When low-level signal is input to the RESET pin, a system reset is performed and the various on-chip hardware
devices are initialized.
When the RESET input changes from low to high, the reset state is canceled and the CPU begins program
execution. (the contents of the various registers should be initialized within the program as necessary.)
=
An on-chip noise elimination circuit, which uses analog delay ( 60 ns) to eliminate noise, is provided for the
RESET pin.
53
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
15. INSTRUCTION SET
Table 15-1. Symbols Used to Describe Operands
Symbol
Description
reg1
reg2
reg3
General registers (r0 to r31): used as source registers
General registers (r0 to r31): used mainly as destination registers
General registers (r0 to r31): used mainly to store the remainders of division results and the higher 3 bits
of multiplication results
imm×
disp×
regID
bit#3
ep
×-bit immediate
×-bit displacement
System register number
3-bit data for specifying the bit number
Element pointer (r30)
cccc
vector
list×
4-bit data indicating the condition code
5-bit data used for specifying the trap vector (00H to 1FH)
List of × registers
Table 15-2. Symbols Used to Describe Opcodes
Symbol
Description
1-bit data of code specifying reg1 or regID
1-bit data of code specifying reg2
1-bit data of code specifying reg3
1-bit displacement data
R
r
w
d
i
1-bit immediate data
cccc
bbb
L
4-bit data indicating condition code
3-bit data for specifying bit number
1-bit data specifying register list
54
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 15-3. Symbols Used in Operation
Symbol
Description
←
Input for
GR [ ]
General register
SR [ ]
System register
zero-extend (n)
sign-extend (n)
Extend n with zeros until word length
Extend n with signs until word length
Read data of size b from address a
Write data b of address a by size c
Read bit b of address a
load-memory (a, b)
store-memory (a, b, c)
load-memory-bit (a, b)
store-memory-bit (a, b, c)
saturated (n)
Write c to bit b of address a
Execute saturation processing of n (n is a two’s complement)
If, as a result of the calculation,
n ≥ 7FFFFFFFH, let it be 7FFFFFFFH.
n ≤ 80000000H, let it be 80000000H
result
Reflect the result in a flag
Byte (8 bits)
Byte
Half-word
Half word (16 bits)
Word (32 bits)
Add
Word
+
−
Subtract
||
Bit concatenation
Multiply
×
÷
Divide
%
Remainder of division result
Logical AND
AND
OR
Logical OR
XOR
Exclusive OR
Logical NOT
NOT
logically shift left by
logically shift right by
arithmetically shift right by
Logical shift left
Logical shift right
Arithmetic shift right
Table 15-4. Symbols Used for Execution Clock
Symbol
Description
i : issue
When executing another instruction immediately after executing an instruction
When repeating the same instruction immediately after executing the instruction
When referring to instruction execution results in the next instruction
r : repeat
l : latency
55
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 15-5. Symbols Used in Flag Operations
Identifier
(Blank)
Description
No change
Clear to 0
0
×
R
Set or cleared according to the results
Previously saved values are restored
Table 15-6. Condition Codes
Condition
Condition Code
(cccc)
Condition Formula
Description
Name (cond)
0000
1000
0001
V
OV = 1
OV = 0
CY = 1
Overflow
No overflow
Carry
NV
C/L
Lower (Less than)
1001
0010
1010
NC/NL
Z/E
CY = 0
Z = 1
No carry
Not lower (Greater than or equal)
Zero
Equal
NZ/NE
Z = 0
Not zero
Not equal
0011
1011
0100
1100
0101
1101
0110
1110
0111
1111
NH
H
(CY or Z) = 1
(CY or Z) = 0
S = 1
Not higher (Less than or equal)
Higher (Greater than)
Negative
N
P
S = 0
Positive
T
–
Always (unconditional)
Saturated
SA
LT
GE
LE
GT
SAT = 1
(S xor OV) = 1
Less than signed
(S xor OV) = 0
Greater than or equal signed
Less than or equal signed
Greater than signed
((S xor OV) or Z) = 1
((S xor OV) or Z) = 0
56
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Instruction Set
(1/7)
Execution
Flags
Clock
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
×
×
×
Z
×
×
×
SAT
ADD
reg1,reg2
imm5,reg2
rr r r r 0 0 1 1 1 0 R R R R R GR[reg2]←GR[reg2]+GR[reg1]
1
1
1
1
1
1
1
1
1
×
×
×
×
×
×
rr r r r 0 1 0 0 1 0 i i i i i GR[reg2]←GR[reg2]+sign-extend(imm5)
ADDI
imm16,reg1,reg2 r r r r r 1 1 0 0 0 0 r r r r r GR[reg2]←GR[reg1]+sign-extend(imm16)
i i ii i i i i i i i i i i i i
AND
reg1,reg2
rr r r r 0 0 1 0 1 0 R R R R R GR[reg2]←GR[reg2]AND GR[reg1]
1
1
1
1
1
1
0
0
×
×
×
ANDI
imm16,reg1,reg2 rr r r r 1 1 0 1 1 0 R R R R R GR[reg2]←GR[reg1]AND zero-
extend(imm16)
0
ii i i i i i i i i i i i i i i
Bcond
disp9
dd d d d 1 0 1 1 d d d c c c c if conditions are satisfied
When
2
2
2
then PC ← PC+sign-
conditions are Note 2 Note 2 Note 2
Note 1
extend(disp9)
satisfied
When
1
1
1
conditions are
not satisfied
GR[reg3]
←
GR[reg2] (23 : 16) II GR[reg2]
BSH
reg2,reg3
reg2,reg3
imm6
rr r r r 1 1 1 1 1 1 0 0 0 0 0
ww w w w 0 1 1 0 1 0 0 0 0 1 0
1
1
4
1
1
4
1
1
4
×
×
0
0
×
×
×
×
(31 : 24) II GR[reg2] (7 : 0) II GR[reg2] (15 : 8)
GR[reg3]
←
GR[reg2] (7 : 0) II GR[reg2] (15 : 8) II
BSW
CALLT
rr r r r 1 1 1 1 1 1 0 0 0 0 0
ww w w w 0 1 1 0 1 0 0 0 0 0 0
GR[reg2] (23 : 16) II GR[reg2] (31 : 24)
00 0 0 0 0 1 0 0 0 i i i i i i CTPC←PC+2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically
shift left by 1)
PC←CTBP+zero-extend(Load-
memory(adr, Half-word))
CLR1
CMOV
CMP
bit#3,
10 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
3
3
3
×
×
disp 16[reg1]
Z flags←Not(Load-memory-bit(adr,bit#3))
Note 3 Note 3 Note 3
dd d d d d d d d d d d d d d d
Store-memory-bit (adr,bit#3,0)
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
Z flags←Not(Load-memory-bit(adr,reg2))
3
3
3
Note 3 Note 3 Note 3
00 0 0 0 0 0 0 1 1 1 0 0 1 0 0
Store-memory-bit (adr,reg2,0)
cccc,imm5,reg2,
reg3
rr r r r 1 1 1 1 1 1 i i i i i if condition are satisfied then
1
1
1
1
1
1
GR[reg3]←sign-extended(imm5)
else GR[reg3]←GR[reg2]
ww w w w 0 1 1 0 0 0 c c c c 0
cccc,reg1,reg2,
reg3
rr r r r 1 1 1 1 1 1 R R R R R if conditions are satisfied
then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
ww w w w 0 1 1 0 0 1 c c c c 0
reg1,reg2
rr r r r 0 0 1 1 1 1 R R R R R result←GR[reg2]−GR[reg1]
rr r r r 0 1 0 0 1 1 i i i i i result←GR[reg2]−sign-extend(imm5)
00 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PC←CTPC
1
1
3
1
1
3
1
1
3
×
×
×
×
×
×
×
×
imm5,reg2
CTRET
DI
R
R
R
R
R
00 0 0 0 0 0 1 0 1 0 0 0 1 0 0 PSW CTPSW
←
00 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID←1
1
1
1
00 0 0 0 0 0 1 0 1 1 0 0 0 0 0
57
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(2/7)
Execution
Flags
Clock
Mnemonic
DISPOSE
Operand
Opcode
Operation
i
r
l
CY OV
S
Z
SAT
imm5,list12
00 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left N+1 N+1 N+1
by 2)
Note 4 Note 4 Note 4
LL L L L L L L L L L 0 0 0 0 0
GR[reg in list12]←Load-memory(sp,Word)
sp←sp+4
repeat 2 steps above untill all regs in list12
is loaded
imm5,list12,[reg1] 00 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shif left N+3 N+3 N+3
by 2)
Note 4 Note 4 Note 4
LL L L L L L L L L L R R R R R
GR[reg in list12]←Load-memory(sp,Word)
Note 5
sp←sp+4
repeat 2 steps above until all regs in list 12
is loaded
PC←GR[reg1]
DIV
reg1,reg2,reg3
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1]
35 35 35
w w w w w 0 1 0 1 1 0 0 0 0 0 0 GR[reg3] GR[reg2]%GR[reg1]
←
DIVH
reg1,reg2
r r r r r 0 0 0 0 1 0 R R R R R GR[reg2]←GR[reg2]÷GR[reg1] Note 6
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1] Note 6
35 35 35
35 35 35
×
×
×
×
×
×
reg1,reg2,reg3
w w w w w 0 1 0 1 0 0 0 0 0 0 0 GR[reg3] GR[reg2]%GR[reg1]
←
DIVHU
DIVU
EI
reg1,reg2,reg3
reg1,reg2,reg3
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1] Note 6
34 34 34
34 34 34
×
×
×
×
×
×
w w w w w 0 1 0 1 0 0 0 0 0 1 0 GR[reg3] GR[reg2]%GR[reg1]
←
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1]
w w w w w 0 1 0 1 1 0 0 0 0 1 0 GR[reg3] GR[reg2]%GR[reg1]
←
10 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID←0
1
1
1
1
1
1
1
1
1
00 0 0 0 0 0 1 0 1 1 0 0 0 0 0
HALT
HSW
00 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Stop
00 0 0 0 0 0 1 0 0 1 0 0 0 0 0
reg2,reg3
rr r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3]←GR[reg2] (15 : 0) II GR[reg2]
×
0
×
×
(31: 6)
w w w w w 0 1 1 0 1 0 0 0 1 0 0
JARL
disp22,reg2
rr r r r 1 1 1 1 0 d d d d d d GR[reg2]←PC+4
2
2
2
PC←PC+sign–extend(disp22)
dd d d d d d d d d d d d d d 0
Note 7
JMP
JR
[reg1]
00 0 0 0 0 0 0 0 1 1 R R R R R PC←GR[reg1]
3
2
3
2
3
2
disp22
00 0 0 0 1 1 1 1 0 d d d d d d PC←PC+sign-extend(disp22)
dd d d d d d d d d d d d d d 0
Note 7
LD.B
disp16[reg1],reg2 rr r r r 1 1 1 0 0 0 R R R R R adr←GR[reg1]+signe-extend(disp16)
1
1
n
GR[reg2]←sign-extend(Load-memory
Note 9
dd d d d d d d d d d d d d d d
(adr,Byte))
58
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(3/7)
Execution
Flags
Clock
Mnemonic
LD.BU
Operand
Opcode
Operation
i
r
l
CY OV
S
Z
SAT
disp16[reg1],reg2 rr r r r 1 1 1 1 0 b R R R R R adr←GR[reg1]+sign-extend(disp16)
1
1
n
GR[reg2]←zero-extend(Load-memory
Note 11
dd d d d d d d d d d d d d d 1
(adr,Byte))
Notes 8, 10
LD.H
disp16[reg1],reg2 rr r r r 1 1 1 0 0 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
1
1
1
1
n
dd d d d d d d d d d d d d d 0 GR[reg2] sign-extend(Load-memory
Note 9
←
Note 8 (adr,Half-word))
LD.HU
disp16[reg1],reg2 rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
n
GR[reg2]←zero-extend(Load-memory
Note 11
dd d d d d d d d d d d d d d 1
(adr,Half-word))
Note 8
LD.W
LDSR
disp16[reg1],reg2 rr r r r 1 1 1 0 0 1 R R R R R adr←GR[reg1]+signe-extend(disp16)
dd d d d d d d d d d d d d d 1 GR[reg2] Load-memory(adr,Word)
1
1
1
1
n
←
Note 9
reg2,regID
rr r r r 1 1 1 1 1 1 R R R R R SR[regID]←GR[reg2]
Other than
1
regID=PSW
00 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Note 12
×
×
×
×
×
regID=PSW
MOV
reg1,reg2
rr r r r 0 0 0 0 0 0 R R R R R GR[reg2]←GR[reg1]
1
1
2
1
1
2
1
1
2
imm5,reg2
imm32,reg1
rr r r r 0 1 0 0 0 0 i i i i i GR[reg2]←sign-extend(imm5)
00 0 0 0 1 1 0 0 0 1 R R R R R GR[reg1]←imm32
ii i i i i i i i i i i i i i i
ii i i i i i i i i i i i i i i
MOVEA
MOVHI
MUL
imm16,reg1,reg2 rr r r r 1 1 0 0 0 1 R R R R R GR[reg2]←GR[reg1]+ sign-extend(imm16)
1
1
1
1
1
1
1
1
2
2
ii i i i i i i i i i i i i i i
imm16,reg1,reg2 rr r r r 1 1 0 0 1 0 R R R R R GR[reg2]←GR[reg1]+(imm16 II 016)
ii i i i i i i i i i i i i i i
GR[reg3] II GR[reg2]
GR[reg2] GR[reg1]
← ×
reg1,reg2,reg3
imm9,reg2,reg3
rr r r r 1 1 1 1 1 1 R R R R R
ww w w w 0 1 0 0 0 1 0 0 0 0 0
2
Note 14
rr r r r 1 1 1 1 1 1 i i i i i GR[reg3] II GR[reg2]←GR[reg2] × sign-
w w w w w 0 1 0 0 1 1 1 1 1 0 0 extend(imm9)
2
Note 14
Note 13
MULH
MULHI
reg1,reg2
rr r r r 0 0 0 1 1 1 R R R R R GR[reg2]←GR[reg2]Note 6 × GR[reg1]Note 6
1
1
1
1
1
1
2
2
2
rr r r r 0 1 0 1 1 1 i i i i i
GR[reg2]
GR[reg2]Note 6
← ×
sign-extend (imm5)
imm5,reg2
imm16,reg1,reg2 rr r r r 1 1 0 1 1 R R R R R R GR[reg2]←GR[reg1]Note 6 × imm16
ii i i i i i i i i i i i i i i
59
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(4/7)
Execution
Flags
Clock
Mnemonic
MULU
Operand
Opcode
Operation
i
r
l
CY OV
S
Z
SAT
GR[reg3] II GR[reg2]
GR[reg2] GR[reg1]
← ×
reg1,reg2,reg3
imm9,reg2,reg3
rr r r r 1 1 1 1 1 1 R R R R R
w w w w w 0 1 0 0 0 1 0 0 0 1 0
1
2
2
Note 14
r r r r r 1 1 1 1 1 1 i i i i i GR[reg3] II GR[reg2]←GR[reg2] × zero-
ww w w w 0 1 0 0 1 1 1 1 1 1 0 extend(imm9)
1
2
2
Note 14
NOP
NOT
NOT1
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pass at least one clock cycle doing nothing
rr r r r 0 0 0 0 0 1 R R R R R GR[reg2]←NOT(GR[reg1])
1
1
3
1
1
3
1
1
3
reg1,reg2
0
×
×
×
bit#3,disp16[reg1] 01 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d d Z flag Not(Load-memory-bit(adr,bit#3))
Note 3 Note 3 Note 3
←
Store-memory-bit(adr,bit#3,Z flag)
reg2,[reg1]
reg1,reg2
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
3
3
3
×
Z flag←Not(Load-memory-bit(adr,reg2))
Note 3 Note 3 Note 3
00 0 0 0 0 0 0 1 1 1 0 0 0 1 0
Store-memory-bit(adr,reg2,Z flag)
OR
rr r r r 0 0 1 0 0 0 R R R R R GR[reg2]←GR[reg2] OR GR[reg1]
1
1
1
1
1
1
0
0
×
×
×
×
ORI
imm16,reg1,reg2 rr r r r 1 1 0 1 0 0 R R R R R GR[reg2]←GR[reg1] OR zero-
ii i i i i i i i i i i i i i i extend(imm16)
PREPARE list12,imm5
00 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp-4,GR[reg in list12],Word) N+1 N+1 N+1
LL L L L L L L L L L 0 0 0 0 1 sp sp-4
Note 4 Note 4 Note 4
←
repeat 1 step above until all regs in list12 is
stored sp←sp-zero-extend(imm5)
list12,imm5,
00 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp-4,GR[reg in list12],Word) N+2 N+2 N+2
sp/immNote 15
LL L L L L L L L L L f f 0 1 1 sp←sp-4
Note 4 Note 4 Note 4
imm16/imm32
repeat 1 step above until all regs in list12 is Note 17 Note 17 Note 17
Note 16 stored sp←sp-zero-extend(imm5)
RETI
00 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP=1
then PC
3
3
3
R
R
R
R
R
←EIPC
00 0 0 0 0 0 1 0 1 0 0 0 0 0 0
PSW
←EIPSW
else if PSW.NP = 1
then
else
PC
PSW ←FEPSW
PC
←EIPC
PSW ←EIPSW
←FEPC
SAR
reg1,reg2
imm5,reg2
cccc,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]arithmetically shift right
0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 by GR[reg1]
1
1
1
1
1
1
1
1
1
×
×
0
0
×
×
×
×
rr r r r 0 1 0 1 0 1 i i i i i GR[reg2]←GR[reg2]arithmetically shift right
by zero-extend(imm5)
SASF
rr r r r 1 1 1 1 1 0 c c c c c if conditions are satisfied
00 0 0 0 0 1 0 0 0 0 0 0 0 0 0 then GR[reg2] (GR[reg2] Logically shift
←
left by 1)
OR 00000001H
else GR[reg2]←(GR[reg2] Logically shift
left by 1)
OR 00000000H
60
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(5/7)
Execution
Flags
Clock
Mnemonic
SATADD
Operand
Opcode
Operation
i
r
l
CY OV
S
×
×
Z
×
×
SAT
×
reg1,reg2
rr r r r 0 0 0 1 1 0 R R R R R GR[reg2]←saturated(GR[reg2]+GR[reg1])
1
1
1
1
1
1
×
×
×
×
imm5,reg2
rr r r r 0 1 0 0 0 1 i i i i i GR[reg2]←saturated(GR[reg2]+sign-
×
extend(imm5)
SATSUB
SATSUBI
reg1,reg2
rr r r r 0 0 0 1 0 1 R R R R R GR[reg2]←saturated(GR[reg2]−GR[reg1])
1
1
1
1
1
1
×
×
×
×
×
×
×
×
×
×
imm16,reg1,reg2 rr r r r 1 1 0 0 1 1 R R R R R GR[reg2]←saturated(GR[reg1]−sign-
ii i i i i i i i i i i i i i i extend(imm16)
SATSUBR reg1,reg2
rr r r r 0 0 0 1 0 0 R R R R R GR[reg2]←saturated(GR[reg1]−GR[reg2])
rr r r r 1 1 1 1 1 1 0 c c c c If conditions are satisfied
1
1
1
1
1
1
×
×
×
×
×
SETF
cccc,reg2
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 then GR[reg2] 00000001H
←
else GR[reg2]←00000000H
SET1
bit#3,disp16[reg1] 00 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
3
3
3
×
×
dd d d d d d d d d d d d d d d Z flag Not(Load-memory-bit(adr,bit#3))
Note 3 Note 3 Note 3
←
Store-memory-bit(adr,bit#3,1)
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
3
3
3
00 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Z flag Not(Load-memory-bit(adr,reg2))
Note 3 Note 3 Note 3
←
Store-memory-bit(adr,reg2,1)
SHL
SHR
reg1,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2] logically shift left by
1
1
1
1
1
1
1
1
1
1
1
1
1
1
×
×
×
×
0
0
0
0
×
×
×
×
×
×
×
×
GR[reg1]
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
imm5,reg2
reg1,reg2
rr r r r 0 1 0 1 1 0 i i i i i GR[reg2]←GR[reg2] logically shift left by
zero-extend(imm5)
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2] logically shift right by
GR[reg1]
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
imm5,reg2
disp7[ep],reg2
rr r r r 0 1 0 1 0 0 i i i i i GR[reg2]←GR[reg2] logically shift right by
zero-extend(imm5)
SLD.B
rr r r r 0 1 1 0 d d d d d d d adr←ep+zero-extend(disp7)
GR[reg2]←sign-extend(Load-
n
Note 9
memory(adr,Byte))
SLD.BU
SLD.H
disp4[ep],reg2
rr r r r 0 0 0 0 1 1 0 d d d d adr←ep+zero-extend(disp4)
GR[reg2]←zero-extend(Load-
1
1
1
1
1
1
n
Note 9
Note 18
memory(adr,Byte))
disp8[ep],reg2
rr r r r 1 0 0 0 d d d d d d d adr←ep+zero-extend(disp8)
n
GR[reg2]←sign-extend(Load-
Note 9
Note 19
memory(adr,Half-word))
SLD.HU
disp5[ep],reg2
rr r r r 0 0 0 0 1 1 1 d d d d adr←ep+zero-extend(disp5)
GR[reg2]←zero-extend(Load-
n
Note 9
Notes 18, 20
memory(adr,Half-word))
SLD.W
SST.B
disp8[ep],reg2
rr r r r 1 0 1 0 d d d d d d 0 adr←ep+zero-extend(disp8)
1
1
1
1
n
GR[reg2]←Load-memory(adr,Word))
Note 9
Note 21
reg2,disp7[ep]
rr r r r 0 1 1 1 d d d d d d d adr←ep+zero-extend(disp7)
1
Store-memory(adr,GR[reg2],Byte)
61
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(6/7)
Execution
Flags
Clock
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z
SAT
SST.H
SST.W
ST.B
reg2,disp8[ep]
reg2,disp8[ep]
rr r r r 1 0 0 1 d d d d d d d adr←ep+zero-extend(disp8)
Note 19 Store-memory(adr,GR[reg2],Half-word)
1
1
1
rr r r r 1 0 1 0 d d d d d d 1 adr←ep+zero-extend(disp8)
Note 21 Store-memory(adr,GR[reg2],Word)
1
1
1
1
1
1
1
1
1
reg2,disp16[reg1] rr r r r 1 1 1 0 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
dd d d d d d d d d d d d d d d
ST.H
reg2,disp16[reg1] rr r r r 1 1 1 0 1 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d 0 Store-memory(adr,GR[reg2],Half-word)
Note 8
ST.W
STSR
reg2,disp16[reg1] rr r r r 1 1 1 0 1 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d 1 Store-memory(adr,GR[reg2],Word)
Note 8
1
1
1
1
1
1
regID,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←SR[regID]
00 0 0 0 0 0 0 0 1 0 0 0 0 0 0
SUB
reg1,reg2
reg1,reg2
reg1
rr r r r 0 0 1 1 0 1 R R R R R GR[reg2]←GR[reg2]−GR[reg1]
rr r r r 0 0 1 1 0 0 R R R R R GR[reg2]←GR[reg1]−GR[reg2]
1
1
5
1
1
5
1
1
5
×
×
×
×
×
×
×
×
SUBR
SWITCH
00 0 0 0 0 0 0 0 1 0 R R R R R adr←(PC+2)+(GR[reg1] logically shift left
by 1)
PC←(PC+2)+sign-extend((Load-
memory(adr,Hafl-word))
logically shift left by 1)
SXB
reg1
00 0 0 0 0 0 0 1 0 1 R R R R R GR[reg1]←sign-extend
1
1
3
1
1
3
1
1
3
(GR[reg1] (7 : 0)
SXH
TRAP
reg1
00 0 0 0 0 0 0 1 1 1 R R R R R GR[reg1]←sign-extend
(GR[reg1] (15 : 0))
vector
00 0 0 0 1 1 1 1 1 1 i i i i i EIPC
00 0 0 0 0 0 1 0 0 0 0 0 0 0 0 EIPSW
←PC+4 (restore PC)
PSW
←
ECR.EICC
←Interrupt code
←1
PSW.EP
PSW.ID
PC
←1
←00000040H (when vector
is 00H to 0FH)
00000050H (when vector
is 10H to 1FH)
TST
reg1,reg2
rr r r r 0 0 1 0 1 1 R R R R R result←GR[reg2] AND GR[reg1]
1
3
1
3
1
3
0
×
×
×
TST1
bit#3,disp16[reg1] 11 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d d Z flag Not(Load-memory-bit(adr,bit#3))
Note 3 Note 3 Note 3
←
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
3
3
3
×
00 0 0 0 0 0 0 1 1 1 0 0 1 1 0 Z flag Not(Load-memory-bit(adr,reg2))
Note 3 Note 3 Note 3
←
62
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(7/7)
Execution
Flags
Clock
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
×
×
Z
×
×
SAT
XOR
reg1,reg2
rr r r r 0 0 1 0 0 1 R R R R R GR[reg2]←GR[reg2] XOR GR[reg1]
1
1
1
1
1
1
0
0
XORI
imm16,reg1,reg2 rr r r r 1 1 0 1 0 1 R R R R R GR[reg2]←GR[reg1] XOR zero-extend
(imm16)
ii i i i i i i i i i i i i i i
ZXB
ZXH
reg1
reg1
00 0 0 0 0 0 0 1 0 0 R R R R R GR[reg1]←zero-extend(GR[reg1] (7 : 0))
00 0 0 0 0 0 0 1 1 0 R R R R R GR[reg1]←zero-extend(GR[reg1] (15 : 0))
1
1
1
1
1
1
Notes 1. dddddddd: Higher 8 bits of disp9.
2. 3 clocks if the final instruction includes PSW write access.
3. If there is no wait state (3 + the number of read access wait states).
4. N is the total number of list 12 read registers. (according to the number of wait states. Also, if there are
no wait states, N is the number of list 12 registers.)
5. RRRRR other than 00000.
6. Only the lower half word data are valid.
7. ddddddddddddddddddddd: Higher 21 bits of disp22.
8. ddddddddddddddd: Higher 15 bits of disp16.
9. According to the number of wait states (1 if there are no wait states).
10. b: bit 0 of disp16.
11. According to the number of wait states (2 if there are no wait states).
12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
reg1 field is used in the op code. Therefore, the meaning of the register specification in the mnemonic
description and in the opcode differs from other instructions.
rrrrr
: regID specification
RRRRR: reg2 specification
13. 11111: Lower 5 bits of imm9.
1111 : Lower 4 bits of imm9.
14. 1 when r = w (the lower 32 bits of the results are not written in the register) or w = r0 (the higher 32 bits
of the results are not written in the register).
15. sp/imm: specified by bits 19 and 20 of the sub opcode.
16. ff = 00: load sp in ep.
01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: load 32-bit immediate data (bits 63 to 32) in ep.
17. If imm=imm32, N + 3 clocks.
18. rrrrr other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.
63
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD
Condition
Rating
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +4.6
−0.5 to +0.5
−0.5 to HVDD + 0.5
−0.5 to +0.5
−0.5 to HVDD + 0.5
−0.5 to VDD + 0.5
−0.5 to VDD + 1.0
4.0
Unit
V
Power supply voltage
VDD pin
HVDD
CVDD
CVSS
AVDD
AVSS
VI
HVDD pin, HVDD ≥ VDD
CVDD pin
V
V
CVSS pin
V
AVDD pin
V
AVSS pin
V
Input voltage
X1 pin, except MODE3 pin
MODE3 pin
V
V
Clock input voltage
VK
IOL
X1, VDD = 3.0 to 3.6 V
1 pin
V
Low-level output current
mA
mA
mA
mA
V
Total of all pins
1 pin
100
High-level output current
LOH
−4.0
Total of all pins
HVDD = 5.0 V ± 10 %
−100
Output voltage
VO
−0.5 to HVDD + 0.5
−0.5 to HVDD + 0.5
−0.5 to AVDD + 0.5
−0.5 to HVDD + 0.5
−0.5 to AVDD + 0.5
−40 to +70
Analog input voltage
VIAN
P70/ANI0 to
AVDD > HVDD
V
P77/ANI7 pins
HVDD ≥ AVDD
V
A/D converter reference input
voltage
AVREF
AVDD > HVDD
HVDD ≥ AVDD
µPD703100-40
V
V
Operating ambient temperature
Storage temperature
TA
°C
°C
°C
µPD703100-33, 703101-33, 703102-33
−40 to +85
Tstg
−60 to +150
Caution
1. Do not make direct connections of the output (or input/output) pins of the IC product with
each other, and also avoid direct connections to VDD, VCC, or GND. However, the open drain
pins or the open collector pins can be directly connected with each other. A direct
connection can also be made for an external circuit designed with timing specifications that
prevent conflicting output from pins subject to high-impedance state.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
64
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Capacitance (TA = 25°C, VDD = HVDD = CVDD = VSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Condition
MIN.
TYP.
MAX.
15
Unit
pF
fc = 1 MHz
Unmeasured pins returned to 0 V.
Input/output capacitance
Output capacitance
CIO
pF
15
CO
pF
15
Operating Conditions
Operation
Mode
Operating Ambient
Temperature (TA)
Power Supply Voltage
(VDD, HVDD)
Internal Operating Clock Frequency (φ)
Direct mode
µPD703100-40
2 to 40 MHz
−40 to +70°C
−40 to +85°C
−40 to +70°C
−40 to +85°C
VDD = 3.0 to 3.6 V,
HVDD = 5.0 V ±10%
µPD703100-33, 703101-33, 703102-33
µPD703100-40
2 to 33 MHz
20 to 40 MHz
20 to 33 MHz
PLL mode
µPD703100-33, 703101-33, 703102-33
Recommended Oscillation Circuits
(a) Ceramic resonator or crystal resonator connection (TA = –40 to +70°C ... µPD703100-40,
TA = –40 to +85°C ... µPD703100-33, µPD703101-33, µPD703102-33)
X1
X2
C1
C2
Cautions 1. Connect the oscillation circuit as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken line.
3. Throughly evaluate the matching between the µPD703100-33, µPD703100-40, µPD703101-33,
and µPD703102-33 and the oscillators.
(b) External clock input (TA = –40 to +70°C ... µPD703100-40, TA = –40 to +85°C ... µPD703100-33, µPD703101-
33, µPD703102-33)
X1
X2
Open
External clock
Caution Input CMOS-level voltage to the X1 pin.
65
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
DC Characteristics (TA = –40 to +70°C ... µPD703100-40,TA = –40 to +85°C ... µPD703100-33, µPD703101-33,
µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±10%, VSS=0 V)
Parameter
Symbol
VIH
Condition
Except Note 1
MIN.
2.2
TYP.
MAX.
HVDD + 0.3
HVDD + 0.3
+0.8
Unit
V
High-level input voltage
Note 1
0.8HVDD
−0.5
V
Low-level input voltage
VIL
VXH
VXL
Except Note 1 and Note 2
V
Note 1
−0.5
0.2HVDD
VDD + 0.3
VDD + 0.3
0.15VDD
0.15VDD
V
High-level clock input voltage
Low-level clock input voltage
X1 pin
Direct mode
PLL mode
Direct mode
PLL mode
0.8VDD
0.8VDD
−0.3
V
V
X1 pin
V
−0.3
V
Schmitt-triggered input
threshold voltage
HVT+
Note 1, rising edge
Note 1, falling edge
Note 1
3.0
2.0
V
−
HVT
V
Schmitt-triggered input
hysteresis width
HVT+
0.5
V
−
–HVT
High-level output voltage
VOH
IOH = −2.5 mA
IOH = −100 µA
IOL = 2.5 mA
0.7HVDD
V
V
HVDD − 0.4
Low-level output voltage
VOL
ILIH
0.45
10
V
High-level input leakage
current
Except V
I = HVDD or Note 2
µA
Low-level input leakage
current
ILIL
ILOH
ILOL
ILIAN
Except V
I = 0 V or Note 2
−10
10
µA
µA
µA
µA
High-level output leakage
current
VO = HVDD
VO = 0 V
Note 2
Low-level output leakage
current
−10
Analog pin input leakage
current
T.B.D.
otes 1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/S12, P37/INTP133/SCK2, P104/INTP120/TC0 to
P107/INTP123/TC3, Pl14/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,
P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2,
RESET
2. When the P70/ANI0 to P77/ANI7 pins are used as analog input.
Remark TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
66
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
DC Characteristics (TA = –40 to +70°C ... µPD703100-40,TA = –40 to +85°C ... µPD703100-33, µPD703101-33,
µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±10%, VSS = 0 V)
Parameter
Symbol
IDD1
Condition
VDD + CVDD
MIN.
TYP.
MAX.
Unit
mA
mA
mA
Power supply
current
During
Direct mode
2.0 × fx
1.8 × fx
3.6 × fx
3.0 × fx
3.6 × fx
normal
HVDD
operation
PLL mode
VDD + CVDD
2.7 × fx
− 17.0
HVDD
1.3 × fx
− 3.6
3.0 × fx
mA
HALT mode
IDD2
Direct mode
PLL mode
VDD + CVDD
HVDD
1.4 × fx
0.8 × fx
2.5 × fx
1.6 × fx
2.5 × fx
mA
mA
mA
VDD + CVDD
1.8 × fx
− 10.0
HVDD
0.8 × fx
− 1.0
1.6 × fx
mA
IDLE mode
IDD3
Direct mode
PLL mode
VDD + CVDD
HVDD
1.5
10
1.8
10
20
10
3.0
50
mA
µA
mA
µA
µA
µA
VDD + CVDD
HVDD
3.0
50
STOP
mode
IDD4
VDD + CVDD
HVDD
100
50
Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
2. Direct mode:
fX = 2 to 40 MHz (µPD703100-40)
fX = 2 to 33 MHz (µPD703100-33, µPD703101-33, µPD703102-33)
PLL mode:
fX = 20 to 40 MHz (µPD703100-40)
fX = 20 to 33 MHz (µPD703100-33, µPD703101-33, µPD703102-33)
67
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Data Hold Characteristics(TA = –40 to +70°C ... µPD703100-40, TA = –40 to +85°C ... µPD703100-33, µPD703101-
33, µPD703102-33)
Parameter
Data hold voltage
Symbol
VDDDR
Condition
MIN.
1.5
TYP.
MAX.
3.6
Unit
V
STOP mode, VDD = VDDDR
HVDDDR
STOP mode,
VDDDR
5.5
V
HVDD = HVDDDR
Data hold current
IDDDR
tRVD
VDD = VDDDR
T.B.D.
T.B.D.
µA
µs
Power supply voltage rise
time
200
Power supply voltage fall time
tFVD
tHVD
200
0
µs
Power supply voltage hold
time (to STOP mode setting)
ms
STOP mode release signal
input time
tDREL
VIHDR
VILDR
0
ns
V
Data hold high-level input
voltage
Note
Note
0.8 HVDDDR
HVDDDR
Data hold low-level input
voltage
0
0.2 HVDDDR
V
Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to
P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, Pl16/INTP142/SI3, P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12,P113/TI14,
P123/TI15, P20/NMI, P23/RXD0/SI0 ,P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
Remark TYP. values are reference values for when TA = 25°C.
STOP mode setting
VDDDR
VDD
t
FVD
tRVD
t
HVD
tDREL
HVDD
V
IHDR
RESET (input)
NMI (input)
VIHDR
(Released by falling edge)
NMI (input)
(Released by rising edge)
VILDR
68
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
AC Characteristics (TA = –40 to +70°C ... µPD703100-40, TA = –40 to +85°C ... µPD703100-33, µPD703101-33,
µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±10%, VSS = 0 V, output pin load
capacitance: CL = 50 pF)
AC Test Input Waveform
(a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/
INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/
TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/
INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14,
P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/
SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
HVDD
0.8HVDD
0.2HVDD
0.8HVDD
0.2HVDD
Test
points
Input signal
0 V
(b) Pins other than those listed in (a) above
2.4 V
2.2 V
2.2 V
0.8 V
Test
points
Input signal
0.8 V
0.4 V
AC Test Output Test Points
2.4 V
0.8 V
2.4 V
0.8 V
Test
points
Output Signal
69
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Load Condition
DUT
(Measured Device)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert
a buffer or other element to reduce the devide's load capacitance 50 pF.
(1) Clock timing
Parameter
X1 input cycle
Symbol
Condition
µPD703100-40
MIN.
12.5
15
MAX.
250
Unit
ns
<1>
tCYX
Direct
mode
µPD703100-33,
703101-33,
250
ns
703102-33
PLL mode
µPD703100-40
125
150
250
250
ns
ns
µPD703100-33,
703101-33,
703102-33
X1 input high-level width
X1 input low-level width
X1 input rise time
<2>
<3>
<4>
<5>
–
tWXH
tWXL
tXR
tXF
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
5
50
5
ns
ns
ns
50
ns
4
ns
10
4
ns
X1 input fall time
ns
10
40
33
ns
CPU operating frequency
φ
µPD703100-40
2
2
MHz
MHz
µPD703100-33, 703101-33,
703102-33
CLKOUT output cycle
<6>
<7>
tCYK
tWKH
tWKL
tKR
30
500
ns
ns
ns
ns
ns
ns
CLKOUT input high-level width
CLKOUT input low-level width
CLKOUT input rise time
0.5T – 7
0.5T – 4
<8>
<9>
5
5
CLKOUT input fall time
<10>
<11>
tKF
CLKOUT output delay time from X1 ↓
tDXK
Direct mode
T.B.D.
T.B.D.
Remark T = tCYK
Parameter
Symbol
φP
Condition
PLL mode
TYP.
T.B.D.
Unit
Free-running oscillation frequency
–
MHz
70
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
<1>
<2>
<3>
<4>
<5>
X1
(PLL mode)
<1>
<3>
<2>
<4>
X1
(Direct mode)
<5>
<11>
<9>
<11>
CLKOUT (output)
<10>
<7>
<8>
<6>
(2) Output waveform (other than X1, CLKOUT)
Parameter
Symbol
Condition
MIN.
MAX.
10
Unit
ns
Output rise time
Output fall time
<12>
<13>
tOR
tOF
10
ns
<12>
<13>
Signals other than X1, CLKOUT
71
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(3) Reset timing
Parameter
RESET high-level width
RESET low-level width
Symbol
Condition
MIN.
500
MAX.
Unit
ns
<14>
<15>
tWRSH
tWRSL
When power supply is on, and
STOP mode has been released
500 + TOS
ns
Other than when power supply is
on, and STOP mode has been
released
500
ns
Remark TOS: Oscillation stabilization time
<14>
<15>
RESET (input)
72
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
73
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(4) SRAM, external ROM, or external I/O access timing
(a) Access timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
<16> tDKA
Condition
Unit
ns
MIN.
2
MAX.
10
Address, CSn output delay time (from
CLKOUT ↓)
Address, CSn output hold time (from
<17>
<18>
<19>
<20>
<21>
<22>
<23>
tHKA
2
2
2
2
2
2
2
10
14
14
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
CLKOUT ↓)
RD, IORD ↓ delay time
(from CLKOUT ↑)
tDKRDL
tHKRDH
tDKWRL
tHKWRH
tDKBSL
tHKBSH
RD, IORD ↑ delay time
(from CLKOUT ↑)
UWR, LWR, IOWR ↓ delay time (from
CLKOUT ↑)
UWR, LWR, IOWR ↑ delay time (from
CLKOUT ↑)
BCYST ↓ delay time (from CLKOUT
↓)
BCYST ↑ delay time (from CLKOUT
↓)
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
<24>
<25>
<26>
tSWK
tHKW
tSKID
15
2
ns
ns
ns
Data input setup time
18
(to CLKOUT ↑)
Data input hold time
<27>
<28>
<29>
tHKID
tDKOD
tHKOD
2
2
2
ns
ns
ns
(from CLKOUT ↑)
Data output delay time
10
10
(from CLKOUT ↓)
Data output hold time
(from CLKOUT ↓)
Remarks 1. Maintain at least one of the data input hold times tHKID and tHRDID.
2. n = 0 to 7
74
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(a) Access timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
<16>
<22>
<17>
A0 to A23 (Output)
CSn (Output)
<23>
BCYCT (Output)
<18>
<20>
<19>
RD, IORD (Output)
[Read time]
<21>
<27>
UWR, LWR, IOWR (Output)
[Write time]
<26>
D0 to 15 (I/O)
[Read time]
<28>
<29>
D0 to 15 (I/O)
[Write time]
<25>
<25>
<24>
<24>
WAIT (Input)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
75
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
<30>
Condition
MIN.
MAX.
Unit
ns
Data input setup time (to address)
Data input setup time (to RD)
RD, IORD low-level width
RD, IORD high-level width
tSAID
tSRDID
tWRDL
tWRDH
tDARD
(1.5 + wD + w) T – 28
(1 + wD + w) T – 32
<31>
<32>
<33>
<34>
ns
(1 + wD + w) T – 10
T – 10
ns
ns
RD, IORD ↓ delay time from address,
0.5T – 10
ns
CSn
Address delay time from RD, IORD ↑
<35>
<36>
<37>
<38>
<39>
<40>
tDRDA
tHRDID
tDRDOD
tSAW
(0.5 + i) T – 10
0
ns
ns
ns
ns
ns
ns
Data input hold time (from RD, IORD )
↑
Data output delay time from RD, IORD
WAIT setup time (to address)
WAIT setup time (to BCYST ↓)
WAIT hold time (to BCYST ↑)
↑
(0.5 + i) T – 10
Note
Note
Note
T – 25
T – 25
tSBSW
tHBSW
0
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
5. Maintain at least one of the data input hold times tHKID and tHRDID.
6. n = 0 to 7
76
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
UWR, LWR, IOWR (Output)
RD, IORD (Output)
D0 to 15 (I/O)
<33>
<32>
<35>
<37>
<34>
<31>
<30>
<36>
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
77
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
<38>
Condition
Note
MIN.
MAX.
T – 25
T – 25
Unit
ns
WAIT setup time (to address)
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
tSAW
tSBSW
tHBSW
tDAWR
<39>
<40>
<41>
Note
ns
Note
0
ns
UWR, LWR, IOWR ↓ delay time from
0.5T – 10
ns
address, CSn
Address setup time (to UWR, LWR,
<42>
<43>
tSAWR
(1.5 + wD + w) T – 10
0.5T – 10
ns
ns
IOWR ↑)
Address delay time from UWR, LWR,
tDWRA
IOWR ↑
UWR, LWR, IOWR high-level width
UWR, LWR, IOWR low-level width
<44>
<45>
<46>
tWWRH
tWWRL
tSODWR
T – 10
ns
ns
ns
(1 + wD + w) T – 10
(1.5 + wD + w) T – 10
Data output setup time
(to UWR, LWR, IOWR ↑)
Data output hold time
<47>
tHWROD
0.5T – 10
ns
(from UWR, LWR, IOWR ↑)
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. n = 0 to 7
78
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
RD, IORD (Output)
UWR, LWR, IOWR (Output)
D0 to 15 (I/O)
<42>
<43>
<41>
<45>
<44>
<46>
<47>
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
79
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (1/2)
Parameter
Symbol
<24> tSWK
tHKW
Condition
Unit
ns
MIN.
15
2
MAX.
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
RD low-level width
<25>
<32>
ns
tWRDL
(1 + w
D
+ w
F
+ w)
ns
T – 10
RD high-level width
<33>
<34>
<35>
<37>
<38>
<39>
<40>
<41>
<42>
<43>
tWRDH
tDARD
tDRDA
tDRDOD
tSAW
T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD ↓ delay time from address, CSn
Address delay time from RD ↑
Data output delay time from RD ↑
WAIT setup time (to address)
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
IOWR ↓ delay time from address
Address setup time (to IOWR ↑)
0.5T – 10
(0.5 + i) T – 10
(0.5 + i) T – 10
Note
Note
Note
T – 25
T – 25
tSBSW
tHBSW
tDAWR
tSAWR
tDWRA
0
0.5T – 10
(1.5 + wD + w) T – 10
0.5T – 10
Address delay time from UWR, LWR,
IOWR ↑
IOWR high-level width
<44>
<45>
<48>
tWWRH
tWWRL
tDWRRD
T – 10
(1 + wD + w) T – 10
0
ns
ns
ns
ns
ns
ns
IOWR low-level width
RD ↑ delay time from IOWR ↑
wF = 0
wF = 1
T – 10
IOWR ↓ delay time from DMAAKm ↓
DMAAKm ↑ delay time from IOWR ↑
<49>
<50>
tDDAWR
tDWRDA
0.5T – 10
(0.5 + wF) T – 10
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0 to 7, m = 0 to 3
80
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<33>
<32>
<35>
RD (Output)
UWR, LWR (Output)
DMAAKm (Output)
IORD (Output)
<34>
<48>
<49>
<41>
<50>
<43>
<42>
<45>
<44>
IOWR (Output)
D0 to 15 (I/O)
<37>
<38>
<24>
<25>
<24>
<25>
WAIT (Input)
<40>
<39>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
81
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2)
Parameter
Symbol
<24> tSWK
tHKW
Condition
MIN.
15
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
IORD low-level width
<25>
<32>
2
ns
tWRDL
(1 + wD + wF + w)
T – 10
ns
IORD high-level width
<33>
<34>
<35>
<37>
<38>
<39>
<40>
<41>
<42>
<43>
tWRDH
tDARD
tDRDA
tDRDOD
tSAW
T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IORD ↓ delay time from address, CSn
Address delay time from IORD ↑
Data output delay time from IORD ↑
WAIT setup time (to address)
0.5T – 10
(0.5 + i) T – 10
(0.5 + i) T – 10
Note
Note
Note
T – 25
T – 25
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
UWR, LWR ↓ delay time from address
Address setup time (to UWR, LWR ↑)
tSBSW
tHBSW
tDAWR
tSAWR
tDWRA
0
0.5T – 10
(1.5 + wD + w) T – 10
0.5T – 10
Address delay time from UWR, LWR,
IOWR ↑
UWR, LWR high-level width
<44>
<45>
<48>
tWWRH
tWWRL
tDWRRD
T – 10
(1 + wD + w) T – 10
0
ns
ns
ns
ns
ns
ns
UWR, LWR low-level width
IORD ↑ delay time from UWR, LWR↑
wF = 0
wF = 1
T – 10
IORD ↓ delay time from DMAAKm ↓
DMAAKm ↑ delay time from IORD ↑
<51>
<52>
tDDARD
tDRDDA
0.5T – 10
0.5T – 10
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0 to 7, m = 0 to 3
82
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<42>
<45>
<43>
<35>
<41>
<44>
UWR, LWR (Output)
<48>
RD (Output)
<51>
<52>
DMAAKm (Output)
IOWR (Output)
IORD (Output)
D0 to 15 (I/O)
<34>
<33>
<32>
<35>
<37>
<38>
<24>
<25>
<24>
<25>
WAIT (Input)
<40>
<39>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
83
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (1/2)
Parameter
Symbol
<24>
Condition
MIN.
15
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
tSWK
tHKW
tSKID
<25>
<26>
2
ns
Data input setup time
18
ns
(to CLKOUT ↑)
Data input hold time
<27>
<30>
tHKID
2
ns
ns
(from CLKOUT ↑)
Off-page data input setup time (to
address)
tSAID
(1.5 + wD + w) T – 28
(1 + wD + w) T – 32
Off-page data input setup time (to RD)
Off-page RD low-level width
RD high-level width
<31>
<32>
<33>
<36>
<37>
<53>
tSRDID
tWRDL
ns
ns
ns
ns
ns
ns
(1 + wD + w) T – 10
0.5T – 10
tWRDH
tHRDID
tDRDOD
tWORDL
Data input hold time (from RD)
Data output delay time from RD ↑
On-page RD low-level width
0
(0.5 + i) T – 10
(1.5 + wPR + w)
T – 10
On-page data input setup time
(to address)
<54>
<55>
tSOAID
(1.5 + wPR + w) T – 28
(1.5 + wPR + w) T – 32
ns
ns
On-page data input setup time (to RD)
tSORDID
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wPR: the number of waits due to the PRC register.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. Maintain at least one of the data input hold times tHKID and tHRDID.
84
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (2/2)
T1
TDW
TW
T2
TO1 TPRW
TW
TO2
CLKOUT (Output)
Off-page address Note
CSn (Output)
On-page address Note
UWR, LWR (Output)
RD (Output)
<26>
<30>
<31>
<54>
<33>
<53>
<55>
<32>
<37>
<36>
<27>
<36>
<27>
<26>
<25>
D0 to 15 (I/O)
<25>
<24>
<24>
<25>
<24>
<25>
<24>
WAIT (Input)
BCYST (Output)
Note On-page and off-page addresses are as follows.
PRC register
On-page Addresses
Off-page Addresses
MA5
MA4
MA3
0
0
0
1
0
0
1
1
0
1
1
1
A0, A1
A0 to A2
A0 to A3
A0 to A4
A2 to A23
A3 to A23
A4 to A23
A5 to A23
Remarks 1. This is the timing for the following case.
Number of waits due to the DWC1 and DWC2 registers (TDW): 1
Number of waits due to the PRC register (TPRW)
2. The broken lines indicate high impedance.
3. n = 0 to 7
: 1
85
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(6) DRAM access timing
(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter
Symbol
<24>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Data output delay time from OE ↑
Row address setup time
tSWK
tHKW
tSKID
tHKID
tDRDOD
tASR
15
<25>
<26>
<27>
<37>
<56>
<57>
<58>
<59>
<60>
2
18
2
(0.5 + i) T – 10
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
Row address hold time
tRAH
tASC
tCAH
tRC
Column address setup time
Column address hold time
(1.5 + wDA + w) T – 10
Read/write cycle time
(3 + wRP + wRH + wDA + w)
T – 10
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP) T – 10
ns
ns
tRAS
(2.5 + wRH + wDA + w)
T – 10
RAS hold time
<63>
<64>
<65>
<66>
<67>
tRSH
tRAL
tCAS
tCRP
tCSH
(1.5 + wDA + w) T – 10
(2 + wDA + w) T – 10
(1 + wDA + w) T – 10
(1 + wRP) T – 10
ns
ns
ns
ns
ns
Column address read time for RAS
CAS pulse width
CAS-RAS precharge time
CAS hold time
(2 + wRH + wDA + w)
T – 10
WE setup time
<68>
<69>
<70>
<71>
<72>
tRCS
tRRH
tRCH
tCPN
tOEA
(2 + wRP + wRH) T – 10
0.5T – 10
ns
ns
ns
ns
ns
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
CAS precharge time
T – 10
(2 + wRP + wRH) T – 10
Output enable access time
(2 + wRP + wRH + wDA + w)
T – 28
RAS access time
<73>
tRAC
(2 + wRH + wDA + w)
T – 28
ns
Access time from column address
CAS access time
<74>
<75>
tAA
(1.5 + wDA + w) T – 28
(1 + wDA + w) T – 28
ns
ns
tCAC
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
86
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)
Parameter
RAS column address delay time
RAS-CAS delay time
Symbol
<76>
Condition
Unit
ns
MIN.
(0.5 + wRH) T – 10
(1 + wRH) T – 10
0
MAX.
tRAD
tRCD
tOEZ
<77>
<78>
ns
Output buffer turn-off delay time (from
ns
OE ↑)
Output buffer turn-off delay time (from
<79>
tOFF
0
CAS ↑)
Remarks 1. T = tCYK
2. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
87
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
TRPW
T1
TRHW
T2
TDAW
TW
T3
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<56>
<57>
<59>
Row address
Column address
<63>
<64>
<76>
<61>
<62>
<60>
<67>
<77>
<65>
<66>
UCAS (Output)
LCAS (Output)
<69>
<70>
<71>
<68>
<73>
<75>
WE (Output)
OE (Output)
<79>
<74>
<27>
<72>
<37>
<78>
<26>
D0 to D15 (I/O)
<24>
<25>
<24>
<25>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
88
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
89
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
<26>
Condition
MIN.
18
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Data output delay time from OE ↑
Column address setup time
Column address hold time
RAS hold time
tSKID
tHKID
tDRDOD
tASC
tCAH
tRSH
tRAL
<27>
<37>
<58>
<59>
<63>
<64>
<65>
<68>
<69>
<70>
<72>
<74>
<75>
<78>
2
(0.5 + i) T – 10
(0.5 + wCP) T – 10
(1.5 + wDA) T – 10
(1.5 + wDA) T – 10
(2 + wCP + wDA) T – 10
(1 + wDA) T – 10
(1 + wCP) T – 10
0.5T – 10
Column address read time for RAS
CAS pulse width
tCAS
tRCS
tRRH
tRCH
tOEA
tAA
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
Output enable access time
Access time from column address
CAS access time
T – 10
(1 + wCP + wDA) T – 28
(1.5 + wCP + wDA) T – 28
tCAC
tOEZ
(1 + wDA) T – 28
Output buffer turn-off delay time (from
0
0
OE ↑)
Output buffer turn-off delay time (from
<79>
tOFF
ns
CAS ↑)
Access time from CAS precharge
CAS precharge time
<80>
<81>
<82>
<83>
tACP
tCP
(2 + wCP + wDA) T – 28
ns
ns
ns
ns
(1 + wCP) T – 10
High-speed page mode cycle time
RAS hold time for CAS precharge
tPC
(2 + wCP + wDA) T – 10
tRHCP
(2.5 + wCP + wDA) T – 10
Remarks 1. T = tCYK
2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
90
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<59>
<63>
Column address
<64>
<83>
<81>
<65>
<82>
UCAS (Output)
LCAS (Output)
<69>
<70>
<68>
WE (Output)
OE (Output)
<75>
<79>
<37>
<72>
<26>
<74>
<80>
<78>
<27>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
91
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Row address setup time
Symbol
<24>
Condition
MIN.
15
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tSWK
tHKW
tASR
tRAH
tASC
tCAH
tRC
<25>
<56>
<57>
<58>
<59>
<60>
2
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
Row address hold time
Column address setup time
Column address hold time
Read/write cycle time
(1.5 + wDA + w) T – 10
(3 + wRP + wRH + wDA + w)
T – 10
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP) T – 10
ns
ns
tRAS
(2.5 + wRH + wDA + w)
T – 10
RAS hold time
<63>
<64>
<65>
<66>
<67>
tRSH
tRAL
tCAS
tCRP
tCSH
(1.5 + wDA + w) T – 10
(2 + wDA + w) T – 10
(1 + wDA + w) T – 10
(1 + wRH) T – 10
ns
ns
ns
ns
ns
Column address read time (from RAS
CAS pulse width
↑
)
CAS-RAS precharge time
CAS hold time
(2 + wRH + wDA + w)
T – 10
CAS precharge time
<71>
<76>
<77>
<84>
tCPN
tRAD
tRCD
tWCS
(2 + wRP + wRH) T – 10
(0.5 + wRH) T – 10
(1 + wRH) T – 10
ns
ns
ns
ns
RAS column address delay time
RAS-CAS delay time
WE setup time (to CAS ↓)
(1 + wRP + wRH )
T – 10
WE hold time (from CAS ↓)
Data setup time (to CAS ↓)
Data hold time (from CAS ↓)
<85>
<86>
<87>
tWCH
tDS
(1 + wDA + w) T – 10
ns
ns
ns
(1.5 + wRP + wRH
)
T – 10
tDH
(1.5 + wDA + w) T – 10
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
92
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)
TRPW
T1
TRHW
T2
TDAW
TW
T3
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<56>
<61>
<57>
<59>
Row address
Column address
<63>
<64>
<76>
<62>
<60>
<67>
<77>
<65>
<66>
UCAS (Output)
LCAS (Output)
<71>
OE (Output)
WE (Output)
<84>
<85>
<86>
<87>
D0 to D15 (I/O)
<24>
<25>
<24>
<25>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
93
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
<58>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
Column address setup time
Column address hold time
RAS hold time
tASC
tCAH
tRSH
tRAL
tCAS
tCP
(0.5 + wCP) T – 10
(1.5 + wDA) T – 10
(1.5 + wDA) T – 10
(2 + wCP + wDA) T – 10
(1 + wDA) T – 10
(1 + wCP) T – 10
<59>
<63>
<64>
<65>
<81>
<83>
Column address read time (from RAS
CAS pulse width
↑
)
CAS precharge time
RAS hold time for CAS precharge
tRHCP
(2.5 + wCP + wDA
)
T – 10
WE setup time (to CAS ↓)
WE hold time (from CAS ↓)
Data setup time (to CAS ↓)
Data hold time (from CAS ↓)
WE read time (from RAS ↑)
WE read time (from CAS ↑)
Data setup time (to WE ↓)
Data hold time (from WE ↓)
WE pulse width
<84>
<85>
<86>
<87>
<88>
<89>
<90>
<91>
<92>
tWCS
tWCH
tDS
wCP ≥ 1
wCPT – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1 + wDA) T – 10
(0.5 + wCP) T – 10
(1.5 + wDA) T – 10
(1.5 + wDA) T – 10
(1 + wDA) T – 10
0.5T – 10
tDH
tRWL
tCWL
tDSWE
tDHWE
tWP
wCP = 0
wCP = 0
wCP = 0
wCP = 0
wCP = 0
(1.5 + wDA) T – 10
(1 + wDA) T – 10
Remarks 1. T = tCYK
2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
94
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<59>
<63>
Column address
<64>
<83>
<81>
<65>
UCAS (Output)
LCAS (Output)
<89>
<88>
OE (Output)
WE (Output)
<84>
<85>
<92>
<91>
<90>
<86>
<87>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW ): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
95
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (1/3)
Parameter
Symbol
<26>
Condition
MIN.
18
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Data output delay time from OE ↑
Row address setup time
tSKID
tHKID
tDRDOD
tASR
tRAH
tASC
tCAH
tRP
<27>
<37>
<56>
<57>
<58>
<59>
<61>
<64>
<66>
<67>
<68>
<69>
<70>
<73>
<74>
<75>
<76>
<77>
<78>
2
(0.5 + i) T – 10
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
Row address hold time
Column address setup time
Column address hold time
RAS precharge time
(0.5 + wDA) T – 10
(0.5 + wRP) T – 10
(2 + wCP + wDA) T – 10
(1 + wRP) T – 10
Column address read time (from RAS
CAS-RAS precharge time
CAS hold time
↑
)
tRAL
tCRP
tCSH
tRCS
tRRH
tRCH
tRAC
tAA
(1.5 + wRH + wDA) T – 10
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
RAS access time
(2 + wRP + wRH) T – 10
0.5T – 10
1.5T – 10
(2 + wRH + wDA) T – 28
Access time from column address
CAS access time
(1.5 + wDA) T – 28
(1 + wDA) T – 28
tCAC
tRAD
tRCD
tOEZ
Column address delay time from RAS
RAS-CAS delay time
(0.5 + wRH) T – 10
(1 + wRH) T – 10
0
Output buffer turn-off delay time (from
OE)
Access time from CAS precharge
CAS precharge time
<80>
<81>
<83>
<93>
<94>
<95>
<96>
<97>
<98>
tACP
tCP
tRHCP
tHPC
(1.5 + wCP + wDA
)
T – 28
ns
ns
ns
ns
ns
ns
ns
ns
ns
(0.5 + wCP) T – 10
(2 + wCP + wDA) T – 10
(1 + wDA + wCP) T – 10
RAS hold time for CAS precharge
Read cycle time
RAS pulse width
tRASP
tHCAS
tOCH1
tOCH2
tDHC
(2.5 + wRH + wDA) T – 10
CAS pulse width
(0.5 + wDA) T – 10
(2 + wRH + wDA) T – 10
(0.5 + wDA) T – 10
0
CAS hold time from OE
Off-page
On-page
Data input hold time (from CAS ↓)
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
96
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (2/3)
Parameter
Symbol
<99> tOEA1
Condition
MIN.
MAX.
Unit
ns
Output enable access
time
Off-page
On-page
(2 + wPR + wRH + wDA)
T – 28
<100>
tOEA2
(1 + wCP + wDA
)
T – 28
ns
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
97
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (3/3)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<57>
<56>
<59>
Row address
<76>
Column address
Column address
<64>
<74>
<61>
<94>
<67>
<83>
<75>
<66>
<77>
<95>
<93>
<81>
UCAS (Output)
LCAS (Output)
<69>
<70>
<68>
<95>
<80>
WE (Output)
OE (Output)
<97>
<96>
<100> <26>
<37>
<75>
<98>
<27>
<27>
<78>
<74>
<26>
D0 to D15 (I/O)
BCYST (Output)
WAIT (Input)
Data
Data
<73>
<99>
Note For on-page access from another cycle during the RASn low level signal.
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
98
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
99
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (1/2)
Parameter
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS precharge time
Symbol
<56>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tASR
tRAH
tASC
tCAH
tRP
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
<57>
<58>
<59>
<61>
<63>
<64>
(0.5 + wDA) T – 10
(0.5 + wRP) T – 10
(1.5 + wDA) T – 10
(2 + wCP + wDA) T – 10
RAS hold time
tRSH
tRAL
Column address read time
(from RAS ↑)
CAS-RAS precharge time
CAS hold time
<66>
<67>
<76>
<77>
<81>
<83>
<85>
<87>
<88>
tCRP
tCSH
tRAD
tRCD
tCP
(1 + wRP) T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1.5 + wRH + wDA) T – 10
Column address delay time from RAS
RAS-CAS delay time
(0.5 + wRH) T – 10
(1 + wRH) T – 10
CAS precharge time
(0.5 + wCP) T – 10
(2 + wCP + wDA) T – 10
(1 + wDA) T – 10
RAS hold time for CAS precharge
WE hold time (from CAS ↓)
Data hold time (from CAS ↓)
tRHCP
tWCH
tDH
(0.5 + wDA) T – 10
(1.5 + wDA) T – 10
WE read time
On-page
On-page
On-page
tRWL
wCP = 0
wCP = 0
wCP = 0
(from RAS ↑)
WE read time
<89>
tCWL
(0.5 + wDA) T – 10
ns
(from CAS ↑)
WE pulse width
Write cycle time
RAS pulse width
CAS pulse width
<92>
<93>
tWP
tHPC
(1 + wDA) T – 10
ns
ns
ns
ns
ns
ns
ns
ns
(1 + wDA + wCP) T – 10
<94>
tRASP
tHCAS
tWCS1
tWCS2
tDS1
(2.5 + wRH + wDA
)
T – 10
(0.5 + wDA) T – 10
T – 10
wCPT – 10
T – 10
(0.5 + wCP) T – 10
<95>
WE setup time
Off-page
On-page
Off-page
On-page
<101>
<102>
<103>
<104>
(1 + wRP + wRH
)
(to CAS ↓)
wCP ≥ 1
Data setup time
(1.5 + wRP + wRH
)
(to CAS ↓)
tDS2
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
100
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (2/2)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<57>
<56>
<59>
<58>
<59>
Row address
<76>
Column address
Column address
<64>
<61>
<94>
<67>
<77>
<83>
<66>
<95>
<89>
<81>
<63>
UCAS (Output)
LCAS (Output)
<93>
<88>
<95>
RD (Output)
OE (Output)
<102>
<85>
<101>
<85>
<92>
WE (Output)
D0 to D15 (I/O)
BCYST (Output)
WAIT (Input)
<103>
<87>
<104>
<87>
Data
Data
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
101
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Data output delay time from OE ↑
IOWR ↓ delay time from address
<24>
tSWK
tHKW
15
2
<25>
<37>
<41>
<42>
ns
tDRDOD
tDAWR
tSAWR
(0.5 + i) T – 10
(0.5 + wRP) T – 10
ns
ns
Address setup time
(2 + wRP + wRH + wDA)
T – 10
ns
(to UWR, LWR IOWR ↑)
Address delay time from IOWR ↑
RD ↑ delay time from IOWR ↑
<43>
<48>
tDWRA
0.5T – 10
0
ns
ns
ns
ns
tDWRRD
wF = 0
wF = 1
T – 10
IOWR low-level width
<50>
tWWRL
(2 + wRH + wDA + w)
T – 10
Row address setup time
Row address hold time
Column address setup time
Column address hold time
<56>
<57>
<58>
<59>
tASR
tRAH
tASC
tCAH
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
ns
ns
ns
ns
(1.5 + wDA + wF + w)
T – 10
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA +
wF +w) T – 10
ns
RAS precharge time
RAS hold time
<61>
<63>
tRP
(0.5 + wRP) T – 10
ns
ns
tRSH
(1.5 + wDA + wF + w)
T – 10
Column address read time for RAS
CAS pulse width
<64>
<65>
tRAL
(2 + wCP + wDA + w
F
+ w)
ns
ns
T – 10
tCAS
(1 + wDA + wF + w)
T – 10
CAS-RAS precharge time
CAS hold time
<66>
<67>
tCRP
tCSH
(1 + wRP) T – 10
ns
ns
F
(2 + wRH + wDA + w +w)
T – 10
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
CAS precharge time
<68>
<69>
<70>
<71>
<76>
<77>
tRCS
tRRH
tRCH
tCPN
tRAD
tRCD
(2 + wRP + wRH) T – 10
0.5T – 10
ns
ns
ns
ns
ns
ns
1.5T – 10
(2 + wRP + wRH) T – 10
(0.5 + wRH) T – 10
(1 + wRH) T – 10
RAS column address delay time
RAS-CAS delay time
102
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
103
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) R external I/O transfer) (2/3)
Parameter
Symbol
<78> tOEZ
Condition
MIN.
0
MAX.
Unit
ns
Output buffer turn-off delay time (from
OE ↑)
Output buffer turn-off delay time (from
<79>
tOFF
0
ns
CAS ↑)
CAS precharge time
<81>
<82>
tCP
tPC
(0.5 + wCP) T – 10
ns
ns
High-speed page mode cycle time
(2 + wCP + wDA + w
F
+ w)
T – 10
RAS hold time for CAS precharge
RAS pulse width
<83>
<94>
<96>
<97>
tRHCP
tRASP
tOCH1
tOCH2
(2.5 + wCP + wDA + w
F
+ w)
ns
ns
ns
ns
T – 10
(2.5 + wRH + wDA + w
T – 10
F
+ w)
OE → CAS hold time
(from CAS ↑)
Off-page
On-page
(2.5 + wRP + wRH + wDA
+ wF + w) T – 10
(1.5 + wCP + wDA + w
F
+ w)
T – 10
CAS ↓ delay time from DMAAKm ↓
CAS ↓ delay time from IOWR ↓
<105>
<106>
tDDACS
tDRDCS
(1.5 + wRH) T – 10
(1 + wRH) T – 10
ns
ns
Remarks 1. T=tCYK
2. w: the number of waits due to WAIT.
3. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. m = 0 to 3
104
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (3/3)
TRPW T1 TRHW T2 TDAW TW
T3 TCPW TO1 TDAW TW TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<57>
<56>
<59>
Row address
<76>
Column address
Column address
<64>
<61>
<94>
<60>
<69>
<77>
<65>
<83>
<63>
<66>
<67>
<81>
UCAS (Output)
LCAS (Output)
<70>
<71>
<82>
<96>
<79>
RD (Output)
OE (Output)
<105>
<48>
<97>
DMAAKm (Output)
WE (Output)
<68>
IORD (Output)
IOWR (Output)
D0 to D15 (I/O)
WAIT (Input)
<106>
<42>
<43>
<78>
<37>
<41>
<50>
<24>
Data
Data
<25>
<24>
<24>
<25>
<25>
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
105
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3)
Parameter
Symbol
<24>
Condition
MIN.
15
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
IORD low-level width
tSWK
tHKW
tWRDL
tWRDH
tDARD
tDRDA
tASR
<25>
<32>
<33>
<34>
<35>
<56>
<57>
<58>
<59>
<60>
2
(2 + wRH + wDA + wF + w) T – 10
T – 10
IORD high-level width
IORD ↑ delay time from address, CSn
Address delay time from IORD ↑
Row address setup time
0.5T – 10
(0.5 + i) T – 10
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
Row address hold time
tRAH
Column address setup time
Column address hold time
Read/write cycle time
tASC
tCAH
(1.5 + wDA + wF) T – 10
tRC
(3 + wRP + wRH + wDA + wF + w)
T – 10
RAS precharge time
<61>
<63>
<64>
<65>
<66>
<67>
<71>
<76>
<77>
<81>
<82>
<83>
<85>
<88>
<89>
<92>
<94>
<101>
<102>
tRP
tRSH
tRAL
tCAS
tCRP
tCSH
tCPN
tRAD
tRCD
tCP
(0.5 + wRP) T – 10
(1.5 + wDA + wF) T – 10
(2 + wCP + wDA + wF + w) T – 10
(1 + wDA + wF) T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RAS hold time
Column address read time for RAS
CAS pulse width
CAS-RAS precharge time
CAS hold time
(1 + wRP) T – 10
(2 + wRH + wDA + wF + w) T – 10
(2 + wRP + wRH + w) T – 10
(0.5 + wRH) T – 10
CAS precharge time
RAS column address delay time
RAS-CAS delay time
(1 + wRH + w) T – 10
CAS precharge time
(0.5 + wCP + w) T – 10
(2 + wCP + wDA + wF + w) T – 10
(2.5 + wCP + wDA + w) T – 10
(1 + wDA) T – 10
High-speed page mode cycle time
RAS hold time for CAS precharge
WE hold time (from CAS ↓)
WE read time (from RAS ↑)
WE read time (from CAS ↑)
WE pulse width
tPC
tRHCP
tWCH
tRWL
tCWL
tWP
wCP = 0
wCP = 0
wCP = 0
(1.5 + wDA + w) T – 10
(1 + wDA + w) T – 10
(1 + wDA + w) T – 10
RAS pulse width
tRASP
tWCS1
tWCS2
(2.5 + wRH + wDA + wF + w) T – 10
(1 + wRH + wRP + w) T – 10
wCPT – 10
WE setup time
Off-page
On-page
wCP = 0
(to CAS ↓)
wCP ≥ 1
106
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
9. n = 0 to 7
107
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (2/3)
Parameter
Symbol
Condition
Unit
ns
MIN.
(1.5 + wRH + w) T – 10
(1 + wRH + w) T – 10
0
MAX.
CAS ↓ delay time from DMAAKm ↓
CAS ↓ delay time from IORD ↓
IORD ↑ delay time from WE ↑
<105>
tDDACS
tDRDCS
tDWERD
<106>
<107>
ns
wF= 0
wF= 1
ns
T – 10
ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. m = 0 to 3
108
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (3/3)
TRPW T1 TRHW TW
T2 TDAW T3 TCPW TW
TO1 TDAW TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<56>
<57>
<58>
<59>
Row address
<76>
<61>
Column address
Column address
<64>
<94>
<60>
<77>
<65>
<66>
<67>
<81>
<63>
UCAS (Output)
LCAS (Output)
<71>
<82>
<83>
RD (Output)
OE (Output)
<102>
<88>
<89>
<101>
<105>
<85>
WE (Output)
<92>
DMAAKm (Output)
IOWR (Output)
IORD (Output)
D0 to D15 (I/O)
WAIT (Input)
<106>
<107>
<35>
<34>
<32>
<24>
<25>
<33>
Data
Data
<24>
<24>
<25>
<25>
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
109
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(i) CBR refresh timing
Parameter
RAS precharge time
RAS pulse width
Symbol
Condition
MIN.
(1.5 + wRRW) T – 10
(1.5 + w
MAX.
Unit
ns
ns
ns
ns
ns
ns
<61>
tRP
tRAS
RCW Note) T – 10
<62>
<108>
<109>
<110>
<111>
(1.5 + w
RCW Note) T – 10
CAS hold time
tCHR
tWRFL
tRPC
tDKRF
REFRQ pulse width
RAS precharge CAS hold time
(3 + w
RRW + wRCW Note) T – 10
(0.5 + wRRW) T – 10
2
REFRQ active delay time
10
10
(from CLKOUT ↑)
REFRQ inactive delay time
<112>
<113>
tHKRF
2
ns
ns
(from CLKOUT ↑)
CAS setup time
tCSR
T – 10
Note At least one clock cycle is inserted by default for wRCW regardless of the settings of the RCW0 to RCW2 bits
of the RWC register.
Remarks 1. T = tCYK
2. wRRW: the number of waits due to the RRW0 and RRW1 bits of the RWC register.
3. wRCW: the number of waits due to the RCW0 to RCW2 bits of the RWC register.
TRRW
T1
T2
TRCWNote
TRCW
T3
TI
CLKOUT (Output)
REFRQ (Output)
RASn (Output)
<111>
<112>
<109>
<61>
<62>
<110>
<110>
<113>
<108>
UCAS (Output)
LCAS (Output)
Note This TRCW is always inserted regardless of the settings of the RCW0 to RCW2 bits of the RWC register.
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 2
2. n = 0 to 7
110
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(j) CBR self-refresh timing
Parameter
Symbol
<111> tDKRF
Condition
MIN.
2
MAX.
10
Unit
ns
REFRQ active delay time
(from CLKOUT ↑)
REFRQ inactive delay time
<112>
tHKRF
2
10
ns
(from CLKOUT ↑)
CAS hold time
<114>
<115>
tCHS
tRPS
−5
ns
ns
RAS precharge time
(1 + 2wSRW) T – 10
Remarks 1. T = tCYK
2. wSRW: the number of waits due to the SRW0 to SRW2 bits of the RWC register.
TRRW
TH
TH
TH
TRCW
TH
TI
TSRW
TSRW
CLKOUT (Output)
REFRQ (Output)
RASn (Output)
<111>
<112>
<115>
<114>
UCAS (Output)
LCAS (Output)
Output signals
other than above
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 1
Number of waits due to the SRW0 to SRW2 bits of the RWC register (TSRW): 2
2. The broken lines indicate high impedance.
3. n = 0 to 7
111
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(7) DMAC timing
Parameter
Symbol
Condition
Unit
ns
MIN.
MAX.
DMARQn setup time (to CLKOUT ↑)
DMARQn hold time (from CLKOUT ↑)
<116>
tSDRK
tHKDR1
tHKDR2
tDKDA
15
<117>
<118>
<119>
2
ns
Until DMAAKn ↓
ns
DMAAKn output delay time
2
10
10
10
10
ns
(from CLKOUT ↓)
DMAAKn output hold time
<120>
<121>
<122>
tHKDA
tDKTC
tHKTC
2
2
2
ns
ns
ns
(from CLKOUT ↓)
TCn output delay time
(from CLKOUT ↓)
TCn output hold time
(from CLKOUT ↓)
Remark n = 0 to 3
CLKOUT (Output)
<117>
<116>
<118>
DMARQn (Input)
DMAAKn (Output)
<116>
<119>
<120>
<122>
<121>
TCn (Output)
Remark n = 0 to 3
112
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
113
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (1/2)
Parameter
Symbol
Condition
MIN.
15
MAX.
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
HLDRQ setup time (to CLKOUT ↑)
HLDRQ hold time (from CLKOUT ↑)
HLDAK delay time from CLKOUT ↓
HLDRQ high-level width
<123>
tSHRK
tHKHR
<124>
<125>
<126>
<127>
<128>
<129>
<130>
<131>
2
tDKHA
2
tWHQH
tWHAL
tDKCF
T + 17
T – 8
HLDAK low-level width
Bus float delay time from CLKOUT ↓
Bus output delay time from HLDAK ↓
HLDAK ↓ delay time from HLDRQ ↓
HLDAK ↑ delay time from HLDRQ ↑
10
tDHAC
0
tDHQHA1
tDHQHA2
2.5T
0.5T
1.5T
Remark T = tCYK
114
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (2/2)
T1
T2
T3
TI
TH
TH
TH
TI
T1
CLKOUT (Output)
<123>
<124>
<123>
<123>
<124>
<123>
<126>
HLDRQ (Intput)
HLDAK (Output)
A0 to A23 (Output)
D0 to D15 (I/O)
CSn/RASn (Output)
BCYST (Output)
RD (Output)
<125>
<128>
<125>
<131>
<130>
<127>
<129>
Address
Undefined
Data
WE (Output)
UCAS (Output)
LCAS (Output)
WAIT (Input)
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 7
115
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(9) Interrupt timing
Parameter
NMI high-level width
NMI low-level width
Symbol
<132>
Condition
MIN.
500
MAX.
Unit
ns
tWNIH
tWNIL
tWITH
tWITL
<133>
<134>
<135>
500
ns
INTPn high-level width
INTPn low-level width
4T + 10
4T + 10
ns
ns
Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153
2. T = tCYK
<132>
<134>
<133>
NMI (Input)
<135>
INTPn (Input)
Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153
(10) RPU timing
Parameter
TI1n high-level width
Symbol
<136>
Condition
MIN.
MAX.
Unit
ns
tWTIH
tWTIL
tWTCH
tWTCL
3T + 18
3T + 18
3T + 18
3T + 18
TI1n low-level width
<137>
<138>
<139>
ns
TCLR1n high-level width
TCLR1n low-level width
ns
ns
Remarks 1. n = 0 to 5
2. T = tCYK
<136>
<137>
TI1n (Input)
<138>
<139>
TCLR1n (Input)
Remark n = 0 to 5
116
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(11) UART0, UART1 timing (clock-synchronized or master mode only)
Parameter
Symbol
<140>
Condition
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
tCYSK0
tWSK0H
tWSK0L
tSRXSK
tHSKRX
tDSKTX
tHSKTX
250
SCKn high-level width
<141>
<142>
<143>
<144>
<145>
<146>
Output
0.5tCYSK0 – 20
SCKn low-level width
Output
0.5tCYSK0 – 20
RXDn setup time (to SCKn ↑)
RXDn hold time (from SCKn ↑)
TXDn output delay time (from SCKn ↓)
TXDn output hold time (from SCKn ↑)
30
0
20
0.5tCYSK0 – 5
Remark n = 0, 1
<140>
<142>
<141>
SCKn (I/O)
<143>
<144>
RXDn (Input)
Input data
<145>
<146>
TXDn (Output)
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0, 1
117
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(12) CSI0 to CSI3 timing
(a) Master mode
Parameter
SCKn cycle
Symbol
<147>
Condition
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tCYSK1
tWSK1H
tWSK1L
tSSISK
100
SCKn high-level width
<148>
<149>
<150>
<151>
<152>
<153>
Output
0.5tCYSK1 – 20
SCKn low-level width
Output
0.5tCYSK1 – 20
SIn setup time (to SCKn ↑)
SIn hold time (from SCKn ↑)
SOn output delay time (from SCKn ↓)
SOn output hold time (from SCKn ↑)
30
0
tHSKSI
tDSKSO
tHSKSO
20
0.5tCYSK1 – 5
Remark n = 0 to 3
(b) Slave mode
Parameter
SCKn cycle
Symbol
Condition
Input
MIN.
100
30
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
<147>
<148>
<149>
<150>
<151>
<152>
<153>
tCYSK1
tWSK1H
tWSK1L
tSSISK
SCKn high-level width
Input
SCKn low-level width
Input
30
SIn setup time (to SCKn ↑)
SIn hold time (from SCKn ↑)
SOn output delay time (from SCKn ↓)
SOn output hold time (from SCKn ↑)
10
tHSKSI
tDSKSO
tHSKSO
10
30
tWSK1H
Remark n = 0 to 3
<147>
<149>
<148>
SCKn (I/O)
<150>
<151>
Sln (Input)
Input data
<152>
<153>
SOn (Output)
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 3
118
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
A/D Converter Characteristics (TA = –40 to +70°C ... µPD703100-40, TA = –40 to +85°C ... µPD703100-33,
µPD703101-33, µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10%,
VSS = 0 V, HVDD – 0.5 V < AVDD < HVDD, output pin load capacitance: CL = 50
pF)
Parameter
Symbol
–
Condition
MIN.
10
TYP.
MAX.
Unit
bit
Resolution
Total error
–
± 4
LSB
LSB
µs
Quantization error
Conversion time
Sampling time
–
± 1/2
tCONV
tSAMP
–
5
833
ns
Zero scale error
Full scale error
± 2
± 2
LSB
LSB
LSB
V
–
Nonlinearity error
Analog input voltage
Analog input resistance
AVREF input voltage
AVREF input current
AVDD current
–
± 1
VIAN
RAN
AVREF
AIREF
AIDD
−0.3
AVREF + 0.3
2
MΩ
V
AVREF = AVDD
4.5
5.5
1.6
6
mA
mA
119
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
17. PACKAGE DRAWING
144 PIN PLASTIC LQFP (FINE PITCH) (20 20)
A
B
108
109
73
72
detail of lead end
C
D
S
R
Q
144
1
37
36
F
M
G
J
H
I
K
P
M
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
A
22.0±0.2
0.866±0.008
+0.009
0.787
B
20.0±0.2
–0.008
+0.009
0.787
C
20.0±0.2
–0.008
D
F
22.0±0.2
1.25
0.866±0.008
0.049
G
1.25
0.049
+0.05
0.22
H
0.009±0.002
–0.04
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.0±0.2
0.5±0.2
–0.008
+0.008
0.020
–0.009
+0.055
M
0.145
0.10
0.006±0.002
–0.045
N
P
Q
0.004
1.4±0.1
0.055±0.004
0.005±0.003
0.125±0.075
+7°
3°
+7°
3°
R
S
–3°
–3°
1.7 MAX.
0.067 MAX.
S144GJ-50-8EU-2
120
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
18. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 18-1. Surface Mounting Type Soldering Conditions
µPD703100GJ-40-8EU
µPD703100GJ-33-8EU
: 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
: 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
µPD703101GJ-33-xxx-8EU : 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
µPD703102GJ-33-xxx-8EU : 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
Recommended
Condition
Soldering Method
Infrared reflow
Partial heating
Soldering Conditions
Symbol
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher), Count:
two times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours)
IR35-103-2
Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
121
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
122
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Related Documents µPD70F3102-33 Data Sheet (U13844E)
µPD703100-A33, µPD703100-A40, µPD703101-A33, µPD703102-A33 Data Sheet (To be
prepared)
µPD70F3102-A33 Data Sheet (U13845E)
V850 Family Application Note Flash Memory Self-Programming Library (U13261E)
Reference Materials: Electrical Characteristics for Microcomputer (IEI-601Note
)
Note This document number is that of Japanese version.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V850E/MS1 Family and V850 are trademarks of NEC Corporation.
123
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
124
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
125
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33,
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
Lisence not needed
: µPD703100-33, 703100-40
The customer must judge the need for lisence : µPD703101-33, 703102-33
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
相关型号：
UPD703103AGJ-UEN-A
Microcontroller, 32-Bit, 50MHz, MOS, PQFP144, 20 X 20 MM, FINE PITCH, PLASTIC, LQFP-144
NEC
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