UPD70F3102-33_技术文档

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUITS

µ

PD70F3102-33

V850E/MS1^TM

32-/16-BIT SINGLE-CHIP MICROCONTROLLER

The µPD70F3102-33 is a product that substitutes the internal mask ROM of the µPD703102-33 with flash

memory. This enables users to perform on-board program writing and erasure, enabling effective evaluation during

system development, small-lot production of multiple devices, and rapid production start, and quick development and

time-to-market.

A version using a 3.3 V power supply for external pins, the µPD70F3102-A33, is also available.

For additional information, refer to the following user’s manuals. Be sure to read them before starting

design.

V850E/MS1 User’s Manual Hardware:

U12688E

V850E/MS1 User’s Manual Architecture: U12197E

FEATURES

•

µPD703102-33 compatible

Can be replaced by the µPD703102-33 with internal mask ROM for mass production

•

Internal flash memory: 128 KB

ORDERING INFORMATION

Part Number

Package

µPD70F3102GJ-33-8EU

µPD70F3102GJ-33-UEN

144-pin plastic LQFP (fine pitch) (20 × 20)

The information contained in this document is being issued in advance of the production cycle for the

device. The parameters for the device may change before final production or NEC Corporation, at its own

discretion, may withdraw the device prior to its production.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. U13844EJ2V0DS00 (2nd edition)

Date Published July 2000 N CP(K)

Printed in Japan

The mark shows major revised points.

1999

©

µPD70F3102-33

PIN CONFIGURATION (Top View)

144-pin plastic LQFP (fine pitch) (20 × 20)

•

µPD70F3102GJ-33-8EU

µPD70F3102GJ-33-UEN

INTP103/DMARQ3/P07

INTP102/DMARQ2/P06

INTP101/DMARQ1/P05

INTP100/DMARQ0/P04

TI10/P03

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

A16/P60

A17/P61

A18/P62

A19/P63

A20/P64

A21/P65

A22/P66

A23/P67

TCLR10/P02

TO101/P01

TO100/P00

V

SS

9

HV^DD

INTP113/DMAAK3/P17

INTP112/DMAAK2/P16

INTP111/DMAAK1/P15

INTP110/DMAAK0/P14

TI11/P13

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

CS0/RAS0/P80

CS1/RAS1/P81

CS2/RAS2/P82

CS3/RAS3/P83

CS4/RAS4/IOWR/P84

CS5/RAS5/IORD/P85

CS6/RAS6/P86

CS7/RAS7/P87

LCAS/LWR/P90

UCAS/UWR/P91

RD/P92

WE/P93

BCYST/P94

OE/P95

HLDAK/P96

HLDRQ/P97

VSS

TCLR11/P12

TO111/P11

TO110/P10

INTP123/TC3/P107

INTP122/TC2/P106

INTP121/TC1/P105

INTP120/TC0/P104

TI12/P103

TCLR12/P102

TO121/P101

TO120/P100

ANI7/P77

ANI6/P76

ANI5/P75

ANI4/P74

ANI3/P73

ANI2/P72

ANI1/P71

ANI0/P70

AV^DD

AVSS

AVREF

REFRQ/PX5

WAIT/PX6

CLKOUT/PX7

TO150/P120

TO151/P121

TCLR15/P122

TI15/P123

INTP150/P124

INTP151/P125

INTP152/P126

74

73

2

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

PIN IDENTIFICATION

A0 to A23:

ADTRG:

ANI0 to ANI7:

AV^DD:

Address Bus

P50 to P57:

P60 to P67:

P70 to P77:

P80 to P87:

P90 to P97:

P100 to P107:

P110 to P117:

P120 to P127:

PA0 to PA7:

PB0 to PB7:

PX5 to PX7:

RAS0 to RAS7:

RD:

Port 5

Port 6

Port 7

Port 8

Port 9

Port 10

Port 11

Port 12

Port A

Port B

Port X

AD Trigger Input

Analog Input

Analog Power Supply

Analog Reference Voltage

Analog Ground

AV^REF:

AV^SS:

BCYST:

CKSEL:

Bus Cycle Start Timing

Clock Generator Operating Mode

Select

CLKOUT:

CS0 to CS7:

CV^DD:

Clock Output

Chip Select

Clock Generator Power Supply

Clock Generator

Data Bus

Row Address Strobe

Read

CV^SS:

D0 to D15:

REFRQ:

Refresh Request

Reset

DMAAK0 to DMAAK3: DMA Acknowledge

DMARQ0 to DMARQ3: DMA Request

RESET:

RXD0, RXD1:

SCK0 to SCK3:

SI0 to SI3:

Receive Data

Serial Clock

HLDAK:

Hold Acknowledge

Hold Request

HLDRQ:

Serial Input

HV^DD:

Power Supply for External Pins SO0 to SO3:

TC0 to TC3:

Serial Output

Terminal Count Signal

INTP100 to INTP103,

INTP110 to INTP113,

INTP120 to INTP123,

INTP130 to INTP133,

INTP140 to INTP143,

TCLR10 to TCLR15: Timer Clear

TI10 to TI15:

Timer Input

TO100, TO101,

TO110, TO111,

INTP150 to INTP153: Interrupt Request from Peripherals TO120, TO121,

IORD:

I/O Read Strobe

I/O Write Strobe

Lower Column Address Strobe

Lower Write Strobe

Mode

TO130, TO131,

TO140, TO141,

TO150, TO151:

TXD0, TXD1:

UCAS:

IOWR:

LCAS:

Timer Output

LWR:

Transmit Data

MODE0 to MODE3:

NMI:

Upper Column Address Strobe

Upper Write Strobe

Power Supply for Internal Unit

Programming Power Supply

Ground

Non-Maskable Interrupt Request UWR:

OE:

Output Enable

Port 0

V^DD:

P00 to P07:

P10 to P17:

P20 to P27:

P30 to P37:

P40 to P47:

V^PP:

Port 1

V^SS:

Port 2

WAIT:

WE:

Wait

Port 3

Write Enable

Port 4

X1, X2:

Crystal

3

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

INTERNAL BLOCK DIAGRAM

NMI

HLDRQ

CPU

BCU

Flash memory

128 KB

HLDAK

INTP100 to INTP103,

INTC

INTP110 to INTP113,

CS0 to CS7/RAS0 to RAS7

INTP120 to INTP123,

INTP130 to INTP133,

INTP140 to INTP143,

INTP150 to INTP153

IOWR

Instruction queue

PC

IORD

Multiplier

(32 × 32 → 64)

DRAMC

REFRQ

BCYST

WE

TO100, TO101,

TO110, TO111,

TO120, TO121,

RD

Barrel

shifter

OE

Page ROM

controller

TO130, TO131,

TO140, TO141,

TO150, TO151

RPU

RAM

4 KB

System registers

UWR/UCAS

LWR/LCAS

WAIT

General-purpose

registers

(32 bits × 32)

TCLR10 to TCLR15

TI10 to TI15

ALU

A0 to A23

D0 to D15

DMARQ0 to DMARQ3

DMAAK0 to DMAAK3

TC0 to TC3

DMAC

SIO

SO0/TXD0

SI0/RXD0

SCK0

UART0/CSI0

BRG0

UART1/CSI1

BRG1

SO1/TXD1

SI1/RXD1

SCK1

CKSEL

CLKOUT

X1

Port

CG

X2

CVDD

CVSS

SO2

SI2

CSI2

SCK2

MODE0 to MODE3

RESET

BRG2

System

controller

SO3

SI3

VPP

CSI3

SCK3

V

DD

SS

ANI0 to ANI7

V

AVREF

AVSS

ADC

AVDD

ADTRG

4

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

CONTENTS

1. DIFFERENCES AMONG PRODUCTS ..............................................................................................

6

1.1 Differences Between µPD70F3102-33 and µPD703102-33 ......................................................

1.2 Differences Between µPD70F3102-33 and µPD70F3102A-33..................................................

2. PIN FUNCTIONS.................................................................................................................................

2.1 Port Pins ......................................................................................................................................

7

2.2 Non-Port Pins .............................................................................................................................. 10

2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins ................................ 14

3. FLASH MEMORY PROGRAMMING ................................................................................................. 17

3.1 Selection of Communication System........................................................................................ 17

3.2 Flash Memory Programming Functions ................................................................................... 18

3.3 Connecting the Dedicated Flash Programmer......................................................................... 18

4. ELECTRICAL SPECIFICATIONS....................................................................................................... 19

4.1 Normal Operation Mode ............................................................................................................. 19

4.2 Flash Memory Programming Mode........................................................................................... 74

5. PACKAGE DRAWINGS...................................................................................................................... 76

6. RECOMMENDED SOLDERING CONDITIONS................................................................................. 78

5

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

1. DIFFERENCES AMONG PRODUCTS

1.1 Differences Between µPD70F3102-33 and µPD703102-33

Product

µPD70F3102-33

µPD703102-33

Item

Internal ROM

Flash memory

Provided (V^PP)

Mask ROM

None

Flash memory programming pin

Flash memory programming mode

Provided (MODE0 = L, MODE1 = H,

MODE2 = L, MODE3/V^PP= 7.8 V)

None

Electrical specifications

Others

Consumption current etc. differ (see individual data sheets).

Circuit scale and master layout differ, thus noise immunity, noise radiation, etc. differ.

Cautions 1. There are differences in noise immunity and noise radiation between the flash memory

version and mask ROM version. When pre-producing an application set with the flash

memory version and then mass-producing it with the mask ROM version, be sure to conduct

sufficient evaluation for commercial samples (not engineering samples) of the mask ROM

version.

2. When switching from the flash memory version to the mask ROM version, write the same

code to the free area of the internal ROM.

1.2 Differences Between µPD70F3102-33 and µPD70F3102A-33

Product

µPD70F3102-33

µPD70F3102A-33

Item

HV^DD

4.5 to 5.5 V

3.0 to 3.6 V

Electrical specifications

Package

See individual data sheets.

• 144-pin plastic LQFP (fine pitch) (20 × 20)

• 157-pin plastic FBGA (14 × 14)

• 144-pin plastic LQFP (fine pitch) (20 × 20)

6

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

2. PIN FUNCTIONS

2.1 Port Pins

(1/3)

Alternate Function

TO100

Pin Name

P00

I/O

Function

Port 0

8-bit I/O port

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P35

P36

P37

P40 to P47

TO101

Input/output can be specified in 1-bit units.

TCLR10

TI10

INTP100/DMARQ0

INTP101/DMARQ1

INTP102/DMARQ2

INTP103/DMARQ3

TO110

I/O

Port 1

8-bit I/O port

TO111

Input/output can be specified in 1-bit units.

TCLR11

TI11

INTP110/DMAAK0

INTP111/DMAAK1

INTP112/DMAAK2

INTP113/DMAAK3

NMI

Input

I/O

Port 2

P20 is an input-only port.

–

When a valid edge is input, it operates as an NMI input. The status of

the NMI input is shown by bit 0 of register P2.

P21 to P27 is a 7-bit I/O port.

TXD0/SO0

RXD0/SI0

SCK0

Input/output can be specified in 1-bit units.

TXD1/SO1

RXD1/SI1

SCK1

I/O

Port 3

TO130

8-bit I/O port

TO131

Input/output can be specified in 1-bit units.

TCLR13

TI13

INTP130

INTP131/SO2

INTP132/SI2

INTP133/SCK2

D0 to D7

I/O

Port 4

8-bit I/O port

Input/output can be specified in 1-bit units.

7

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(2/3)

Alternate Function

D8 to D15

Pin Name

I/O

Function

P50 to P57

Port 5

8-bit I/O port

Input/output can be specified in 1-bit units.

P60 to P67

P70 to P77

I/O

Port 6

A16 to A23

8-bit I/O port

Input/output can be specified in 1-bit units.

Input

I/O

Port 7

ANI0 to ANI7

8-bit input-only port

P80

Port 8

CS0/RAS0

CS1/RAS1

CS2/RAS2

CS3/RAS3

CS4/RAS4/IOWR

CS5/RAS5/IORD

CS6/RAS6

CS7/RAS7

LCAS/LWR

UCAS/UWR

RD

8-bit I/O port

P81

Input/output can be specified in 1-bit units.

P82

P83

P84

P85

P86

P87

P90

I/O

Port 9

8-bit I/O port

P91

Input/output can be specified in 1-bit units

P92

P93

WE

P94

BCYST

P95

OE

P96

HLDAK

P97

HLDRQ

P100

P101

P102

P103

P104

P105

P106

P107

I/O

Port 10

TO120

8-bit I/O port

TO121

Input/output can be specified in 1-bit units.

TCLR12

TI12

INTP120/TC0

INTP121/TC1

INTP122/TC2

INTP123/TC3

8

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(3/3)

Pin Name

P110

I/O

Function

Alternate Function

TO140

TO141

TCLR14

TI14

Port 11

8-bit I/O port

P111

P112

P113

P114

P115

P116

P117

P120

P121

P122

P123

P124

P125

P126

P127

PA0

Input/output can be specified in 1-bit units.

INTP140

INTP141/SO3

INTP142/SI3

INTP143/SCK3

TO150

TO151

TCLR15

TI15

I/O

Port 12

8-bit I/O port

Input/output can be specified in 1-bit units.

INTP150

INTP151

INTP152

INTP153/ADTRG

A0

Port A

8-bit I/O port

PA1

A1

Input/output can be specified in 1-bit units.

PA2

A2

PA3

A3

PA4

A4

PA5

A5

PA6

A6

PA7

A7

PB0

Port B

A8

8-bit I/O port

PB1

A9

Input/output can be specified in 1-bit units.

PB2

A10

PB3

A11

PB4

A12

PB5

A13

PB6

A14

PB7

A15

PX5

Port X

REFRQ

WAIT

3-bit I/O port

PX6

Input/output can be specified in 1-bit units.

PX7

CLKOUT

9

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

2.2 Non-Port Pins

(1/4)

Alternate Function

P00

Pin Name

TO100

TO101

TO110

TO111

TO120

TO121

TO130

TO131

TO140

TO141

TO150

TO151

TCLR10

TCLR11

TCLR12

TCLR13

TCLR14

TCLR15

TI10

I/O

Function

Pulse signal output of timers 10 to 15

Output

P01

P10

P11

P100

P101

P30

P31

P110

P111

P120

P121

Input

External clear signal input of timers 10 to 15

P02

P12

P102

P32

P112

P122

Input

External count clock input of timers 10 to 15

P03

TI11

P13

TI12

P103

TI13

P33

TI14

P113

TI15

P123

INTP100

INTP101

INTP102

INTP103

INTP110

INTP111

INTP112

INTP113

INTP120

INTP121

INTP122

INTP123

Input

External maskable interrupt request input, or timer 10 external capture

trigger input

P04/DMARQ0

P05/DMARQ1

P06/DMARQ2

P07/DMARQ3

P14/DMAAK0

P15/DMAAK1

P16/DMAAK2

P17/DMAAK3

P104/TC0

P105/TC1

P106/TC2

P107/TC3

External maskable interrupt request input, or timer 11 external capture

trigger input

External maskable interrupt request input, or timer 12 external capture

trigger input

10

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(2/4)

Pin Name

INTP130

INTP131

INTP132

INTP133

INTP140

INTP141

INTP142

INTP143

INTP150

INTP151

INTP152

INTP153

SO0

I/O

Function

Alternate Function

Input

External maskable interrupt request input, or timer 13 external capture

trigger input

P34

P35/SO2

P36/SI2

P37/SCK2

P114

Input

Output

Input

I/O

External maskable interrupt request input, or timer 14 external capture

trigger input

P115/SO3

P116/SI3

P117/SCK3

P124

External maskable interrupt request input, or timer 15 external capture

trigger input

P125

P126

P127/ADTRG

P22/TXD0

P25/TXD1

P35/INTP131

P115/INTP141

P23/RXD0

P26/RXD1

P36/INTP132

P116/INTP142

P24

CSI0 to CSI3 serial transmission data output (3-wire)

CSI0 to CSI3 serial reception data input (3-wire)

CSI0 to CSI3 serial clock input/output (3-wire)

SO1

SO2

SO3

SI0

SI1

SI2

SI3

SCK0

SCK1

P27

SCK2

P37/INTP133

P117/INTP143

P22/SO0

P25/SO1

P23/SI0

SCK3

TXD0

Output

Input

I/O

UART0 and UART1 serial transmission data output

UART0 and UART1 serial reception data input

16-bit data bus for external memory

TXD1

RXD0

RXD1

P26/SI1

D0 to D7

D8 to D15

A0 to A7

A8 to A15

A16 to A23

LWR

P40 to P47

P50 to P57

PA0 to PA7

PB0 to PB7

P60 to P67

P90/LCAS

P91/UCAS

P92

Output

24-bit address bus for external memory

Output

External data bus lower byte write enable signal output

External data bus upper byte write enable signal output

External data bus read strobe signal output

Write enable signal output for DRAM

UWR

RD

WE

P93

OE

Output enable signal output for DRAM

P95

11

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(3/4)

Alternate Function

P90/LWR

Pin Name

LCAS

I/O

Function

Output

Column address strobe signal output for lower data of DRAM

Column address strobe signal output for higher data of DRAM

Row address strobe signal output for DRAM

UCAS

P91/UWR

RAS0 to RAS3

RAS4

P80/CS0 to P83/CS3

P84/CS4/IOWR

P85/CS5/IORD

P86/CS6

RAS5

RAS6

RAS7

P87/CS7

BCYST

CS0 to CS3

Output

Strobe signal output indicating start of bus cycle

Chip select signal output

P94

P80/RAS0 to

P83/RAS3

CS4

P84/RAS4/IOWR

P85/RAS5/IORD

P86/RAS6

CS5

CS6

CS7

P87/RAS7

WAIT

REFRQ

IOWR

IORD

Input

Output

Input

Control signal input that inserts a wait in the bus cycle

Refresh request signal output for DRAM

DMA write strobe signal output

PX6

PX5

P84/RAS4/CS4

P85/RAS5/CS5

DMA read strobe signal output

DMARQ0 to

DMARQ3

DMA request signal input

P04/INTP100 to

P07/INTP103

DMAAK0 to

DMAAK3

Output

DMA acknowledge signal output

P14/INTP110 to

P17/INTP113

TC0 to TC3

DMA termination (terminal count) signal output

P104/INTP120 to

P107/INTP123

HLDAK

HLDRQ

ANI0 to ANI7

NMI

Output

Input

Bus hold acknowledge output

Bus hold request input

P96

P97

Input

Analog input to A/D converter

Non-maskable interrupt request input

System clock output

P70 to P77

Input

P20

PX7

–

CLKOUT

CKSEL

Output

Input

Input that specifies the clock generator's operation mode

Operation mode specification

MODE0 to

MODE2

–

MODE3

RESET

X1

V^PP

Input

–

System reset input

–

Connecting system clock resonator. In the case of an external clock, it is

input to X1.

–

X2

–

ADTRG

AV^REF

AV^DD

Input

–

A/D converter external trigger input

P127/INTP153

Reference voltage applied to A/D converter

Positive power supply for A/D converter

–

12

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(4/4)

Pin Name

AV^SS

I/O

–

Function

Ground potential for A/D converter

Alternate Function

–

CV^DD

CV^SS

V^DD

–

Positive power supply for the dedicated clock generator

Ground potential for dedicated clock generator

Positive power supply (internal unit power supply)

Positive power supply (external pin power supply)

Ground potential

–

HV^DD

V^SS

–

V^PP

–

High-voltage application pin during program write/verify

MODE3

13

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins

Table 2-1 shows the I/O circuit type of each pin and the recommended connection of unused pins, and Figure 2-1

shows the schematic circuit diagram for each I/O circuit type.

In the case of connection to V^DDor V^SSvia a resistor, connection of a resistor of 1 to 10 kΩ is recommended.

Table 2-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (1/2)

I/O Circuit

Recommended Connection of Unused Pins

Type

P00/TO100, P01/TO101

P02/TCLR10, P03/TI10

5

Input: Independently connect to HV^DDor V^SSvia a resistor.

Output: Leave open.

5-K

P04/INTP100/DMARQ0 to

P07/INTP103/DMARQ3

P10/TO110, P11/TO111

P12/TCLR11, P13/TI11

5

5-K

P14/INTP110/DMAAK0 to

P17/INTP113/DMAAK3

P20/NMI

2

5

Connect directly to V^SS.

P21

Input: Independently connect to HV^DDor V^SSvia a resistor.

Output: Leave open.

P22/TXD0/SO0

P23/RXD0/SI0

5-K

P24/SCK0

P25/TXD1/SO1

P26/RXD1/SI1

5

5-K

P27/SCK1

P30/TO130, P31/TO131

P32/TCLR13, P33/TI13

P34/INTP130

5

5 - K

P35/INTP131/SO2

P36/INTP132/SI2

P37/INTP133/SCK2

P40/D0 to P47/D7

P50/D8 to P57/D15

P60/A16 to P67/A23

P70/ANI0 to P77/ANI7

5

9

Connect directly to V^SS.

14

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

Table 2-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (2/2)

I/O Circuit

Type

Recommended Connection of Unused Pins

P80/CS0/RAS0 to P83/CS3/RAS3

5

Input: Independently connect to HV^DDor V^SSvia a resistor.

Output: Leave open.

P84/CS4/RAS4/IOWR,

P85/CS5/RAS5/IORD

P86/CS6/RAS6, P87/CS7/RAS7

P90/LCAS/LWR

P91/UCAS/UWR

P92/RD

P93/WE

P94/BCYST

P95/OE

P96/HLDAK

P97/HLDRQ

P100/TO120, P101/TO121

P102/TCLR12, P103/TI12

5

Input: Independently connect to HV^DDor V^SSvia a resistor.

Output: Leave open.

5-K

P104/INTP120/TC0 to

P107/INTP123/TC3

P110/TO140, P111/TO141

P112/TCLR14, P113/TI14

P114/INTP140

5

5-K

P115/INTP141/SO3

P116/INTP142/SI3

P117/INTP143/SCK3

P120/TO150, P121/TO151

P122/TCLR15, P123/TI15

P124/INTP150 to P126/INTP152

P127/INTP153/ADTRG

PA0/A0 to PA7/A7

PB0/A8 to PB7/A15

PX5/REFRQ

5

5-K

5

PX6/WAIT

PX7/CLKOUT

CKSEL

1

2

Connect directly to HV^DD.

–

RESET

MODE0 to MODE2

MODE3/V^PP

Connect to V^SSvia a resistor (R^VPP).

Connect directly to V^SS.

AV^REF, AV^SS

–

AV^DD

Connect directly to HV^DD.

15

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

Figure 2-1. Pin Input/Output Circuits

Type 1

Type 5-K

V

DD

V

DD

Data

P-ch

IN/OUT

P-ch

IN

Output

disable

N-ch

Input

enable

Type 2

Type 9

P-ch

Comparator

IN

+

–

N-ch

IN

V

REF (threshold voltage)

Input enable

Schmitt-triggered input with hysteresis characteristics

Type 5

V

DD

Data

P-ch

IN/OUT

Output

disable

N-ch

Input

enable

Caution Replace V^DDin the circuit diagrams with HV^DD.

16

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

3. FLASH MEMORY PROGRAMMING

The following two flash memory programming methods are available.

(1) On-board programming

The program is written to the flash memory using a dedicated flash programmer after the µPD70F3102-33 is

mounted on the target board. Install the connectors, etc., required for communication with the dedicated flash

programmer, on the target board.

(2) Off-board programming

The program is written to the flash memory using a dedicated adapter before the µPD70F3102-33 is mounted on

the target board.

3.1 Selection of Communication System

Writing to the flash memory is done via serial communication using the dedicated flash programmer. Select one

of the communication modes listed in Table 3-1. Base your selection of the communication mode on the selection

format shown in Table 3-1. Refer to the number of V^PPpulses shown in Table 3-1 when selecting the communication

mode.

Table 3-1. Communication Modes

Communication Mode

CSI0

Pins Used

Number of V^PPPulses

SO0 (serial data output)

SI0 (serial data input)

SCK0 (serial clock input)

0

UART0

TXD0 (serial data output)

RXD0 (serial data input)

8

Figure 3-1. Communication Mode Selection Format

7.8 V

V

PP

VDD

V

SS

V

DD

RESET

V

SS

17

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

3.2 Flash Memory Programming Functions

Flash memory programming is performed by sending and receiving commands and data according to the selected

communication mode. Table 3-2 shows the main flash memory programming functions.

Table 3-2. Main Flash Memory Programming Functions

Function

Batch erasure

Description

Erases the contents of the entire memory.

Batch blank check

Data write

Checks whether the entire memory has been erased.

Writes data to flash memory based on the write start address and the number of bytes to be written.

Compares the contents of the entire memory with the input data.

Batch verify

3.3 Connecting the Dedicated Flash Programmer

The connection of the dedicated flash programmer to the µPD70F3102-33 differs depending on the

communication mode. Figures 3-2 and 3-3 show the various connection types.

Figure 3-2. Connection of Dedicated Flash Programmer for CSI0 Mode

Dedicated flash programmer

CLK

µ

PD70F3102-33

CLK

V

PP

V

PP

DD

VDD

V

RESET

SCK

SO

RESET

SCK0

SI0

SI

SO0

VSS

Figure 3-3. Connection of Dedicated Flash Programmer for UART0 Mode

Dedicated flash programmer

CLK

µ

PD70F3102-33

CLK

V

PP

V

PP

DD

V

DD

RESET

TxD

RESET

RXD0

TXD0

RxD

V

SS

V

SS

18

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

4. ELECTRICAL SPECIFICATIONS

4.1 Normal Operation Mode

Absolute Maximum Ratings (T^A= 25°C)

Parameter

Supply voltage

Symbol

V^DD

Conditions

Ratings

Unit

V

V^DDpin

–0.5 to +4.6

–0.5 to +7.0

HV^DD

CV^DD

CV^SS

AV^DD

AV^SS

V^I

HV^DDpin, HV^DD≥ V^DD

CV^DDpin

V

–0.5 to +4.6

V

CV^SSpin

–0.5 to +0.5

V

AV^DDpin

–0.5 to HV^DD+ 0.5

–0.5 to +0.5

V

AV^SSpin

V

Input voltage

Except X1 pin, MODE3/V^PPpin

MODE3/V^PPpin

–0.5 to HV^DD+ 0.5

–0.5 to V^DD+ 0.5

–0.5 to +11.0

V

MODE3/V^PPpin in flash memory

programming mode

V

Clock input voltage

Output current, low

V^K

I^OL

X1, V^DD= 3.0 to 3.6 V

1 pin

–0.5 to V^DD+ 1.0

4.0

V

mA

V

Total of all pins

1 pin

100

Output current, high

I^OH

–4.0

Total of all pins

HV^DD= 5.0 V ±10%

–100

Output voltage

V^O

–0.5 to HV^DD+ 0.5

–0.5 to AV^DD+ 0.5

–0.5 to HV^DD+ 0.5

–0.5 to AV^DD+ 0.5

–40 to +85

Analog input voltage

V^IAN

P70/ANI0 to

AV^DD> HV^DD

V

P77/ANI7 pins

HV^DD≥ AV^DD

V

A/D converter reference input

voltage

AV^REF

AV^DD> HV^DD

V

HV^DD≥ AV^DD

V

Operating ambient temperature

Storage temperature

T^A

°C

T^stg

–65 to +125

Cautions 1. Do not directly connect output pins (or I/O pins) of IC products, and do not connect them

directly to V^DD, V^CC, or GND. However, open-drain pins and open-collector pins can be

directly connected to each other. Moreover, external circuits that implement a timing that

avoids conflict with the output of pins that go into high-impedance can be directly

connected.

2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily

for any parameter. That is, the absolute maximum ratings are rated values at which the

product is on the verge of suffering physical damage, and therefore the product must be

used under conditions that ensure that the absolute maximum ratings are not exceeded.

The ratings and conditions indicated for DC characteristics and AC characteristics

represent the quality assurance range during normal operation.

19

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

Capacitance (T^A= 25°C, V^DD= HV^DD= CV^DD= V^SS= 0 V)

Parameter

Input capacitance

Symbol

C^I

Conditions

MIN.

TYP.

MAX.

15

Unit

pF

f^C= 1 MHz

Unmeasured pins returned to 0 V

I/O capacitance

C^IO

15

pF

Output capacitance

C^O

15

pF

Operating Conditions

Operation

Mode

Internal Operation Clock Frequency

Operating Ambient Temperature

Supply Voltage (V^DD, HV^DD)

(φ)

(T^A)

Direct mode

10 to 33 MHz

–40 to +85°C

V^DD= 3.0 to 3.6 V,

HV^DD= 5.0 V ±10%

PLL mode

20 to 33 MHz^Note

–40 to +85°C

V^DD= 3.0 to 3.6 V,

HV^DD= 5.0 V ±10%

Note Set the input clock frequency used in PLL mode to 4.0 to 6.6 MHz.

20

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

Recommended Oscillator

(a) Connection of ceramic resonator (T^A= –40 to +85°C)

(i) Murata Mfg. Co., Ltd. (T^A= –40 to +85°C)

X1

X2

Rd

C1

C2

Oscillation

Stabilization Time

(MAX.)

Type

Product Name

Oscillation

Frequency

f^XX(MHz)

Recommended Circuit

Constant

Oscillation Voltage

Range

T^OST(ms)

C1 (pF)

100

C2 (pF)

100

R^d(kΩ) MIN. (V) MAX. (V)

Surface

mount

CSAC4.00MGC040

CSTCC4.00MG0H6

CSAC5.00MGC040

CSTCC5.00MG0H6

CSAC6.60MT

4.0

5.0

6.6

8.0

4.0

5.0

6.6

8.0

0

3.0

3.6

0.5

0.3

0.4

0.2

0.1

0.2

0.3

0.5

0.1

On-chip On-chip

100 100

On-chip On-chip

30 30

On-chip On-chip

30 30

On-chip On-chip

100 100

On-chip On-chip

100 100

On-chip On-chip

30 30

On-chip On-chip

30 30

On-chip On-chip

CSTCC6.60MG0H6

CSAC8.00MT

CSTCC8.00MG0H6

CSA4.00MG040

CST4.00MGW040

CSA5.00MG040

CST5.00MGW040

CSA6.60MTZ

Lead

CST6.60MTW

CSA8.00MTZ

CST8.00MTW

Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.

2. Do not wire any other signal lines in the area indicated by the broken lines.

3. Thoroughly evaluate the matching between the µPD70F3102-33 and the resonator.

21

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(ii) TDK Corporation (T^A= –40 to +85°C)

X1

X2

Rd

C1

C2

Oscillation

Stabilization Time

(MAX.)

Manufacturer

TDK

Product Name

Oscillation

Frequency

f^XX(MHz)

Recommended Circuit

Constant

Oscillation Voltage

Range

T^OST(ms)

C1 (pF)

C2 (pF)

R^d(kΩ) MIN. (V) MAX. (V)

CCR4.0MC3

CCR5.0MC3

CCR8.0MC5

4.0

5.0

8.0

On-chip On-chip

0

3.0

3.6

0.17

0.15

0.11

Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.

2. Do not wire any other signal lines in the area indicated by the broken lines.

3. Thoroughly evaluate the matching between the µPD70F3102-33 and the resonator.

(iii) Kyocera Corporation (T^A= –20 to +80°C)

X1

X2

Rd

C1

C2

Oscillation

Stabilization Time

(MAX.)

Manufacturer

Kyocera

Product Name

Oscillation

Frequency

f^XX(MHz)

Recommended Circuit

Constant

Oscillation Voltage

Range

T^OST(ms)

C1 (pF)

C2 (pF)

R^d(kΩ) MIN. (V) MAX. (V)

PBRC5.00BR-A

PBRC6.00BR-A

PBRC6.60BR-A

5.0

6.0

6.6

On-chip On-chip

0

3.0

3.6

0.06

Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.

2. Do not wire any other signal lines in the area indicated by the broken lines.

3. Thoroughly evaluate the matching between the µPD70F3102-33 and the resonator.

22

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(b) External clock input (T^A= –40 to +85°C)

X1

X2

Open

External clock

Caution Input a CMOS level voltage to the X1 pin.

Cautions when turning on/off the power

The µPD70F3102-33 is configured with power supply pins for the internal unit (V^DD) and for the external pins

(HV^DD).

The operation guaranteed range is V^DD= CV^DD= 3.0 to 3.6 V, HV^DD= 5.0 V ±10%. The input and output state of

ports may be undefined when the voltage exceeds this range.

23

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

DC Characteristics (T^A= –40 to 85°C, V^DD= CV^DD= 3.0 to 3.6 V, HV^DD= 5.0 V ±10%, V^SS= 0 V)

Parameter

Symbol

V^IH

Conditions

Except Note 1

MIN.

2.2

TYP.

MAX.

HV^DD+ 0.3

+0.8

Unit

V

Input voltage, high

Note 1

0.8HV^DD

–0.5

V

Input voltage, low

V^IL

V^XH

V^XL

Except Notes 1 and 2

Note 1

V

–0.5

0.2HV^DD

V^DD+ 0.3

0.15V^DD

V

Clock input voltage, high

Clock input voltage, low

X1 pin

Direct mode

PLL mode

Direct mode

PLL mode

0.8V^DD

–0.3

V

X1 pin

V

–0.3

V

Schmitt-triggered input

threshold voltage

HV^T⁺

HV^T^–

Note 1, rising edge

Note 1, falling edge

Note 1

3.0

2.0

V

Schmitt-triggered input

hysteresis width

HV^T⁺

–HV^T^–

0.5

V

Output voltage, high

V^OH

I^OH= –2.5 mA

I^OH= –100 µA

I^OL= 2.5 mA

0.7HV^DD

V

HV^DD– 0.4

Output voltage, low,

V^OL

I^LIH

0.45

10

V

Input leakage current, high

Input leakage current, low

Output leakage current, high

Output leakage current, low

V

^I= HV^DD, except Note 2

^I= 0 V, except Note 2

µA

I^LIL

–10

10

I^LOH

I^LOL

V^O= HV^DD

V^O= 0 V

–10

Notes 1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,

P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2,

P104/INTP120/TC0 to P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3,

P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10,

P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11,

P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1,

P27/SCK1, MODE0 to MODE2, RESET

2. When using the P70/AN10 to P77/ANI7 pins as analog inputs.

Remark TYP. values are reference values for when T^A= 25°C, V^DD= CV^DD= 3.3 V, HV^DD= 5.0 V.

24

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

DC Characteristics (T^A= –40 to 85°C, V^DD= CV^DD= 3.0 to 3.6 V, HV^DD= 5.0 V ±10%, V^SS= 0 V)

Parameter

During normal

Symbol

I^DD1

Conditions

V^DD+ CV^DD

MIN.

TYP.

MAX.

Unit

mA

Supply

current

Direct mode

2.0 × f^X

1.8 × f^X

4.5 × f^X

3.0 × f^X

4.5 × f^X

HV^DD

PLL mode

V^DD+ CV^DD

2.7 × f^X

– 17.0

HV^DD

1.3 × f^X

3.0 × f^X

mA

– 3.6

During HALT

I^DD2

Direct mode

PLL mode

V^DD+ CV^DD

HV^DD

1.4 × f^X

0.8 × f^X

3.0 × f^X

1.5 × f^X

3.0 × f^X

mA

V^DD+ CV^DD

1.8 × f^X

– 10.0

HV^DD

0.8 × f^X

1.5 × f^X

mA

– 1.0

During IDLE

During STOP

I^DD3

Direct mode

PLL mode

V^DD+ CV^DD

HV^DD

V^DD+ CV^DD

HV^DD

3.0

0.5

3.0

0.5

20

10

1.0

10

mA

µA

V^DD+ CV^DD

HV^DD

1.0

50

I^DD4

–40°C ≤ T

A

≤ +40°C

≤ +85°C

20

600

20

µA

+40°C < T

A

10

µA

Remarks 1. TYP. values are reference values for when T^A= 25°C, V^DD= CV^DD= 3.3 V, HV^DD= 5.0 V.

2. Direct mode: f^X= 10 to 33 MHz

PLL mode:

f^X= 20 to 33 MHz

3. The f^Xunit is MHz.

25

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

Data Retention Characteristics (T^A= –40 to +85°C)

Parameter

Symbol

V^DDDR

Conditions

MIN.

1.5

TYP.

MAX.

3.6

Unit

V

Data retention voltage

STOP mode, V^DD= V^DDDR

STOP mode, HV^DD= HV^DDDR

HV^DDDR

I^DDDR

V^DDDR

5.5

V

Data retention current

V^DD=

V^DDDR

50

µA

µs

ms

–40°C ≤ TA ≤ +40°C

+40°C < TA ≤ +85°C

600

Supply voltage rise time

Supply voltage fall time

t^RVD

t^FVD

t^HVD

200

0

Supply voltage hold time

(from STOP mode setting)

STOP release signal input time

t^DREL

0

ns

V

Data retention high-level input

voltage

V^IHDR

Note

0.8HV^DDDR

HV^DDDR

Data retention low-level input

voltage

V^ILDR

0

0.2HV^DDDR

V

Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,

P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2,

P104/INTP120/TC0 to P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3,

P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10,

P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13,

P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1,

MODE0 to MODE2, RESET

Remark TYP. values are reference values for when T^A= 25°C.

STOP mode setting

V

DDDR

V

DD

t

FVD

tRVD

t

HVD

tDREL

HVDD

V

IHDR

RESET (input)

NMI (input)

IHDR

(released by falling edge)

NMI (input)

(released by rising edge)

V

ILDR

26

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

AC Characteristics (T^A= –40 to +85°C, V^DD= CV^DD= 3.0 to 3.6 V, HV^DD= 5.0 V ±10%, V^SS= 0 V, Output Pin

Load Capacitance: C^L= 50 pF)

AC Test Input Waveforms

(a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,

P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to

P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3,

P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,

P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,

P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET

HVDD

0.8HV^DD

0.2HVDD

0.8HVDD

0.2HVDD

Measurement

points

Input signal

0 V

(b) Other than (a)

2.4 V

0.4 V

2.2 V

0.8 V

2.2 V

0.8 V

Measurement

points

Input signal

AC Test Output Measurement Points

2.4 V

0.8 V

2.4 V

0.8 V

Measurement

points

Output signal

Load Conditions

DUT

(Device under test)

CL = 50 pF

Caution If the load capacitance exceeds 50 pF due to the circuit configuration, reduce the load

capacitance of the device to 50 pF or less by inserting a buffer or by some other means.

27

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(1) Clock timing

Parameter

Symbol

<1>

Conditions

In direct mode

MIN.

15

150

5

MAX.

250

Unit

ns

X1 input cycle

t^CYX

t^WXH

t^WXL

t^XR

In PLL mode

In direct mode

In PLL mode

In direct mode

In PLL mode

In direct mode

In PLL mode

In direct mode

In PLL mode

250

ns

X1 input high-level width

X1 input low-level width

X1 input rise time

<2>

<3>

<4>

<5>

ns

50

5

ns

50

ns

4

10

4

ns

X1 input fall time

t^XF

ns

10

33

100

ns

CPU operating frequency

CLKOUT output cycle

CLKOUT high-level width

CLKOUT low-level width

CLKOUT rise time

–

φ

10

MHz

ns

<6>

<7>

<8>

<9>

<10>

t^CYK

t^WKH

t^WKL

t^KR

30

0.5T – 7

0.5T – 4

ns

5

ns

CLKOUT fall time

t^KF

ns

Remark T = t^CYK

<1>

<2>

<3>

<4>

<5>

X1

(PLL mode)

<1>

<3>

<2>

<4>

X1

(Direct mode)

<5>

CLKOUT (output)

<9>

<10>

<7>

<8>

<6>

28

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(2) Output waveform (other than X1, CLKOUT)

Parameter

Symbol

Conditions

MIN.

MAX.

10

Unit

ns

Output rise time

Output fall time

<12>

<13>

t^OR

t^OF

10

ns

<12>

<13>

Signals other than X1, CLKOUT

(3) Reset timing

Parameter

Symbol

Conditions

MIN.

500

MAX.

Unit

ns

RESET pin high-level width

RESET pin low-level width

<14>

<15>

t^WRSH

t^WRSL

At power ON, STOP mode release

500 + T^OS

500

ns

Except at power ON, STOP mode

release

ns

Remark T^OS: Oscillation stabilization time

<14>

<15>

RESET (input)

29

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(4) SRAM, external ROM, external I/O access timing

(a) Access timing (SRAM, external ROM, external I/O) (1/2)

Parameter

Symbol

Conditions

MIN.

2

MAX.

10

Unit

ns

Address, CSn output delay time

<16>

t^DKA

(from CLKOUT↓)

Address, CSn output hold time

<17>

<18>

<19>

<20>

<21>

<22>

<23>

t^HKA

2

10

14

10

ns

(from CLKOUT↓)

RD, IORD↓ delay time

(from CLKOUT↑)

t^DKRDL

t^HKRDH

t^DKWRL

t^HKWRH

t^DKBSL

t^HKBSH

RD, IORD↑ delay time

(from CLKOUT↑)

UWR, LWR, IOWR↓ delay time

(from CLKOUT↑)

UWR, LWR, IOWR↑ delay time

(from CLKOUT↑)

BCYST↓ delay time

(from CLKOUT↓)

BCYST↑ delay time

(from CLKOUT↓)

WAIT setup time (to CLKOUT↓)

WAIT hold time (from CLKOUT↓)

<24>

<25>

<26>

t^SWK

t^HKW

t^SKID

15

2

ns

Data input setup time

18

(to CLKOUT↑)

Data input hold time

<27>

<28>

<29>

t^HKID

t^DKOD

t^HKOD

2

ns

(from CLKOUT↑)

Data output delay time

10

(from CLKOUT↓)

Data output hold time

(from CLKOUT↓)

Remarks 1. Observe at least one of the data input hold times, t^HKIDor t^HRDID.

2. n = 0 to 7

30

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(a) Access timing (SRAM, external ROM, external I/O) (2/2)

T1

TW

T2

CLKOUT (Output)

<16>

<17>

A0 to A23 (Output)

CSn (Output)

<22>

<23>

BCYST (Output)

<19>

<21>

<18>

<20>

RD, IORD (Output)

[Read time]

UWR, LWR, IOWR (Output)

[Write time]

<26>

<27>

D0 to 15 (I/O)

[Read time]

<28>

<29>

D0 to 15 (I/O)

[Write time]

<25>

<24>

WAIT (Input)

Remarks 1. Timing when number of waits specified by registers DWC1 and DWC2 is 0.

2. Broken lines indicate high impedance.

3. n = 0 to 7

31

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(b) Read timing (SRAM, external ROM, external I/O) (1/2)

Parameter

Symbol

<30>

Conditions

MIN.

MAX.

Unit

ns

Data input setup time (to address)

Data input setup time (to RD)

RD, IORD low-level width

RD, IORD high-level width

t^SAID

t^SRDID

t^WRDL

t^WRDH

t^DARD

(1.5 + w^D+ w) T – 28

(1 + w^D+w) T – 32

<31>

<32>

<33>

<34>

ns

(1 + w^D+ w) T – 10

T – 10

ns

Delay time from address, CSn to

0.5T – 10

ns

RD, IORD↓

Delay time from RD, IORD↑ to

<35>

<36>

t^DRDA

(0.5 + i) T – 10

0

ns

address

Data input hold time

t^HRDID

(from RD, IORD↑)

Delay time from RD, IORD↑ to

<37>

t^DRDOD

(0.5 + i) T – 10

ns

data output

WAIT setup time (to address)

WAIT setup time (to BCYST↓)

WAIT hold time (from BCYST↑)

<38>

<39>

<40>

t^SAW

t^SBSW

t^HBSW

Note

T – 25

ns

0

Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0.

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^D: Number of waits specified by registers DWC1, DWC2

4. i: Number of idle states inserted when a write cycle follows the read cycle.

5. Observe at least one of the data input hold times, t^HKIDor t^HRDID.

6. n = 0 to 7

32

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(b) Read timing (SRAM, external ROM, external I/O) (2/2)

T1

TW

T2

CLKOUT (Output)

A0 to A23 (Output)

CSn (Output)

UWR, LWR, IOWR (Output)

<33>

<32>

<35>

<37>

RD, IORD (Output)

<34>

<31>

<30>

<36>

D0 to D15 (I/O)

<38>

WAIT (Input)

<39>

<40>

BCYST (Output)

Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0.

2. Broken lines indicate high impedance.

3. n = 0 to 7

33

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(c) Write timing (SRAM, external ROM, external I/O) (1/2)

Parameter

Symbol

Conditions

Note

MIN.

MAX.

Unit

ns

WAIT setup time (to address)

WAIT setup time (to BCYST↓)

WAIT hold time (from BCYST↑)

<38>

t^SAW

t^SBSW

t^HBSW

t^DAWR

T – 25

<39>

<40>

<41>

Note

ns

Note

0

ns

Delay time from address, CSn to

0.5T – 10

ns

UWR, LWR, IOWR↓

Address setup time

<42>

<43>

<44>

t^SAWR

t^DWRA

t^WWRH

(1.5 + w^D+ w) T – 10

0.5T – 10

ns

(to UWR, LWR, IOWR↑)

Delay time from UWR, LWR,

IOWR↑ to address

UWR, LWR, IOWR high-level

width

T – 10

UWR, LWR, IOWR low-level width

<45>

<46>

t^WWRL

(1 + w^D+ w) T – 10

(1.5 + w^D+ w) T – 10

ns

Data output setup time (to UWR,

t^SODWR

LWR, IOWR↑)

Data output hold time (from UWR,

<47>

t^HWROD

0.5T – 10

ns

LWR, IOWR↑)

Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0.

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^D: Number of waits specified by registers DWC1 and DWC2

4. n = 0 to 7

34

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(c) Write timing (SRAM, external ROM, external I/O) (2/2)

T1

TW

T2

CLKOUT (Output)

A0 to A23 (Output)

CSn (Output)

RD, IORD (Output)

<42>

<43>

<41>

<44>

<45>

UWR, LWR, IOWR (Output)

<46>

<47>

D0 to D15 (I/O)

<38>

WAIT (Input)

<39>

<40>

BCYST (Output)

Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0.

2. Broken lines indicate high impedance.

3. n = 0 to 7

35

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(d) DMA flyby transfer timing (SRAM → external I/O transfer) (1/2)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

ns

WAIT setup time (to CLKOUT↓)

WAIT hold time (from CLKOUT↓)

RD low-level width

<24>

t^SWK

t^HKW

15

<25>

<32>

<33>

<34>

2

(1 + w^D+ w^F+ w) T – 10

T – 10

ns

t^WRDL

t^WRDH

t^DARD

ns

RD high-level width

ns

Delay time from address, CSn to

0.5T – 10

ns

RD↓

Delay time from RD↑ to address

<35>

<37>

t^DRDA

(0.5 + i) T – 10

ns

Delay time from RD↑ to data

t^DRDOD

output

WAIT setup time (to address)

WAIT setup time (to BCYST↓)

WAIT hold time (from BCYST↑)

<38>

<39>

<40>

<41>

t^SAW

t^SBSW

t^HBSW

t^DAWR

Note

T – 25

ns

0

Delay time from address to

0.5T – 10

IOWR↓

Address setup time (to IOWR↑)

<42>

<43>

t^SAWR

t^DWRA

(1.5 + w^D+ w) T – 10

0.5T – 10

ns

Delay time from IOWR↑ to

address

IOWR high-level width

<44>

<45>

<48>

t^WWRH

t^WWRL

t^DWRRD

T – 10

(1 + w^D+ w) T – 10

0

ns

IOWR low-level width

Delay time from IOWR↑ to RD↑

w^F= 0

w^F= 1

T – 10

Delay time from DMAAKm↓ to

IOWR↓

<49>

<50>

t^DDAWR

0.5T – 10

Delay time from IOWR↑ to

DMAAKm↑

t^DWRDA

(0.5 + w^F) T – 10

ns

Note During the first WAIT sampling, when number of waits specified by registers DWC1 and DWC2 is 0.

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^D: Number of waits specified by registers DWC1, DWC2

4. w^F: Number of waits inserted to source-side access during DMA flyby transfer

5. i: Number of idle states inserted when a write cycle follows the read cycle

6. n = 0 to 7, m = 0 to 3

36

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2)

T1

TW

T2

CLKOUT (Output)

A0 to A23 (Output)

CSn (Output)

<33>

<32>

<35>

RD (Output)

UWR, LWR (Output)

DMAAKm (Output)

IORD (Output)

<34>

<48>

<49>

<41>

<50>

<43>

<42>

<45>

<44>

IOWR (Output)

<37>

D0 to D15 (I/O)

WAIT (Input)

<38>

<24>

<25>

<24>

<25>

<40>

<39>

BCYST (Output)

Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0.

2. Broken lines indicate high impedance.

3. n = 0 to 7, m = 0 to 3

37

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

ns

WAIT setup time (to CLKOUT↓)

WAIT hold time (from CLKOUT↓)

IORD low-level width

<24>

t^SWK

t^HKW

15

<25>

<32>

<33>

<34>

2

(1 + w^D+ w^F+ w) T – 10

T – 10

ns

t^WRDL

t^WRDH

t^DARD

ns

IORD high-level width

ns

Delay time from address, CSn to

0.5T – 10

ns

IORD↓

Delay time from IORD↑ to address

<35>

<37>

t^DRDA

(0.5 + i) T – 10

ns

Delay time from IORD↑ to data

t^DRDOD

output

WAIT setup time (to address)

WAIT setup time (to BCYST↓)

WAIT hold time (from BCYST↑)

<38>

<39>

<40>

<41>

t^SAW

t^SBSW

t^HBSW

t^DAWR

Note

T – 25

ns

0

Delay time from address to UWR,

0.5T – 10

LWR↓

Address setup time (to UWR,

<42>

<43>

t^SAWR

(1.5 + w^D+ w) T – 10

0.5T – 10

ns

LWR↑)

Delay time from UWR, LWR to

address

t^DWRA

UWR, LWR high-level width

UWR, LWR low-level width

<44>

<45>

<48>

t^WWRH

t^WWRL

t^DWRRD

T – 10

(1 + w^D+ w) T – 10

0

ns

Delay time from UWR, LWR↑ to

IORD↑

w^F= 0

w^F= 1

T – 10

Delay time from DMAAKm↓ to

IORD↓

<51>

<52>

t^DDARD

0.5T – 10

Delay time from IORD↑ to

DMAAKm↑

t^DRDDA

0.5T – 10

ns

Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0.

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^D: Number of waits specified by registers DWC1 and DWC2.

4. w^F: Number of waits inserted to source-side access during DMA flyby transfer.

5. i: Number of idle states inserted when a write cycle follows the read cycle.

6. n = 0 to 7, m = 0 to 3

38

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(e) DMA flyby transfer timing (external I/O → SRAM transfer) (2/2)

T1

TW

T2

CLKOUT (Output)

A0 to A23 (Output)

CSn (Output)

<42>

<45>

<43>

<41>

<44>

UWR, LWR (Output)

<48>

RD (Output)

<51>

<52>

DMAAKm (Output)

IOWR (Output)

IORD (Output)

D0 to D15 (I/O)

WAIT (Input)

<34>

<33>

<32>

<35>

<37>

<38>

<24>

<25>

<24>

<25>

<40>

<39>

BCYST (Output)

Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0 and w^F= 0.

2. Broken lines indicate high impedance.

3. n = 0 to 7, m = 0 to 3

39

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(5) Page ROM access timing (1/2)

Parameter

Symbol

Conditions

MIN.

15

MAX.

Unit

ns

WAIT setup time (to CLKOUT↓)

WAIT hold time (from CLKOUT↓)

<24>

t^SWK

t^HKW

t^SKID

<25>

<26>

2

ns

Data input setup time

18

ns

(to CLKOUT↑)

Data input hold time

<27>

<30>

<31>

t^HKID

2

ns

(from CLKOUT↑)

Off-page data input setup time

(to address)

t^SAID

(1.5 + w^D+w) T – 28

(1 + w^D+ w) T – 32

Off-page data input setup time

(to RD)

t^SRDID

Off-page RD low-level width

RD high-level width

<32>

<33>

<36>

<37>

t^WRDL

t^WRDH

t^HRDID

t^DRDOD

(1 + w^D+ w) T – 10

0.5T – 10

ns

Data input hold time (from RD)

0

Delay time from RD↑ to data

(0.5 + i) T – 10

output

On-page RD low-level width

<53>

<54>

t^WORDL

t^SOAID

(1.5 + w^PR+ w) T – 10

ns

On-page data input setup time

(to address)

(1.5 + w^PR+ w) T – 28

(1.5 + w^PR+ w) T – 32

On-page data input setup time

(to RD)

<55>

t^SORDID

ns

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^D: Number of waits specified by registers DWC1 and DWC2.

4. w^PR: Number of waits specified by register PRC.

5. i: Number of idle states inserted when a write cycle follows the read cycle.

6. Observe at least one of the data input hold times, t^HKIDor t^HRDID.

40

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(5) Page ROM access timing (2/2)

T1

TDW

TW

T2

TO1 TPRW

TW

TO2

CLKOUT (Output)

Off-page address ^Note

CSn (Output)

On-page address ^Note

UWR, LWR (Output)

RD (Output)

<26>

<30>

<31>

<54>

<33>

<53>

<55>

<32>

<37>

<36>

<27>

<36>

<27>

<26>

<25>

D0 to D15 (I/O)

WAIT (Input)

<25>

<24>

<25>

<24>

<25>

<24>

BCYST (Output)

Note On-page addresses and off-page addresses are as follows.

PRC Register

On-Page Addresses

Off-Page Addresses

MA5

MA4

MA3

0

1

0

1

0

1

A0, A1

A0 to A2

A0 to A3

A0 to A4

A2 to A23

A3 to A23

A4 to A23

A5 to A23

Remarks 1. These timings are for the following cases:

Number of waits (TDW) specified by registers DWC1 and DWC2: 1

Number of waits (TPRW) specified by register PRC: 1

2. Broken lines indicate high impedance.

3. n = 0 to 7

41

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(6) DRAM access timing

(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)

Parameter

Symbol

<24>

Conditions

MIN.

MAX.

Unit

ns

WAIT setup time (to CLKOUT↓)

WAIT hold time (from CLKOUT↓)

Data input setup time (to CLKOUT↑)

Data input hold time (from CLKOUT↑)

Delay time from OE↑ to data output

Row address setup time

t^SWK

t^HKW

t^SKID

t^HKID

t^DRDOD

t^ASR

15

<25>

<26>

<27>

<37>

<56>

<57>

<58>

<59>

<60>

2

18

2

(0.5 + i) T – 10

(0.5 + w^RP) T – 10

(0.5 + w^RH) T – 10

0.5T – 10

Row address hold time

t^RAH

t^ASC

t^CAH

t^RC

Column address setup time

Column address hold time

(1.5 + w^DA+ w) T – 10

Read/write cycle time

(3 + w^RP+ w^RH+ w^DA+ w)

T – 10

RAS recharge time

RAS pulse time

<61>

<62>

t^RP

(0.5 + w^RP) T – 10

ns

t^RAS

(2.5 + w^RH+ w^DA+ w)

T – 10

RAS hold time

<63>

<64>

<65>

<66>

<67>

<68>

<69>

<70>

<71>

<72>

t^RSH

t^RAL

t^CAS

t^CRP

t^CSH

t^RCS

t^RRH

t^RCH

t^CPN

t^OEA

(1.5 + w^DA+ w) T – 10

(2 + w^DA+ w) T – 10

(1 + w^DA+ w) T – 10

(1 + w^RP) T – 10

ns

Column address read time for RAS

CAS pulse width

CAS to RAS precharge time

CAS hold time

(2 + w^RH+ w^DA+ w) T – 10

(2 + w^RP+ w^RH) T – 10

0.5T – 10

WE setup time

WE hold time (from RAS↑)

WE hold time (from CAS↑)

CAS precharge time

T – 10

(2 + w^RP+ w^RH) T – 10

Output enable access time

(2 + w^RP+ w^RH+ w^DA+ w)

T – 28

RAS access time

<73>

<74>

<75>

t^RAC

t^AA

(2 + w^RH+ w^DA+ w) T – 28

(1.5 + w^DA+ w) T – 28

(1 + w^DA+ w) T – 28

ns

Access time from column address

CAS access time

t^CAC

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^RP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

5. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

6. i: Number of idle states inserted when a write cycle follows the read cycle.

42

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)

Parameter

Symbol

Conditions

MIN.

(0.5 + w^RH) T – 10

(1 + w^RH) T – 10

0

MAX.

Unit

ns

RAS column address delay time

RAS to CAS delay time

<76>

t^RAD

t^RCD

t^OEZ

<77>

<78>

ns

Output buffer turn off delay time

ns

(from OE↑)

Output buffer turn off delay time

<79>

t^OFF

0

ns

(from CAS↑)

Remarks 1. T = t^CYK

2. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

43

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)

TRPW

T1

TRHW

T2

TDAW

TW

T3

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

<58>

<56>

<57>

<59>

Row address

Column address

<63>

<64>

<76>

<61>

<62>

<60>

<67>

<77>

<65>

<66>

UCAS (Output)

LCAS (Output)

<69>

<70>

<71>

<68>

<73>

<75>

WE (Output)

OE (Output)

<79>

<74>

<27>

<37>

<72>

<78>

<26>

D0 to D15 (I/O)

<24>

<25>

<24>

<25>

WAIT (Input)

Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):

Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1

Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1

Number of waits (TDAW) specified by DACxx bit of register DRCn: 1

2. Broken lines indicate high impedance.

3. n = 0 to 7

44

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

[MEMO]

45

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(b) Read timing (high-speed DRAM access: on-page) (1/2)

Parameter

Symbol

<26>

Conditions

MIN.

18

MAX.

Unit

ns

Data input setup time (to CLKOUT↑)

Data input hold time (from CLKOUT↑)

Delay time from OE↑ to data output

Column address setup time

Column address hold time

RAS hold time

t^SKID

t^HKID

t^DRDOD

t^ASC

t^CAH

t^RSH

t^RAL

<27>

<37>

<58>

<59>

<63>

<64>

<65>

<68>

<69>

<70>

<72>

<74>

<75>

<78>

2

(0.5 + i) T – 10

(0.5 + w^CP) T – 10

(1.5 + w^DA) T – 10

(2 + w^CP+ w^DA) T – 10

(1 + w^DA) T – 10

(1 + w^CP) T – 10

0.5 T – 10

Column address read time for RAS

CAS pulse width

t^CAS

t^RCS

t^RRH

t^RCH

t^OEA

t^AA

WE setup time (to CAS↓)

WE hold time (from RAS↑)

WE hold time (from CAS↑)

Output enable access time

Access time from column address

CAS access time

T – 10

(1 + w^CP+ w^DA) T – 28

(1.5 + w^CP+ w^DA) T – 28

(1 + w^DA) T – 28

t^CAC

t^OEZ

Output buffer turn-off delay time

0

(from OE↑)

Output buffer turn-off delay time

<79>

t^OFF

ns

(from CAS↑)

Access time from CAS precharge

CAS precharge time

<80>

<81>

<82>

<83>

t^ACP

t^CP

(2 + w^CP+ w^DA) T – 28

ns

(1 + w^CP) T – 10

(2 + w^CP+ w^DA) T – 10

(2.5 + w^CP+ w^DA) T – 10

High-speed page mode cycle time

RAS hold time from CAS precharge

t^PC

t^RHCP

Remarks 1. T = t^CYK

2. w^CP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

3. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. i: Number of idle states inserted when a write cycle follows the read cycle.

46

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(b) Read timing (high-speed DRAM access: on-page) (2/2)

TCPW

TO1

TDAW

TO2

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

<58>

<59>

<63>

Column address

<64>

<83>

<81>

<65>

<82>

UCAS (Output)

LCAS (Output)

<69>

<70>

<68>

WE (Output)

OE (Output)

<75>

<79>

<37>

<72>

<26>

<74>

<80>

<78>

<27>

D0 to D15 (I/O)

WAIT (Input)

Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):

Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1

Number of waits (TDAW) specified by DACxx bit of register DRCn: 1

2. Broken lines indicate high impedance.

3. n = 0 to 7

47

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)

Parameter

Symbol

<24>

Conditions

MIN.

15

MAX.

Unit

ns

WAIT setup time (to CLKOUT↓)

WAIT hold time (from CLKOUT↓)

Row address setup time

Row address hold time

t^SWK

t^HKW

t^ASR

t^RAH

t^ASC

t^CAH

t^RC

<25>

<56>

<57>

<58>

<59>

<60>

2

(0.5 + w^RP) T – 10

(0.5 + w^RH) T – 10

0.5T – 10

Column address setup time

Column address hold time

Read/write cycle time

(1.5 + w^DA+ w) T – 10

(3 + w^RP+ w^RH+ w^DA+ w)

T – 10

RAS precharge time

RAS pulse time

<61>

<62>

t^RP

(0.5 + w^RP) T – 10

ns

t^RAS

(2.5 + w^RH+ w^DA+ w)

T – 10

RAS hold time

<63>

<64>

t^RSH

t^RAL

(1.5 + w^DA+ w) T – 10

(2 + w^DA+ w) T – 10

ns

Column address read time (from

RAS↑)

CAS pulse width

<65>

<66>

<67>

<71>

<76>

<77>

<84>

<85>

<86>

<87>

t^CAS

t^CRP

t^CSH

t^CPN

t^RAD

t^RCD

t^WCS

t^WCH

t^DS

(1 + w^DA+ w) T – 10

(1 + w^RH) T – 10

ns

CAS to RAS precharge time

CAS hold time

(2 + w^RH+ w^DA+ w) T – 10

(2 + w^RP+ w^RH) T – 10

(0.5+ w^RH) T – 10

CAS precharge time

RAS column address delay time

RAS to CAS delay time

WE setup time (to CAS↓)

WE hold time (from CAS↓)

Data setup time (to CAS↓)

Data hold time (from CAS↓)

(1 + w^RH) T – 10

(1 + w^RP+ w^RH) T – 10

(1 + w^DA+ w) T – 10

(1.5 + w^RP+ w^RH) T – 10

(1.5 + w^DA+ w) T – 10

t^DH

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^RP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

5. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

48

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)

TRPW

T1

TRHW

T2

TDAW

TW

T3

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

<58>

<56>

<57>

<59>

Row address

Column address

<63>

<64>

<76>

<61>

<62>

<60>

<67>

<77>

<65>

<66>

UCAS (Output)

LCAS (Output)

<71>

OE (Output)

WE (Output)

<84>

<85>

<86>

<87>

D0 to D15 (I/O)

<24>

<25>

<24>

<25>

WAIT (Input)

Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):

Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1

Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1

Number of waits (TDAW) specified by DACxx bit of register DRCn: 1

2. Broken lines indicate high impedance.

3. n = 0 to 7

49

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(d) Write timing (high-speed page DRAM access: on-page) (1/2)

Parameter

Column address setup time

Column address hold time

RAS hold time

Symbol

Conditions

MIN.

MAX.

Unit

ns

<58>

t^ASC

t^CAH

t^RSH

t^RAL

(0.5 + w^CP) T – 10

(1.5 + w^DA) T – 10

(2 + w^CP+ w^DA) T – 10

<59>

<63>

<64>

ns

Column address read time (from

ns

RAS↑)

CAS pulse width

<65>

<81>

<83>

<84>

<85>

<86>

<87>

<88>

<89>

<90>

<91>

<92>

t^CAS

t^CP

(1 + w^DA) T – 10

(1 + w^CP) T – 10

(2.5 + w^CP+ w^DA) T – 10

w^CPT – 10

ns

CAS precharge time

RAS hold time for CAS precharge

WE setup time (to CAS↓)

WE hold time (from CAS↓)

Data setup time (to CAS↓)

Data hold time (from CAS↓)

WE read time (from RAS↑)

WE read time (from CAS↑)

Data setup time (to WE↓)

Data hold time (from WE↓)

WE pulse width

t^RHCP

t^WCS

t^WCH

t^DS

w^CP≥ 1

(1 + w^DA) T – 10

(0.5 + w^CP) T – 10

(1.5 + w^DA) T – 10

(1 + w^DA) T – 10

0.5T – 10

t^DH

t^RWL

t^CWL

t^DSWE

t^DHWE

t^WP

w^CP= 0

(1.5 + w^DA) T – 10

(1 + w^DA) T – 10

Remarks 1. T = t^CYK

2. w^CP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

3. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

50

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(d) Write timing (high-speed page DRAM access: on-page) (2/2)

TCPW

TO1

TDAW

TO2

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

<58>

<59>

<63>

Column address

<64>

<83>

<81>

<65>

UCAS (Output)

LCAS (Output)

<89>

<88>

OE (Output)

WE (Output)

<84>

<85>

<92>

<91>

<90>

<86>

<87>

D0 to D15 (I/O)

WAIT (Input)

Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):

Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1

Number of waits (TDAW) specified by DACxx bit of register DRCn: 1

2. Broken lines indicate high impedance.

3. n = 0 to 7

51

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(e) Read timing (EDO DRAM) (1/3)

Parameter

Symbol

Conditions

MIN.

18

MAX.

Unit

ns

Data input setup time (to

<26>

t^SKID

CLKOUT↑)

Data input hold time (from

<27>

t^HKID

2

ns

CLKOUT↑)

Delay time from OE↑ to data output

Row address setup time

Row address hold time

<37>

<56>

<57>

<58>

<59>

<61>

t^DRDOD

t^ASR

t^RAH

t^ASC

t^CAH

t^RP

(0.5 + i) T – 10

(0.5 + w^RP) T – 10

(0.5 + w^RH) T – 10

0.5T – 10

ns

Column address setup time

Column address hold time

RAS precharge time

(0.5 + w^DA) T – 10

(0.5 + w^RP) T – 10

(2 + w^CP+ w^DA) T – 10

(1 + w^RP) T – 10

(1.5 + w^RH+ w^DA) T – 10

(2 + w^RP+w^RH) T – 10

0.5T – 10

Column address read time (to RAS↑) <64>

t^RAL

t^CRP

t^CSH

t^RCS

t^RRH

t^RCH

t^RAC

t^AA

CAS to RAS precharge time

CAS hold time

<66>

<67>

<68>

<69>

<70>

<73>

<74>

<75>

<76>

WE setup time (to CAS↓)

WE hold time (from RAS↑)

WE hold time (from CAS↑)

RAS access time

1.5T – 10

(2 + w^RH+ w^DA) T – 28

(1.5 + w^DA) T – 28

(1 + w^DA) T – 28

Access time from column address

CAS access time

t^CAC

t^RAD

Delay time from RAS to column

address

(0.5 + w^RH) T – 10

RAS to CAS delay time

<77>

<78>

t^RCD

t^OEZ

(1 + w^RH) T – 10

0

ns

Output buffer turn-off delay time

(from OE)

Access time from CAS precharge

CAS precharge time

<80>

<81>

<83>

<93>

<94>

<95>

<96>

<97>

<98>

t^ACP

t^CP

t^RHCP

t^HPC

(1.5 + w^CP+ w^DA) T – 28

ns

(0.5 + w^CP) T – 10

(2 + w^CP+ w^DA) T – 10

(1 + w^DA+ w^CP) T – 10

(2.5 + w^RH+ w^DA) T – 10

(0.5 + w^DA) T – 10

(2 + w^RH+ w^DA) T – 10

(0.5 + w^DA) T – 10

0

RAS hold time for CAS precharge

Read cycle time

RAS pulse width

t^RASP

t^HCAS

t^OCH1

t^OCH2

t^DHC

CAS pulse width

Hold time from

OE to CAS

Off-page

On-page

Data input hold time (from CAS↓)

Remarks 1. T = t^CYK

2. w^RP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

3. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

5. w^CP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

6. i: Number of idle states inserted when a write cycle follows the read cycle.

52

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(e) Read timing (EDO DRAM) (2/3)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

ns

Output enable

access time

Off-page

On-page

<99>

t^OEA1

(2 + w^RP+ w^RH+ w^DA)

T – 28

<100>

t^OEA2

(1 + w^CP+ w^DA) T – 28

ns

Remarks 1. T = t^CYK

2. w^RP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

3. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

5. w^CP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

53

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(e) Read timing (EDO DRAM) (3/3)

TRPW

T1

TRHW

T2

TDAW TCPW

TB

TDAW

TE

CLKOUT (Output)

<58>

<57>

<56>

<59>

A0 to A23 (Output)

RASn (Output)

Row address

<76>

Column address

<64>

<74>

<61>

<94>

<67>

<83>

<75>

<66>

<77>

<95>

<93>

<81>

UCAS (Output)

LCAS (Output)

<69>

<70>

<68>

<95>

<80>

WE (Output)

OE (Output)

<97>

<96>

<100> <26>

<37>

Note

<75>

<98>

<27>

<78>

<74>

<26>

D0 to D15 (I/O)

BCYST (Output)

WAIT (Input)

Data

<73>

<99>

Note In case of on-page access from another cycle, while RASn is low level.

Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):

Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1

Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1

Number of waits (TDAW) specified by DACxx bit of register DRCn: 1

Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1

2. Broken lines indicate high impedance.

3. n = 0 to 7

54

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

[MEMO]

55

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(f) Write timing (EDO DRAM) (1/2)

Parameter

Row address setup time

Row address hold time

Column address setup time

Column address hold time

RAS precharge time

Symbol

Conditions

MIN.

MAX.

Unit

ns

<56>

<57>

<58>

<59>

<61>

<63>

<64>

t^ASR

t^RAH

t^ASC

t^CAH

t^RP

(0.5 + w^RP) T – 10

(0.5 + w^RH) T –10

0.5T – 10

(0.5 + w^DA) T – 10

(0.5 + w^RP) T – 10

(1.5 + w^DA) T – 10

(2 + w^CP+ w^DA) T – 10

RAS hold time

t^RSH

t^RAL

Column address read time

(to RAS↑)

CAS to RAS precharge time

CAS hold time

<66>

<67>

<76>

t^CRP

t^CSH

t^RAD

(1 + w^RP) T – 10

(1.5 + w^RH+ w^DA) T – 10

(0.5 + w^RH) T – 10

ns

Delay time from RAS to column

address

RAS to CAS delay time

<77>

<81>

<83>

<85>

<87>

<88>

t^RCD

t^CP

(1 + w^RH) T – 10

(0.5 + w^CP) T – 10

(2 + w^CP+ w^DA) T – 10

(1 + w^DA) T – 10

ns

CAS precharge time

RAS hold time for CAS precharge

WE hold time (from CAS↓)

Data hold time (from CAS↓)

t^RHCP

t^WCH

t^DH

(0.5 + w^DA) T – 10

(1.5 + tw^DA) T – 10

WE read time (to

On-page

t^RWL

w^CP= 0

RAS↑)

WE read time (to

<89>

t^CWL

(0.5 + w^DA) T – 10

ns

CAS↑)

WE pulse width

Write cycle time

RAS pulse width

CAS pulse width

<92>

<93>

t^WP

t^HPC

(1 + w^DA) T – 10

(1 + w^DA+ w^CP) T – 10

(2.5 + w^RH+ w^DA) T – 10

(0.5 + w^DA) T – 10

(1 + w^RP+ w^RH) T – 10

w^CPT – 10

ns

<94>

t^RASP

t^HCAS

t^WCS1

t^WCS2

t^DS1

<95>

WE setup time

Off-page

On-page

Off-page

On-page

<101>

<102>

<103>

<104>

(to CAS↓)

w^CP≥ 1

Data setup time

(1.5 + w^RP+ w^RH) T – 10

(0.5 + w^CP) T – 10

(to CAS↓)

t^DS2

Remarks 1. T = t^CYK

2. w^RP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

3. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

5. w^CP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

56

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(f) Write timing (EDO DRAM) (2/2)

TRPW

T1

TRHW

T2

TDAW TCPW

TB

TDAW

TE

CLKOUT (Output)

<58>

<57>

<56>

<59>

<58>

<59>

A0 to A23 (Output)

RASn (Output)

Row address

<76>

Column address

<64>

<61>

<94>

<67>

<77>

<83>

<66>

<95>

<89>

<81>

<63>

UCAS (Output)

LCAS (Output)

<93>

<88>

<95>

RD (Output)

OE (Output)

<102>

<85>

<101>

<85>

<92>

WE (Output)

D0 to D15 (I/O)

BCYST (Output)

WAIT (Input)

<103>

<87>

<104>

<87>

Data

Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):

Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1

Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1

Number of waits (TDAW) specified by DACxx bit of register DRCn: 1

Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1

2. Broken lines indicate high impedance.

3. n = 0 to 7

57

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (1/3)

Parameter

Symbol

Conditions

MIN.

15

MAX.

Unit

ns

WAIT setup time (to CLKOUT↓)

WAIT hold time (from CLKOUT↓)

Delay time from OE↑ to data output

Delay time from address to IOWR↓

Address setup time (to IOWR↑)

Delay time from IOWR↑ to address

Delay time from IOWR↑ to RD↑

<24>

t^SWK

t^HKW

<25>

<37>

<41>

<42>

<43>

<48>

2

t^DRDOD

t^DAWR

t^SAWR

t^DWRA

t^DWRRD

(0.5 + i) T – 10

(0.5 + w^RP) T – 10

(2 + w^RP+ w^RH+ w^DA+ w) T –10

0.5T – 10

w^F= 0

w^F= 1

0

T – 10

IOWR low-level width

<50>

<56>

<57>

<58>

<59>

<60>

t^WWRL

t^ASR

t^RAH

t^ASC

t^CAH

t^RC

(2 + w^RH+ w^DA+ w) T – 10

(0.5 + w^RP) T – 10

(0.5 + w^RH) T – 10

0.5T – 10

Row address setup time

Row address hold time

Column address setup time

Column address hold time

Read/write cycle time

(1.5 + w^DA+ w^F+ w) T – 10

(3 + w^RP+ w^RH+ w^DA+ w^F+

w) T – 10

RAS precharge time

<61>

<63>

<64>

<65>

<66>

<67>

<68>

<69>

<70>

<71>

<76>

<77>

t^RP

(0.5 + w^RP) T – 10

(1.5 + w^DA+ w^F+ w) T – 10

(2 + w^CP+ w^DA+ w^F+ w) T – 10

(1 + w^DA+ w^F+ w) T – 10

(1 + w^RP) T –10

ns

RAS hold time

t^RSH

t^RAL

t^CAS

t^CRP

t^CSH

t^RCS

t^RRH

t^RCH

t^CPN

t^RAD

t^RCD

Column address read time for RAS

CAS pulse width

CAS to RAS precharge time

CAS hold time

(2 + w^RH+ w^DA+ w^F+ w) T – 10

(2 + w^RP+ w^RH) T – 10

0.5T – 10

WE setup time (to CAS↓)

WE hold time (from RAS↑)

WE hold time (from CAS↑)

CAS precharge time

1.5T – 10

(2 + w^RP+ w^RH) T – 10

(0.5 + w^RH) T – 10

RAS column address delay time

RAS to CAS delay time

(1 + w^RH) T – 10

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^RP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

5. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

6. w^CP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

7. w^F: Number of waits inserted to source-side access during DMA flyby transfer

8. i: Number of idle states inserted when a write cycle follows the read cycle.

58

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (2/3)

Parameter

Symbol

<78> t^OEZ

Conditions

MIN.

0

MAX.

Unit

ns

Output buffer turn-off delay time

(from OE↑)

Output buffer turn-off delay time

<79>

t^OFF

0

ns

(from CAS↑)

CAS precharge time

<81>

<82>

t^CP

t^PC

(0.5 + w^CP) T – 10

ns

High-speed mode cycle time

(2 + w^CP+ w^DA+ w^F+ w)

T – 10

RAS hold time for CAS precharge

RAS pulse width

<83>

<94>

<96>

<97>

t^RHCP

t^RASP

t^OCH1

t^OCH2

(2.5 + w^CP+ w^DA+ w^F+

w) T – 10

ns

(2.5 + w^RH+ w^DA+ w^F+

w) T – 10

Hold time from

OE to CAS

Off-page

On-page

(2.5 + w^RP+ w^RH+

w^DA+ w^F+ w) T – 10

(from CAS↑)

(1.5 + w^CP+ w^DA+ w^F+

w) T – 10

Delay time from DMAAKm↓ to

CAS↓

<105> t^DDACS

<106> t^DRDCS

(1.5 + w^RH) T – 10

Delay time from IOWR↓ to CAS↓

(1 + w^RH) T – 10

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^CP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

5. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

6. w^RP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

7. w^F: Number of waits inserted to source-side access during DMA flyby transfer

8. m = 0 to 3

59

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (3/3)

TRPW T1 TRHW T2 TDAW TW

T3 TCPW TO1 TDAW TW TO2

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

<58>

<57>

<56>

<59>

Row address

<76>

Column address

<64>

<61>

<94>

<60>

<69>

<77>

<65>

<83>

<63>

<66>

<67>

<81>

UCAS (Output)

LCAS (Output)

<70>

<71>

<82>

<96>

<79>

RD (Output)

OE (Output)

<105>

<48>

<97>

DMAAKm (Output)

WE (Output)

<68>

IORD (Output)

IOWR (Output)

D0 to D15 (I/O)

WAIT (Input)

<106>

<42>

<43>

<78>

<37>

<41>

<50>

<24>

Data

<25>

<24>

<25>

BCYST (Output)

Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):

Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1

Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1

Number of waits (TDAW) specified by DACxx bit of register DRCn: 1

Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1

Number of waits inserted to source-side access during DMA flyby transfer: 0

2. Broken lines indicate high impedance.

3. n = 0 to 7, m = 0 to 3

60

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3)

Parameter

WAIT setup time (to CLKOUT↓)

WAIT hold time (from CLKOUT↓)

IORD low-level width

Symbol

<24>

Conditions

MIN.

15

MAX.

Unit

ns

t^SWK

t^HKW

t^WRDL

t^WRDH

t^DARD

t^DRDA

t^ASR

t^RAH

t^ASC

t^CAH

t^RC

<25>

<32>

<33>

<34>

<35>

<56>

<57>

<58>

<59>

<60>

<61>

<63>

<64>

<65>

<66>

<67>

<71>

<76>

<77>

<81>

<82>

<83>

<85>

<88>

<89>

<92>

<94>

2

(2 + w^RH+ w^DA+ w^F+ w) T – 10

T – 10

IORD high-level width

Delay time from address to IORD↑

Delay time from IORD↑ to address

Row address setup time

Row address hold time

Column address setup time

Column address hold time

Read/write cycle time

0.5T – 10

(0.5 + i) T – 10

(0.5 + w^RP) T – 10

(0.5 + w^RH) T – 10

0.5T – 10

(1.5 + w^DA+ w^F) T – 10

(3 + w^RP+ w^RH+ w^DA+ w^F+ w) T – 10

(0.5 + w^RP) T – 10

RAS precharge time

t^RP

RAS hold time

t^RSH

t^RAL

t^CAS

t^CRP

t^CSH

t^CPN

t^RAD

t^RCD

t^CP

(1.5 + w^DA+ w^F) T – 10

(2 + w^CP+ w^DA+ w^F+ w) T – 10

(1 + w^DA+ w^F) T – 10

(1 + w^RP) T – 10

Column address read time for RAS

CAS pulse width

CAS to RAS precharge time

CAS hold time

(2 + w^RH+ w^DA+ w^F+ w) T – 10

(2 + w^RP+ w^RH+ w) T – 10

(0.5 + w^RH) T – 10

CAS precharge time

RAS column address delay time

RAS to CAS delay time

CAS precharge time

(1 + w^RH+ w) T – 10

(0.5 + w^CP+ w) T – 10

(2 + w^CP+ w^DA+ w^F+ w) T – 10

(2.5 + w^CP+ w^DA+ w) T – 10

(1 + w^DA) T – 10

High-speed page mode cycle time

RAS hold time for CAS precharge

WE hold time (from CAS↓)

WE read time (to RAS↑)

WE read time (to CAS↑)

WE pulse width

t^PC

t^RHCP

t^WCH

t^RWL

t^CWL

t^WP

w^CP= 0

(1.5 + w^DA+ w) T – 10

(1 + w^DA+ w) T – 10

(2.5 + w^RH+ w^DA+ w^F+ w) T – 10

RAS pulse width

t^RASP

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. w^DA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

5. w^RP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

6. w^CP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

7. w^F: Number of waits inserted to source-side access during DMA flyby transfer.

8. i: Number of idle states inserted when a write cycle follows the read cycle.

9. n = 0 to 7

61

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (2/3)

Parameter

Symbol

Conditions

w^CP= 0

MIN.

MAX.

Unit

ns

WE setup time

(to CAS↓)

Off-page

On-page

<101> t^WCS1

<102> t^WCS2

<105> t^DDACS

(1 + w^RH+ w^RP+ w) T – 10

w^CPT – 10

w^CP≥ 1

ns

Delay time from DMAAKm↓ to

CAS↓

(1.5 + w^RH+ w) T – 10

ns

Delay time from IORD↓ to CAS↓

Delay time from WE↑ to IORD↑

<106> t^DRDCS

<107> t^DWERD

(1 + w^RH+ w) T – 10

ns

w^F= 0

w^F= 1

0

T – 10

Remarks 1. T = t^CYK

2. w: Number of waits due to WAIT

3. w^RH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

4. w^RP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

5. w^CP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)

6. w^F: Number of waits inserted to source-side access during DMA flyby transfer

7. m = 0 to 3

62

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (3/3)

TRPW T1 TRHW TW

T2 TDAW T3 TCPW TW TO1 TDAW TO2

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

<56>

<57>

<58>

<59>

Row address

<76>

<61>

Column address

<64>

<94>

<60>

<77>

<65>

<66>

<67>

<81>

<63>

UCAS (Output)

LCAS (Output)

<71>

<82>

<83>

RD (Output)

OE (Output)

<102>

<88>

<89>

<101>

<105>

<85>

WE (Output)

DMAAKm (Output)

IOWR (Output)

IORD (Output)

D0 to D15 (I/O)

WAIT (Input)

<92>

<106>

<107>

<35>

<34>

<32>

<24>

<25>

<33>

Data

<24>

<25>

BCYST (Output)

Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):

Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1

Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1

Number of waits (TDAW) specified by DACxx bit of register DRCn: 1

Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1

Number of waits inserted to source-side access during DMA flyby transfer: 0

2. Broken lines indicate high impedance.

3. n = 0 to 7, m = 0 to 3

63

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(i) CBR refresh timing

Parameter

RAS precharge time

RAS pulse width

Symbol

Conditions

MIN.

(1.5 + w^RRW) T – 10

(1.5 + w

MAX.

Unit

ns

<61>

t^RP

t^RAS

t^CHR

t^WRFL

RCW ^Note) T – 10

<62>

<108>

<109>

ns

(1.5 + w

RCW ^Note) T – 10

ns

CAS hold time

REFRQ pulse width

(3 +w

^RRW+ w^RCW^Note

T – 10

)

ns

RAS precharge CAS hold time

<110>

<111>

t^RPC

(0.5 + w^RRW) T – 10

2

ns

REFRQ active delay time

t^DKRF

10

(from CLKOUT↓)

REFRQ inactive delay time

<112>

<113>

t^HKRF

2

ns

(from CLKOUT↓)

CAS setup time

t^CSR

T – 10

Note w^RCWis inserted for at least 1 clock, regardless of the setting of bits RCW0 to RCW2 of register RWC.

Remarks 1. T = t^CYK

2. w^RRW: Number of waits specified by bits RRW0 and RRW1 of register RWC

3. w^RCW: Number of waits specified by bits RCW0 to RCW2 of register RWC.

TRRW

T1

T2

TRCW^Note

TRCW

T3

TI

CLKOUT (Output)

REFRQ (Output)

RASn (Output)

<111>

<112>

<109>

<61>

<62>

<110>

<113>

<108>

UCAS (Output)

LCAS (Output)

Note This TRCW is always inserted, regardless of the setting of bits RCW0 to RCW2 of register RWC.

Remarks 1. These timings are for the following cases:

Number of waits (TRRW) specified by bits RRW0 and RRW1 of register RWC: 1

Number of waits (TRCW) specified by bits RCW0 to RCW2 of register RWC: 2

2. n = 0 to 7

64

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(j) CBR self refresh timing

Parameter

Symbol

<111> t^DKRF

Conditions

MIN.

2

MAX.

10

Unit

ns

REFRQ active delay time

(from CLKOUT↓)

REFRQ inactive delay time

<112>

t^HKRF

2

10

ns

(from CLKOUT↓)

CAS hold time

<114>

<115>

t^CHS

t^RPS

–5

ns

RAS precharge time

(1 + 2w^SRW) T – 10

Remarks 1. T = t^CYK

2. w^SRW: Number of waits specified by bits SRW0 to SRW2 of register RWC.

TRRW

TH

TRCW

TH

TI

TSRW

CLKOUT (Output)

REFRQ (Output)

RASn (Output)

<111>

<112>

<115>

<114>

UCAS (Output)

LCAS (Output)

Output signals

other than above

Remarks 1. These timings are for the following cases:

Number of waits (TRRW) specified by bits RRW0 and RRW1 of register RWC: 1

Number of waits (TRCW) specified by bits RCW0 to RCW2 of register RWC: 1

Number of waits (TSRW) specified by bits SRW0 to SRW2 of register RWC: 2

2. Broken lines indicate high impedance.

3. n = 0 to 7

65

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(7) DMAC timing

Parameter

Symbol

Conditions

MIN.

15

MAX.

Unit

ns

DMARQn setup time

<116>

t^SDRK

(to CLKOUT↑)

DMARQn hold time

<117>

<118>

<119>

t^HKDR1

t^HKDR2

t^DKDA

2

Until DMAAKn↓

2

ns

(from CLKOUT↑)

DMAAKn output delay time

10

(from CLKOUT↓)

DMAAKn output hold time

<120>

<121>

<122>

t^HKDA

t^DKTC

t^HKTC

2

ns

(from CLKOUT↓)

TCn output delay time

(from CLKOUT↓)

TCn output hold time

(from CLKOUT↓)

Remark n = 0 to 3

CLKOUT (Output)

<117>

<116>

<118>

DMARQn (Input)

DMAAKn (Output)

<116>

<119>

<120>

<122>

<121>

TCn (Output)

Remark n = 0 to 3

66

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

[MEMO]

67

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(8) Bus hold timing (1/2)

Parameter

Symbol

Conditions

MIN.

15

MAX.

Unit

ns

HLDRQ setup time (to CLKOUT↑)

<123>

t^SHRK

t^HKHR

HLDRQ hold time

<124>

2

ns

(from CLKOUT↑)

Delay time from CLKOUT↓ to

<125>

t^DKHA

2

10

ns

HLDAK

HLDRQ high-level width

HLDAK low-level width

<126>

<127>

<128>

t^WHQH

t^WHAL

t^DKCF

T + 17

T – 8

ns

Delay time from CLKOUT↓ to bus

float

Delay time from HLDAK↑ to bus

<129>

t^DHAC

0

ns

output

Delay time from HLDRQ↓ to

HLDAK↓

<130> t^DHQHA1

<131> t^DHQHA2

2.5T

0.5T

Delay time from HLDRQ↑ to

HLDAK↑

1.5T

Remark T = t^CYK

68

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(8) Bus hold timing (2/2)

T1

T2

T3

TI

TH

TI

T1

CLKOUT (Output)

<123>

<124>

<123>

<124>

<123>

<126>

HLDRQ (Intput)

HLDAK (Output)

A0 to A23 (Output)

D0 to D15 (I/O)

CSn/RASn (Output)

BCYST (Output)

RD (Output)

<125>

<128>

<125>

<131>

<130>

<127>

<129>

Address

Undefined

Data

WE (Output)

UCAS (Output)

LCAS (Output)

Remarks 1. Broken lines indicate high impedance.

2. n = 0 to 7

69

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(9) Interrupt timing

Parameter

NMI high-level width

NMI low-level width

INTPn high-level width

INTPn low-level width

Symbol

Conditions

MIN.

500

MAX.

Unit

ns

<132>

t^WNIH

t^WNIL

t^WITH

t^WITL

<133>

<134>

<135>

500

ns

4T + 10

ns

Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, and 150 to 153

2. T = t^CYK

<132>

<134>

<133>

NMI (Input)

<135>

INTPn (Input)

Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, and 150 to 153

(10) RPU timing

Parameter

TI1n high-level width

TI1n low-level width

Symbol

Conditions

MIN.

MAX.

Unit

ns

<136> t^WTIH

<137> t^WTIL

<138> t^WTCH

<139> t^WTCL

3T + 18

ns

TCLR1n high-level width

TCLR1n low-level width

ns

Remarks 1. n = 0 to 5

2. T = t^CYK

<136>

<137>

<139>

TI1n (Input)

<138>

TCLR1n (Input)

Remark n = 0 to 5

70

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(11) UART0, UART1 timing (synchronized with clock, master mode only)

Parameter

Symbol

<140>

Conditions

Output

MIN.

MAX.

Unit

ns

SCKn cycle

t^CYSK0

t^WSK0H

t^WSK0L

t^SRXSK

t^HSKRX

t^DSKTX

250

SCKn high-level width

<141>

<142>

<143>

<144>

<145>

Output

0.5t^CYSK0– 20

ns

SCKn low-level width

Output

0.5t^CYSK0– 20

ns

RXDn setup time (to SCKn↑)

RXDn hold time (from SCKn↑)

30

0

ns

TXDn output delay time

20

ns

(from SCKn↓)

TXDn output hold time

<146>

t^HSKTX

0.5t^CYSK0– 5

ns

(from SCKn↑)

Remark n = 0, 1

<140>

<142>

<141>

SCKn (I/O)

<143>

<144>

RXDn (Input)

Input data

<145>

<146>

TXDn (Output)

Output data

Remarks 1. Broken lines indicate high impedance.

2. n = 0, 1

71

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

(12) CSI0 to CSI3 timing

(a) Master mode

Parameter

SCKn cycle

Symbol

Conditions

Output

MIN.

MAX.

Unit

ns

<147>

t^CYSK1

t^WSK1H

t^WSK1L

t^SSISK

100

SCKn high-level width

SCKn low-level width

SIn setup time (to SCKn↑)

SIn hold time (from SCKn↑)

<148>

<149>

<150>

<151>

Output

0.5t^CYSK1– 20

Output

0.5t^CYSK1– 20

30

0

t^HSKSI

t^DSKSO

t^HSKSO

SOn output delay time (from SCKn↓) <152>

20

SOn output hold time (from SCKn↑)

<153>

0.5t^CYSK1– 5

Remark n = 0 to 3

(b) Slave mode

Parameter

SCKn cycle

Symbol

Conditions

Input

MIN.

100

30

MAX.

Unit

ns

<147>

<148>

<149>

<150>

<151>

t^CYSK1

t^WSK1H

t^WSK1L

t^SSISK

SCKn high-level width

SCKn low-level width

SIn setup time (to SCKn↑)

SIn hold time (from SCKn↑)

Input

30

10

t^HSKSI

t^DSKSO

t^HSKSO

10

SOn output delay time (from SCKn↓) <152>

30

SOn output hold time (from SCKn↑)

<153>

t^WSK1H

Remark n = 0 to 3

<147>

<149>

<148>

SCKn (I/O)

Sln (Input)

<150>

<151>

Input data

<152>

<153>

SOn (Output)

Output data

Remarks 1. Broken lines indicate high impedance.

2. n = 0 to 3

72

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

A/D Converter Characteristics (T^A= –40 to +85°C, V^DD= CV^DD= 3.0 to 3.6 V, HV^DD= 5.0 V ±10%,

V^SS= 0 V, HV^DD– 0.5 V ≤ AV^DD≤ HV^DD, Output Pin Load Capacitance: C^L= 50 pF)

Parameter

Symbol

–

Conditions

MIN.

10

TYP.

MAX.

Unit

bit

Resolution

Overall error

–

±4

±1/2

10

LSB

µs

Quantization error

Conversion time

Sampling time

–

t^CONV

t^SAMP

–

5

833

ns

Zero scale error

Scale error

±2

LSB

V

–

Linearity error

–

±1

Analog input voltage

Analog input resistance

AV^REFinput voltage

AV^REFinput current

AV^DDcurrent

V^IAN

R^AN

AV^REF

AI^REF

AI^DD

–0.3

4.5

AV^REF+ 0.3

2

MΩ

V

AV^REF= AV^DD

5.5

1.6

6

mA

73

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

4.2 Flash Memory Programming Mode

Basic Characteristics (T^A= 10 to 40°C (When Rewriting), T^A= –40 to +85°C (Other Than When Rewriting))

Parameter

Operating frequency

Power supply voltage

Symbol

f^X

Conditions

MIN.

20

TYP.

MAX.

33

Unit

MHz

V

V^DD

3.6

HV^DD

V^PP

5.5

V

V^DDhigh-level detection

0.8V^DD

7.5

V^DD

7.8

1.2V^DD

8.1

V

V^PPH

V^PPhigh-voltage

detection

V

HV^DDsupply current

V^PPsupply current

Number of writes

I^DD

I^PP

50

mA

V^PP= 8.1 V

150

mA

C^WRT

K category^Note

P category^Note

5

Times

10

20

Other than K, P

category^Note

Write time

Erase time

t^WRT

Per 1 byte

20

200

60

µs

t^ERASE

K, P category^Note

s

(Recommendation:

Step erase = 5 s)

Other than K, P

category^Note

20

s

(Recommendation:

Step erase = 0.2 s)

Temperature during write

T^PRG

K, P category^Note

10

40

85

°C

Other than K, P

category^Note

Note The category is indicated by the fifth letter from the left of the lot number.

Caution The I category is applied to engineering samples only. The number of rewrites is not guaranteed

for the I category products.

74

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

Serial Write Operation Characteristics

Parameter

V^DD↑ to V^PP↑ set time

Symbol

Conditions

V^PP= 7.8 V

MIN.

200

TYP.

MAX.

Unit

ns

<201>

<202>

<203>

<204>

<205>

<206>

<207>

<208>

t^DRPSR

t^PSRRF

t^RFOF

t^COUNT

t^CH

V^PP↑ to RESET↑ set time

RESET↑ to V^PPcount start time

Count execution time

1

µs

5T + 500

µs

10

ms

µs

V^PPcounter high-level width

V^PPcounter low-level width

V^PPcounter rise time

1

t^CL

µs

t^R

3

µs

V^PPcounter fall time

t^F

µs

V^DD, HVDD

VDD, HVDD

0 V

<204>

<201>

<203>

<206>

<205>

<207>

VPPH

VPP

HVDD

0 V

<208>

<202>

HVDD

0 V

RESET (Input)

75

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

5. PACKAGE DRAWINGS

144-PIN PLASTIC LQFP (FINE PITCH) (20x20)

A

B

108

109

73

72

detail of lead end

S

C

D

R

Q

144

1

37

36

F

M

G

H

I

J

K

P

S

N

S

L

M

NOTE

Each lead centerline is located within 0.10 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

D

F

22.0±0.2

20.0±0.2

22.0±0.2

1.25

G

1.25

+0.05

0.22

H

−0.04

I

J

0.10

0.5 (T.P.)

1.0±0.2

0.5±0.2

K

L

+0.055

M

0.145

−0.045

N

P

Q

0.10

1.4±0.1

0.125±0.075

+7°

3°

R

S

−3°

1.7 MAX.

S144GJ-50-8EU-3

76

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

144-PIN PLASTIC LQFP (FINE PITCH) (20x20)

A

B

108

109

73

72

detail of lead end

S

C

D

R

Q

144

1

37

36

F

M

G

H

J

I

K

P

S

L

S

N

M

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.08 mm of

its true position (T.P.) at maximum material condition.

A

B

C

D

F

22.0±0.2

20.0±0.2

22.0±0.2

1.25

G

H

1.25

0.22±0.05

I

0.08

J

0.5 (T.P.)

1.0±0.2

0.5±0.2

K

L

+0.03

0.17

M

−0.07

N

P

Q

0.08

1.4

0.10±0.05

+4°

3°

R

S

−3°

1.5±0.1

S144GJ-50-UEN

77

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

6. RECOMMENDED SOLDERING CONDITIONS

These products should be soldered and mounted under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document “Semiconductor Device

Mounting Technology Manual (C10535E)”.

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 6-1. Surface Mounting Type Soldering Conditions

µPD70F3102GJ-33-8EU: 144-pin plastic LQFP (Fine Pitch) (20 × 20)

Soldering Method

Infrared reflow

Soldering Conditions

Recommended Condition Symbol

IR35-103-2

Package peak temperature: 235°C, Time: 30 seconds max. (at

210°C or higher), Count: Twice or less, Exposure limit: 3 days^Note

(after that, prebake at 125°C for 10 hours)

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

–

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution The recommended soldering conditions of the µPD70F3102GJ-33-UEN are yet to be determined.

78

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

[MEMO]

79

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

80

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, pIease contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

•

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.

Benelux Office

Hong Kong

Eindhoven, The Netherlands

Tel: 040-2445845

Tel: 2886-9318

Fax: 2886-9022/9044

Fax: 408-588-6130

800-729-9288

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 01-30-67 58 99

Fax: 0211-65 03 490

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 65-253-8311

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 65-250-3583

Tel: 91-504-2787

Fax: 01908-670-290

Fax: 91-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

NEC Electronics Italiana s.r.l.

Milano, Italy

Tel: 02-66 75 41

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Fax: 02-2719-5951

Fax: 02-66 75 42 99

Tel: 08-63 80 820

NEC do Brasil S.A.

Fax: 08-63 80 388

Electron Devices Division

Rodovia Presidente Dutra, Km 214

07210-902-Guarulhos-SP Brasil

Tel: 55-11-6465-6810

Fax: 55-11-6465-6829

J99.1

81

Preliminary Data Sheet U13844EJ2V0DS00

µPD70F3102-33

Related Documents µPD70F3102A-33 Data Sheet (U13845E)

µPD703100-33, 703100-40, 703101-33, 703102-33 Data Sheet (U13995E)

µPD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Sheet (U14168E)

Reference Materials Electrical Characteristics for Microcomputer (IEI-601)^Note

Note This document number is that of Japanese version.

The related documents in this publication may include preliminary versions. However, preliminary versions

are not marked as such.

The V850E/MS1 is a trademark of NEC Corporation.

• The information contained in this document is being issued in advance of the production cycle for the

device. The parameters for the device may change before final production or NEC Corporation, at its own

discretion, may withdraw the device prior to its production.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M5 98. 8


型号：	UPD70F3102-33
厂家：	NEC
描述：	32-/16-BIT SINGLE-CHIP MICROCONTROLLER 32位/ 16位单芯片微控制器微控制器
文件：	总82页 (文件大小：465K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD70F3102-33 [NEC]

相关型号：

UPD70F3102A

UPD70F3102AF1-33-FAA

UPD70F3102AF1-33-FAA-A

UPD70F3102AGJ-33-8EU

UPD70F3102AGJ-33-8EU

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UPD70F3102AGJ-33-UEN

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UPD70F3102GJ-33-8EU

UPD70F3102GJ-33-8EU-A

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