UPD72107GC-3B9 [NEC]
LAP-B CONTROLLER(Link Access Procedure Balanced mode); LAP -B控制器(链路访问过程平衡模式)型号: | UPD72107GC-3B9 |
厂家: | NEC |
描述: | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
文件: | 总32页 (文件大小:180K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72107
LAP-B CONTROLLER
Link Access Procedure Balanced mode
The µPD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single
chip.
FEATURES
• Memory-based interface
Memory-based command
Memory-based status
• Complied with ITU-T recommended X.25 (LAP-B84
edition)
HDLC frame control
Memory-based transmit/receive data
• MAX.4 Mbps serial transfer rate
• NRZ, NRZI coding
Sequence control
Flow control
• ITU-T recommended X.75 supported
• TTC standard JT-T90 supported
• Optional functions
Option frame
Global address frame
Error check deletion frame
• Powerful test functions
Data loopback function
Loopback test link function
Frame trace function
• Abundant statistical information
• Detailed mode setting function
• Modem control function
• On-chip DMAC (Direct Memory Access Controller)
24-bit address
Byte/word transfer enabled (switch with external pin)
ORDERING INFORMATION
Part Number
µPD72107CW
µPD72107GC-3B9
µPD72107L
Package
64-pin plastic shrink DIP (750 mils)
80-pin plastic QFP (14 x 14 mm)
68-pin plastic QFJ (950 x 950 mils)
The information in this document is subject to change without notice.
Document No. S12962EJ5V0DS00 (5th edition)
Date Published October 1998 N CP(K)
Printed in Japan
1998
©
µPD72107
BLOCK DIAGRAM
D0-D7
A16D8
TxC
TxD
RTS
CTS
-A23D15
A0-A15
IORD
IOWR
MRD
Internal controller
TxFIFO
Transmitter
MWR
UBE
CS
Bus
interface
ASTB
AEN
READY
HLDRQ
HLDAK
CRQ
Internal bus
INT
CLRINT
B/W
CD
Receiver
RxFIFO
PU
DMAC
RxC
RxD
VCC
GND
RESET
CLK
Name
Function
Bus interface
An interface between the µPD72107 and external memory or external host processor
Internal controller
Manages LAP-B protocol including control of the DMAC block, transmitter block, and receiver block
DMAC
Controls the transfer of data on the external memory to the internal controller or transmitter block,
and controls the writing of data in the internal controller or receiver block to the external memory
(Direct Memory
Access Controller)
TxFIFO
A 16-byte buffer for when transmit data is sent from the DMAC to the transmitter block
A 32-byte buffer for when receive data is sent from the receiver block to the DMAC
Converts the contents of TxFIFO into an HDLC frame and transmits it as serial data
Receives HDLC frame and writes internal data to RxFIFO
RxFIFO
Transmitter
Receiver
Internal bus
An 8-bit address bus and 8-bit data bus that connect the internal controller, DMAC, FIFO, serial block,
and bus interface block
2
µPD72107
PIN CONFIGURATION (Top View)
64-pin plastic shrink DIP (750 mils)
µPD72107CW
IC
RxC
RxD
TxC
TxD
CTS
IC
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RTS
2
CD
3
CRQ
AEN
4
5
ASTB
READY
HLDAK
HLDRQ
CLRINT
INT
6
7
RESET
NC
8
9
IC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
B/W
PU
UBE
MWR
MRD
GND
IOWR
IORD
CS
CLK
GND
A0
A1
A2
VCC
A3
A4
D7
A5
D6
A6
D5
A7
D4
A8
D3
A9
D2
A10
A11
A12
A13
A14
A15
A16D8
A17D9
D1
D0
A23D15
A22D14
A21D13
A20D12
A19D11
A18D10
3
µPD72107
80-pin plastic QFP (14 × 14 mm)
µPD72107GC-3B9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
NC
1
60
D1
D0
HLDRQ
HLDAK
READY
ASTB
AEN
NC
2
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
3
A23D15
A22D14
A21D13
NC
4
5
6
7
A20D12
A19D11
A18D10
NC
CRQ
CD
8
9
RTS
NC
10
11
12
13
14
15
16
17
18
19
20
NC
IC
A17D9
A16D8
A15
RxC
RxD
NC
A14
TxC
TxD
CTS
IC
A13
A12
A11
A10
NC
NC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4
µPD72107
68-pin plastic QFJ (950 × 950 mils)
µPD72107L
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
RESET
IC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CLRINT
INT
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
B/W
PU
UBE
MWR
MRD
GND
IOWR
IORD
CS
CLK
GND
GND
A0
A1
A2
VCC
A3
VCC
A4
D7
A5
D6
A6
D5
A7
D4
A8
D3
A9
D2
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
5
µPD72107
1. PINS
1.1 Pin Functions
SDIP
QFP
QFJ
Active
Level
–
Pin Name
I/O
–
Function
Pin No. Pin No. Pin No.
VCC
47
68
70
27
28
74
26
50
51
15
16
55
14
+5 V power supply
Ground (0 V)
GND
14
51
–
–
Note that there is more than one ground pin.
CLK
13
8
I
I
–
L
System clock input
(Clock)
RESET
(Reset)
Input clock of 1 MHz to 8.2 MHz.
22
10
Initializes the internal µPD72107. Active width of
more than 7 CLK clock cycles is required (clock
input is required).
After reset, this pin becomes a bus slave.
Pull up to high level when using in normal operation.
PU
12
48
25
71
13
52
I
I
–
L
(Pull Up)
CS
When bus master
(Chip Select)
Set to disable.
When bus slave
Read/write operation from the host processor at low
level is enabled.
MRD
52
53
75
76
56
57
O
L
L
When bus master
(Memory Read)
3-state
Reads the data of the external memory at low level.
When bus slave
High impedance
MWR
O
When bus master
(Memory Write)
3-state
Writes the data to the external memory at low level.
When bus slave
High impedance
IORD
49
50
60
72
73
5
53
54
64
I
I
L
L
This pin is used when the external host processor
reads the contents of the internal registers of the
µPD72107.
(I/O Read)
IOWR
This pin is used when the external host processor
writes the data to the internal registers of the
µPD72107.
(I/O Write)
ASTB
O
H
This pin is used to latch the address output from
the µPD72107 externally.
(Address Strobe)
6
µPD72107
SDIP
QFP
QFJ
Active
Level
–
Pin Name
I/O
–
Function
Pin No. Pin No. Pin No.
NC
9
1, 7,
11, 15,
20, 21,
29, 40,
41, 50,
51, 55,
61, 69,
80
1
5
Use this pin open.
(No Connection)
35
IC
1
7
12
2
9
–
–
Do not connect anything to this pin.
(Internally
Connected)
UBE
19
10
54
23
11
58
77
I/O
L/H
When bus master (output)
(Upper Byte
Enable)
3-state
The signal output from this pin changes according
to the input value of the B/W pin.
• Byte transfer mode (B/W = 0)
UBE is always high impedance.
• Word transfer mode (B/W = 1)
Indicates that valid data is either in pins D0 to D7
or pins A16D8 to A23D15 (or both).
UBE
A0
0
D0 to D7 A16D8 to A23D15
0
0
1
1
1
×
0
×
1
×
×
When bus slave (input)
UBE pin becomes input, and indicates that valid
data is either in pins D0 to D7 or pins A16D8 to
A23D15.
UBE
A0
0
D0 to D7 A16D8 to A23D15
0
0
1
1
×
1
×
×
×
0
1
7
µPD72107
SDIP
Pin No. Pin No. Pin No.
11 24 12
QFP
QFJ
Active
Level
L/H
Pin Name
I/O
I
Function
B/W
Specifies the data bus that accesses the external
memory when bus master.
(Byte/Word)
B/W = 0
B/W = 1
Byte units (8 bits)
Word units (16 bits)
After power-on, fix the status of the B/W pin.
In the case of word access, the lower data bus is the
contents data of even addresses.
READY
(Ready)
59
4
63
I
H
An input signal that is used to extend the MRD and
MWR signal widths output by the µPD72107 to
adapt to low-speed memory. When the READY
signal is low level, the MRD and MWR signals
maintain active low. Do not change the READY
signal at any time other than the specified setup/
hold time.
HLDRQ
57
58
2
61
62
O
H
H
H
–
A hold request signal to the external host processor.
WhenaDMAoperationisperformedintheµPD72107,
this signal is activated to switch from bus slave to
bus master.
(Hold Request)
HLDAK
3
6
I
A hold acknowledge signal from the external host
processor. When the µPD72107 detects that this
signal is active, the bus slave switches to bus
master, and a DMA operation is started.
When bus master, this signal enables the latched
higher addresses and outputs them to system ad-
dress bus. This signal is also used for disabling
other system bus drivers.
(Hold Acknowledge)
AEN
61
65
O
(Address Enable)
A0, A1
15, 16
30, 31
17, 18
I/O
Bidirectional 3-state address lines.
3-state
When bus master (output)
Indicatethelower2-bitaddressesofmemoryaccess.
When bus slave (input)
Input addresses when the external host processor
I/O accesses the µPD72107.
A2 to A15
17 to 30 32 to 47 19 to 32
O
–
When bus master
(except
40, 41)
3-state
Output bit 2 to bit 15 of memory access addresses.
When bus slave
Become high impedance.
8
µPD72107
SDIP
Pin No. Pin No. Pin No.
A16D8 to A23D15 31 to 38 48 to 58 33 to 41
QFP
QFJ
Active
Level
–
Pin Name
I/O
I/O
Function
Bidirectional 3-state address/data buses. Multiplex
pins of the higher 16 bits to 23 bits of addresses
and the higher 8 bits to 15 bits of data.
Bidirectional 3-state data buses.
(except 50,(except 35) 3-state
51, 55)
D0 to D7
39 to 46 59 to 67 42 to 49
(except 61)
I/O
–
3-state
When bus master
Whenwritingtoexternalmemory, thesepinsbecome
input if reading at output.
When bus slave
Usually, these pins become high impedance. When
theexternalhostprocessorreadsI/OoftheµPD72107,
the internal register data is output.
CRQ
62
8
66
I
H
A signal requesting command execution to the
µPD72107 by the external host processor. The
µPD72107 starts fetching commands from on the
external memory at the rising edge of this signal.
An interrupt signal from the µPD72107 to the
external host processor.
(Command
Request)
INT
55
56
78
79
59
60
O
I
H
H
(Interrupt)
CLRINT
A signal inactivating the INT signal being output by
theµPD72107. TheµPD72107generatestheCLRINT
signal in the LSI internal circuit at the rising edge of
this signal, and forcibly makes the INT output signal
low.
(Clear Interrupt)
CTS
6
18
8
I
–
A general-purpose input pin.
(Clear To Send)
TheµPD72107reportsthe“CTSpinchangedetection
status” to the external host processor when the
input level of this pin is changed in the general-
purpose input/output pin support (setting RSSL to
1 by the “system initialization command”). The
change of input level is recognized only when the
same level is sampled twice in succession after
sampling in 8-ms cycles and detecting the change.
Moreover, when the external host processor issues
a “general-purpose input/output pin read command”
to the µPD72107, the µPD72107 reports the pin
information of this pin to the external host processor
bya“general-purposeinput/outputpinreadresponse
status”.
The change can be detected even in the clock input
stop status of TxC and RxC.
9
µPD72107
SDIP
Pin No. Pin No. Pin No.
64 10 68
QFP
QFJ
Active
Level
–
Pin Name
RTS
I/O
O
Function
A general-purpose output pin.
(Request To Send)
The output value of this pin can be changed by
issuingan“RTSpinwritecommand”fromtheexternal
host processor to the µPD72107. Moreover, when
theexternalhostprocessorissuesa“general-purpose
input/output pin read command” to the µPD72107,
the µPD72107 reports the pin information of this pin
to the external host processor by a “general-purpose
input/output pin read response status”.
CD
63
9
67
I
–
A general-purpose input pin.
(Carrier Detect)
The µPD72107 reports the “CD pin change detection
status” to the external host processor when the
input level of this pin is changed in the general-
purpose input/output pin support (setting RSSL to
1 by the “system initialization command”). The
change of input level is recognized only when the
same level is sampled twice in succession after
sampling in 8-ms cycles and detecting the change.
Moreover, when the external host processor issues
a “general-purpose input/output pin read command”
to the µPD72107, the µPD72107 reports the pin
information of this pin to the external host processor
bya“general-purposeinput/outputpinreadresponse
status”.
The change can be detected even in the clock input
stop status of TxC and RxC.
TxD
5
4
17
16
7
6
O
–
–
A serial transmit data output pin.
(Transmit Data)
TxC
I/O
When CLK is set to 01 or 10 by “operation mode
setting LCW” (output)
(Transmit Clock)
3-state
Outputs a clock that divides by 16 the input signal
of the RxC pin or CLK pin made by the µPD72107.
Caution TxC becomes input because CLK = 00
is the default after reset. It becomes
output after setting CLK to 01 or 10 by
“operation mode setting LCW”.
When CLK is set to 00 by “operation mode setting
LCW” (input)
Inputs transmit clock externally.
Remark LCW: abbreviation for Link Command Word
10
µPD72107
SDIP
QFP
QFJ
Active
Level
–
Pin Name
RxD
I/O
I
Function
Pin No. Pin No. Pin No.
3
2
14
13
4
3
A serial receive data input pin.
(Receive Data)
RxC
I
–
When CLK is set to 01 or 10 by “operation mode
setting LCW”
(Receive Clock)
Sixteen times the clock input of the transmit/receive
clock for the on-chip DPLL of the µPD72107
When CLK is set to 00 by “operation mode setting
LCW”
One time the clock input of the receive clock
Remark LCW: abbreviation for Link Command Word
1.2 Pin Status after Reset of µPD72107
The status of the output pins and input/output pins after reset in the µPD72107 is as shown in Table 1-1.
Table 1-1. Pin Status after Reset
Pin Number
During Reset
Pin Name
I/O
64-pin SDIP
80-pin QFP
68-pin QFJ
Note
4
5
16
17
6
7
TxC
TxD
I/O
High impedance
H
O
Note
15, 16
17 to 30
30, 31
17, 18
19 to 32
A0, A1
I/O
High impedance
High impedance
Note
Note
32 to 47
A2 to A15
O
(except 40, 41)
31 to 38
39 to 46
48 to 58
33 to 41
A16D8 to A23D15
D0 to D7
I/O
High impedance
High impedance
(except 50, 51, 55)
(except 35)
Note
59 to 67
42 to 49
I/O
(except 61)
Note
Note
Note
52
53
54
55
57
60
61
64
75
76
77
78
2
56
57
58
59
61
64
65
68
MRD
MWR
UBE
O
O
High impedance
High impedance
I/O
High impedance
INT
O
L
L
HLDRQ
ASTB
AEN
O
O
O
O
5
L
6
L
10
RTS
H
Note 3-state
Remarks 1. The status after reset is released is the same as the status during reset.
2. Input low level to the RESET pin for more than 7 clocks of the system clock.
11
µPD72107
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C)
Parameter
Power supply voltage
Input voltage
Symbol
VDD
VI
Conditions
Ratings
–0.5 to +7.0
Unit
V
–0.5 to VDD + 0.3
–0.5 to VDD + 0.3
–40 to +85
V
Output voltage
VO
V
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–40 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
DC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%)
Parameter
Input voltage, low
Symbol
VILC
VIL
Conditions
MIN.
–0.5
–0.5
+3.3
+2.2
TYP.
MAX.
+0.8
Unit
V
CLK pin
Other pins
+0.8
V
Input voltage, high
VIHC
VIH
CLK and PU pins
Other pins
VDD + 0.3
VDD + 0.3
0.4
V
V
Output voltage, low
Output voltage, high
Power supply current
Input leakage current
Output leakage current
VOL
VOH
IDD
IOL = 2.5 mA
V
IOH = –400 µA
At operation
0.7 × VDD
V
20
50
mA
µA
µA
ILI
0 V ≤ VIN ≤ VDD
0 V ≤ VOUT ≤ VDD
±10
±10
ILO
Capacitance (TA = +25°C, VDD = 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
Input capacitance
CI
fC = 1 MHz
–
–
–
8
8
8
Output capacitance
I/O capacitance
CO
CIO
Unmeasured pins returned to 0 V
15
pF
20
pF
12
µPD72107
AC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%)
When bus master (1)
Parameter
CLK cycle time
Symbol
tCYK
tKKL
Conditions
MIN.
121
50
MAX.
1000
Unit
ns
CLK low-level time
CLK high-level time
CLK rise time
ns
tKKH
tKR
50
ns
1.5 – 3.0 V
3.0 – 1.5 V
10
10
ns
CLK fall time
tKF
ns
Load condition
DUT
CL = 50 pF
CL includes jig capacitance.
Caution If the load capacitance exceeds 50 pF due to the configuration of the circuit, keep the load
capacitance of this device to within 50 pF by inserting a buffer or by some other means.
Remark DUT: device under test
AC test input/output waveform (except clock)
2.4 V
2.2 V
0.8 V
2.2 V
0.8 V
Test points
0.4 V
System clock
tKF
tKR
tKKL
3.0 V
CLK
1.5 V
tKKH
tCYK
13
µPD72107
When bus master (2)
Parameter
Symbol
tDHQH
tDHQL
tSHA
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HLDRQ ↑ delay time (vs. CLK ↓)
HLDRQ ↓ delay time (vs. CLK ↑)
HLDAK setup time (vs. CLK ↑)
HLDAK hold time (vs. CLK ↑)
AEN ↑ delay time (vs. CLK ↓)
AEN ↓ delay time (vs. CLK ↑)
ASTB ↑ delay time (vs. CLK ↑)
ASTB high-level width
100
100
35
20
tHHA
tDAEH
tDAEL
tDSTH
tSTSTH
tDSTL
tDA
100
100
70
tKKH–15
ASTB ↓ delay time (vs. CLK ↓)
100
100
ADR/UBE/MRD/MWR delay time
(vs. CLK ↑)
ADR/UBE/MRD/MWR float time
tFA
70
ns
(vs. CLK ↑)
ADR setup time (vs. ASTB ↓)
ADR hold time (vs. ASTB ↓)
tSAST
tHSTA
tKKH–35
tKKL–20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MRD ↓ delay time (vs. ADR float) tDAR
MRD ↓ delay time (vs. CLK ↑)
MRD low-level width
tDRL
70
70
tRRL2
tDRH
tSDR
tHRD
tDWL
tWWL2
tDWH
tSRY
tHRY
2tCYK–50
MRD ↑ delay time (vs. CLK ↑)
Data setup time (vs. MRD ↑)
Data hold time (vs. MRD ↑)
MWR ↓ delay time (vs. CLK ↑)
MWR low-level width
100
0
70
70
2tCYK–50
MWR ↑ delay time (vs. CLK ↑)
READY setup time (vs. CLK ↑)
READY hold time (vs. CLK ↑)
35
20
14
CLK
tDHQL
tDHQH
HLDRQ
tSHA
tHHA
tHHA
HLDAK
AEN
tDAEH
tDAEL
tDSTL
tDSTH
ASTB
tSTSTH
tDA
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Address
A16D8-A23D15
Output data
tSAST
tHSTA
A0, A1/A2-A15
UBE
Address
tWWL2
MWR
tDWL
tHRY
tHRY
tDWH
READY
tFA
tSRY
tSRY
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Address
Input data
A16D8-A23D15
µ
tDAR
tSDR
tDRH
tFA
tDA
tHRD
MRD
tRRL2
tDRL
µPD72107
When bus slave (1)
Parameter
Symbol
tWWL
Conditions
MIN.
100
0
MAX.
Unit
ns
IOWR low-level width
CS low-level hold time
tHWCS
ns
(vs. IOWR ↑)
ADR/UBE/CS low-level setup time tSAW
0
ns
(vs. IOWR ↓)
ADR/UBE hold time (vs. IOWR ↑)
Data setup time (vs. IOWR ↑)
Data hold time (vs. IOWR ↑)
IORD low-level width
tHWA
tSDW
tHWD
tRRL
tSAR
0
100
0
ns
ns
ns
ns
ns
150
35
ADR/CS low-level setup time
(vs. IORD ↓)
ADR/CS low-level hold time
tHRA
0
ns
(vs. IORD ↑)
Data delay time (vs. IORD ↓)
Data float time (vs. IORD ↑)
RESET low-level width
tDRD
120
100
ns
ns
ns
ns
ns
ns
tFRD
10
tRSTL
tSVDD
tSYWR
tRVWR
7tCYK
1000
2tCYK
200
VDD setup time (vs. RESET ↑)
RESET ↑ –1st • IOWR/IORD
IOWR/IORD recovery time
16
µPD72107
When bus slave
CS
t
SAW
t
WWL
t
HWCS
IOWR
t
HWA
A0-A23
UBE
t
SDW
t
HWD
D0-D15
CS
A0-A23
t
SAR
t
HRA
t
RRL
IORD
t
DRD
t
FRD
Hi-Z
Hi-Z
D0-D15
V
DD
t
SVDD
t
RSTL
RESET
t
SYWR
IORD/IOWR
t
RVWR
IORD
IOWR
t
RVWR
t
RVWR
t
RVWR
17
µPD72107
When bus slave (2)
Parameter
Symbol
Conditions
MIN.
–20
MAX.
Unit
ns
IOWR/IORD high-level setup time
tSWR
(vs. HLDAK ↑)
IOWR/IORD high-level hold time
tHWR
100
ns
(vs. AEN ↓)
HLDAK
tSWR
IOWR/IORD
AEN
tHWR
IOWR/IORD
When bus slave (3)
Parameter
Symbol
tCLCLH
tDIH
Conditions
MIN.
100
MAX.
Unit
ns
CLRINT high-level width
INT ↑ delay time (vs. CLK ↑)
INT ↓ delay time (vs. CLRINT ↑)
CRQ high-level width
100
100
ns
tDIL
ns
tCRCRH
100
ns
CLK
CLRINT
tCLCLH
INT
tDIH
tDIL
CRQ
tCRCRH
18
µPD72107
Serial block (1)
Parameter
Symbol
tCYS
Conditions
MIN.
250
110
110
MAX.
DC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TxC/RxC cycle time
When on-chip DPLL is not used
TxC/RxC low-level time
TxC/RxC high-level time
TxC/RxC rise time
tSSL
tSSH
tSR
20
12
TxC/RxC fall time
tSF
TxD delay time (vs. TxC ↓)
RxD setup time (vs. RxC ↑)
RxD hold time (vs. RxC ↑)
tDTXD
tSRXD
tHRXD
100
50
70
Serial clock (when on-chip DPLL is not used)
tSF
tSR
tSSL
2.2 V
TxC/RxC
0.8 V
tSSH
tCYS
TxC (input)
TxD
tDTXD
tDTXD
RxC
tSRXD
tHRXD
RxD
19
µPD72107
Serial block (2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
RxC cycle time
tCYR
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
30.3
125
1000
RxC low-level time
RxC high-level time
RxC rise time
tSSRL
tSSRH
tSRR
tSRF
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
10
50
ns
ns
ns
ns
ns
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
10
50
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
5
10
RxC fall time
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
5
10
Transmit/receive data cycle
tCYD
When on-chip DPLL is used (source clock = RxC)
When on-chip DPLL is used (source clock = CLK)
500
2000
16000
50
TxC low-level time
tTCTCL
tTCTCH
tDTCTD
tHTCTD
When on-chip DPLL is used
0.5tCYD–25
0.5tCYD–25
ns
ns
ns
ns
TxC high-level time
TxD delay time (vs. TxC ↓)
TxD hold time (vs. TxC ↑)
0.5tCYD–25
Serial clock (when on-chip DPLL is used)
tCYR
tSSRL
tSSRH
tSRR
tSRF
RxC
TxC
TxD
tTCTCL
tTCTCH
tHTCTD
tDTCTD
tCYD
20
µPD72107
Serial block (3)
Parameter
Symbol
tDRTH
tDRTL
tSCD
Conditions
MIN.
MAX.
100
Unit
ns
RTS ↑ delay time (vs. CLK ↑)
RTS ↓ delay time (vs. CLK ↑)
CD setup time (vs. CLK ↑)
CD hold time (vs. CLK ↑)
CTS setup time (vs. CLK ↑)
CTS hold time (vs. CLK ↑)
100
ns
35
20
35
20
ns
tHCD
ns
tSCT
ns
tHCT
ns
CLK
RTS
CD
tDRTL
tDRTH
tHCD
tSCD
tHCT
CTS
tSCT
21
µPD72107
3. APPLICATION CIRCUIT EXAMPLE
(1) Connection with SIFC (µPD98201)
µ
µ
PD98201
PD72107
TxD
RxD
BINA
BOUT1
BCLK
LAP-B
SIFC
TxC
RxC
22
µ
PD72107 System Configuration Example (Local Memory Type)
Local memory 64 Kbytes
RD
WR
CS
UBE
A0-A15
D0-D15
µ
Host processor
PD72107
MEMR
MEMW
IOR
MRD
MWR
IORD
IOWR
CS
A
B
µ
PD71086
OE
IOW
Decoder
AB0-AB7
A
B
PD71086
OE
A0-A15
A0-A15
D0-D7
µ
µ
µ
AB8-AB15
AB16-AB19
BHE
A
B
PD71086
OE
A16D8-A23D15
UBE
DB0-DB15
A
B
PD71086
OE
D0-D15
AEN
INT
Local
bus request
INT
Access
contention
resolution
circuit
HLDRQ
µ
HLDAK
WAIT
µ
µ
PD72107 System Configuration Example (Main Memory Sharing Type)
Host processor
µ
PD72107
INT
INTP
CS
µ
PD70116
PD71059
A0
INT
INT
IORD
IOWR
CS
INTAK
INTAK
RD WR D0-D7
MRD
RD
WR
MWR
HLDRQ
HLDAK
AEN
HLDRQ
HLDAK
ASTB
ASTB
D0-D7
Decoder
A16-A19
STB OE
OE STB
µ
PD71082
A16D8-A23D15
A16-A19
AD8-AD15
µ
PD71082×3
A0-A15
UBE
A0-A15
AD0-AD7
UBE
BUF R/W
BUFEN
D8-D15
µ
PD71086×2
D0-D7
T
OE
RD WR
CS UBE D0-D7 D8-D15
Memory
µ
µPD72107
5. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
32
1
A
K
L
J
I
C
B
F
D
M
R
M
N
H
G
NOTES
ITEM MILLIMETERS
INCHES
+0.028
1. Controlling dimension
millimeter.
+0.68
A
58.0
2.283
–0.008
–0.20
2. Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
B
C
1.78 MAX.
0.070 MAX.
0.070 (T.P.)
1.778 (T.P.)
3. Item "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
0.9 MIN.
3.2±0.3
0.035 MIN.
0.126±0.012
0.020 MIN.
0.51 MIN.
+0.011
0.159
+0.26
4.05
I
–0.008
–0.20
J
5.08 MAX.
0.200 MAX.
0.750 (T.P.)
K
19.05 (T.P.)
+0.009
0.669
L
17.0±0.2
–0.008
+0.004
0.010
+0.10
0.25
M
–0.003
–0.05
N
R
0.17
0.007
0 to 15°
0 to 15°
P64C-70-750A,C-3
25
µPD72107
80 PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C D
R
Q
21
20
80
1
F
P
J
G
M
H
I
K
M
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
17.2±0.4
14.0±0.2
0.677±0.016
+0.009
0.551
–0.008
+0.009
0.551
C
14.0±0.2
–0.008
D
F
17.2±0.4
0.825
0.677±0.016
0.032
G
0.825
0.032
+0.004
0.012
H
0.30±0.10
–0.005
I
0.13
0.005
J
K
0.65 (T.P.)
1.6±0.2
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.8±0.2
–0.008
+0.004
0.006
+0.10
0.15
M
–0.003
–0.05
N
P
0.10
0.004
+0.005
0.106
2.7±0.1
–0.004
Q
R
S
0.1±0.1
5°±5°
0.004±0.004
5°±5°
3.0 MAX.
0.119 MAX.
S80GC-65-3B9-5
26
µPD72107
68 PIN PLASTIC QFJ (950 x 950 mil)
A
B
68
1
C D
G
H
J
F
E
S
U
T
ITEM MILLIMETERS
INCHES
K
Q
S
A
B
25.2±0.2
0.992±0.008
M
M
N
+0.004
0.953
24.20±0.1
−0.005
P
I
+0.004
0.953
C
24.20±0.1
−0.005
D
E
25.2±0.2
0.992±0.008
NOTES
1. Controlling dimension
+0.007
0.076
1.94±0.15
−0.006
millimeter.
F
0.6
0.024
+0.009
0.173
2. Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
G
4.4±0.2
−0.008
+0.009
H
2.8±0.2
0.110
−0.008
I
0.9 MIN.
0.035 MIN.
+0.004
0.134
J
3.4±0.1
−0.005
K
1.27 (T.P.)
0.050 (T.P.)
+0.003
M
0.42±0.08
0.017
−0.004
N
P
0.12
0.005
+0.009
23.12±0.2
0.910
−0.008
0.006
Q
T
0.15
R 0.8
R 0.031
+0.08
0.22
+0.003
0.009
U
−0.07
−0.004
P68L-50A1-3
27
µPD72107
6. RECOMMENDED SOLDERING CONDITIONS
The µPD72107 should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
Forsolderingmethodsandconditionsotherthanthoserecommendedbelow, contactyourNECsalesrepresentative.
Surface mounting type
• µPD72107GC-3B9: 80-pin plastic QFP (14 × 14 mm)
Soldering Method
Infrared reflow
Soldering Conditions
Recommended Condition Symbol
IR35-00-3
Package peak temperature: 235°C, Time: 30 sec. Max.
(at 210°C or higher), Count: three times or less
VPS
Package peak temperature: 215°C, Time: 40 sec. Max.
(at 200°C or higher), Count: three times or less
VP15-00-3
WS60-00-1
Wave soldering
Solder bath temperature: 260°C, Time: 10 sec. Max.,
Count: one time, Preheating temperature: 120°C Max.
(package surface temperature)
Partial heating
Pin temperature: 300°C Max., Duration: 3 sec. Max. (per pin row)
–
Caution Do not use different soldering methods together (except for partial heating).
• µPD72107L: 68-pin plastic QFJ (950 × 950 mils)
Soldering Method
VPS
Soldering Conditions
Recommended Condition Symbol
VP15-00-1
Package peak temperature: 215°C, Time: 40 sec. Max.
(at 200°C or higher), Count: one time
Partial heating
Pin temperature: 300°C Max., Duration: 3 sec. Max. (per pin row)
–
Insertion type
• µPD72107CW: 64-pin plastic shrink DIP (750 mils)
Soldering Method
Soldering Conditions
Wave soldering (pin only)
Partial heating
Solder bath temperature: 260°C Max., Time: 10 sec. Max.
Pin temperature: 300°C Max., Duration: 3 sec. Max. (per a pin)
Caution Wave soldering must be applied only to pins. Be sure to avoid jet soldering the package body.
28
µPD72107
[MEMO]
29
µPD72107
[MEMO]
30
µPD72107
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
31
µPD72107
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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