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UPD75216 [NEC]

4-BIT SINGLE-CHIP MICROCOMPUTER; 4位单片机
UPD75216
型号： UPD75216
厂家： NEC    NEC
描述：

4-BIT SINGLE-CHIP MICROCOMPUTER
4位单片机

计算机
文件： 总72页 (文件大小：521K)
中文：  中文翻译
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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD75216A  
4-BIT SINGLE-CHIP MICROCOMPUTER  
DESCRIPTION  
The µPD75216A is a microcomputer with a CPU capable of 1-, 4-, and 8-bit data processing, ROM, RAM, I/O ports,  
a fluorescent display tube controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM,  
a serial interface and a vectored interrupt function integrated on a single-chip.  
The µPD75216A is a product with the ROM capacity and the number of display segments extended for the  
µPD75208.  
It uses the VCR, ECR and CD fluorescent display tubes as display devices and is most suitable for applications  
requiring the timer/watch function and high-speed interrupt servicing. It can help to provide the unit with many  
functions and to decrease performance costs.  
Functions are described in detail in the following User’s Manual. Be sure to read when carrying out design work.  
µPD75216A User’s Manual: IEM-988  
FEATURES  
• Architecture equal to that of an 8-bit microcomputer  
• High-speed operation : Minimum instruction execution time : 0.95 µs (when operated at 4.19 MHz)  
• Instruction execution time variable function realizing a wide range of operating voltages  
• On-chip large-capacity program memory : 16K bytes  
• Watch operation with an ultra low current consumption : 5µA TYP. (at the 3 V operation)  
• On-chip programmable fluorescent display tube controller/driver  
• Timer function : 4 ch  
• 14-bit PWM output capability with the voltage synthesizer type electronic tuner  
• Buzzer output capability  
• Interrupt function with importance attached to applications  
• For power-off detection  
• For remote controlled reception  
• Product with an on-chip PROM : µPD75P216A, µPD75P218 (on-chip EPROM : WQFN package)  
APPLICATION FIELD  
VCR, CD player, ECR, etc.  
The information in this document is subject to change without notice.  
Document No. IC-1999C  
(O. D. No. IC-7177D)  
Date Published February 1994 P  
Printed in Japan  
The mark ★ shows major revised points.  
© NEC Corporation 1990  
µPD75216A  
ORDERING INFORMATION  
Ordering Code  
Package  
Quality Grade  
µPD75216ACW-×××  
64-pin plastic shrink DIP (750 mil)  
Standard  
Standard  
µPD75216AGF-×××-3BE  
64-pin plastic QFP (14 × 20 mm)  
Remarks ××× is a ROM code number.  
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by  
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.  
2
µPD75216A  
LIST OF FUNCTIONS  
Item  
Function  
Instruction execution time  
• 0.95, 1.91, 15.3 µs (Main system clock : 4.19 MHz operation)  
• 122 µs (Subsystem clock : 32.768 kHz operation)  
On-chip memory  
General register  
ROM  
RAM  
16256 × 8 bits  
512 × 4 bits  
• 4-bit manipulation : 8 × 4 banks  
• 8-bit manipulation : 4 × 4 banks  
Input/output port  
®
33  
8
CMOS input pin  
FIP dual-function pin  
included  
20 CMOS input/output pins • Direct LED drive capability : 8  
On-chip pull-down resistor by mask option capability : 4  
•
FIP dedicated pin  
excluded  
1
4
CMOS output pin  
PWM/pulse output  
P-ch open-drain,  
high-voltage,  
• LED drive capability  
•
On-chip pull-down resistor by mask option capability  
high-current output pin  
FIP controller/driver  
• No. of segments : 9 to 16 segments  
• No. of digits : 9 to 16 digits  
• Dimmer function : 8 levels  
• On-chip pull-down resistor by mask option capability  
• Key scan interrupt generation  
Timer  
4 channels  
• Timer/pulse generator : 14-bit PWM output enabled  
• Watch timer  
: Buzzer output enabled  
• Timer/event counter  
• Basic interval timer  
: Watchdog timer application capability  
Serial interface  
• MSB start/LSB start switchable  
• Serial bus configuration capability  
Vectored interrupt  
Test input  
External : 3, Internal : 5  
External : 1, Internal : 1  
System clock oscillator  
• Ceramic/crystal oscillator for main system clock oscillation : 4.194304 MHz standard  
• Crystal oscillator for subsystem clock oscillation : 32.768 kHz standard  
Standby function  
Mask option  
STOP/HALT mode  
• Power-on reset, power-on flag  
• High withstand voltage port : Pull-down resistor or open-drain output  
• Port 6 : Pull-down resistor  
Operating temperature range  
Operating voltage  
Package  
–40 to +85 °C  
2.7 to 6.0 V (standby data hold : 2.0 to 6.0 V)  
• 64-pin plastic shrink DIP (750 mil)  
• 64-pin plastic QFP (14 × 20 mm)  
3
µPD75216A  
CONTENTS  
1. PIN CONFIGURATION (TOP VIEW) ......................................................................................................... 6  
2. BLOCK DIAGRAM ...................................................................................................................................... 8  
3. PIN FUNCTIONS ........................................................................................................................................ 9  
3.1 PORT PINS ............................................................................................................................................................. 9  
3.2 NON-PORT PINS .................................................................................................................................................. 10  
3.3 PIN INPUT/OUTPUT CIRCUIT LIST.................................................................................................................... 11  
3.4 UNUSED PINS TREATMENT .............................................................................................................................. 12  
3.5 P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS ......................................................................... 13  
3.6 XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS ..................................................................................... 13  
4. MEMORY CONFIGURATION ................................................................................................................... 14  
5. PERIPHERAL HARDWARE FUNCTIONS................................................................................................. 17  
5.1 PORTS.................................................................................................................................................................... 17  
5.2 CLOCK GENERATOR............................................................................................................................................ 18  
5.3 BASIC INTERVAL TIMER ..................................................................................................................................... 19  
5.4 WATCH TIMER...................................................................................................................................................... 20  
5.5 TIMER/EVENT COUNTER ................................................................................................................................... 21  
5.6 TIMER/PULSE GENERATOR ............................................................................................................................... 22  
5.7 SERIAL INTERFACE ............................................................................................................................................. 23  
5.8 FIP CONTROLLER /DRIVER ................................................................................................................................ 25  
5.9 POWER-ON FLAG (MASK OPTION) ................................................................................................................... 27  
6. INTERRUPT FUNCTIONS......................................................................................................................... 28  
7. STANDBY FUNCTIONS............................................................................................................................ 30  
8. RESET FUNCTIONS.................................................................................................................................. 31  
9. INSTRUCTION SET................................................................................................................................... 34  
10. MASK OPTION SELECTION .................................................................................................................... 43  
11. APPLICATION BLOCK DIAGRAM............................................................................................................ 44  
11.1 VCR TIMER TUNER............................................................................................................................................. 44  
11.2 CD PLAYER .......................................................................................................................................................... 45  
11.3 ECR ....................................................................................................................................................................... 45  
12. ELECTRICAL SPECIFICATIONS ............................................................................................................... 46  
13. CHARACTERISTIC CURVES .................................................................................................................... 59  
14. PACKAGE INFORMATION ....................................................................................................................... 63  
4
µPD75216A  
15. RECOMMENDED SOLDERING CONDITIONS ........................................................................................ 66  
APPENDIX A. LIST OF µPD75216A SERIES PRODUCT FUNCTIONS ........................................................67  
APPENDIX B. DEVELOPMENT TOOLS ......................................................................................................... 69  
APPENDIX C. RELATED DOCUMENTS......................................................................................................... 70  
5
µPD75216A  
1. PIN CONFIGURATION (TOP VIEW)  
S3  
S2  
S1  
1
2
3
4
5
6
7
8
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
V
DD  
S4  
S5  
S6  
S7  
S8  
S9  
S0  
P00/INT4  
P01/SCK  
P02/SO  
P03/SI  
P10/INT0  
P11/INT1  
P12/INT2  
P13/TI0  
P20  
V
V
PRE  
9
LOAD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
T15/S10  
T14/S11  
T13/S12/PH0  
T12/S13/PH1  
T11/S14/PH2  
T10/S15/PH3  
T9  
T8  
T7  
T6  
T5  
T4  
T3  
µ
P21  
P22  
P23/BUZ  
P30  
P31  
P32  
P33  
P60  
P61  
P62  
23  
42  
T2  
P63  
P40  
P41  
P42  
P43  
PPO  
X1  
24  
25  
26  
27  
28  
29  
30  
31  
41  
40  
39  
38  
37  
36  
35  
34  
T1  
T0  
RESET  
P53  
P52  
P51  
P50  
XT2  
X2  
V
SS  
32  
33  
XT1  
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33  
P41  
P42  
P43  
PPO  
X1  
52  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
P01/SCK  
P00/INT4  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
S0  
S1  
S2  
S3  
X2  
V
SS  
V
DD  
µPD75216AGF-×××-3BE  
XT1  
XT2  
P50  
P51  
P52  
P53  
S4  
S5  
S6  
S7  
S8  
S9  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19  
6
µPD75216A  
PIN NAME  
P00-P03 : Port 0  
P10-P13 : Port 1  
P20-P23 : Port 2  
P30-P33 : Port 3  
P40-P43 : Port 4  
P50-P53 : Port 5  
P60-P63 : Port 6  
PH0-PH3 : Port H  
SCK  
SO  
SI  
: Serial Clock  
: Serial Output  
: Serial Input  
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4  
INT2  
: External Test Input 2  
TI0  
: Timer Input 0  
X1, X2  
XT1, XT2  
RESET  
VLOAD, VPRE  
: Main System Clock Oscillation 1, 2  
: Subsystem Clock Oscillation 1, 2  
: Reset Input  
T0-T15  
S0-S15  
PPO  
: Digit Output 0-15  
: Segment Output 0-15  
: Pulse Output  
: FIP Driver Power Supply Pin  
BUZ  
: Fixed Frequency Output  
7
PORT0  
PORT1  
4
4
P00–P03  
P10–P13  
BASIC  
INTERVAL  
TIMER  
CY  
SP(8)  
PROGRAM  
COUNTER(14)  
ALU  
INTBT  
PORT2  
PORT3  
PORT4  
PORT5  
PORT6  
4
4
4
4
4
P20–P23  
P30–P33  
P40–P43  
P50–P53  
P60–P63  
TI0/P13  
TIMER/EVENT  
COUNTER  
#0  
BANK  
INTT0  
TIMER/PULSE  
GENERATOR  
GENERAL REG.  
PPO  
ROM  
PROGRAM  
MEMORY  
INTTPG  
DECODE  
AND  
CONTROL  
SI/P03  
SO/P02  
SCK/P01  
RAM  
DATA MEMORY  
512 × 4 BITS  
16256 × 8 BITS  
SERIAL  
INTERFACE  
10  
T0–T9  
INTSIO  
T10/S15/PH3–  
T13/S12/PH0  
4
2
INT0/P10  
INT1/P11  
INT2/P12  
FIP  
T14/S11,T15/  
S10  
CONTROLLER/  
DRIVER  
INTERRUPT  
CONTROL  
S0–S9  
10  
INTW  
X
f/2N  
INT4/P00  
V
V
PRE  
SYSTEM CLOCK  
GENERATOR  
LOAD  
CPU CLOCK  
WATCH  
TIMER  
CLOCK  
DIVIDER  
STAND BY  
CONTROL  
Φ
SUB  
MAIN  
INTKS  
µ
PORTH  
4
PH0–PH3  
BUZ/P23  
XT1 XT2 X1  
X2  
DD V VSS RESET  
µPD75216A  
3. PIN FUNCTIONS  
3.1 PORT PINS  
Input / Output  
Dual-  
8-Bit  
I/O  
Pin Name  
I/O  
Function  
4-bit input port (PORT0).  
After Reset  
Input  
Circuit Type  
*
Function Pin  
×
P00  
P01  
Input  
Input/output  
Input/output  
Input  
INT4  
SCK  
SO  
B
F
P02  
G
B
B
P03  
SI  
P10  
INT0  
INT1  
INT2  
TI0  
Input  
Input  
Input  
Noise elimination function available  
Noise elimination function available  
P11  
P12  
4-bit input port (PORT1).  
P13  
4-bit input/output port (PORT2).  
P20  
Input/  
–––  
×
E
output  
P21  
–––  
P22  
–––  
P23  
BUZ  
–––  
Input/  
Programmable 4-bit input/ output port (PORT3).  
Input/output specifiable in 1-bit units.  
Input  
Input  
Input  
Input  
P30 to P33  
E
E
E
V
output  
●
×
Input/  
P40 to P43  
P50 to P53  
P60 to P63  
–––  
–––  
–––  
4-bit input/output port (PORT4).  
LED direct drive capability.  
output  
Input/  
4-bit input/output port (PORT5).  
LED direct drive capability.  
output  
Programmable 4-bit input/output port (PORT6).  
Input/output specifiable in bit-wise.  
Input/  
output  
On-chip pull-down resistor available (mask  
option). Suitable for key input.  
×
4-bit P-ch open-drain, high-voltage, high-current  
output port (PORTH).  
I
PH0  
PH1  
PH2  
PH3  
Output  
T13/S12  
T12/S13  
T11/S14  
T10/S15  
Low level  
(with an on-  
chip pull-  
down resistor)  
or high  
impedance.  
LED direct drive capability. On-chip pull-down  
resistor available (mask option).  
*
Schmitt-triggered inputs are circled.  
9
µPD75216A  
3.2 NON-PORT PINS  
Input / Output  
Dual-  
Function  
After Reset  
Pin Name  
T0 to T9  
I/O  
Circuit Type  
*
Function Pin  
Output  
FIP controller/  
driver output  
pins.  
Low level  
(With an on-  
chip pull-  
down  
resistor) or  
high  
impedance  
(without a  
pull-down  
resistor)  
–––  
Digit output high-voltage high-current  
output.  
I
T10/S15 to  
T13/S12  
Digit/segment output dual-function  
high-voltage high-current output.  
Extra pins can be used as PORTH.  
PH3 to PH0  
Pull-down  
resistor can be  
incorporated in  
bit-wise (mask  
option).  
T14/S11,  
T15/S10  
Digit/segment output dual-function  
high-voltage high-current output.  
Static output also possible.  
–––  
Segment output high voltage output.  
Static output also possible.  
S9  
Segment high-voltage output.  
S0 to S8  
PPO  
Output  
Input  
–––  
Timer/pulse generator pulse output.  
High  
D
impedance  
External event pulse input for timer/event counter.  
Serial clock input/output.  
TI0  
SCK  
SO  
P13  
P01  
P02  
P03  
P00  
B
F
Input  
Input  
Input  
Input/output  
Input/output  
Serial data input pin or serial data input/output.  
Serial data input or normal input.  
G
SI  
Input  
Input  
B
B
INT4  
Edge-detected vectored interrupt input (rising and falling  
edge detection).  
Input  
Edge-detected vectored interrupt input with noise  
INT0  
P10  
B
elimination function (detection edge selection possible).  
INT1  
INT2  
BUZ  
P11  
P12  
P23  
Input  
Edge-detected testable input (rising edge detection).  
B
E
Input  
Input/output  
Fixed frequency output (for buzzer or system clock  
trimming).  
Input  
X1, X2  
–––  
Crystal/ceramic connect pin for main system clock  
oscillation.  
External clock input to X1 and its inverted clock input to  
X2.  
Crystal connect pin for subsystem clock oscillation.  
External clock input to XT1 and XT2 open.  
XT1  
Input  
–––  
–––  
XT2  
System reset input (low level active).  
FIP controller/driver output buffer power supply.  
FIP controller/driver pull-down resistor connect pin.  
Positive power supply.  
Input  
–––  
–––  
–––  
–––  
–––  
RESET  
VPRE  
B
I
I
VLOAD  
VDD  
VSS  
GND potential.  
*
Schmitt-triggered inputs are circled.  
10  
µPD75216A  
3.3 PIN INPUT/OUTPUT CIRCUIT LIST  
TYPE A  
TYPE F  
data  
VDD  
IN/OUT  
Type D  
Type B  
output  
disable  
P-ch  
IN  
N-ch  
Input/Output Circuit Consisting of Type D Push-Pull Output  
and Type B Schmitt-Triggered Input  
CMOS-Specified Input Buffer  
TYPE B  
TYPE G  
V
DD  
P-ch output  
disable  
P-ch  
data  
IN/OUT  
IN  
N-ch  
Type B  
Schmitt-Triggered Input Having Hysteresis Characteristics  
TYPE D  
Input/Output Circuit Capable of Switching between Push-Pull  
Output and N-ch Open-Drain Output (with P-ch OFF).  
TYPE V  
VDD  
data  
data  
IN/OUT  
P-ch  
Type D  
output  
disable  
OUT  
output  
disable  
N-ch  
Type A  
Pull-down  
Resistor  
Push-Pull Output which can be Set to Output High Impedance  
(with Both P-ch and N-ch Set to OFF)  
(Mask Option)  
TYPE E  
TYPE I  
V
DD  
V
DD  
data  
IN/OUT  
Type D  
output  
disable  
data  
P-ch  
P-ch  
OUT  
Pull-down Resistor  
(Mask Option)  
N-ch  
Type A  
V
LOAD  
V
PRE  
Input/Output Circuit Consisting of Type D Push-Pull Output  
and Type A Input Buffer  
11  
µPD75216A  
3.4 UNUSED PINS TREATMENT  
Pin  
P00/INT4  
Recommended Connection  
Connect to VSS  
P01/SCK  
Connect to VSS or VDD  
P02/SO  
P03/SI  
P10/INT0 to P12/INT2  
P13/TI0  
Connect to VSS  
P20 to P22  
P23/BUZ  
Input state : Connect to VSS or VDD  
Ouput state : Leave open  
P30 to P33  
P40 to P43  
P50 to P53  
P60 to P63  
PPO  
Leave open  
S0 to S9  
T15/S10 to T14/S11  
T0 to T9  
T10/S15/PH3 to T13/S12/PH0  
XT1  
Connect to VSS or VDD  
Leave open  
XT2  
RESET when there is an on-  
chip power-on reset circuit  
VLOAD when there is no on-  
chip load resistor  
Connect to VDD  
Connect to VSS or VDD  
12  
µPD75216A  
3.5 P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS  
P00/INT4 and RESET pins have the function (especially for IC test) to test µPD75216A internal operations in  
addition to the functions described in sections 3.1 and 3.2.  
The test mode is set when a voltage larger than VDD is applied to one of these pins. If noise larger than VDD is  
applied in normal operation, the test mode may be set thereby adversely affecting normal operation.  
Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins,  
if cables for the related signals are routed in parallel, wiring noise larger than VDD may be applied to the P00/INT4  
and RESET pins causing errors.  
Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure  
against noise using the following external components.  
•
Connect diode with small VF (0.3 V or less) between  
VDD and P00/INT4, RESET  
•
Connect a capacitor between the pins and VDD.  
VDD  
VDD  
VDD  
VDD  
P00/INT4, RESET  
P00/INT4, RESET  
3.6 XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS  
When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source  
clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched  
between high and low the minimum number of times (once or less per second).  
If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because  
of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch  
becomes fast).  
If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the  
P50 pin as shown below.  
µPD75216A  
P50  
XT1  
XT2  
0.0068 µF  
32.768 kHz  
13  
µPD75216A  
4. MEMORY CONFIGURATION  
• Program memory (ROM) ................................. 16256 words × 8 bits  
• 0000H to 0001H : Vector table for writing program start address by reset  
• 0002H to 000FH : Vector table for writing program start address by interrupt  
• 0020H to 007FH : Table area to be referred to by GETI instruction  
• Data Memory  
• Data area ....................................................... 512 words × 4 bits (000H to 1FFH)  
• Peripheral hardware area ............................ 128 words × 4 bits (F80H to FFFH)  
14  
µPD75216A  
Fig. 4-1 Program Memory Map  
Address  
7
6
0
0000H  
0002H  
0004H  
0006H  
0008H  
000AH  
000CH  
000EH  
MBE  
Internal Reset Start Address (Most Significant 6 Bits)  
Internal Reset Start Address (Least Significant 8 Bits)  
RBE  
MBE  
MBE  
MBE  
MBE  
MBE  
MBE  
MBE  
RBE INTBT/INT4 Start Address  
(Most Significant 6 Bits)  
(Least Significant 8 Bits)  
(Most Significant 6 Bits)  
(Least Significant 8 Bits)  
(Most Significant 6 Bits)  
(Least Significant 8 Bits)  
(Most Significant 6 Bits)  
(Least Significant 8 Bits)  
(Most Significant 6 Bits)  
(Least Significant 8 Bits)  
(Most Significant 6 Bits)  
(Least Significant 8 Bits)  
(Most Significant 6 Bits)  
(Least Significant 8 Bits)  
CALLF  
!faddr  
Instruction  
Entry Address  
INTBT/INT4 Start Address  
INT0 Start Address  
RBE  
RBE  
INT0 Start Address  
INT1 Start Address  
INT1 Start Address  
RBE INTCSI0 Start Address  
INTCSI0 Start Address  
BRCB  
!caddr  
Instruction  
Branch Address  
INTT0 Start Address  
INTT0 Start Address  
INTTPG Start Address  
INTTPG Start Address  
INTKS Start Address  
INTKS Start Address  
RBE  
RBE  
RBE  
CALL !addr  
Instruction  
Subroutine Entry  
Address  
BR !addr  
Instruction  
Branch Address  
0020H  
GETI Instruction Reference Table  
BR $ addr Instruction  
Relative Branch  
007FH  
0080H  
Address  
(-15 to -1 and +2 to +16)  
07FFH  
0800H  
Branch Destination  
Address and  
Subroutine Entry  
Address to be Set  
by GETI Instruction  
0FFFH  
1000H  
BRCB  
!caddr Instruction  
Branch Address  
1FFFH  
2000H  
BRCB  
!caddr Instruction  
Branch Address  
2FFFH  
3000H  
BRCB  
!caddr Instruction  
Branch Address  
3F7FH  
Remarks In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC  
changed is enabled by BR PCDE and BR PCXA instructions.  
15  
µPD75216A  
Fig. 4-2 Data Memory Map  
000H  
General  
Register  
Area  
(32 × 4)  
256 × 4  
01FH  
020H  
Bank 0  
Stack Area  
General  
Static RAM  
(512 × 4)  
0FFH  
100H  
256 × 4  
Bank 1  
1BFH  
1C0H  
Display Data  
Memory,  
etc.  
(64 × 4)  
1FFH  
F80H  
Not Incorporated  
Peripheral  
Hardware  
Area  
128 × 4  
Bank 15  
FFFH  
16  
µPD75216A  
5. PERIPHERAL HARDWARE FUNCTIONS  
5.1 PORTS  
I/O ports have the following three functions.  
•
•
•
CMOS input (PORT0, 1)  
: 8  
CMOS input/output (PORT2, 3, 4, 5, 6)  
: 20  
P-ch open-drain, high-voltage, high-current output (PORTH) : 4  
Total 32  
Table 5-1 Port Functions  
Port Name  
PORT0  
Function  
Operation and Feature  
Remarks  
4-bit input  
Always read or test possible irrespective of the dual-function Shares the pins with SI, SO, SCK  
pin operating mode.  
and INT4.  
Always read or test possible, P10 and P11 are inputs with the  
noise elimination function.  
PORT1  
Shares the pins with INT0 to INT  
2 and TI0.  
PORT3  
PORT6  
4-bit  
Can be set bit-wise to the input or output mode. Port 6 can  
incorporate a pull-down resistor as a mask option.  
input/output  
Can be set to the input or output mode in 4-bit units.  
Ports 4 and 5 can input/output data in pairs in 8-bit units.  
Ports 4 and 5 can directly drive LEDs.  
PORT2  
PORT4  
PORT5  
P23 shares the pin with BUZ.  
PORTH  
4-bit output  
P-ch open-drain high-voltage, high-current output port. Can Shares the pins with T10/S15 to  
drive an FIP and LED directly. Can incorporate a pull-down T13/S12.  
resistor bit-wise as a mask option.  
17  
µPD75216A  
5.2 CLOCK GENERATOR  
The clock generator operations are determined by the processor clock control register (PCC) and the system clock  
control register (SCC).  
The clock generator has two types: main system clock and subsystem clock.  
The instruction execution time can be changed.  
•
•
0.95 µs, 1.91 µs, 15.3 µs (Main system clock: at 4.19 MHz operation)  
122 µs (Subsystem clock: at 32.768 kHz operation)  
Fig. 5-1 Clock Generator Block Diagram  
XT1  
• FIP Controller  
• Basic Interval Timer (BT)  
• Timer/Event Counter  
• Serial Interface  
• Watch Timer  
• INT0 Noise Eliminator  
Subsystem  
Clock  
Oscillator  
f
XT  
Watch Timer  
XT2  
X1  
Timer/Pulse  
Generator  
1/8~1/4096  
Main System  
Clock  
Oscillator  
f
XX  
Frequency Divider  
f
X
X2  
1/2 1/6  
SCC  
Oscillation  
Stop  
Frequency  
Divider  
SCC3  
1/4  
Φ
SCC0  
PCC  
• CPU  
• INT0 Noise Eliminator  
• INT1 Noise Eliminator  
PCC0  
PCC1  
4
HALT F/F  
S
PCC2  
PCC3  
HALT*  
STOP*  
Q
R
PCC2 and  
PCC3  
Clear  
Wait Release Signal from BT  
RES Signal (Internal Reset)  
STOP F/F  
Q
S
R
Standby Release Signal from  
Interrupt Control Circuit  
*
Instruction execution  
Remarks 1. fX = Main system clock frequency  
2. fXT = Subsystem clock frequency  
3. fXX = System clock frequency  
4. Φ = CPU clock  
5. PCC: Processor clock control register  
6. SCC: System clock control register  
7. 1 clock cycle (tCY) of Φ is 1 machine cycle of an instruction. For tCY, see ”AC Characteristics“ in 12.  
ELECTRICAL SPECIFICATIONS.  
18  
µPD75216A  
5.3 BASIC INTERVAL TIMER  
The basic interval timer has the following functions:  
•
•
•
•
Interval timer operation to generate reference time  
Watchdog timer application to detect inadvertent program loop  
Wait time select and count upon standby mode release  
Count contents read  
Fig. 5-2 Basic Interval Timer Configuration  
From Clock  
Generator  
Clear  
Clear  
f
f
f
f
XX/25  
XX/27  
Set  
Basic Interval Timer  
(8-Bit Frequency Divider)  
BT Interrupt  
Request Flag  
MPX  
XX/29  
Vectored  
Interrupt  
Request  
Signal  
XX/212  
BT  
IRQBT  
3
Wait Release  
Signal During  
Standby Release  
BTM3  
BTM2  
BTM1  
BTM0  
BTM  
SET1*  
4
8
Internal Bus  
*
Instruction execution  
19  
µPD75216A  
5.4 WATCH TIMER  
The µPD75216A incorporates one channel of watch timer. The watch timer has the following functions.  
•
Sets the test flag (IRQW) at 0.5 sec intervals.  
The standby mode can be released by IRQW.  
•
•
•
0.5 second interval can be set with the main system clock and subsystem clock.  
The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection.  
The fixed frequencies (2.048 kHz) can be output to the P23/BUZ pin for use to generate buzzer sound and trim  
the system clock oscillator frequency.  
•
Since the frequency divider can be cleared, the watch can be started from zero second.  
Fig. 5-3 Watch Timer Block Diagram  
f
W
27  
(256 Hz : 3.91 ms)  
INTW  
IRQW  
Set Signal  
f
XX  
Selector  
f
W
214  
128  
(32.768 kHz)  
From  
Clock  
Generator  
f
W
Selector  
Frequency Divider  
Clear  
(32.768 kHz)  
2Hz  
f
XT  
0.5 sec  
(32.768 kHz)  
f
16  
W
(2.048 kHz)  
Output Buffer  
P23/BUZ  
WM  
WM7 WM6  
PORT2.3  
Bit 2 of PMGB  
P23  
Port 2  
Output  
Latch  
Input/Output  
Mode  
WM5  
WMW4 M3  
WM2  
WM1  
WM0  
8
Internal Bus  
Remarks Values at fXX = 4.194304 MHz and fXT = 32.768 kHz are indicated in parentheses.  
20  
µPD75216A  
5.5 TIMER/EVENT COUNTER  
The µPD75216A incorporates one channel of timer/event counter. The timer/event counter has the following  
functions.  
Program interval timer operation  
•
•
•
Event counter operation  
Count state read function  
Fig. 5-4 Timer/Event Counter Block Diagram  
Internal Bus  
8
*
SET1  
8
8
TM0  
TMOD0  
Modulo Register (8)  
TMn7 TMn6 TMn5 TMn4 TMn3 TMnT2Mn1 TMn0  
8
Match  
Comparator (8)  
INTT0  
IRQT0  
Set Signal  
8
Input Buffer  
P13/TI0  
T0  
Count Register (8)  
Clear  
MPX  
CP  
From Clock  
Generator  
Timer Operation Start  
IRQT0  
Clear  
*
Instruction execution.  
21  
µPD75216A  
5.6 TIMER/PULSE GENERATOR  
The µPD75216A incorporates one channel of timer/pulse generator which can be used as a timer or a pulse  
generator. The timer/pulse generator has the following functions.  
(a) Functions available in the timer mode  
• 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels  
• Square wave output to PPO pin  
(b) Functions available in the PWM pulse generation mode  
• 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable  
to tuning)  
215  
fXX  
• Fixed time interval (  
= 7.81 ms : at 4.19 MHz operation) interrupt generation  
If pulse output is not necessary, the PPO pin can be used as a 1-bit output port.  
Note If the STOP mode is set while the timer/pulse generator is in operation, miss-operation may result.  
To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode  
register.  
Fig. 5-5 Block Diagram of Timer/Pulse Generator (Timer Mode)  
Internal Bus  
8
8
MODL  
MODH  
Modulo Register L (8)  
Modulo Register H (8)  
TPGM3  
(Set to "1")  
INTTPG  
IRQTPG  
Set Signal  
Modulo Latch H (8)  
8
Match  
Output Buffer  
PPO  
Comparator (8)  
8
T F/F  
Selector  
Set  
Frequency  
Divider  
CP  
fX  
1/2  
Prescalar Select Latch (5)  
Clear  
Count Register (8)  
Clear  
TPGM4 TPGM5 TPGM7  
TPGM1  
22  
µPD75216A  
Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode)  
Internal Bus  
8
8
MODH  
MODL  
(2)  
Modulo Register H (8)  
Modulo Register L (6)  
TPGM3  
MODH (8)  
Modulo Latch (14)  
MODL7-2 (6)  
Output Buffer  
TPGM1  
1/2  
PWM Pulse Generator  
Selector  
TPGM5  
PPO  
fx  
Frequency Divider  
INTTPG  
(IRQTPG Set Signal)  
215  
TPGM7  
(
= 7.81 ms : at 4.19 MHz operation)  
f
X
5.7 SERIAL INTERFACE  
The µPD75216A serial interface has the following functions.  
•
•
•
Clock synchronous 8-bit send/receive operation (simultaneous send/receive)  
Clock synchronous 8-bit serial bus operation (data input/output from the SO pin. N-ch open-drain SO output)  
Start LSB/MSB switching  
The above functions facilitates data communication with another microcomputer of µPD7500 series and 78K  
series via serial bus and coupling with peripheral devices.  
23  
Fig 5-7 Serial Interface Block Diagram  
Internal Bus  
8
SET1 *2  
8
8
P03/SI  
SIO0  
SIO7  
SIO  
SIOM  
SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0  
Shift Register (8)  
*1  
SO Output  
Latch  
P02/SO  
INTSIO  
IRQSIO  
Overflow  
Serial Clock  
Counter (3)  
Set Signal  
IRQSIO  
Clear Signal  
Clear  
Serial Start  
P01/SCK  
R
S
Q
Φ
f
f
xx/24  
MPX  
xx/210  
µ
*
1. CMOS output and N-ch open drain output switchable output buffer.  
2. Instruction execution  
µPD75216A  
5.8 FIP CONTROLLER/DRIVER  
The on-chip FIP controller/driver has the following functions:  
•
Generates the segment and digit signals by automatically reading the display data memory executing DMA  
operation.  
•
•
•
•
Can select up to a total of 26 display devices in the range of 9 to 16 segments and 9 to 16 digits.  
Can apply the remaining display output as static output.  
Can adjust the brightness at 8 levels using the dimmer function.  
Can apply key scan operations.  
•
•
Generates interrupt at the key scan timing (IRQKS)  
Can generate key scan data output from the segment output pin.  
•
•
Owns the high-voltage output pin (40 V) which can directly drive the FIP.  
•
•
Segment special pins (S0 to S9)  
: VOD = 40 V, IOD = 3 mA  
Digit output pins (T0 to T15) : VOD = 40 V, IOD = 15 mA  
Can incorporate pull-down resistors bit-wise as mask options.  
Differences between µPD75261A and µPD75238 display output function are shown in Table 5-2.  
Table 5-2 Differences between µPD75216A and µPD75238 display output function  
µPD75216A  
µPD75238  
High-voltage output display  
FIP output total  
Segment output  
Digit output  
:
:
:
26  
FIP output total  
Segment output  
Digit output  
:
:
:
34  
9 to 16  
9 to 16  
9 to 24  
9 to 16  
Display data area  
1C0H to 1FFH  
1A0H to 1FFH  
Output dual-function pin  
S12 to S15  
(PORTH)  
S0 to S23  
(PORT10 to PORT15)  
KS0 to KS2  
Key scan register  
KS0, KS1  
25  
µPD75216A  
Fig. 5-8 FIP Controller/Driver Block Diagram  
Internal Bus  
Key Scan  
Flag (KSF)  
4
4
4
Display  
Mode  
Register  
Digit  
Dimmer  
Select  
Register  
Select  
Register  
Display Data Memory  
(64 × 4 Bits)  
Key Scan Registers (KS0, KS1)  
12  
Port H  
4
INTKS  
IRQKS  
Generation  
Signal  
Digit Signal  
Generator  
Segment Data Latch (16)  
4
4
Selector  
2
2
4
4
10  
Selector  
4
10  
2
High-Voltage Output Buffer  
10  
10  
2
4
T15/S10, T13/S12/PH0-  
T14/S11 T10/S15/PH3  
T0-T9  
S0-S9  
V
LOAD  
V
PRE  
Note The FIP controller/driver can only operate in the high and intermediate-speeds (PCC = 0011B or  
0010B) of the main system clock (SCC.0 = 0). It may cause errors with any other clock or in the  
standby mode. Thus, be sure to stop FIP controller operation (DSPM.3 = 0) and then shift the unit  
to any other clock mode or the standby mode.  
26  
µPD75216A  
5.9 POWER-ON FLAG (MASK OPTION)  
The power-on flag (PONF) is automatically set (1) when the power-on reset circuit is activated and the power-  
on reset signal is generated (See Fig. 8-1 Reset Signal Generator).  
The PONF is mapped at bit 0 of address FD1H in the data memory space and can be tested by the memory bit  
manipulation instructions (SKT, SKF, SKTCLR) or cleared (CLR1).  
Note The PONF cannot be set by SET1 instruction.  
27  
µPD75216A  
6. INTERRUPT FUNCTIONS  
The µPD75216A has eight types of interrupt sources and can generate multiple interrupts with priority order.  
It is also equipped with two types of test sources. INT2 is an edge detected testable input.  
The µPD75216A interrupt control circuit has the following functions:  
•
Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt  
enable flag (IE×××) and the interrupt master enable flag (IME).  
•
•
•
•
Function of setting any interrupt start address.  
Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS).  
Interrupt request flag (IRQ×××) test function. (Interrupt generation can be checked by software.)  
Standby mode release function. (Interrupt to be released by interrupt enable flag can be selected.)  
28  
Fig. 6-1 Interrupt Control Circuit Block Diagram  
Internal Bus  
4
2
2
2
(IME)  
IPS  
IST  
IM1  
IM0  
Interrupt Enable Flag (IE XXX  
)
Decoder  
INT  
BT  
IRQBT  
IRQ4  
Both Edges  
Detection  
Circuit  
INT4  
/P00  
VRQn  
Edge  
INT0  
/P10  
Detection  
Circuit  
IRQ0  
*
Edge  
INT1  
/P11  
Vector  
Table  
Address  
Generator  
Circuit  
IRQ1  
Detection  
Circuit  
*
Priority Control  
Circuit  
INTSIO  
IRQSIO  
IRQT0  
IRQTPG  
IRQKS  
IRQW  
IRQ2  
INTT0  
INTTPG  
INTKS  
INTW  
Standby Release  
Signal  
Rising Edge  
Detection  
Circuit  
INT2  
/P12  
µ
*
Noise eliminator  
µPD75216A  
7. STANDBY FUNCTIONS  
Two standby modes (STOP mode and HALT mode) are available for the µPD75216A to decrease power  
consumption in the program standby mode.  
Table 7-1 Operation Status in Standby Mode  
STOP Mode  
STOP instruction  
HALT Mode  
HALT instruction  
Set instruction  
Setting enabled only with main system  
clock.  
Setting enabled with either main system  
clock or subsystem clock.  
System clock when set  
Oscillation stops only with main system  
clock.  
Stops only with CPU clock Φ (Oscillation  
Clock oscillator  
continued).  
Operation stopped.  
Operation (IRQBT set at reference time  
intervals).  
Basic interval timer  
Serial interface  
Operation enabled only when external  
SCK input is selected for serial clock.  
Operation enabled when serial clock other  
than Φ is specified.  
Operation enabled only when TI0 pin  
input is specified for count clock.  
Operation enabled.  
Timer/event counter  
Operation enabled.  
Operation stopped.  
Timer/pulse generator  
Watch timer  
Operation enabled only fXT is selected for Operation enabled.  
count clock.  
Operation disabled (display off mode set before disabling).  
Operation stopped.  
FIP controller/driver  
CPU  
Interrupt request signal (except INT0, INT1, INT2) enabled by interrupt enable flag  
or RESET input.  
Release signal  
30  
µPD75216A  
8. RESET FUNCTIONS  
The reset signal (RES) generator has a configuration shown in Fig. 8-1.  
Fig. 8-1 Reset Signal Generator  
RESET  
Internal Reset Signal  
(RES)  
Mask  
Option  
SWB  
Bit  
Power-On  
Reset  
Generator  
Manipulation  
Instruction  
Execution  
SWA  
Power-On Flag  
(PONF)  
The power-on reset generator is a circuit to generate a one-shot pulse upon detection of the start-up of the power  
voltage. This pulse is used in the following three ways according to SWA, SWB mask option specification shown  
in Fig. 8-1. (Refer to 10. MASK OPTION SELECTION.  
31  
µPD75216A  
Fig. 8-2 Reset Operation by Power-On Reset  
Supply Voltage  
*
Wait  
0 V  
(31.3ms:4.19MHz)  
Internal Reset Signal  
(RES)  
Operating  
Mode  
HALT Mode  
Internal Reset Operation  
*
Wait time does not include a time from RES signal generation to oscillation start.  
Fig. 8-3 Reset Operation by RESET Input  
Wait  
(31.3ms:4.19MHz)  
RESET Input  
Operating  
Mode  
Operating Mode or  
Standby Mode  
HALT Mode  
Internal Reset Operation  
Each hardware state after reset operation is shown in Table 8-1.  
32  
µPD75216A  
Table 8-1 Hardware Statuses after Reset  
RESET Input upon  
Power-on Reset or  
in Operation  
Hardware  
RESET Input in Standby Mode  
Program counter (PC)  
PSW Carry flag (CY)  
Sets the low-order 6 bits of program  
memory address 0000H to PC13-8 and  
the contents of address 0001H to PC7-0.  
Same as left  
Hold  
Undefined  
0
0
Skip flag (SK0 to SK2)  
0
Interrupt status flag (IST0, IST1)  
Bank enable flags (MBE, RBE)  
0
Sets bit 6 of program memory address  
0000H to RBE and bit 7 to MBE.  
Same as left  
Stack pointer (SP)  
Undefined  
Undefined  
Data memory (RAM)  
Hold*1  
Undefined  
General registers (X, A, H, L, D, E, B, C)  
Bank select registers (MBS, RBS)  
Basic interval Counter (BT)  
Hold  
Undefined  
0, 0  
0, 0  
Undefined  
Undefined  
timer  
Mode register (BTM)  
0
0
Timer/event  
counter  
Counter (T0)  
0
0
Modulo register (TMOD0)  
Mode register (TM0)  
FFH  
FFH  
0
0
Timer/pulse  
generator  
Modulo register (MODH, MODL)  
Mode register (TPGM)  
Hold  
Undefined  
0
0
Watch timer  
Mode register (WM)  
0
0
Serial  
Shift register (SIO)  
Hold  
Undefined  
interface  
Mode register (SIOM)  
Only bit 4 set to 1, other bits set to 0  
Only bit 4 set to 1, other bits set to 0  
Clock  
generator  
Processor clock control register (PCC)  
System clock control register (SCC)  
Interrupt request flag (IRQ×××)  
Interrupt enable flag (IE×××)  
Priority select register (IPS)  
INT0 and INT1 mode registers (IM0, IM1)  
Output buffer  
0
0
0
Reset (0)  
0
0
Interrupt  
Reset (0)  
0
0
0
0, 0  
Off  
0, 0  
Digital port  
Port H  
Off  
Output latch  
Clear (0)  
0
Clear (0)  
Input/outputmoderegister(PMGA,PMGB)  
Output latch  
0
Hold  
0
Undefined  
FIP controller/ Display mode register (DSPM)  
0
driver  
Digit select register (DIGS)  
1000B  
0
1000B  
Dimmer select register (DIMS)  
Display data memory  
0
Undefined  
Off  
Hold  
Off  
Output buffer  
Power on flag (PONF)  
Hold  
1 or undefined*2  
*
1. Data of data memory addresses 0F8H to 0FDH becomes indeterminate by RESET input.  
2. 1 upon power-on reset, indeterminate after RESET input in operation.  
33  
µPD75216A  
9. INSTRUCTION SET  
(1) Operand identifier and description  
Enter an operand in the operand column of each instruction using the description method relating to the  
operand identifier of the instruction (For details, refer to RA75X Assembler Package User’s Manual Language  
Volume (EEU-730)). If more than one description method is available, select one. Capital alphabetic letters, plus  
and minus signs are keywords. Describe them as they are.  
In the case of immediate data, describe appropriate numerical values or labels.  
Symbols can be described as labels in place of mem, fmem, pmem, bit, etc. (For details, refer toµPD75216A  
User’s Manual (IEM-988)). Available labels are limited for fmem and pmem.  
Identifier  
reg  
Description Method  
X, A, B, C, D, E, H, L  
X, B, C, D, E, H, L  
reg 1  
rp  
XA, BC, DE, HL  
BC, DE, HL  
BC, DE  
rp1  
rp2  
rp’  
XA, BC, DE, HL, XA’, BC’, DE’, HL’  
BC, DE, HL, XA’, BC’, DE’, HL’  
rp’1  
rpa  
HL, HL+, HL-, DE, DL  
DE, DL  
rpa1  
n4  
n8  
4-bit immediate data or label  
8-bit immediate data or label  
mem  
bit  
8-bit immediate data or label*  
2-bit immediate data or label  
fmem  
pmem  
FB0H to FBFH and FF0H to FFFH immediate data or labels  
FC0H to FFFH immediate data or labels  
addr  
0000H to 3F7FH immediate data or labels  
12-bit immediate data or label  
caddr  
faddr  
11-bit immediate data or label  
taddr  
20H to 7FH immediate data (bit0 = 0) or label  
PORTn  
IE×××  
RBn  
PORT0 to PORT6  
IEBT, IESIO, IET0, IETPG, IE0, IE1, IEKS, IEW, IE4  
RB0 to RB3  
MBn  
MB0, MB1, MB15  
*
For 8-bit data processing, only even addresses can be specified.  
34  
µPD75216A  
(2) Legend for operation description  
A
: A register; 4-bit accumulator  
: B register  
B
C
: C register  
D
: D register  
E
: E register  
H
: H register  
L
: L register  
X
: X register  
XA  
BC  
DE  
HL  
XA’  
BC’  
DE’  
HL’  
PC  
SP  
CY  
PSW  
MBE  
RBE  
: Register pair (XA); 8-bit accumulator  
: Register pair (BC)  
: Register pair (DE)  
: Register pair (HL)  
: Expanded register pair (XA’)  
: Expanded register pair (BC’)  
: Expanded register pair (DE’)  
: Expanded register pair (HL’)  
: Program counter  
: Stack pointer  
: Carry flag; Bit accumulator  
: Program status word  
: Memory bank enable flag  
: Register bank enable flag  
PORTn : Port n (n = 0 to 6)  
IME  
IPS  
: Interrupt master enable flag  
: Interrupt priority select register  
: Interrupt enable flag  
IE×××  
RBS  
MBS  
PCC  
•
: Register bank select register  
: Memory bank select register  
: Processor clock control register  
: Address and bit delimiter  
: Contents addressed by ××  
: Hexadecimal data  
(××)  
××H  
35  
µPD75216A  
(3) Description of symbols in the addressing area column  
*1  
MB = MBE • MBS  
(MBS = 0, 1, 15)  
*2  
*3  
MB = 0  
MBE = 0 : MB = 0 (00H to 7FH)  
MB = 15 (80H to FFH)  
Data Memory  
Addressing  
MBE = 1 : MB = MBS (MBS = 0, 1, 15)  
*4  
MB = 15, fmem = FB0H to FBFH,  
FF0H to FFFH  
*5  
*6  
*7  
MB = 15, pmem = FC0H to FFFH  
addr = 0000H to 3F7FH  
addr = (Current PC) – 15 to (Current PC) – 1,  
(Current PC) + 2 to (Current PC) + 16  
Program Memory  
Addressing  
*8  
caddr = 0000H to 0FFFH (PC13, 12 = 00B) or  
1000H to 1FFFH (PC13, 12 = 01B) or  
2000H to 2FFFH (PC13, 12 = 10B) or  
3000H to 3F7FH (PC13, 12 = 11B)  
*9  
faddr = 0000H to 07FFH  
taddr = 0020H to 007FH  
*10  
Remarks 1. MB indicates accessible memory bank.  
2. In *2, MB = 0 irrespective of MBE and MBS.  
3. In *4 and *5, MB = 15 irrespective of MBE and MBS.  
4. *6 to *10 indicate addressable areas.  
(4) Description of the machine cycle column  
S indicates the number of machine cycles required for skip operation by an instruction having skip function.  
The S value varies as follows:  
•
•
•
When not skipped ................................................................................................... S = 0  
When 1-byte or 2-byte instructions are skipped ................................................. S = 1  
When 3-byte instructions are skipped (BR !addr, CALL !addr instruction)..... S = 2  
Note GETI instruction is skipped in one machine cycle.  
One machine cycle is equal to one cycle(=tCY) of CPU clock Φ and three time periods are available  
according to PCC setting.  
36  
µPD75216A  
No. of Machine  
Addressing  
Area  
Skip  
Condition  
Mnemonic  
MOV  
Operands  
A, #n4  
Operation  
Note 1  
Bytes  
Cycle  
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
1
1
A←n4  
Stack A  
reg1, #n4  
XA, #n8  
HL, #n8  
2
reg1←n4  
XA←n8  
HL←n8  
rp2←n8  
A←(HL)  
2
Stack A  
Stack B  
2
rp2, #n8  
A, @HL  
2
1
*1  
*1  
*1  
*2  
*1  
*1  
*1  
*3  
*3  
*3  
*3  
A, @HL+  
A, @HL–  
A, @rpa1  
XA, @HL  
@HL, A  
2 + S  
A←(HL), then L←L+1  
A←(HL), then L←L–1  
A←(rpa1)  
L = 0  
2 + S  
L = FH  
1
2
XA←(HL)  
1
(HL)←A  
@HL, XA  
A, mem  
XA, mem  
mem, A  
mem, XA  
A, reg  
2
(HL)←XA  
2
A←(mem)  
2
XA←(mem)  
(mem)←A  
2
2
(mem)←XA  
A←reg  
2
XA, rp'  
2
XA←rp'  
reg1, A  
2
reg1←A  
rp'1, XA  
A, @HL  
2
rp'1←XA  
XCH  
1
A↔(HL)  
*1  
*1  
*1  
*2  
*1  
*3  
*3  
A, @HL+  
A, @HL–  
A, @rpa1  
XA, @HL  
A, mem  
XA, mem  
A, reg1  
2 + S  
A↔(HL), then L←L+1  
A↔(HL), then L←L–1  
A↔(rpa1)  
L = 0  
2 + S  
L = FH  
1
2
2
2
1
2
3
3
XA↔(HL)  
A↔(mem)  
XA↔(mem)  
A↔reg1  
XA, rp'  
XA↔rp'  
MOVT  
XA, @PCDE  
XA, @PCXA  
XA←(PC13–8+DE)ROM  
XA←(PC13–8+XA)ROM  
Note 2  
Note 1. Instruction Group  
2. Table reference  
37  
µPD75216A  
No. of Machine  
Addressing  
Area  
Skip  
Condition  
Note Mnemonic  
Operand  
Operation  
CY←(fmem.bit)  
Bytes  
Cycle  
MOV1  
CY, fmem.bit  
CY, pmem.@L  
CY, @H+mem.bit  
fmem.bit, CY  
pmem.@L, CY  
@H+mem.bit, CY  
A, #n4  
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
2
*4  
*5  
*1  
*4  
*5  
*1  
2
CY←(pmem7–2+L3–2.bit(L1–0))  
CY←(H+mem3–0.bit)  
(fmem.bit)←CY  
(pmem7–2+L3–2.bit(L1–0))←CY  
(H+mem3–0.bit)←CY  
A←A+n4  
2
2
2
2
ADDS  
1 + S  
carry  
carry  
carry  
carry  
carry  
XA, #n8  
2 + S  
XA←XA+n8  
A, @HL  
1 + S  
A←A+(HL)  
*1  
*1  
*1  
*1  
XA, rp'  
2 + S  
XA←XA+rp'  
rp'1, XA  
A, @HL  
2 + S  
rp'1←rp'1+XA  
A, CY←A+(HL)+CY  
XA, CY←XA+rp'+CY  
rp'1, CY←rp'1+XA+CY  
A←A–(HL)  
ADDC  
SUBS  
SUBC  
AND  
1
XA, rp'  
2
rp'1, XA  
A, @HL  
2
1 + S  
borrow  
borrow  
borrow  
XA, rp'  
2 + S  
XA←XA–rp'  
rp'1, XA  
A, @HL  
2 + S  
rp'1←rp'1–XA  
A, CY←A–(HL)–CY  
XA, CY←XA–rp'–CY  
rp'1, CY←rp'1–XA–CY  
A←A n4  
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
XA, rp'  
rp'1, XA  
A, #n4  
A, @HL  
A←A (HL)  
*1  
*1  
*1  
XA, rp'  
XA←XA rp'  
rp'1, XA  
A, #n4  
rp'1←rp'1 XA  
A←A n4  
OR  
A, @HL  
A←A (HL)  
XA, rp'  
XA←XA rp'  
rp'1, XA  
A, #n4  
rp'1←rp'1 XA  
A←A n4  
XOR  
A, @HL  
A←A (HL)  
XA, rp'  
XA←XA rp'  
rp'1, XA  
rp'1←rp'1 XA  
Note Instruction Group  
38  
µPD75216A  
No. of Machine  
Addressing  
Area  
Skip  
Condition  
Note 1  
Mnemonic  
Operands  
Operation  
Bytes  
Cycle  
RORC  
NOT  
A
1
2
1
1
2
2
1
2
2
2
1
2
2
2
1
1
1
1
1
CY←A0, A3←CY, An–1←An  
A←A  
A
2
INCS  
reg  
rp1  
1 + S  
1 + S  
2 + S  
2 + S  
1 + S  
2 + S  
2 + S  
2 + S  
1 + S  
2 + S  
2 + S  
2 + S  
1
reg←reg+1  
reg = 0  
rp1←rp1+1  
rp1 = 00H  
(HL) = 0  
(mem) = 0  
reg = FH  
rp = FFH  
reg = n4  
(HL) = n4  
A = (HL)  
XA = (HL)  
A = reg  
@HL  
(HL)←(HL)+1  
(mem)←(mem)+1  
reg←reg–1  
*1  
*3  
mem  
reg  
DECS  
SKE  
rp'  
rp'←rp'–1  
reg, #n4  
@HL, #n4  
A, @HL  
XA, @HL  
A, reg  
XA.rp'  
CY  
Skip if reg = n4  
Skip if (HL) = n4  
Skip if A = (HL)  
Skip if XA = (HL)  
Skip if A = reg  
Skip if XA = rp'  
CY←1  
*1  
*1  
*1  
XA = rp'  
SET1  
CLR1  
SKT  
CY  
1
CY←0  
CY  
1 + S  
1
Skip if CY = 1  
CY←CY  
CY = 1  
NOT1  
CY  
Note 1. Instruction Group  
2. Accumulator manipulation  
39  
µPD75216A  
No. of Machine  
Addressing  
Area  
Skip  
Condition  
Note Mnemonic  
Operands  
mem.bit  
Operation  
(mem.bit)←1  
Bytes  
Cycle  
SET1  
2
2
*3  
*4  
*5  
*1  
*3  
*4  
*5  
*1  
*3  
*4  
*5  
*1  
*3  
*4  
*5  
*1  
*4  
*5  
*1  
*4  
*5  
*1  
*4  
*5  
*1  
*4  
*5  
*1  
*6  
fmem.bit  
2
2
(fmem.bit)←1  
pmem.@L  
2
2
(pmem7–2+L3–2.bit(L1–0))←1  
(H+mem3–0.bit)←1  
@H + mem.bit  
mem.bit  
2
2
2
2
(mem.bit)←0  
CLR1  
SKT  
SKF  
fmem.bit  
2
2
(fmem.bit)←0  
pmem.@L  
2
2
(pmem7–2+L3–2.bit(L1–0))←0  
(H+mem3–0.bit)←0  
@H+mem.bit  
mem.bit  
2
2
2
2 + S  
2 + S  
2 + S  
2 + S  
2 + S  
2 + S  
2 + S  
2 + S  
2 + S  
2 + S  
2 + S  
2
Skip if (mem.bit) = 1  
(mem.bit) = 1  
(fmem.bit) = 1  
(pmem.@L) = 1  
(@H+mem.bit) = 1  
(mem.bit) = 0  
(fmem.bit) = 0  
(pmem.@L) = 0  
(@H+mem.bit) = 0  
(fmem.bit) = 1  
(pmem.@L) = 1  
(@H+mem.bit)=1  
fmem.bit  
2
Skip if (fmem.bit) = 1  
pmem.@L  
2
Skip if (pmem7–2+L3–2.bit(L1–0)) = 1  
Skip if (H+mem3–0.bit) = 1  
Skip if (mem.bit) = 0  
@H+mem.bit  
mem.bit  
2
2
fmem.bit  
2
Skip if (fmem.bit) = 0  
pmem.@L  
2
Skip if (pmem7–2+L3–2.bit(L1–0)) = 0  
Skip if (H+mem3–0.bit) = 0  
Skip if (fmem.bit) = 1 and clear  
Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear  
Skip if (H+mem3–0.bit)=1 and clear  
CY←CY (fmem.bit)  
@H+mem.bit  
fmem.bit  
2
SKTCLR  
AND1  
OR1  
2
pmem.@L  
2
@H+mem.bit  
CY, fmem.bit  
CY, pmem.@L  
CY, @H+mem.bit  
CY, fmem.bit  
CY, pmem.@L  
CY, @H+mem.bit  
CY, fmem.bit  
CY, pmem.@L  
CY, @H+mem.bit  
addr  
2
2
2
2
CY←CY (pmem7–2+L3–2.bit(L1–0))  
CY←CY (H+mem3–0.bit)  
CY←CY (fmem.bit)  
2
2
2
2
2
2
CY←CY (pmem7–2+L3–2.bit(L1–0))  
CY←CY (H+mem3–0.bit)  
CY←CY (fmem.bit)  
2
2
XOR1  
BR  
2
2
2
2
CY←CY (pmem7–2+L3–2.bit(L1–0))  
CY←CY (H+mem3–0.bit)  
2
2
—
—
PC13–0←addr  
(Optimum instruction is  
selected from among BR !addr,  
BRCB !caddr and BR $addr by an  
assembler.)  
!addr  
$addr  
!caddr  
PCDE  
PCXA  
3
1
2
2
2
3
2
2
3
3
PC13–0←addr  
*6  
*7  
*8  
PC13–0←addr  
BRCB  
BR  
PC13–0←PC13,12+caddr11–0  
PC13–0←PC13–8+DE  
PC13–0←PC13–8+XA  
Note Instruction Group  
40  
µPD75216A  
No. of Machine  
Addressing  
Area  
Skip  
Condition  
Note  
Mnemonic  
CALL  
Operation  
Operands  
!addr  
Bytes  
Cycle  
3
3
(SP–4) (SP–1) (SP–2)←PC11–0  
(SP–3)← MBE, RBE, PC13, 12  
PC13–0←addr, SP←SP–4  
*6  
CALLF  
RET  
!faddr  
2
1
1
2
3
(SP–4) (SP–1) (SP–2)←PC11–0  
(SP–3)← MBE, RBE, PC13, 12  
PC13–0←000, faddr, SP←SP–4  
*9  
MBE, RBE, PC13, 12←(SP+1)  
PC11–0←(SP) (SP+3) (SP+2)  
SP←SP+4  
Unconditional  
RETS  
3 + S  
MBE, RBE, PC13, 12←(SP+1)  
PC11–0←(SP) (SP+3) (SP+2)  
SP←SP+4  
then skip unconditionally  
RETI  
1
3
×, ×, PC13, 12←(SP+1)  
PC11–0←(SP) (SP+3) (SP+2)  
PSW←(SP+4) (SP+5), SP←SP+6  
rp  
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
(SP–1) (SP–2)←rp, SP←SP–2  
(SP–1)←MBS, (SP–2)←RBS, SP←SP–2  
rp←(SP+1) (SP), SP←SP+2  
MBS←(SP+1), RBS←(SP), SP←SP+2  
IME (IPS.3)←1  
PUSH  
POP  
BS  
rp  
BS  
EI  
IE×××  
IE×××←1  
DI  
IME (IPS.3)←0  
IE×××  
IE×××←0  
IN  
A, PORTn  
XA, PORTn  
PORTn, A  
PORTn, XA  
A←PORTn  
(n = 0 to 6)  
(n = 4)  
*
*
XA←PORTn+1, PORTn  
PORTn←A  
(n = 2 to 6)  
(n = 4)  
OUT  
PORTn+1, PORTn←XA  
Set HALT Mode (PCC.2←1)  
Set STOP Mode (PCC.3←1)  
No Operation  
HALT  
STOP  
NOP  
SEL  
RBn  
RBS←n  
MBS←n  
(n = 0 to 3)  
(n = 0, 1, 15)  
MBn  
*10  
*
MBE = 0 or MBE = 1 and MBS = 15 must be set for execution of IN/OUT instruction.  
Note Instruction Group  
41  
µPD75216A  
No. of Machine  
Addressing  
Area  
Skip  
Condition  
Note Mnemonic  
GETI  
Operation  
• TBR instruction  
Operands  
taddr  
Bytes  
Cycle  
*
1
3
*10  
PC13–0←(taddr)4–0+(taddr+1)  
------------------------  
----------------------------------------------------  
• TCALL instruction  
(SP–4)(SP–1)(SP–2)←PC11–0  
(SP–3)← MBE, RBE, PC13, 12  
PC13–0←(taddr)4–0+(taddr+1)  
SP←SP–4  
------------------------  
Depends on  
----------------------------------------------------  
• (taddr) (taddr+1) instruction  
executed in the case of  
instruction except TBR and  
TCALL instructions  
instructions  
referred to.  
*
TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table.  
Note Instruction Group  
42  
µPD75216A  
10. MASK OPTION SELECTION  
The µPD75216A has the following mask options enabling or disabling on-chip components.  
(1) Pin  
Pin  
Mask Option  
Pull-up resistor incorporation enabled bit-wise  
P60 to P63  
T0/T9  
T10/S15/PH3 to T13/S12/PH0  
T14/S11, T15/S10  
S0 to S9  
XT1, XT2  
Deletion of subsystem clock oscillator feedback resistor  
possible  
Note 1. In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by  
removing the feedback resistor from the oscillator.  
2. The feedback resistor must be incorporated when using subsystem clock.  
(2) Power-on reset generator, power-on flag (PONF)  
One of the following three can be selected.  
Switch Selection  
(See Fig. 8-1)  
Power-On Flag (PONF)  
Internal Reset Signal (RES)  
Power-On Reset Generator  
SWA  
ON  
SWB  
ON  
Incorporated  
Incorporated  
Generate automatically  
Not generate automatically  
–––––  
Incorporated  
Incorporated  
ON  
OFF  
OFF  
Not incorporated  
Not incorporated  
OFF  
43  
µPD75216A  
11. APPLICATION BLOCK DIAGRAM  
11.1 VCR TIMER TUNER  
Main Power Supply  
+
V
Super Capacitor  
V
DD  
SS  
Power  
Failure  
Detection  
INT4  
10  
T0–T9  
Fluorescent Display Panel (FIP)  
PPO  
INT1  
LPF  
S0–S15 16  
Electronic  
Tuner  
16 Segments × 10 Digits  
µPD75216A  
Timer  
Tuner  
Remote  
Controlled  
Reception  
Tape Counter  
Tape Count Pulse  
Tape Up/Down  
Key Matrix  
(16 × 4)  
PORT6  
SCK  
System Controller  
SO  
SCK  
SO  
Microcomputer SI  
INT0  
BUZ  
Remote Controlled  
Signal  
µPD75104/75106  
EEPROM™  
µPC2800A  
µPD6252  
BZ  
Piezoelectric Buzzer  
X1  
X2  
XT1  
XT2  
44  
µPD75216A  
11.2 CD PLAYER  
14  
T0–S13  
SIO  
SCK  
SI/SO  
Servo  
Control IC  
Fluorescent Display Panel (FIP)  
S0–S11 12  
12 Segments × 14 Digits  
Loading  
Circuit  
µPD75216A  
Key Matrix  
(12 × 4)  
PORT6  
INT0  
BUZ  
BZ  
Remote Controlled  
Signal  
µPC2800A  
X1  
X2  
11.3 ECR  
Main Power Supply  
+
V
DD  
V
SS  
Power  
Failure  
Detection  
INT4  
16  
T0–T15  
Fluorescent Display Panel (FIP)  
S0–S9 10  
10 Segments × 16 Digits  
RAM  
µPD75216A  
Key Matrix  
(10 × 4)  
Printer  
PPO  
XT2  
BZ  
X1  
X2  
XT1  
45  
µPD75216A  
12. ELECTRICAL SPECIFICATIONS  
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
RATING  
UNIT  
VDD  
VLOAD  
VPRE  
VI  
–0.3 to +7.0  
V
V
VDD –40 to VDD +0.3  
Power supply voltage  
VDD –12 to VDD +0.3  
V
Input voltage  
–0.3 to VDD +0.3  
V
VO  
Pins except display output pins  
Display output pins  
–0.3 to VDD +0.3  
V
Output voltage  
VOD  
VDD –40 to VDD +0.3  
V
1 pin except display output pins  
–15  
–15  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mW  
mW  
°C  
S0 to S9  
1 pin  
1 pin  
IOH  
T0 to T15  
–30  
Output current high  
Total of pins except display output pins  
Total of display output pins  
1 pin  
–20  
–120  
17  
Output current low  
IOL  
PT  
Total of pins  
60  
Plastic QFP  
450  
Total loss*1  
Plastic shrink DIP  
600  
Topt  
Tstg  
–40 to +85  
–65 to +150  
Operatingtemperature  
Storage temperature  
°C  
Note Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even  
momentarily. In other words, the absolute maximum ratings are rated values at which the product is on  
the verge of suffering physical damage, and therefore, the product must be used under conditions which  
ensure that the absolute maximum ratings are not exceeded.  
★
OPERATING VOLTAGE (Ta = –40 to +85 °C)  
MIN.  
PARAMETER  
CPU *2  
MAX.  
TEST CONDITIONS  
UNIT  
V
V
V
V
*3  
4.5  
4.5  
2.7  
6.0  
6.0  
6.0  
6.0  
Display controller  
Time/pulse generator  
Other hardware *2  
CAPACITANCE ( Ta = 25 °C, VDD = 0 V )  
UNIT  
MAX.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN.  
TYP.  
Input capacitance  
CIN  
pF  
pF  
pF  
pF  
15  
15  
35  
15  
f = 1 MHz  
Unmeasured pin returned  
to 0 V  
Except display output  
Output capacitance  
Display output  
COUT  
CIO  
Input /output capacitance  
46  
µPD75216A  
*
1. Calculation of total loss  
Design so that the sum of the following three power consumption values for the µPD75216ACW/GF will be  
less than the total loss PT (It is recommended to use the system with 80 % or less of the rating).  
➀ CPU loss  
: Given as VDD (MAX.) × IDD1 (MAX.)  
➁ Output pin loss  
: There are normal output pin loss and display output pin loss. It is necessary  
to add a loss derived from the flow of maximum current to each output pin.  
➂ Pull-down register loss : Power loss due to a pull-down resistor incorporated in the display output pin  
by mask option.  
Example Suppose 4-LED output with 9SEG × 11DIGIT, VDD = 5 V + 10 % and 4.19 MHz oscillation and let a current of  
3 mA, 15 mA and up to 10 mA flow to the segment pin, timing pin and LED output pin, respectively.  
Further, let the voltage of fluorescent display tube (VLOAD voltage) be –30 V and normal voltage be small.  
➀
➁
CPU loss : 5.5 V × 9.0 mA = 49.5 mW  
Pin loss : Segment pin ..... 2V × 3 mA × 9 = 54 mW  
Timing pin......... 2V × 15 mA = 30 mW  
10  
× 2 V × 10 mA × 4 = 53 mW  
LED output ........  
15  
(30 + 5.5V)2  
× 10 = 504.1 mW  
➂
Pull-down resistor loss ........  
25 kΩ  
PT = ➀+ ➁ + ➂ = 690.6 mW  
In this example, since the allowable total loss is 600 mW for the shrink DIP package, it is necessary to  
decrease power consumption by decreasing the number of on-chip pull-down resistors. In this example,  
power consumption can be adjusted to 577.8 mW by incorporating pull-down resistors in only 11 digit  
outputs and 7 segment outputs and externally mounting pull-down resistors to the 2 remaining segment  
outputs.  
★
2. Except the system clock oscillator, display controller and timer/pulse generator.  
3. The operating voltage range varies depending on the cycle time. Refer to the section describing AC  
characteristics.  
47  
µPD75216A  
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V )  
RECOMMENDED CIRCUIT  
PARAMETER  
RESONATOR  
TEST CONDITIONS  
MIN.  
2.0  
TYP.  
MAX.  
5.0  
UNIT  
MHz  
Oscillator frequency  
(fXX) *2  
VDD = Oscillation  
voltage range  
X1  
X2  
Ceramic  
resonator*1  
After VDD reaches the  
minimum value in  
the oscillation  
Oscillation  
stabilization time *3  
C1  
C1  
C2  
4
ms  
voltage range  
Oscillator frequency  
(fXX) *2  
2.0  
4.19  
5.0 *4  
10  
MHz  
ms  
X1  
X2  
Crystal  
resonator*1  
VDD = 4.5 to 6.0 V  
Oscillation stabilization  
time *3  
C2  
30  
ms  
X1 input frequency  
(fX) *2  
5.0  
MHz  
ns  
2.0  
X1  
X2  
External  
clock  
X1 input high and low  
level widths (tXH, tXL)  
250  
100  
µPD74HCU04  
*
1. Refer to RECOMMENDED OSCILLATOR CONSTANTS.  
2. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution  
time.  
3. Time required for oscillation to become stabilized after VDD reaches the minimum value in the oscillation  
voltage range or STOP mode release.  
<
4. When oscillator frequency is “4.19 < fXX 5.0 MHz”, do not select “PCC = 0011” as instruction execution time.  
–
If “PCC = 0011” is selected, 1 machine cycle becomes less than 0.95 µs, with the result that the specified MIN.  
value of 0.95 µs cannot be observed.  
★
Note When the main system clock oscillator is used, the following should be noted concerning wiring in the area  
in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.  
• The wiring should be kept as short as possible.  
• No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current.  
• The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect  
to a ground pattern carrying a high current.  
• A signal should not be taken from the oscillator.  
48  
µPD75216A  
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)  
MAX.  
35  
RECOMMENDED CIRCUIT  
MIN.  
32  
TYP.  
UNIT  
kHz  
RESONATOR  
PARAMETER  
TEST CONDITIONS  
Oscillator frequency  
(fXT) *2  
32.768  
XT1  
XT2  
Crystal  
resonator*1  
R
VDD = 4.5 to 6.0 V  
s
s
2
1.0  
Oscillation stabilization  
time *3  
C3  
C4  
10  
XT1 input frequency  
(fXT)  
kHz  
100  
32  
32  
10  
XT1 XT2  
Leave Open  
External  
clock  
XT1 input high and low  
level widths (tXTH, tXTL)  
µs  
*
1. Recommended resonators are shown in following page.  
2. Oscillator characteristics only. Refer to the description of AC characteristics for instruction execution time.  
3. Oscillation stabilization time is a time required for oscillation to become stabilized after VDD reaches the  
minimum value in the oscillation voltage range.  
Note When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area  
in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.  
★
• The wiring should be kept as short as possible.  
• No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current.  
• The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect  
to a ground pattern carrying a high current.  
• A signal should not be taken from the oscillator.  
The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current,  
and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is  
therefore required with the wiring method when the subsystem clock is used.  
49  
µPD75216A  
RECOMMENDED OSCILLATOR CONSTANTS  
MAIN SYSTEM CLOCK : CERAMIC OSCILLATOR (Ta = –40 to +85 °C)  
EXTERNAL  
OSCILLATION  
CAPACITANCE (pF)  
VOLTAGE RANGE (V)  
MANUFACTURER  
PRODUCT NAME  
REMARKS  
C1  
C2  
MIN.  
MAX.  
CSA 2.00MG  
CSA 4.19MG  
CSA 4.91MG  
CST 2.00MG  
CST 4.19MG  
CST 4.91MG  
KBR–2.0MS  
KBR–4.0MS  
KBR–4.19MS  
KBR–4.19MS  
FCR 3.58M2  
FCR 4.00M2  
FCR 4.19M2  
FCR 4.19MC  
30  
30  
4.0  
Murata Mfg. Co., Ltd.  
6.0  
On-chip C type  
Not required Not required  
47  
33  
47  
33  
Kyocera Corp.  
4.0  
4.0  
6.0  
6.0  
30  
30  
TDK  
Not required  
Not required  
On-chip C type  
MAIN SYSTEM CLOCK : CRYSTAL RESONATOR (Ta = –40 to +85 °C)  
EXTERNAL  
OSCILLATION  
LOAD  
CAPACITANCE  
CL (pF)  
FREQUENCY  
(MHz)  
CAPACITANCE (pF)  
VOLTAGE RANGE (V)  
HOLDER  
MANUFACTURER  
Kinseki  
REMARKS  
C1  
20  
C2  
20  
MIN.  
4.0  
MAX.  
6.0  
2.00  
4.19  
4.91  
HC–18/U  
HC–49/U  
HC-43/U  
16  
Note Carry out fine adjustment of crystal oscillator frequency on the external capacitance C1.  
SUBSYSTEM CLOCK : 32.768 kHz CRYSTAL RESONATOR (Ta = –10 to +60 °C)  
EXTERNAL  
OSCILLATION  
LOAD  
CAPACITANCE  
CL (pF)  
CAPACITANCE (pF)  
VOLTAGE RANGE (V)  
MODEL  
NAME  
MANUFACTURER  
REMARKS  
C4  
R
MIN.  
(V)  
MAX.  
(V)  
C3  
(pF)  
(kΩ)  
(pF)  
P–3  
22  
22  
22  
33  
330  
330  
Kinseki  
12  
14  
2.7  
6.0  
CFS–308  
Citizen Watch Co.  
Note Carry out fine adjustment of crystal oscillator frequency on the external capacitance C3.  
50  
µPD75216A  
DC CHARACTERISTICS (Ta = –40 to 85 °C, VDD = 2.7 to 6.0 V)  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN.  
UNIT  
TYP.  
MAX.  
VIH1  
VIH2  
VIH3  
Except below  
0.7 VDD  
0.75 VDD  
VDD–0.4  
0.65 VDD  
0.7 VDD  
0
V
V
VDD  
VDD  
Ports 0, 1, RESET  
X1, X2, XT1  
Input voltage high  
V
VDD  
VDD = 4.5 to 6.0 V  
V
VDD  
VIH4  
Port 6  
V
VDD  
VIL1  
VIL2  
VIL3  
Except below  
V
0.3 VDD  
0.2 VDD  
0.4  
Ports 0, 1, 6, RESET  
X1, X2, XT1  
Input Voltage low  
Output voltage high  
Output voltage low  
0
V
0
V
VDD–1.0  
VDD–0.5  
V
VDD = 4.5 to 6.0V, IOH = –1 mA  
All output pins  
VOH  
VOL  
V
IOH = –100 µA  
VDD = 4.5 to 6.0V, IOL = 15 mA  
VDD = 4.5 to 6.0V, IOL = 1.6 mA  
IOL = 400 µA  
0.4  
V
2.0  
0.4  
0.5  
3
Ports 4, 5  
V
All output pins  
V
ILIH1  
ILIH2  
ILIL1  
ILIL2  
ILOH  
ILOL1  
ILOL2  
Except X1,X2,XT1  
X1, X2, XT1  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
mA  
mA  
mA  
mA  
kΩ  
kΩ  
kΩ  
mA  
mA  
µA  
µA  
µA  
µA  
µA  
µA  
Input leakage current  
high  
VIN = VDD  
VIN = 0 V  
20  
–3  
Except X1,X2,XT1  
X1, X2, XT1  
Input leakage current  
low  
–20  
3
Output leakage current high  
All output pins VOUT = VDD  
Except display output VOUT = 0 V  
–3  
Output leakage current  
low  
Display output  
S0 to S9  
–10  
VOUT = VLOAD = VDD – 35 V  
VPRE = VDD – 9 ±1 V*1  
–3  
–1.5  
–15  
–7  
–5.5  
–3.5  
–22  
–15  
80  
VDD =  
VPRE = 0 V  
4.5 to 6.0 V  
VOD =  
Display output current  
IOD  
VPRE = VDD – 9 ±1 V*1  
VDD – 2 V  
T0 to T15  
VPRE = 0 V  
VDD = 4.5 to 6.0 V  
VOD – VLOAD = 35 V  
20  
200  
1000  
135  
9.0  
Port 6  
VIN = VDD  
RP6  
RL  
Built-in pull-down  
20  
resistor (mask option)  
Display output  
25  
70  
3.0  
0.55  
600  
200  
40  
VDD = 5 V ±10 %*3  
4.19 MHz  
crystal  
oscillation  
C1 = C2 =  
15pF  
IDD1  
VDD = 3 V ±10 %*4  
VDD = 5 V ±10 %  
1.5  
1800  
600  
120  
15  
IDD2  
HALT mode  
VDD = 3 V ±10 %  
VDD = 3 V ±10 %  
Supply current*2  
IDD3  
IDD4  
32 kHz crystal  
oscillation*5  
HALT mode VDD = 3 V ±10 %  
VDD = 5 V ±10 %  
5
0.5  
0.1  
20  
XT1 = 0 V  
STOP mode  
IDD5  
VDD = 3 V ±10 %  
10  
51  
µPD75216A  
*
1. The following external circuit is recommended.  
µPD75216A  
+5 V  
VDD  
RD9, 1EL  
RD9, 1EL : Zener Diode (NEC)  
V
PRE  
Zener Voltage = 8.29 to 9.30 V  
68 kΩ  
VLOAD  
–30 V  
V
SS  
2. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included.  
3. When the processor clock control register (PCC) is set to 0011 and is operated in the high-speed mode.  
4. When the PCC register is set to 0000 and is operated in the low-speed mode.  
5. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with  
main system clock oscillation stopped.  
POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = –40 to +85 °C)  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN.  
4.5  
TYP.  
MAX.  
6.0  
UNIT  
V
Power-on reset  
operating voltage high  
VDDH  
Power-on reset  
operating voltage low  
0.2  
V
0
10  
1
VDDL  
tr  
Power supply voltage  
rise time  
*1  
µs  
Power supply voltage  
off time  
toff  
s
10  
2
VDD = 5 V ±10 %  
100  
20  
µA  
µA  
Power-on reset circuit*2  
current consumption  
IDDPR  
VDD = 2.7 V  
*
1. 217/fXX (31.3 ms at fXX = 4.19 MHz)  
2. Current with on-chip power-on reset circuit or power-on flag.  
V
DDH  
V
DD  
V
DDL  
t
off  
t
r
Remarks Start the power supply smoothly.  
52  
µPD75216A  
AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V)  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
VDD = 4.5 to 6.0 V  
MIN.  
TYP.  
122  
MAX.  
UNIT  
32  
32  
0.95  
3.8  
µs  
µs  
Operation with main  
system clock  
CPU clock cycle time  
(minimum instruction  
execution time = 1  
machine cycle) *1  
tCY  
Operation with sub-  
system clock  
114  
125  
µs  
VDD = 4.5 to 6.0 V  
MHz  
kHz  
0
0
0.6  
fTI  
TI0 input frequency  
165  
tTIH,  
tTIL  
µs  
µs  
VDD = 4.5 to 6.0 V  
0.83  
3
TI0 input high and low-  
level widths  
Input  
0.8  
0.95  
µs  
µs  
µs  
µs  
VDD = 4.5 to 6.0 V  
Output  
Input  
SCK cycle time  
tKCY  
3.2  
3.8  
Output  
Input  
µs  
0.4  
tKCY/2–50  
1.6  
VDD = 4.5 to 6.0 V  
tKH,  
tKL  
ns  
Output  
Input  
SCK high and low-level  
widths  
µs  
ns  
Output  
t
KCY/2–150  
100  
tSIK  
tKSI  
SI setup time (to SCK↑)  
SI hold time (from SCK↑)  
ns  
ns  
ns  
ns  
µs  
µs  
400  
VDD = 4.5 to 6.0 V  
300  
SO output delay time  
from SCK↓  
tKSO  
1000  
*2  
2tCY  
10  
INT0  
INT1  
tINTH,  
Interrupt input high and  
low-level widths  
tINTL  
µs  
µs  
INT2, 4  
10  
RESET low-level width  
tRSL  
53  
µPD75216A  
t
CY VS  
V
DD  
*
1. CPU clock (Φ) cycle time is determined by the  
oscillator frequency of the connected resonator,  
the system clock control register (SCC) and the  
processor clock control register (PCC). The cycle  
time tCY characteristics for power supply voltage  
VDD when the main system clock is in operation is  
shown below.  
(Main System Clock in Operation)  
40  
32  
30  
6
5
Operation Guaranteed  
Range  
2. 2tCY or 128/fXX is set by interrupt mode register  
(IM0) setting.  
4
3
µ
2
1
0.5  
0
1
2
3
4
5
6
Power Supply Voltage VDD [V]  
54  
µPD75216A  
AC Timing Test Points (Except X1 and XT1 Inputs)  
0.75 VDD  
0.2 VDD  
0.75 VDD  
0.2 VDD  
Test Points  
Clock Timing  
1/fX  
t
XL  
t
XH  
X1 Input  
VDD - 0.4 V  
0.4 V  
1/fXT  
tXTL  
t
XTH  
XT1 Input  
VDD - 0.4 V  
0.4 V  
TI0 Timing  
1/fTI  
t
TIL  
tTIH  
TI0  
55  
µPD75216A  
Serial Transfer Timing  
t
KCY  
tKH  
tKL  
SCK  
tSIK  
t
KSI  
SI  
Input Data  
t
KSO  
SO  
Output Data  
Interrupt Input Timing  
tINTL  
tINTH  
INT0,1,2,4  
RESET Input Timing  
tRSL  
RESET  
56  
µPD75216A  
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40  
to +85 °C)  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN.  
2.0  
TYP.  
0.1  
MAX.  
6.0  
UNIT  
V
Data retention power  
supply voltage  
VDDDR  
Data retention power  
IDDDR  
tSREL  
VDDDR = 2.0V  
10  
µA  
µs  
supply current *1  
Release signal set time  
0
Release by RESET  
217/fX  
ms  
ms  
Oscillation stabilization  
tWAIT  
wait time *2  
Release by interrupt request  
*3  
*
1. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included.  
2. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation  
start.  
3. According to the setting of the basic interval timer mode register (BTM) (see below).  
BTM3  
—
BTM2  
BTM1  
BTM0  
Wait Time (Values at fXX = 4.19 MHz in parentheses)  
220/fXX (approx. 250 ms)  
0
0
1
1
0
1
0
1
0
1
1
1
—
217/fXX (approx. 31.3 ms)  
—
215/fXX (approx. 7.82 ms)  
—
213/fXX (approx. 1.95 ms)  
Data Retention Timing (STOP Mode Release by RESET)  
Internal Reset Operation  
HALT Mode  
Operating Mode  
STOP Mode  
Data Retention Mode  
VDD  
tSREL  
VDDDR  
STOP Instruction Execution  
RESET  
t
WAIT  
57  
µPD75216A  
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)  
HALT Mode  
Operating Mode  
STOP Mode  
Data Retention Mode  
VDD  
t
SREL  
VDDDR  
STOP Instruction Execution  
Standby Release Signal  
(Interrupt Request)  
t
WAIT  
58  
µPD75216A  
13. CHARACTERISTIC CURVES  
IDD vs VDD  
(Ta = 25 °C)  
5000  
High-Speed  
Mode (0011)  
Medium-Speed  
Mode (0010)  
Low-Speed  
Mode (0000)  
1000  
HALT Mode  
(0100)  
500  
µ
Subsystem  
Clock  
Operating  
Mode  
100  
50  
Subsystem  
Clock HALT  
Mode  
STOP Mode  
(1000)  
Power-on  
reset  
circuit and  
power-on flag  
incorporated  
10  
5
X1  
X2  
XT1  
XT2  
330 kΩ  
4.19 MHz  
32.768 kHz  
33 pF  
15 pF 15 pF  
22 pF  
1
0
1
2
3
4
5
6
Supply Voltage VDD [V]  
Remarks Values of the processor clock control register (PCC) is indicated in parenthesis.  
59  
µPD75216A  
IOL vs VOL (Ports 0, 2, 3, 6)  
(Ta = 25 °C)  
20  
15  
10  
5
V
DD = 5 V  
V
V
DD = 6 V  
DD = 4 V  
V
DD = 3 V  
V
DD = 2.7 V  
0
0
1
2
3
4
5
Output Voltage Low VOL [V]  
IOH vs (VDD – VOH) (Ports 0, 2, 3, 6)  
(Ta = 25 °C)  
–20  
V
DD = 5 V  
–15  
–10  
–5  
V
DD = 6 V  
VDD = 4 V  
VDD = 3 V  
V
DD = 2.7 V  
0
0
1
2
3
4
5
VDD– VOH [V]  
60  
µPD75216A  
IOL vs VOL (Ports 4, 5)  
(Ta = 25 °C)  
20  
15  
10  
5
VDD = 5 V  
6 V  
4 V  
VDD = 3 V  
VDD = 2.7 V  
0
0
1
2
3
4
5
Output Voltage Low VOL [V]  
IOH vs (VDD – VOH) (Ports 4, 5)  
(Ta = 25 °C)  
–20  
VDD = 6 V  
–15  
–10  
–5  
V
DD = 5 V  
VDD = 4 V  
V
DD = 3 V  
V
DD = 2.7 V  
0
0
1
2
3
4
5
VDD– VOH [V]  
61  
µPD75216A  
IOD vs (VDD to VOD) (T0 to T15)  
(Ta = 25 °C)  
–40.0  
–30.0  
–20.0  
–10.0  
V
DD – VPRE = 8 V  
V
DD – VPRE = 10 V  
V
DD – VPRE = 6 V  
V
DD – VPRE = 4 V  
0
0
1
2
3
4
5
VDD– VOD [V]  
IOD vs (VDD – VOD) (S0 to S9)  
(Ta = 25 °C)  
–10.0  
V
DD – VPRE = 10 V  
V
DD – VPRE = 8 V  
V
DD – VPRE = 6 V  
–5.0  
V
DD – VPRE = 4 V  
0
0
1
2
3
4
5
VDD– VOD [V]  
62  
µPD75216A  
14. PACKAGE INFORMATION  
64 PIN PLASTIC SHRINK DIP (750 mil)  
64  
33  
32  
1
A
K
L
F
D
M
R
B
C
M
N
NOTE  
ITEM MILLIMETERS  
INCHES  
1) Each lead centerline is located within 0.17 mm (0.007 inch) of  
its true position (T.P.) at maximum material condition.  
A
B
C
58.68 MAX.  
1.78 MAX.  
1.778 (T.P.)  
2.311 MAX.  
0.070 MAX.  
0.070 (T.P.)  
2) Item "K" to center of leads when formed parallel.  
+0.004  
0.020  
D
0.50±0.10  
–0.005  
F
G
H
I
0.9 MIN.  
3.2±0.3  
0.035 MIN.  
0.126±0.012  
0.020 MIN.  
0.170 MAX.  
0.200 MAX.  
0.750 (T.P.)  
0.669  
0.51 MIN.  
4.31 MAX.  
5.08 MAX.  
19.05 (T.P.)  
17.0  
J
K
L
+0.004  
0.010  
+0.10  
0.25  
M
–0.003  
–0.05  
N
R
0.17  
0.007  
0~15°  
0~15°  
P64C-70-750A,C-1  
63  
µPD75216A  
64 PIN PLASTIC QFP (14×20)  
A
B
detail of lead end  
51  
52  
33  
32  
S
C
D
R
Q
64  
1
20  
19  
F
H
I
M
J
G
K
L
M
P
N
NOTE  
ITEM MILLIMETERS  
INCHES  
Each lead centerline is located within 0.20 mm (0.008 inch) of  
its true position (T.P.) at maximum material condition.  
A
B
C
23.6±0.4  
20.0±0.2  
14.0±0.2  
0.929±0.016  
+0.008  
0.795  
–0.009  
+0.009  
0.551  
–0.008  
D
F
17.6±0.4  
1.0  
0.693±0.016  
0.039  
G
1.0  
0.039  
+0.004  
0.016  
H
0.40±0.10  
–0.005  
I
0.20  
0.008  
J
1.0 (T.P.)  
0.039 (T.P)  
+0.008  
0.071  
K
L
1.8±0.2  
0.8±0.2  
–0.009  
+0.009  
0.031  
–0.008  
+0.10  
0.15  
+0.004  
0.006  
M
–0.05  
–0.003  
N
P
Q
R
S
0.10  
0.004  
2.7  
0.106  
0.1±0.1  
5°±5°  
3.0 MAX.  
0.004±0.004  
5°±5°  
0.119 MAX.  
P64GF-100-3B8,3BE,3BR-2  
64  
µPD75216A  
64-pin ceramic QFP for ES (reference) (unit : mm)  
14.2  
12.0  
64  
52  
51  
1
19  
20  
33  
32  
1.0  
0.4  
0.15  
Note 1. Care is needed since the metal cap is con-  
nected to pin 26 and set to the positive  
power supply level.  
2. Care is needed since the lead of the base is  
formed obliquely.  
3. The lead length is not stipulated since the  
cutting of the lead ends is not progress-  
controlled.  
Bottom  
View  
65  
µPD75216A  
★
15. RECOMMENDED SOLDERING CONDITIONS  
This product should be soldered and mounted under the conditions recommended below.  
For details of recommended soldering conditions for the surface mounting type, refer to the document  
“Semiconductor Device Mount Technology” (IEI-1207).  
For soldering methods and conditions other than those recommended below, contact our salesman.  
Table 15-1 Surface Mounting Type Conditions  
µPD75216AGF-×××-3BE : 64-pin plastic QFP (14 × 20 mm)  
Recommended  
Soldering Method  
Wave soldering  
Soldering Conditions  
Condition Symbol  
Solder bath temperature: 260 °C or less, Duration: 10 sec. max.  
Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required  
at 125 °C)  
WS60-107-1  
Preheating temperature : 120 °C max. (package surface temperature)  
IR-30-107-1  
VP15-107-1  
–––  
Package peak temperature: 230 °C, Duration: 30 sec. max. (at 210 °C or above),  
Number of times: Once, Time limit: 7 days*(thereafter 10 hours prebaking required  
at 125 °C)  
Infrared reflow  
VPS  
Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above),  
Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required  
at 125 °C)  
Pin part temperature: 300 °C or below , Duration: 3 sec. max. (per device side)  
Pin part heating  
*
For the storage period after dry-pack decompression storage conditions are max. 25 °C, 65 % RH.  
Note Use of more than one soldering method should be avoided (except in the case of pin part heating).  
Notice  
A Version of this product with improved recommended soldering condition is available. For details  
(improvements such as infrared reflow peak temperature extension (235 °C), number of times: twice,  
relaxation of time limit, etc.), contact NEC sales personnel.  
Table 15-2 Insertion Type Soldering Conditions  
µPD75216ACW-××× : 64-pin plastic shrink DIP (750 mil)  
Soldering Method  
Soldering Conditions  
Wave soldering  
(lead part only)  
Solder bath temperature: 260 °C or below , Duration: 10 sec. max.  
Pin part temperature: 260 °C or below , Duration: 10 sec. max.  
Pin part heating  
Note Ensure that the application of wave soldering is limited to the lead part and no solder touches the main  
unit directly.  
66  
µPD75216A  
APPENDIX A.  
LIST OF µPD75216A SERIES PRODUCT FUNCTIONS  
Product Name  
µPD75206  
µPD75208  
µPD75212A  
12160 × 8  
µPD75216A µPD75P216A µPD75P218*  
Item  
6016 × 8  
369 × 4  
8064 × 8  
497 × 4  
16256 × 8  
512 × 4  
32640 × 8  
1024 × 4  
ROM (byte)  
RAM (× 4 bits)  
Instruction cycle  
• 0.95, 1.91, 15.3 µs (Main system clock : 4.19 operation)  
• 122 µs (Subsystem clock : 32.768 kHz operation)  
I/O ports  
33  
8
Serial input, timer input, interrupt input dual function  
CMOS input  
CMOS input/  
output  
20 • LED direct drive capability : 8  
• LED direct drive capability : 8  
• No pull-down resistor  
FIP® dual-func-  
tion pin included  
andFIPdedicated  
pin excluded  
• Mask option pull-down resistor incorporation  
capability : 4  
5
• PWM/pulse output : 1  
• PWM/pulse output : 1  
• LED direct drive capability : 4  
• No pull-down resistor  
CMOS output  
• LED direct drive capability : 4  
• Mask option pull-down resistor incorporation  
capability : 4  
High-voltage  
output  
FIP controller/  
driver  
26 • 40 V MAX.  
• Pull-downresistorincorporationoropen-drainoutput  
• 40 V MAX.  
• S0 to S8, T0 to T9 : pull-down  
resister  
specifiable by mask option  
•
S9, T10 to T15 : open-drain  
output  
9 to 12 segments  
9 to 16 segments  
No. of segments  
No. of digits  
9 to 16 digits  
Timer  
4
• Timer/pulse generator  
:
:
14 bit PWM output capability  
Buzzer output capability  
channels • Watch timer  
• Timer/event counter  
• Basic internal timer  
• MSB start/LSB start switchable  
• Serial bus configuration possible  
External : 3 , Internal : 5  
:
Watchdog timer application capability  
Serial interface  
Vectored interrupt  
Test input  
External : 1 , Internal : 1  
System clock oscillator  
•
Main system clock oscillation ceramic/crystal oscillation circuit : 4.194304 MHz standard  
• Subsystem clock oscillation crystal oscillation circuit : 32.768 kHz standard  
Incorporated (mask option) None  
Power-on reset circuit  
Low supply voltage data retention  
16K mode/32K mode switch function  
Operating temperature range  
Operating voltage  
Yes (2 V)  
None  
Incorporated  
–10 to +70 °C –40 to +70 °C  
–40 to +85 °C  
2.7 to 6.0 V  
5V ±10 %  
2.7 to 6.0 V  
Package  
• 64-pin plastic shrink DIP (750 mil)  
• 64-pin plastic QFP (14 × 20 mm)  
• 64-pinplastic  
shrink DIP  
(750 mil)  
• 64-pin plastic  
shrink DIP  
(750 mil)  
• 64-pin plastic  
QFP(14×20mm)  
• 64-pin ceramic  
WQFN  
(14 × 20 mm)  
67  
µPD75216A  
*
Can be operated at 6.0 MHz. If used in 16K mode, can be used for evaluation and limited production of the  
µPD75216A series.  
68  
µPD75216A  
APPENDIX B. DEVELOPMENT TOOLS  
The following development tools are available for the development of systems using the µPD75216A.  
IE-75000-R*1  
In-circuit emulator for the 75X series  
IE-75001-R  
IE-75000-R-EM*2  
EP-75216ACW-R  
EP-75216AGF-R  
Emulation board for the IE-75000-R and IE-75001-R  
Emulation probe for µPD75216ACW  
Emulation probe for µPD75216AGF the 64-pin conversion socket  
EV-9200G-64  
EV-9200G-64  
PG-1500  
PROM programmer  
PA-75P216ACW  
PROM programmer adapter for µPD75P216ACW/75P218CW in  
connection with PG-1500  
PA-75P218GF  
PA-75P218KB  
PROM programmer adapter for µPD75P218GF in connection with  
PG-1500  
PROM programmer adapter for µPD75P218KB in connection with  
PG-1500.  
IE control program  
PG-1500 controller  
Host machine  
• PC-9800 series (MS-DOS™ Ver.3.30 to Ver.5.00A*3)  
• IBM PC/AT™ (PC DOS™ Ver.3.1)  
RA75X relocatable assembler  
*
1. Maintenance product  
2. Not incorporated in the IE-75001-R  
3. The task swap function, which is provided with Ver.5.00/5.00A, is not available with this software.  
★
Remarks For development tools manufactured by a third party, see the 75X Series Selection Guide (IF-151).  
69  
µPD75216A  
APPENDIX C. RELATED DOCUMENTS  
Device Related Documents  
Document Name  
User’s Manual  
Document No.  
Instruction Application Table  
Application Note  
75X Series Selection Guide  
Development Tools Related Documents  
Document Name  
IE-75000-R/IE-75001-R User’s Manual  
IE-75000-R-EM User’s Manual  
Document No.  
EP-75216ACW-R User’s Manual  
EP-75216AGF-R User’s Manual  
PG-1500 User’s Manual  
RA75X Assembler Package User’s Manual  
Operation Volume  
Language Volume  
PG-1500 Controller User’s Manual  
Other Documents  
Document Name  
Package Manual  
Document No.  
Surface Mount Technology Manual  
Quality Grade on NEC Semiconductor Devices  
NEC Semiconductor Device Reliability & Quality Control  
Electrostatic Discharge (ESD) Test  
Semiconductor Devices Quality Guarantee Guide  
Microcomputer Related Products Guide Other Manufactures Volume  
Note The contents of the above related documents are subjected to change without notice. The latest documents  
should be used for design, etc.  
70  
µPD75216A  
71  
µPD75216A  
[MEMO]  
No part of this document may be copied or reproduced in any form or by any means without the prior written  
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this  
document.  
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual  
property rights of third parties by or arising from use of a device described herein or any other liability arising  
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights  
or other intellectual property rights of NEC Corporation or others.  
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear  
reactor control systems and life support systems. If customers intend to use NEC devices for above applications  
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact  
our sales people in advance.  
Application examples recommended by NEC Corporation  
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,  
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.  
Special  
:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,  
Anticrime systems, etc.  
M4 92.6  
EEPROM is a trademark of NEC Corporation.  
FIP is a trademark of NEC Corporation.  
MS-DOS is a trademark of Microsoft Corporation.  
PC DOS, PC/AT are trademarks of IBM Corporation.  

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