UPD753012AGC-XXX-8BT-A [NEC]

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80;

UPD753012AGC-XXX-8BT-A


型号：	UPD753012AGC-XXX-8BT-A
厂家：	NEC
描述：	Microcontroller, 4-Bit, MROM, 6MHz, MOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80 微控制器
文件：	总88页 (文件大小：434K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD753012A, 753016A, 753017A

4-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The µPD753017A is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing

capability comparable to that of an 8-bit microcontroller.

It has an on-chip LCD controller/driver with a larger ROM capacity and extended CPU functions compared with

the conventional µPD75316B, and can provide high-speed operation at a low supply voltage of 1.8 V. It can be

supplied in a small plastic TQFP package (12 × 12 mm) and is suitable for small sets using LCD panels.

Detailed descriptions of functions are provided in the following document. Be sure to

read the document before designing.

µPD753017 User’s Manual : U11282E

FEATURES

•

Low voltage operation: VDD = 1.8 to 5.5 V

· Can be driven by two 1.5 V batteries

On-chip memory

•

Capableofhigh-speedoperationandvariableinstruction

execution time for power saving

•

· 0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz operation)

· 0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation)

· 122 µs (at 32.768 kHz operation)

· Program memory (ROM):

12288 × 8 bits (µPD753012A)

16384 × 8 bits (µPD753016A)

24576 × 8 bits (µPD753017A)

· Data memory (RAM):

•

•

Internal programmable LCD controller/driver

Small plastic TQFP (12 × 12 mm)

· Suitable for small sets such as cameras

One-time PROM: µPD75P3018A

1024 × 4 bits

•

APPLICATION

Remote controllers, camera-integrated VCRs, cameras, gas meters, etc.

In this document, unless otherwise specified, the description is made based on µPD753017A as typical

product.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

Document No. U11662EJ2V1DS00 (2nd edition)

Date Published August 2000 N CP(K)

Printed in Japan

The mark shows major revised points.

1996, 2000

©

µPD753012A, 753016A, 753017A

ORDERING INFORMATION

Part number

Package

µPD753012AGC-XXX-3B9

µPD753012AGC-XXX-8BT

µPD753012AGK-XXX-BE9

µPD753012AGK-XXX-9EU

µPD753016AGC-XXX-3B9

µPD753016AGC-XXX-8BT

µPD753016AGK-XXX-BE9

µPD753016AGK-XXX-9EU

µPD753017AGC-XXX-3B9

µPD753017AGC-XXX-8BT

µPD753017AGK-XXX-BE9

µPD753017AGK-XXX-9EU

80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)

80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)

80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)

80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

Remark XXX indicates ROM code suffix.

2

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

FUNCTION OUTLINE

Parameter

Function

Instruction execution time

• 0.95, 1.91, 3.81, 15.3 µs (main system clock: at 4.19 MHz operation)

• 0.67, 1.33, 2.67, 10.7 µs (main system clock: at 6.0 MHz operation)

• 122 µs (subsystem clock: at 32.768 kHz operation)

Internal memory

ROM 12288 × 8 bits (µPD753012A)

16384 × 8 bits (µPD753016A)

24576 × 8 bits (µPD753017A)

RAM 1024 × 4 bits

General purpose register

• 4-bit operation: 8 × 4 banks

• 8-bit operation: 4 × 4 banks

Input/

output

port

CMOS input

8

On-chip pull-up resistors can be specified by using

CMOS input/output

CMOS output

16 software: 23

8

8

Also used for segment pins

N-ch open-drain

input/output

Withstands 13 V, on-chip pull-up resistors can be specified by using mask

option

Total

40

LCD controller/driver

• Segment number selection : 24/28/32 segments (can be changed to CMOS

output port in 4 time-unit; max. 8)

• Display mode selection

: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),

1/3 duty (1/3 bias), 1/4 duty (1/3 bias)

On-chip split resistor for LCD drive can be specified by using mask option

Timer

5 channels

• 8-bit timer/event counter: 3channels(canbeusedfor16-bittimer/eventcounter, carrier

generator, timer with gate)

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

Serial interface

• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit

• 2-wire serial I/O mode

• SBI mode

Bit sequential buffer

Clock output (PCL)

16 bits

•

•

Φ, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)

Φ, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation)

Buzzer output (BUZ)

• 2, 4, 32 kHz

(main system clock: at 4.19 MHz operation

or subsystem clock: at 32.768 kHz operation)

• 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation)

Vectored interrupt

Test input

External: 3, Internal: 5

External: 1, Internal: 1

System clock oscillator

• Ceramic or crystal oscillator for main system clock oscillation

• Crystal oscillator for subsystem clock oscillation

Standby function

Power supply voltage

Package

STOP/HALT mode

V^DD= 1.8 to 5.5 V

• 80-pin plastic QFP (14 × 14 mm)

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

3

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

CONTENTS

1. PIN CONFIGURATION (Top View) .....................................................................................................6

2. BLOCK DIAGRAM...............................................................................................................................8

3. PIN FUNCTION ....................................................................................................................................9

3.1 Port Pins ......................................................................................................................................9

3.2 Non-port Pins ............................................................................................................................11

3.3 Pin Input/Output Circuits .........................................................................................................13

3.4 Recommended Connection for Unused Pins .........................................................................15

4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE .........................................16

4.1 Differences between Mk I Mode and Mk II Mode ....................................................................16

4.2 Setting Method of Stack Bank Select Register (SBS) ...........................................................17

5. MEMORY CONFIGURATION ............................................................................................................18

6. PERIPHERAL HARDWARE FUNCTIONS .......................................................................................23

6.1 Digital Input/Output Ports ........................................................................................................23

6.2 Clock Generator ........................................................................................................................24

6.3 Subsystem Clock Oscillator Control Functions ....................................................................25

6.4 Clock Output Circuit .................................................................................................................26

6.5 Basic Interval Timer/Watchdog Timer.....................................................................................27

6.6 Watch Timer ..............................................................................................................................28

6.7 Timer/Event Counter.................................................................................................................29

6.8 Serial Interface ..........................................................................................................................33

6.9 LCD Controller/Driver ...............................................................................................................35

6.10 Bit Sequential Buffer ................................................................................................................37

7. INTERRUPT FUNCTION AND TEST FUNCTION ..........................................................................38

8. STANDBY FUNCTION.......................................................................................................................40

9. RESET FUNCTION ............................................................................................................................41

10. MASK OPTION ..................................................................................................................................44

11. INSTRUCTION SET ...........................................................................................................................45

12. ELECTRICAL SPECIFICATIONS......................................................................................................57

13. CHARACTERISTICS CURVES (REFERENCE VALUES) ..............................................................71

14. PACKAGE DRAWINGS.....................................................................................................................73

15. RECOMMENDED SOLDERING CONDITIONS................................................................................77

4

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

APPENDIX A. µPD75316B, 753017A AND 75P3018A FUNCTION LIST...........................................79

APPENDIX B. DEVELOPMENT TOOLS ................................................................................................81

APPENDIX C. RELATED DOCUMENTS ................................................................................................85

5

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

1. PIN CONFIGURATION (Top View)

•

80-pin plastic QFP (14 × 14 mm)

µPD753012AGC-XXX-3B9, 753012AGC-XXX-8BT, 753016AGC-XXX-3B9, 753016AGC-XXX-8BT

µPD753017AGC-XXX-3B9, 753017AGC-XXX-8BT

•

80-pin plastic TQFP (fine pitch) (12 × 12 mm)

µPD753012AGK-XXX-BE9, 753012AGK-XXX-9EU, 753016AGK-XXX-BE9, 753016AGK-XXX-9EU

µPD753017AGK-XXX-BE9, 753017AGK-XXX-9EU

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

S12

S13

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

P60/KR0

X2

2

S14

3

X1

IC^Note

S15

4

S16

5

XT2

S17

6

XT1

S18

VDD

7

S19

P33

8

S20

P32

9

S21

P31/SYNC

P30/LCDCL

P23/BUZ

10

11

12

13

14

15

16

17

18

19

20

S22

S23

S24/BP0

S25/BP1

S26/BP2

S27/BP3

S28/BP4

S29/BP5

S30/BP6

S31/BP7

P22/PCL/PTO2

P21/PTO1

P20/PTO0

P13/TI0

P12/INT2/TI1/TI2

P11/INT1

P10/INT0

P03/SI/SB1

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Note Connect the IC (Internally Connected) pin directly to VDD.

6

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Pin Identification

BIAS

: LCD Power Supply Bias Control

: Bit Port

PCL

: Programmable Clock

BP0-BP7

BUZ

PTO0-PTO2 : Programmable Timer Output 0-2

: Buzzer Clock

RESET

S0-S31

SB0, SB1

SCK

: Reset Input

COM0-COM3

IC

: Common Output 0-3

: Internally Connected

: Segment Output 0-31

: Serial Bus 0, 1

INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4

: Serial Clock

INT2

: External Test Input 2

: Key Return

: LCD Clock

: Port 0

SI

: Serial Input

KR0-KR7

LCDCL

SO

: Serial Output

SYNC

TI0-TI2

V^DD

: LCD Synchronization

: Timer Input 0-2

P00-P03

P10-P13

P20-P23

P30-P33

P40-P43

P50-P53

P60-P63

P70-P73

: Port 1

: Positive Power Supply

: LCD Power Supply 0-2

: Ground

: Port 2

VLC0-VLC2

V^SS

: Port 3

: Port 4

X1, X2

XT1, XT2

: Main System Clock Oscillation 1, 2

: Subsystem Clock Oscillation 1, 2

: Port 5

: Port 6

: Port 7

7

Data Sheet U11662EJ2V1DS00

TI1/TI2/

P12/INT2

PTO1/P21

PTO2/P22/PCL

TOUT0

INTT2

TIMER/EVENT

COUNTER #1

TIMER/EVENT

COUNTER #2

INTT1

BASIC INTERVAL

/WATCHDOG

TIMER

4

4

4

PORT0

PORT1

PORT2

P00-P03

P10-P13

P20-P23

PROGRAM

INTBT

SP (8)

SBS

COUNTER^{Note 1}

TIMER/EVENT

COUNTER

#0

CY

TI0/P13

ALU

PTO0/P20

4

4

4

4

PORT3

PORT4

PORT5

PORT6

PORT7

P30-P33

P40-P43

P50-P53

P60-P63

P70-P73

BANK

INTT0 TOUT0

WATCH

TIMER

BUZ/P23

GENERAL REG.

INTW

f

LCD

ROM^{Note 2}

PROGRAM

MEMORY

DECODE

AND

CONTROL

SI/SB1/P03

SO/SB0/P02

SCK/P01

CLOCKED

SERIAL

INTERFACE

4

RAM

DATA

MEMORY

1024 X 4 BITS

µ

24

8

S0-S23

INTCSI TOUT0

S24/BP0-

S31/BP7

INT0/P10

INT1/P11

LCD

INTERRUPT

CONTROL

CONTROLLER

/DRIVER

4

COM0-COM3

INT2/P12

INT4/P00

3

V

LC0-VLC2

fx/2^N

CPU CLOCK Φ

KR0/P60-

KR7/P73

8

SYSTEM CLOCK

GENERATOR

fLCD

BIAS

CLOCK

OUTPUT

CONTROL

CLOCK

DIVIDER

STAND BY

CONTROL

LCDCL/P30

BIT SEQ.

BUFFER (16)

SUB

MAIN

SYNC/P31

PCL/PTO2/P22

XT1 XT2 X1 X2

IC

VDD

VSS RESET

Notes 1. µPD753012A and 753016A have a 14-bit configuration, and µPD753017A has a 15-bit configuration.

2. Capacity of the ROM depends on the product.

µPD753012A, 753016A, 753017A

3. PIN FUNCTION

3.1 Port Pins (1/2)

Alternate

Function

8-bit

I/O

I/O Circuit

Type^{Note 1}

Pin Name

P00

I/O

Function

After Reset

Input

Input

INT4

SCK

4-bit input port (PORT0).

No

No

No

No

<B>

For P01 to P03, connection of on-chip pull-

up resistors can be specified by software in

3-bit units.

P01

<F>-A

<F>-B

<M>-C

<B>-C

P02

SO/SB0

SI/SB1

INT0

P03

P10

Input

4-bit input port (PORT1).

input

Input

Input

Connection of on-chip pull-up resistors can

be specified by software in 4-bit units.

Only P10/INT0 can select noise elimination

circuit.

P11

INT1

P12

TI1/TI2/INT2

TI0

P13

P20

I/O

PTO0

PTO1

PCL/PTO2

BUZ

4-bit input/output port (PORT2).

E-B

E-B

M-D

M-D

Connection of on-chip pull-up resistors can

be specified by software in 4-bit units.

P21

P22

P23

Programmable 4-bit input/output port

(PORT3).

P30

I/O

LCDCL

SYNC

–

P31

This port can be specified for input/output

bit-wise.

Connection of on-chip pull-up resistor can

be specified by software in 4-bit units.

P32

P33

–

P40-P43^{Note 2}

I/O

–

N-ch open-drain 4-bit input/output port

(PORT4).

Yes High level

(when pull-

up resistors

are

A pull-up resistor can be contained bit-wise

(mask option).

provided) or

high

impedance

Withstand voltage is 13 V in open-drain mode.

P50-P53^{Note 2}

I/O

–

N-ch open-drain 4-bit input/output port

(PORT5).

High level

(when pull-

up resistors

are

provided) or

high

A pull-up resistor can be contained bit-wise

(mask option).

Withstand voltage is 13 V in open-drain mode.

impedance

Notes 1. Circuit types enclosed in brackets indicate the Schmitt trigger input.

2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),

low level input leakage current increases when input or bit manipulation instruction is executed.

9

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

3.1 Port Pins (2/2)

Alternate

Function

8-bit

I/O

I/O Circuit

Type^{Note 1}

Pin Name

P60

I/O

I/O

Function

After Reset

Input

Programmable 4-bit input/output port

(PORT6).

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

S24

S25

S26

S27

S28

S29

S30

S31

Yes

<F>-A

<F>-A

H-A

P61

P62

P63

P70

P71

P72

P73

BP0

BP1

BP2

BP3

BP4

BP5

BP6

BP7

This port can be specified for input/output

bit-wise.

Connection of on-chip pull-up resistors can

be specified by software in 4-bit units.

I/O

Input

4-bit input/output port (PORT7).

Connection of on-chip pull-up resistors can

be specified by software in 4-bit units.

Output

Output

1-bit output port (BIT PORT).

No

Note 2

Also used for segment output pins.

Notes 1. Circuit types enclosed in brackets indicate the Schmitt trigger input.

2. BP0 through BP7 select VLC1 as an input source.

However, the output levels change depending on the external circuit of BP0 through BP7 and V^LC1.

Example

Because BP0 through BP7 are mutually connected inside the µPD753017A, the output levels of BP0

through BP7 are determined by R¹, R2, and R3.

VDD

µPD753017A

R2

BP0

BP1

ON

ON

V

LC1

R1

R3

10

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

3.2 Non-port Pins (1/2)

Alternate

Function

I/O Circuit

Type^{Note 1}

Pin Name

TI0

I/O

Function

After Reset

Input

Input

P13

Inputs external event pulses to the timer/event

counter.

<B>-C

TI1

P12/INT2

TI2

PTO0

PTO1

PTO2

PCL

BUZ

Output

P20

P21

Timer/event counter output

Clock output

Input

E-B

P22/PCL

P22/PTO2

P23

Optional frequency output (for buzzer output

or system clock trimming)

SCK

I/O

P01

P02

Serial clock input/output

Input

<F>-A

<F>-B

SO/SB0

Serial data output

Serial data bus input/output

SI/SB1

INT4

P03

P00

P10

Serial data input

<M>-C

<B>

Serial data bus input/output

Input

Input

Edge detection vectored interrupt input (both

rising edge and falling edge detection)

Input

Input

Edge detection vectored interrupt

input (detection edge can be

selected)

Noise elimination

circuit/asynchronous

selection

INT0

<B>-C

INT0/P10 can select noise

elimination circuit.

INT1

P11

Asynchronous

Rising edge detection testable input Asynchronous

Falling edge detection testable input

Falling edge detection testable input

Segment signal output

INT2

Input

Input

Input

Output

Output

Output

–

P12/TI1/TI2

Input

Input

Input

Note 2

Note 2

Note 2

–

<B>-C

<F>-A

<F>-A

G-A

KR0-KR3

KR4-KR7

S0-S23

P60-P63

P70-P73

–

S24-S31

COM0-COM3

V^LC0-VLC2

BP0-BP7

Segment signal output

H-A

–

–

Common signal output

G-B

LCD drive power

–

On-chip split resistor is enable (mask option).

BIAS

Output

Output

Output

–

Output for external split resistor disconnect

Clock output for externally expanded driver

Note 3

Input

–

LCDCL^{Note 4}

SYNC^{Note 4}

P30

P31

E-B

E-B

Clock output for externally expanded driver

synchronization

Input

Notes 1. Circuit types enclosed in brackets indicate the Schmitt trigger input.

2. Each display output selects the following VLCX as input source.

S0-S31: V^LC1, COM0-COM2: VLC2, COM3: VLC0

3. When a split resistor is contained ....... Low level

When no split resistor is contained ..... High impedance

4. These pins are provided for future system expansion. At present, these pins are used only as pins

P30 and P31.

11

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

3.2 Non-port Pins (2/2)

Alternate

Function

I/O Circuit

Type^Note

Pin Name

X1

I/O

Function

After Reset

–

Input

–

–

–

Crystal/ceramic connection pin for the mainsystem

clock oscillation. When inputting the external

clock, input the external clock to pin X1, and the

inverted phase of the external clock to pin X2.

–

X2

XT1

XT2

Input

–

–

Crystal connection pin for the subsystem clock

oscillation. When the external clock is used, input

the external clock to pin XT1, and the inverted

phase of the external clock to pin XT2. Pin XT1 can

be used as a 1-bit input (test) pin.

–

–

RESET

IC

Input

–

–

–

–

System reset input (low level active)

Internally connected. Connect directly to V^DD.

Positive power supply

–

–

–

–

<B>

–

–

–

–

VDD

–

V^SS

GND

–

Note Circuit types enclosed in brackets indicate the Schmitt trigger input.

12

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

3.3 Pin Input/Output Circuits

The µPD753017A pin input/output circuits are shown schematically.

TYPE A

TYPE D

VDD

VDD

data

P-ch

OUT

P-ch

IN

N-ch

output

disable

N-ch

Push-pull output that can be placed in output

high impedance (both P-ch and N-ch off).

CMOS standard input buffer

TYPE E-B

TYPE B

VDD

P.U.R.

P-ch

P.U.R.

enable

IN

data

IN/OUT

Type D

output

disable

Type A

Schmitt trigger input with hysteresis characteristics

P.U.R. : Pull-Up Resistor

TYPE F-A

TYPE B-C

VDD

V

DD

P.U.R.

P-ch

P.U.R.

enable

P.U.R.

P.U.R.

enable

P-ch

data

IN/OUT

Type D

output

disable

IN

Type B

P.U.R. : Pull-Up Resistor

P.U.R. : Pull-Up Resistor

13

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

TYPE F-B

TYPE H-A

V

DD

P.U.R.

P-ch

P.U.R.

enable

SEG

data

OUT

TYPE G-A

output

disable

(P)

V

DD

P-ch

IN/OUT

data

Bit Port

data

output

disable

N-ch

TYPE D

output

output

disable

(N)

disable

P.U.R. : Pull-Up Resistor

TYPE G-A

TYPE M-C

V

DD

VLC0

P.U.R.

V

LC1

P.U.R.

enable

P-ch

P-ch N-ch

IN/OUT

OUT

data

N-ch

SEG

data

output

disable

N-ch

V

LC2

N-ch

P.U.R. : Pull-Up Resistor

TYPE G-B

TYPE M-D

V

DD

P.U.R.

(Mask Option)

V

LC0

LC1

IN/OUT

data

output

N-ch

V

(+13 V

withstand

voltage)

P-ch N-ch

disable

VDD

input

instruction

P-ch

P.U.R.^Note

OUT

COM or

SEG data

N-ch P-ch

Voltage limitation

circuit

VLC2

(+13 V withstand

voltage)

N-ch

Note The pull-up resistor operates only when an input

instruction is executed (current flows from V^DDto

the pin when the pin is low).

14

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

3.4 Recommended Connection for Unused Pins

Table 3-1. List of Recommended Connection for Unused Pins

Pin

P00/INT4

Recommended Connection

Connect to VSS or VDD

P01/SCK

Connect to VSS or VDD via a resistor individually

P02/SO/SB0

P03/SI/SB1

Connect to VSS

P10/INT0, P11/INT1 Connect to VSS or VDD

P12/TI1/TI2/INT2

P13/TI0

P20/PTO0

P21/PTO1

P22/PTO2/PCL

P23/BUZ

P30/LCDCL

P31/SYNC

P32

Input: Connect to VSS or VDD via a resistor individually

Output: Leave open

P33

P40-P43

Input: Connect to VSS

P50-P53

Output: Connect to VSS (do not connect a pull-up resistor of mask option)

Input: Connect to VSS or VDD via a resistor individually

Output: Leave open

P60/KR0-P63/KR3

P70/KR4-P73/KR7

S0-S23

Leave open

S24/BP0-S31/BP7

COM0-COM3

VLC0-VLC2

Connect to VSS

BIAS

Only if all of VLC0-VLC2 are unused, connect to VSS. In other cases, leave open.

XT1

Connect to VSS

XT2^Note

Leave open

IC

Connect to VDD directly

Note

When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal

feedback resistor).

15

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

4.1 Differences between Mk I Mode and Mk II Mode

The CPU of µPD753017A has the following two modes: Mk I and Mk II, either of which can be selected. The

mode can be switched by the bit 3 of the stack bank select register (SBS).

•

•

Mk I mode: Upward compatible with µPD75316B.

Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes.

Mk II mode: Incompatible with µPD75316B.

Can be used in all the 75XL CPU’s including those products whose ROM capacity is more

than 16K bytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Mk I Mode

Mk II Mode

• µPD753012A : 12288

Program memory (bytes)

• µPD753012A : 12288

• µPD753016A, 753017A : 16384 • µPD753016A : 16384

• µPD753017A : 24576

Number of stack bytes

2 bytes

3 bytes

for subroutine instructions

BRA !addr1 instruction

Not available

Available

CALLA !addr1 instruction

CALL !addr instruction

CALLF !faddr instruction

3 machine cycles

2 machine cycles

4 machine cycles

3 machine cycles

Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and

75XL series. Therefore, this mode is effective for enhancing software compatibility

with products exceeding 16 Kbytes.

When the Mk II mode is selected, the number of stack bytes used during

execution of subroutine call instructions increases by one byte per stack

compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions

are used, the machine cycle becomes longer by one machine cycle. Therefore,

use the Mk I mode if the RAM efficiency and processing performance are more

important than software compatibility.

16

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

4.2 Setting Method of Stack Bank Select Register (SBS)

Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure

4-1 shows the format.

The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be

initialized to 10XXB^Noteat the beginning of a program. When using the Mk II mode, it must be initialized to 00XXB^Note

.

Note

Set the desired value in the XX positions.

Figure 4-1. Stack Bank Select Register Format

3

2

1

0

Address

F84H

Symbol

SBS

SBS3 SBS2 SBS1 SBS0

Stack area specification

0

0

1

1

0

1

0

1

Memory bank 0

Memory bank 1

Memory bank 2

Memory bank 3

Be sure to set bit 2 to 0.

0

Mode switching specification

0

1

Mk II mode

Mk I mode

Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I

mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk

II mode.

17

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

5. MEMORY CONFIGURATION

•

Program memory (ROM) ............... 12288 × 8 bits (µPD753012A)

............... 16384 × 8 bits (µPD753016A)

............... 24576 × 8 bits (µPD753017A)

·

·

·

Addresses 0000H and 0001H

Vector table wherein the program start address and the values set for the RBE and MBE at the time a

RESET signal is generated are written. Reset start is possible from any address.

Addresses 0002H to 000DH

Vector table wherein the program start address and the values set for the RBE and MBE by each vectored

interrupt are written. Interrupt processing can start from any address.

Addresses 0020H to 007FH

Table area referenced by the GETI instruction^Note

.

Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte/3-byte instruction, or two 1-

byte instructions. It is used to decrease the number of program steps.

•

Data memory (RAM)

·

·

Data area …1024 words × 4 bits (000H to 3FFH)

Peripheral hardware area…128 × 4 bits (F80H to FFFH)

18

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Figure 5-1. Program Memory Map (1/3)

(a) µPD753012A

7

6

5

0

0000H

0002H

0004H

0006H

0008H

000AH

000CH

RBE Internal reset start address

MBE

(high-order 6 bits)

Internal reset start address (Iow-order 8 bits)

MBE RBE INTBT/INT4 start address

INTBT/INT4 start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

Branch address of

BR BCXA, BR BCDE,

BR !addr, BRA !addr1^Note

or CALLA !addr1^Note

instruction

MBE RBE INT0 start address

INT0 start address

CALLF !faddr

instruction

entry address

MBE RBE INT1 start address

INT1 start address

BRCB !caddr

instruction

branch address

MBE RBE INTCSI start address

INTCSI start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

CALL !addr instruction

subroutine entry address

INTT0 start address

MBE RBE

INTT0 start address

(Iow-order 8 bits)

(high-order 6 bits)

INTT1, INTT2 start address

MBE RBE

INTT1, INTT2 start address (Iow-order 8 bits)

BR $addr instruction

relative branch address

(–15 to –1, +2 to +16)

0020H

GETI instruction reference table

Branch destination

007FH

0080H

address and

subroutine entry

address when GETI

instruction is executed

07FFH

0800H

0FFFH

1000H

BRCB !caddr instruction

branch address

1FFFH

2000H

BRCB !caddr instruction

branch address

2FFFH

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

8 bits of PC by executing the BR PCDE, BR PCXA instruction.

19

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Figure 5-1. Program Memory Map (2/3)

(b) µPD753016A

7

6

5

0

0000H

0002H

0004H

MBE RBE

MBE RBE

MBE RBE

Internal reset start address (high-order 6 bits)

Internal reset start address (Iow-order 8 bits)

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (Iow-order 8 bits)

Branch address of

BR BCXA, BR BCDE,

BR !addr, BRA !addr1^Note

or CALLA !addr1^Note

instruction

INT0 start address

INT0 start address

(high-order 6 bits)

(Iow-order 8 bits)

CALLF !faddr

instruction

entry address

0006H

0008H

MBE RBE

MBE RBE

MBE RBE

INT1 start address

INT1 start address

INTCSI start address

INTCSI start address

INTT0 start address

INTT0 start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

BRCB !caddr

instruction

branch address

CALL !addr instruction

subroutine entry address

000AH

000CH

MBE RBE INTT1,INTT2 start address (high-order 6 bits)

INTT1,INTT2 start address (Iow-order 8 bits)

BR $addr instruction

relative branch address

(–15 to –1, +2 to +16)

0020H

GETI instruction reference table

007FH

0080H

Branch destination

address and

subroutine entry

address when GETI

instruction is executed

07FFH

0800H

0FFFH

1000H

BRCB !caddr instruction

branch address

1FFFH

2000H

BRCB !caddr instruction

branch address

2FFFH

3000H

BRCB !caddr instruction

branch address

3FFFH

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

8 bits of PC by executing the BR PCDE, BR PCXA instruction.

20

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Figure 5-1. Program Memory Map (3/3)

(c) µPD753017A

7

6

5

0

MBE RBE Internal reset start address (high-order 6 bits)

Internal reset start address (Iow-order 8 bits)

0000H

0002H

0004H

MBE RBE INTBT/INT4 start address

INTBT/INT4 start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

CALLF !faddr

instruction

entry address

MBE RBE INT0 start address

INT0 start address

0006H

0008H

000AH

000CH

MBE RBE INT1 start address

INT1 start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

BRCB !caddr

instruction

branch address

MBE RBE INTCSI start address

INTCSI start address

BR !addr

instruction

branch address

MBE RBE INTT0 start address

INTT0 start address

CALL !addr

instruction

MBE RBE INTT1,INTT2 start address (high-order 6 bits)

INTT1,INTT2 start address (Iow-order 8 bits)

branch address

Branch address of

BR BCDE,

GETI instruction

branch/call

address

BR BCXA,

BRA !addr1^Noteor

CALLA !addr1^Note

instruction

0020H

GETI instruction reference table

007FH

0080H

BR $addr1 instruction

relative branch address

(–15 to –1, +2 to +16)

07FFH

0800H

0FFFH

1000H

BRCB !caddr instruction

branch address

1FFFH

2000H

BRCB !caddr instruction

branch address

2FFFH

3000H

BRCB !caddr instruction

branch address

3FFFH

4000H

BRCB !caddr instruction

branch address

4FFFH

5000H

BRCB !caddr instruction

branch address

5FFFH

Note Can be used only in the Mk II mode.

Caution The interrupt vector start address shown above consists of 14 bits. Set it in 16K space (0000H-

3FFFH).

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

8 bits of PC by executing the BR PCDE, BR PCXA instruction.

21

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Figure 5-2. Data Memory Map

Data memory

Memory bank

000H

(32 × 4)

General purpose register area

01FH

020H

0

256 × 4

(224 × 4)

0FFH

100H

256 × 4

(224 × 4)

1DFH

1E0H

1

(32 × 4)

Display data memory

1FFH

200H

Stack area^Note

Data area

static RAM

(1024 × 4)

256 × 4

2

2FFH

300H

256 × 4

3

3FFH

F80H

Not incorporated

Peripheral

hardware area

128 × 4

15

FFFH

Note For stack area, one memory bank can be selected among memory banks 0 to 3.

22

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

6. PERIPHERAL HARDWARE FUNCTIONS

6.1 Digital Input/Output Ports

There are four types of I/O ports as follows.

· CMOS input (PORT0, 1)

:

8

· CMOS input/output (PORT2, 3, 6, 7)

· N-channel open-drain input/output (PORT4, 5)

· Bit port output (BP0-BP7)

Total

: 16

:

:

8

8

40

Table 6-1. Types and Features of Digital Ports

Port (Pin Name)

Function

Operation and Features

Remarks

PORT0

(P00-P03)

4-bit input

When the serial interface function is used, the alternate

function pins function as output ports depending on the

operation mode.

Also used for the INT4,

SCK, SO/SB0, SI/SB1 pins.

PORT1

(P10-P13)

Input-only port

Also used for the INT0-

INT2 and TI0-TI2 pins.

PORT2

(P20-P23)

4-bit I/O

Can be set to input mode or output mode in 4-bit units.

Also used for the PTO0-

PTO2, PCL, BUZ pins.

PORT3

(P30-P33)

Can be set to input mode or output mode in 1/4-bit

units.

Also used for the LCDCL,

SYNC pins.

PORT4

(P40-P43)

4-bit I/O

Can be set to input mode

or output mode in 4-bit

units.

Ports 4 and 5 are paired

and data can be input/

output in 8-bit units.

On-chip pull-up resistor can

be specified bit-wise by

mask option.

(N-channel

open-drain,

13 V

PORT5

(P50-P53)

withstanding)

PORT6

(P60-P63)

4-bit I/O

Can be set to input mode

or output mode in 1/4-bit

units.

Ports 6 and 7 are paired

and data can be input/

output in 8-bit units.

Also used for the KR0-KR3

pins.

PORT7

(P70-P73)

Can be set to input mode

or output mode in 4-bit

units.

Also used for the KR4-KR7

pins.

BP0-BP7

1-bit output

Outputs data bit-wise. Can be switched to LCD drive

segment output S24-S31 by software.

—

23

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

6.2 Clock Generator

Operation of the clock generator is determined by the processor clock control register (PCC) and system clock

control register (SCC).

The two clocks, the main system clock and subsystem clock, are available.

The instruction excution time can be altered.

• 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (main system clock : at 4.19 MHz operation)

• 0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (main system clock : at 6.0 MHz operation)

• 122 µs (subsystem clock : at 32.768 kHz operation)

Figure 6-1. Clock Generator Block Diagram

· Basic interval timer (BT)

XT1

· Timer/event counter

· Serial interface

· Watch timer

· LCD controller/driver

· INT0 noise elimination circuit

· Clock output circuit

VDD

LCD controller/driver

Watch timer

Subsystem

clock oscillator

fXT

XT2

X1

1/1 to 1/4096

Divider

VDD

f

X

Main system

clock oscillator

X2

1/2 1/41/16

Selector

WM.3

SCC

Oscillation

stop

Divider

SCC3

SCC0

Selector

Φ

· CPU

1/4

· INT0 noise elimination circuit

· Clock output circuit

PCC

PCC0

PCC1

4

HALT F/F

S

PCC2

PCC3

HALT^Note

STOP^Note

R

Q

PCC2,

PCC3

Clear

STOP F/F

Wait release signal from BT

RESET signal

S

Q

R

Standby release signal from

interrupt control circuit

Note Instruction execution

Remarks 1. f^X= Main system clock frequency

2. fXT = Subsystem clock frequency

3. Φ = CPU clock

4. PCC: Processor Clock Control Register

5. SCC: System Clock Control Register

6. One clock cycle (t^CY) of Φ equal to one machine cycle of the instruction.

24

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

6.3 Subsystem Clock Oscillator Control Functions

The µPD753017A subsystem clock oscillator has the following two control functions.

•

•

Selects by software whether an internal feedback resistor is to be used or not^Note

.

Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage

is high (V^DD≥ 2.7 V).

Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor)

by software, connect XT1 to V^SS, and open XT2. This makes it possible to reduce the current

consumption in the subsystem clock oscillator.

The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS).

(See Figure 6-2.)

Figure 6-2. Subsystem Clock Oscillator

SOS.0

Feedback resistor

Inverter

SOS.1

XT1

XT2

VDD

25

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

6.4 Clock Output Circuit

The clock output circuit is provided to output the clock pulses from the P22/PTO2/PCL pin to the application

of remote control wave outputs and peripheral LSI’s.

•

Clock output (PCL) : Φ, 524, 262, 65.5 kHz (at 4.19 MHz operation)

Φ, 750, 375, 93.8 kHz (at 6.0 MHz operation)

Figure 6-3. Clock Output Circuit Block Diagram

From clock

generator

From timer/event

Φ

counter (channel 2)

Output buffer

f

X

/2³

/2⁴

Selector

PCL/PTO2/P22

fX

fX

/2⁶

PORT2.2

Bit 2 of PMGB

P22

output latch

Port 2 I/O mode

specification bit

CLOM3

0

CLOM1 CLOM0 CLOM

4

Internal bus

Remark Special care has been taken in designing the chip so that small-width pulses may not be output

when switching clock output enable/disable.

26

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

6.5 Basic Interval Timer/Watchdog Timer

The basic interval timer/watchdog timer has the following functions.

•

•

•

•

Interval timer operation to generate a reference time interrupt

Watchdog timer operation to detect a runaway of program and reset the CPU

Selects and counts the wait time when the standby mode is released

Reads the contents of counting

Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram

From clock

generator

Clear

Clear

fX

fX

fX

/2⁵

/2⁷

/2⁹

BT

Basic interval timer

(8-bit frequency divider)

Set

MPX

interrupt

request flag

Vectored

interrupt

IRQBT request signal

BT

f

/2¹²

X

3

Wait release signal

when standby is

released.

Internal reset

signal

WDTM

1

BTM3 BTM2 BTM1 BTM0 BTM

4

SET1^Note

8

SET1^Note

Internal bus

Note Instruction execution

27

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

6.6 Watch Timer

The µPD753017A has one channel of watch timer. The watch timer has the following functions.

•

Sets the test flag (IRQW) with 0.5 sec interval.

The standby mode can be released by the IRQW.

•

•

0.5 sec interval can be created by both the main system clock (4.19 MHz) and subsystem clock (32.768 kHz).

Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the

fast feed mode.

•

•

Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ pin, usable for buzzer and trimming of

system clock oscillation frequencies.

Clears the frequency divider to make the clock start with zero seconds.

Figure 6-5. Watch Timer Block Diagram

fW

(512 Hz : 1.95 ms)

2⁶

f^LCD

f^W

(256 Hz : 3.91 ms)

2⁷

f^X

128

Selector

f^W

fW

INTW

IRQW

set signal

2¹⁴

From

clock

generator

(32.768 kHz)

(32.768 kHz)

Selector

Divider

2 Hz

0.5 sec

f^XT

4 kHz 2 kHz

(32.768 kHz)

f^W

2³

fW

2⁴

Clear

Selector

Output buffer

P23/BUZ

WM

PORT2.3

PMGB bit 2

Port 2 input/

P23

output latch

WM7

0

WM5 WM4 WM3 WM2 WM1 WM0

output mode

8

Bit test instruction

Internal bus

The values enclosed in parentheses are applied when f = 4.19 MHz and fXT = 32.768 kHz.

X

28

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

6.7 Timer/Event Counter

The µPD753017A has three channels of timer/event counter. The timer/event counter has the following

functions.

•

Programmable interval timer operation

•

•

•

Square wave output of any frequency to the PTOn pin (n = 0, 1)

Event counter operation

Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided

frequency to the PTOn pin (frequency division operation).

Supplies the shift clock to the serial interface circuit (channel 0 only).

Calls the count value.

•

•

The timer/event counter operates in the following four modes as set by the mode register.

Table 6-2. Operation Modes of Timer/Event Counter

Channel

Channel 0 Channel 1 Channel 2

Mode

8-bit timer/event counter mode

Gate control function

Yes

No^Note

No

Yes

No

Yes

Yes

Yes

PWM pulse generator mode

No

16-bit timer/event counter mode

No

Yes

Yes

Gate control function

Carrier generator mode

No^Note

No

Yes

Note Used for gate control signal generation

29

Data Sheet U11662EJ2V1DS00

Figure 6-6. Timer/Event Counter Block Diagram (Channel 0)

Internal bus

8

8

8

SET1

TOE0

PORT2.0

PMGB bit 2

TMOD0

TM0

Port 2

input/output

mode

TO

enable flag

P20

output latch

–

TM06 TM05 TM04 TM03 TM02

–

–

Modulo register (8)

8

To serial interface

PORT1.3

TOUT0

Match

TOUT

F/F

Comparator (8)

8

P20/PTO0

Output buffer

Input

Reset

buffer

T0

TI0

INTT0

IRQT0

set signal

Count register (8)

Clear

f

X

X

X

/2⁴

/2⁶

/2⁸

MPX

CP

f

From clock

generator

f

f

X

/2¹⁰

Timer operation start

µ

RESET

IRQT0

clear signal

To timer/event counter (channel 2)

Figure 6-7. Timer/Event Counter Block Diagram (Channel 1)

Internal bus

8

TOE1

PORT2.1

PMGB.2

TM1

Port 2

input/output

mode

8

T1

enable flag

P21

output latch

–

TM16 TM15 TM14 TM13 TM12 TM11 TM10

Decoder

TMOD1

Modulo register (8)

PORT1.2

8

P21/PTO1

Match

TOUT

F/F

Comparator (8)

8

Input buffer

Output buffer

TI1/TI2/P12/INT2

Reset

Timer/event counter

output (channel 2)

T1

f

f

f

X

X

X

/2⁵

/2⁶

/2⁸

Count register (8)

Clear

MPX

CP

From clock

generator

f

X

/2¹⁰

/2¹²

f

X

µ

RESET

Timer operation start

16-bit timer/event counter mode

IRQT1 clear signal

Selector

INTT1

IRQT1

set signal

Timer/event counter match signal (channel 2)

(When 16-bit timer/event counter mode)

Timer/event counter reload signal (channel 2)

Timer/event counter comparator (channel 2)

(When 16-bit timer/event counter mode)

Figure 6-8. Timer/Event Counter Block Diagram (Channel 2)

Internal bus

8

8

8

8

TMOD2H

TMOD2

TC2

PORT2.2 PMGB.2

TM2

P22

output latch

Port 2

input/output

Modulo register for high level period setup (8)

Modulo register (8)

8

TM26 TM25 TM24 TM23 TM22 TM21 TM20

Decoder

TGCE

TOE2REMC NRZB NRZ

Reload

8

PORT1.2

MPX (8)

P22/PCL/PTO2

8

Match

Output buffer

TOUT

F/F

Comparator (8)

Input buffer

TI1/TI2/

P12/INT2

Reset

8

Timer/event counter

clock input (channel 1)

f^X

fX/2

T2

Overflow

Carrier generator mode

Count register (8)

Clear

MPX

CP

From clock f^X/2⁴

fX/2⁶

generator

fX/2⁸

fX/2¹⁰

INTT2

IRQT2

set signal

16-bit timer/event counter mode

IRQT2 clear signal

Timer operation start

RESET

µ

Timer/event counter

clear signal (channel 1)

(When 16-bit timer/event

counter mode)

Timer event counter

TOUT F/F (channel 0)

From clock output circuit

Timer/event counter

Timer/event counter

match signal (channel 1)

(When 16-bit timer/event

counter mode)

match signal (channel 1)

(When carrier generator mode)

µPD753012A, 753016A, 753017A

6.8 Serial Interface

The µPD753017A is provided with an 8-bit clocked serial interface. This serial interface operates in the following

four modes:

· Operation stop mode

· 3-wire serial I/O mode

· 2-wire serial I/O mode

· SBI mode

33

Data Sheet U11662EJ2V1DS00

Figure 6-9. Serial Interface Block Diagram

Internal bus

8

Bit test

Bit manipulation

Bit test

8/4

8

8

Slave address register (SVA) (8)

SBIC

CSIM

Match signal

Address comparator

RELT

CMDT

(8)

SO latch

P03/SI/SB1

P02/SO/SB0

SET CLR

Selector

Shift register (SIO)

D

Q

(8)

Busy/

acknowledge

output circuit

Selector

RELD

CMDD

ACKD

Bus release/

command/

acknowledge

detection circuit

µ

INTCSI

P01/SCK

INTCSI

control circuit

IRQCSI

set signal

Serial clock counter

f^X/2³

P01

output Iatch

fX/2⁴

Serial clock

selector

Serial clock control

circuit

fX/2⁶

TOUT0

(from timer/

event counter 0)

External SCK

µPD753012A, 753016A, 753017A

6.9 LCD Controller/Driver

The µPD753017A incorporates a display controller which generates segment and common signals according

to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel

directly.

The µPD753017A LCD controller/driver functions are as follows:

•

•

Display data memory is read automatically by DMA operation and segment and common signals are

generated.

Display mode can be selected from among the following five:

1

2

3

4

5

Static

1/2 duty (time multiplexing by 2), 1/2 bias

1/3 duty (time multiplexing by 3), 1/2 bias

1/3 duty (time multiplexing by 3), 1/3 bias

1/4 duty (time multiplexing by 4), 1/3 bias

•

•

•

•

A frame frequency can be selected from among four in each display mode.

A maximum of 32 segment signal output pins (S0-S31) and four common signal output pins (COM0-COM3).

The segment signal output pins (S24-S27 and S28-S31) can be changed to the output ports in 4-pin units.

Split-resistor can be incorporated to supply LCD drive power (mask option).

· Various bias methods and LCD drive voltages can be applicable.

· When display is off, current flow to the split resistor is cut.

•

•

Display data memory not used for display can be used for normal data memory.

It can also operate by using the subsystem clock.

35

Data Sheet U11662EJ2V1DS00

Figure 6-10. LCD Controller/Driver Block Diagram

Internal bus

4

8

4

4

8

Display

control

register

Port 3

Port mode

Display data

memory

1FFH

1FEH

1F9H

1F8H

1E0H

Display mode register

register group A

output latch

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

1

0

1 0

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

Timing

controller

f

LCD

Multi-

plexer

µ

Selector

LCD drive

voltage control

Segment driver

S24/BP0

Common driver

S31/BP7

S30/BP6

S23

S0

COM3 COM2 COM1 COM0

V

LC2

V

LC1

V

LC0

P31/

P30/

SYNC LCDCL

µPD753012A, 753016A, 753017A

6.10 Bit Sequential Buffer … 16 Bits

The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be

easily performed by changing the address specification and bit specification in sequence, therefore it is useful

when processing a long data bit-wise.

Figure 6-11. Bit Sequential Buffer Format

Address

Bit

FC3H

FC2H

FC1H

FC0H

3

2

1

0

3

2

1

0

3

2

1

0

3

2

1

0

Symbol

BSB3

BSB2

BSB1

BSB0

L register

L = FH

L = CH L = BH

L = 8H L = 7H

L = 4H L = 3H

DECS L

L = 0H

INCS L

Remarks 1. In the pmem.@L addressing, the specified bit moves corresponding to the L register.

2. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification.

37

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

7. INTERRUPT FUNCTION AND TEST FUNCTION

µPD753017A has eight types of interrupt sources and two types of test sources. Among the test sources, INT2

is provided with two testable inputs for edge detection.

µPD753017A has the following functions in the interrupt control circuit.

(1) Interrupt function

•

Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the

interrupt enable flag (IEXXX) and interrupt master enable flag (IME).

Can set any interrupt start address.

•

•

Nesting interrupts wherein the order of priority can be specified by the interrupt priority select register

(IPS).

•

•

Test function of interrupt request flag (IRQXXX). An interrupt generated can be checked by software.

Release the standby mode. A release interrupt can be selected by the interrupt enable flag.

(2) Test function

•

•

Test request flag (IRQXXX) generation can be checked by software.

Release the standby mode. The test source to be released can be selected by the test enable flag.

38

Data Sheet U11662EJ2V1DS00

Figure 7-1. Interrupt Control Circuit Block Diagram

Internal bus

2

1

4

IME IPS

IST1 IST0

Interrupt enable flag (IE×××

)

IM2

IM1

IM0

Decoder

IRQBT

IRQ4

INTBT

VRQn

Both edge

detector

INT4/P00

INT0/P10

Edge

detector

Selec-

tor

Note

IRQ0

Edge

detector

IRQ1

INT1/P11

Vector table

address

generator

Priority control

circuit

INTCSI

INTT0

INTT1

INTT2

INTW

IRQCSI

IRQT0

IRQT1

IRQT2

IRQW

IRQ2

µ

Rising edge

detector

INT2/P12

Selec-

tor

Standby release

signal

KR0/P60

KR3/P63

Falling edge

detector

IM2

Note Noise elimination circuit (Standby release is disabled when noise elimination circuit is selected.)

µPD753012A, 753016A, 753017A

8. STANDBY FUNCTION

In order to save power consumption while a program is in a standby mode, two types of standby modes (STOP

mode and HALT mode) are provided for the µPD753017A.

Table 8-1. Operation Status in Standby Mode

STOP Mode

STOP instruction

HALT Mode

HALT instruction

Set instruction

System clock when set

Settable only when the main system

clock is used.

Settable both by the main system

clock and subsystem clock.

Operation Clock generator

status

Only the main system clock stops

oscillation.

Only the CPU clock Φ halts (oscillation

continues).

Basic interval timer/

watchdog timer

Operation stops

Operation. (The IRQBT is set in the

reference interval.)^{Note 1}

Serial interface

Operable only when an external SCK

input is selected as the serial clock.

Operable^{Note 1}

Timer/event counter

Operable only when a signal input to the

TI0-TI2 pins is specified as the count

clock.

Operable^{Note 1}

Watch timer

Operable when fXT is selected as the

count clock.

Operable

Operable

LCD controller/driver

External interrupt

Operable only when fXT is selected as

the LCDCL.

The INT1, 2, and 4 are operable.

Only the INT0 is not operated.^{Note 2}

CPU

The operation stops.

Release signals

• Interrupt request signal sent from the operable hardware enabled by the interrupt

enable flag.

• Test request signal sent from the test source enabled by the test enable flag.

• RESET input

Notes 1. Cannot operate only when the main system clock stops.

2. Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection

mode register (IM0).

40

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

9. RESET FUNCTION

There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/

watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 9-

1 shows the circuit diagram of the above two inputs.

Figure 9-1. Configuration of Reset Function

RESET

Internal reset signal

Reset signal sent from the basic

interval timer/watchdog timer

WDTM

Internal bus

The µPD753017A is set by the RESET signal generated and each hardware is initialized as listed in Table

9-1. Figure 9-2 shows the timing chart of the reset operation.

Figure 9-2. Reset Operation by RESET Signal Generation

Wait ^Note

RESET

signal

generated

Operation mode or

standby mode

HALT mode

Operation mode

Internal reset operation

Note The following two times can be selected by the mask option.

2¹⁷/fX (21.8 ms : at 6.0 MHz operation, 31.3 ms : at 4.19 MHz operation)

2¹⁵/fX (5.46 ms : at 6.0 MHz operation, 7.81 ms : at 4.19 MHz operation)

Data Sheet U11662EJ2V1DS00

41

µPD753012A, 753016A, 753017A

Table 9-1. Status of Each Hardware after Reset (1/2)

RESET Signal Generation

in Standby Mode

RESET Signal Generation

in Operation

Hardware

Program counter (PC)

Sets the low-order 6 bits of

program memory’s address

Sets the low-order 6 bits of

program memory’s address

0000H to the PC13-PC8 and the 0000H to the PC13-PC8 and the

contents of address 0001H to contents of address 0001H to

the PC7-PC0. Resets the PC14 the PC7-PC0. Resets the PC14

of the µPD753017A to 0.

of the µPD753017A to 0.

PSW

Carry flag (CY)

Held

Undefined

Skip flag (SK0-SK2)

0

0

0

0

Interrupt status flag (IST0)

Bank enable flag (MBE, RBE)

Sets the bit 6 of program

Sets the bit 6 of program

memory’s address 0000H to

the RBE and bit 7 to the MBE.

memory’s address 0000H to

the RBE and bit 7 to the MBE.

Stack pointer (SP)

Undefined

Undefined

Stack bank select register (SBS)

Data memory (RAM)

1000B

1000B

Held

Undefined

General-purpose register (X, A, H, L, D, E, B, C)

Bank select register (MBS, RBS)

Held

Undefined

0, 0

0, 0

Basic interval

timer/

Counter (BT)

Undefined

Undefined

Mode register (BTM)

0

0

0

0

watchdog timer Watchdog timer enable flag (WDTM)

Timer/event

counter (T0)

Counter (T0)

0

0

Modulo register (TMOD0)

Mode register (TM0)

TOE0, TOUT F/F

FFH

0

FFH

0

0, 0

0

0, 0

0

Timer/event

counter (T1)

Counter (T1)

Modulo register (TMOD1)

Mode register (TM1)

TOE1, TOUT F/F

FFH

0

FFH

0

0, 0

0

0, 0

0

Timer/event

counter (T2)

Counter (T2)

Modulo register (TMOD2)

FFH

FFH

FFH

FFH

High level period setting modulo

register (TMOD2H)

Mode register (TM2)

TOE2, TOUT F/F

REMC, NRZ, NRZB

TGE

0

0, 0

0, 0, 0

0

0

0, 0

0, 0, 0

0

Watch timer

Mode register (WM)

0

0

42

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Table 9-1. Status of Each Hardware after Reset (2/2)

RESET Signal Generation

RESET Signal Generation

in Operation

Hardware

in Standby Mode

Serial interface

Shift register (SIO)

Held

Undefined

Operation mode register (CSIM)

SBI control register (SBIC)

0

0

0

0

Slave address register (SVA)

Processor clock control register (PCC)

System clock control register (SCC)

Clock output mode register (CLOM)

Held

Undefined

Clock generator,

clock output

circuit

0

0

0

0

0

0

Sub-oscillator control register (SOS)

0

0

LCD controller/

driver

Display mode register (LCDM)

0

0

Display control register (LCDC)

Interrupt request flag (IRQXXX)

Interrupt enable flag (IEXXX)

Interrupt master enable flag (IME)

INT0, 1, 2 mode registers (IM0, IM1, IM2)

Interrupt priority selection register (IPS)

Output buffer

0

0

Interrupt

Reset (0)

Reset (0)

function

0

0

0

0

0, 0, 0

0, 0, 0

0

0

Digital port

Off

Off

Output latch

Cleared (0)

Cleared (0)

I/O mode registers (PMGA, PMGB)

Pull-up resistor specification register (POGA)

0

0

0

0

Bit sequential buffer (BSB0-BSB3)

Held

Undefined

Data Sheet U11662EJ2V1DS00

43

µPD753012A, 753016A, 753017A

10. MASK OPTION

The µPD753017A has the following mask options.

• P40-P43, P50-P53 mask options

On-chip pull-up resistors can be connected.

<1> On-chip pull-up resistors are specifiable bit-wise.

<2> On-chip pull-up resistors are not specifiable.

• VLC0-VLC2 pins, BIAS pin mask option

On-chip split resistor for LCD drive can be connected.

<1> Split resistor is not connected.

<2> Four 10 kΩ (TYP.) split resistors are connected at the same time.

<3> Four 100 kΩ (TYP.) split resistors are connected at the same time.

• Standby function mask option

Wait times can be selected by a RESET signal.

<1> 2¹⁷/fX (21.8 ms : at fX = 6.0 MHz, 31.3 ms : at fX = 4.19 MHz)

<2> 2¹⁵/fX (5.46 ms : at fX = 6.0 MHz, 7.81 ms : at fX = 4.19 MHz)

• Subsystem clock mask option

Use of the internal feedback resistor can be selected.

<1> Internal feedback resistor can be used.

(Switched ON/OFF via software)

<2> Internal feedback resistor cannot be used.

(Switched out in hardware)

44

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

11. INSTRUCTION SET

(1) Expression formats and description methods of operands

The operand is described in the operand column of each instruction in accordance with the description

method for the operand expression format of the instruction. For details, refer to RA75X Assembler

Package User’s Manual——Language (U12385E). If there are several elements, one of them is selected.

Capital letters and the + and – symbols are key words and are described as they are.

For immediate data, appropriate numbers and labels are described.

Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described.

However, there are restrictions in the labels that can be described for fmem and pmem. For details, see

User’s Manual.

Expression

Description Method

Format

reg

X, A, B, C, D, E, H, L

X, B, C, D, E, H, L

reg1

rp

XA, BC, DE, HL

rp1

rp2

rp'

BC, DE, HL

BC, DE

XA, BC, DE, HL, XA', BC', DE', HL'

BC, DE, HL, XA', BC', DE', HL'

rp'1

rpa

HL, HL+, HL–, DE, DL

DE, DL

rpa1

n4

n8

4-bit immediate data or label

8-bit immediate data or label

mem

bit

8-bit immediate data or label^Note

2-bit immediate data or label

fmem

FB0H-FBFH, FF0H-FFFH immediate data or label

FC0H-FFFH immediate data or label

pmem

addr

0000H-2FFFH immediate data or label (µPD753012A)

0000H-3FFFH immediate data or label (µPD753016A, 753017A)

0000H-5FFFH immediate data or label

addr1

caddr

faddr

12-bit immediate data or label

11-bit immediate data or label

taddr

20H-7FH immediate data (where bit0 = 0) or label

PORTn

IEXXX

RBn

PORT0-PORT7

IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW

RB0-RB3

MBn

MB0, MB1, MB2, MB3, MB15

Note mem can be only used even address in 8-bit data processing.

Data Sheet U11662EJ2V1DS00

45

µPD753012A, 753016A, 753017A

(2) Legend in explanation of operation

A

: A register; 4-bit accumulator

: B register

B

C

: C register

D

: D register

E

: E register

H

: H register

L

: L register

X

: X register

XA

BC

DE

HL

XA'

BC'

DE'

HL'

PC

SP

CY

PSW

MBE

RBE

: XA register pair; 8-bit accumulator

: BC register pair

: DE register pair

: HL register pair

: XA' expanded register pair

: BC' expanded register pair

: DE' expanded register pair

: HL' expanded register pair

: Program counter

: Stack pointer

: Carry flag; bit accumulator

: Program status word

: Memory bank enable flag

: Register bank enable flag

PORTn : Port n (n = 0-7)

IME

IPS

: Interrupt master enable flag

: Interrupt priority selection register

: Interrupt enable flag

IEXXX

RBS

MBS

PCC

.

: Register bank selection register

: Memory bank selection register

: Processor clock control register

: Separation between address and bit

: The contents addressed by XX

: Hexadecimal data

(XX)

XXH

46

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

(3) Explanation of symbols under addressing area column

*1

MB = MBE•MBS

(MBS = 0-3, 15)

*2

*3

MB = 0

MBE = 0 : MB = 0 (000H-07FH)

MB = 15 (F80H-FFFH)

Data memory addressing

MBE = 1 : MB = MBS (MBS = 0-3, 15)

*4

*5

*6

MB = 15, fmem = FB0H-FBFH, FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

µPD753012A

addr = 0000H-2FFFH

addr = 0000H-3FFFH

µPD753016A

753017A

*7

µPD753012A

753016A

addr = (Current PC) – 15 to (Current PC) – 1

(Current PC) + 2 to (Current PC) + 16

753017A

(In Mk I mode)

µPD753017A

addr1 = (Current PC) – 15 to (Current PC) – 1

(Current PC) + 2 to (Current PC) + 16

(In Mk II mode)

*8

µPD753012A

caddr = 0000H-0FFFH (PC13, 12 = 00B) or

1000H-1FFFH (PC13, 12 = 01B) or

2000H-2FFFH (PC13, 12 = 10B)

µPD753016A

caddr = 0000H-0FFFH (PC13, 12 = 00B) or

1000H-1FFFH (PC13, 12 = 01B) or

2000H-2FFFH (PC13, 12 = 10B) or

3000H-3FFFH (PC13, 12 = 11B)

Program memory addressing

µPD753017A

caddr = 0000H-0FFFH (PC14, 13, 12 = 000B) or

1000H-1FFFH (PC14, 13, 12 = 001B) or

2000H-2FFFH (PC14, 13, 12 = 010B) or

3000H-3FFFH (PC14, 13, 12 = 011B) or

4000H-4FFFH (PC14, 13, 12 = 100B) or

5000H-5FFFH (PC14, 13, 12 = 101B)

*9

faddr = 0000H-07FFH

taddr = 0020H-007FH

*10

*11

µPD753012A

µPD753016A

µPD753017A

addr1 = 0000H-2FFFH

addr1 = 0000H-3FFFH

addr1 = 0000H-5FFFH

Remarks 1. MB indicates memory bank that can be accessed.

2. In *2, MB = 0 independently of how MBE and MBS are set.

3. In *4 and *5, MB = 15 independently of how MBE and MBS are set.

4. *6 to *11 indicate the areas that can be addressed.

Data Sheet U11662EJ2V1DS00

47

µPD753012A, 753016A, 753017A

(4) Explanation of number of machine cycles column

S denotes the number of machine cycles required by skip operation when a skip instruction is executed.

The value of S varies as follows.

•

•

•

When no skip is made: S = 0

When the skipped instruction is a 1- or 2-byte instruction: S = 1

When the skipped instruction is a 3-byte instruction^Note: S = 2

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle of CPU clock Φ (= t^CY); time can be selected from among four

types by setting PCC.

48

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

MOV

Operand

Operation

Skip Condition

String effect A

Area

Transfer

A, #n4

1

2

2

2

2

1

1

1

1

2

1

2

2

2

2

2

2

2

2

2

1

1

1

1

2

2

2

1

2

1

2

A ← n4

reg1, #n4

XA, #n8

HL, #n8

rp2, #n8

A, @HL

A, @HL+

A, @HL–

A, @rpa1

XA, @HL

@HL, A

@HL, XA

A, mem

XA, mem

mem, A

mem, XA

A, reg1

reg1 ← n4

XA ← n8

HL ← n8

rp2 ← n8

A ← (HL)

2

String effect A

String effect B

2

2

1

*1

*1

*1

*2

*1

*1

*1

*3

*3

*3

*3

2+S

2+S

1

A ← (HL), then L ← L+1

A ← (HL), then L ← L–1

A ← (rpa1)

L = 0

L = FH

2

XA ← (HL)

1

(HL) ← A

2

(HL) ← XA

2

A ← (mem)

2

XA ← (mem)

(mem) ← A

2

2

(mem) ← XA

A ← reg1

2

XA, rp'

2

XA ← rp'

reg1, A

2

reg1 ← A

rp'1, XA

A, @HL

A, @HL+

A, @HL–

A, @rpa1

XA, @HL

A, mem

XA, mem

A, reg1

2

rp'1 ← XA

XCH

1

A ↔ (HL)

*1

*1

*1

*2

*1

*3

*3

2+S

2+S

1

A ↔ (HL), then L ← L+1

A ↔ (HL), then L ← L–1

A ↔ (rpa1)

L = 0

L = FH

2

XA ↔ (HL)

2

A ↔ (mem)

2

XA ↔ (mem)

A ↔ reg1

1

XA, rp'

2

XA ↔ rp'

Data Sheet U11662EJ2V1DS00

49

µPD753012A, 753016A, 753017A

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

Operand

Operation

Skip Condition

Area

Table

reference

MOVT^{Note 1}XA, @PCDE

1

1

1

1

3

3

3

3

XA ← (PC13–8+DE)ROM

● µPD753017A

XA ← (PC^14–8+DE)ROM

XA, @PCXA

XA ← (PC13–8+XA)ROM

● µPD753017A

XA ← (PC^14–8+XA)ROM

XA, @BCDE^{Note 2}

XA ← (B1,0+CDE)ROM

*6

● µPD753017A

XA ← (B^2–0+CDE)ROM

*11

XA, @BCXA^{Note 2}

XA ← (B1,0+CXA)ROM

*6

● µPD753017A

*11

XA ← (B^2–0+CXA)ROM

Bit transfer

MOV1

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

fmem.bit, CY

pmem.@L, CY

@H+mem.bit, CY

A, #n4

2

2

2

2

2

2

1

2

1

2

2

1

2

2

1

2

2

1

2

2

2

2

CY ← (fmem.bit)

*4

*5

*1

*4

*5

*1

CY ← (pmem^7–2+L3–2.bit(L1–0))

CY ← (H+mem^3–0.bit)

(fmem.bit) ← CY

2

2

2

(pmem^7–2+L3–2.bit(L1–0)) ← CY

(H+mem^3–0.bit) ← CY

A ← A+n4

2

Operation

ADDS

1+S

2+S

1+S

2+S

2+S

1

carry

carry

carry

carry

carry

XA, #n8

XA ← XA+n8

A, @HL

A ← A+(HL)

*1

*1

*1

*1

XA, rp'

XA ← XA+rp'

rp'1, XA

rp'1 ← rp'1+XA

ADDC

SUBS

SUBC

A, @HL

A, CY ← A+(HL)+CY

XA, CY ← XA+rp'+CY

rp'1, CY ← rp'1+XA+CY

A ← A–(HL)

XA, rp'

2

rp'1, XA

2

A, @HL

1+S

2+S

2+S

1

borrow

borrow

borrow

XA, rp'

XA ← XA–rp'

rp'1, XA

rp'1 ← rp'1–XA

A, @HL

A, CY ← A–(HL)–CY

XA, CY ← XA–rp'–CY

rp'1, CY ← rp'1–XA–CY

XA, rp'

2

rp'1, XA

2

Notes 1. The above operations in the shaded boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

2. Only the following bits are valid for the B register.

µPD753012A, 753016A : low-order 2 bits

µPD753017A

: low-order 3 bits

Remark When the µPD753017A is set in the Mk I mode, PC14 is fixed to 0.

50

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

AND

Operand

Operation

Skip Condition

Area

Operation

A, #n4

2

1

2

2

2

1

2

2

2

1

2

2

1

2

1

1

2

2

1

2

2

2

1

2

2

2

1

1

1

1

2

1

A ← A n4

A, @HL

XA, rp'

rp'1, XA

A, #n4

A, @HL

XA, rp'

rp'1, XA

A, #n4

A, @HL

XA, rp'

rp'1, XA

A

A ← A (HL)

XA ← XA rp'

rp'1 ← rp'1 XA

A ← A n4

*1

2

2

OR

2

1

A ← A (HL)

XA ← XA rp'

rp'1 ← rp'1 XA

A ← A v n4

*1

*1

2

2

XOR

2

1

A ← A v (HL)

XA ← XA v rp'

rp'1 ← rp'1 v XA

2

2

Accumulator RORC

manipulation

NOT

1

CY ← A

A ← A

0, A

3

← CY, An–1 ← A

n

A

2

Increment

and

Decrement

INCS

reg

1+S

1+S

2+S

2+S

1+S

2+S

2+S

2+S

1+S

2+S

2+S

2+S

1

reg ← reg+1

rp1 ← rp1+1

reg = 0

rp1

rp1 = 00H

(HL) = 0

(mem) = 0

reg = FH

rp' = FFH

reg = n4

(HL) = n4

A = (HL)

XA = (HL)

A = reg

@HL

(HL) ← (HL)+1

(mem) ← (mem)+1

reg ← reg–1

rp' ← rp'–1

*1

*3

mem

DECS

reg

rp'

Comparison SKE

reg, #n4

@HL, #n4

A, @HL

XA, @HL

A, reg

XA, rp'

CY

Skip if reg = n4

Skip if (HL) = n4

Skip if A = (HL)

Skip if XA = (HL)

Skip if A = reg

Skip if XA = rp'

CY ← 1

*1

*1

*1

XA = rp'

Carry flag

manipulation

SET1

CLR1

SKT

CY

1

CY ← 0

CY

1+S

1

Skip if CY = 1

CY ← CY

CY = 1

NOT1

CY

Data Sheet U11662EJ2V1DS00

51

µPD753012A, 753016A, 753017A

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

SET1

Operand

Operation

Skip Condition

Area

Memory bit

manipulation

mem.bit

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

(mem.bit) ← 1

(fmem.bit) ← 1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

fmem.bit

pmem.@L

2

(pmem^7–2+L3–2.bit(L1–0)) ← 1

(H+mem^3–0.bit) ← 1

@H+mem.bit

mem.bit

2

CLR1

2

(mem.bit) ← 0

fmem.bit

2

(fmem.bit) ← 0

pmem.@L

2

(pmem^7-2+L3-2.bit(L1-0)) ← 0

(H+mem^3-0.bit) ← 0

@H+mem.bit

mem.bit

2

SKT

2+S

2+S

2+S

2+S

2+S

2+S

2+S

2+S

2+S

2+S

2+S

2

Skip if (mem.bit)=1

(mem.bit)=1

fmem.bit

Skip if (fmem.bit)=1

(fmem.bit)=1

(pmem.@L)=1

(@H+mem.bit)=1

(mem.bit)=0

pmem.@L

Skip if (pmem^7–2+L3–2.bit(L1–0))=1

Skip if (H+mem^3–0.bit)=1

Skip if (mem.bit)=0

@H+mem.bit

mem.bit

SKF

fmem.bit

Skip if (fmem.bit)=0

(fmem.bit)=0

(pmem.@L)=0

(@H+mem.bit)=0

(fmem.bit)=1

(pmem.@L)=1

(@H+mem.bit)=1

pmem.@L

Skip if (pmem^7–2+L3–2.bit(L1–0))=0

Skip if (H+mem^3–0.bit)=0

Skip if (fmem.bit)=1 and clear

Skip if (pmem^7–2+L3–2.bit(L1–0))=1 and clear

Skip if (H+mem^3–0.bit)=1 and clear

CY ← CY (fmem.bit)

@H+mem.bit

fmem.bit

SKTCLR

AND1

OR1

pmem.@L

@H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

2

CY ← CY (pmem^7–2+L3–2.bit(L1–0))

CY ← CY (H+mem^3–0.bit)

CY ← CY (fmem.bit)

2

2

2

CY ← CY (pmem^7–2+L3–2.bit(L1–0))

CY ← CY (H+mem^3–0.bit)

CY ← CY v (fmem.bit)

2

XOR1

2

2

CY ← CY v (pmem7–2+L3–2.bit(L1–0))

CY ← CY v (H+mem3–0.bit)

2

52

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

BR^{Note 1}

Operand

Operation

Skip Condition

Area

Branch

addr

–

–

PC13–0 ← addr

*6

Select appropriate instruction from

among the following instructions

according to the assembler being

used.

BR !addr

BRCB !caddr

BR $addr

addr1

–

–

● µPD753012A, 753016A

PC^13–0← addr1

*11

Select appropriate instruction from

among the following instructions

according to the assembler being

used.

BR !addr

BRA !addr1

BRCB !caddr

BR $addr1

● µPD753017A

PC^14–0← addr1

Select appropriate instruction from

among the following instructions

according to the assembler being

used.

BR !addr

BRA !addr1

BRCB !caddr

BR $addr1

!addr

3

3

PC^13–0← addr

*6

*7

● µPD753017A

PC¹⁴← 0, PC13–0 ← addr

$addr

1

1

2

2

PC^13–0← addr

$addr1

● µPD753017A

PC^14–0← addr1

PCDE

2

2

2

2

3

3

3

3

PC^13–0← PC13–8+DE

● µPD753017A

PC14–0 ← PC14–8+DE

PCXA

PC^13–0← PC13–8+XA

● µPD753017A

PC^14–0← PC14–8+XA

BCDE^{Note 2}

PC13–0 ← BCDE

*6

● µPD753017A

PC^14–0← BCDE

*11

BCXA^{Note 2}

PC13–0 ← BCXA

*6

● µPD753017A

PC^14–0← BCXA

*11

Notes 1. The above operations in the shaded boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

2. Only the following bits are valid for the B register.

µPD753012A, 753016A : low-order 2 bits

µPD753017A

: low-order 3 bits

Remark When the µPD753017A is set in the Mk I mode, PC14 is fixed to 0.

Data Sheet U11662EJ2V1DS00

53

µPD753012A, 753016A, 753017A

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

BRA^Note

Operand

Operation

Skip Condition

Area

Branch

!addr

3

3

2

3

3

2

● µPD753012A, 753016A

PC^13–0← addr

*6

!addr1

!caddr

● µPD753017A

PC^14–0← addr1

*11

*8

BRCB^Note

PC13–0 ← PC13,12+caddr11-0

● µPD753017A

PC^14–0← PC14,13,12+caddr11–0

Subroutine

stack control

CALLA^Note

!addr

!addr1

!addr

3

3

3

3

3

● µPD753012A, 753016A

(SP–6)(SP–3)(SP–4) ← PC^11–0

(SP–5) ← 0, 0, PC13, 12

(SP–2) ← ×, ×, MBE, RBE

PC^13–0← addr, SP ← SP–6

*6

*11

*6

● µPD753017A

(SP–6)(SP–3)(SP–4) ← PC^11–0

(SP–5) ← 0, PC14, 13, 12

(SP–2) ← ×, ×, MBE, RBE

PC^14–0← addr1, SP ← SP–6

CALL^Note

3

4

(SP–4)(SP–1)(SP–2) ← PC11–0

(SP–3) ← MBE, RBE, PC¹³, PC12

PC13–0 ← addr, SP ← SP–4

● µPD753012A, 753016A

(SP–6)(SP–3)(SP–4) ← PC^11–0

(SP–5) ← 0, 0, PC13, 12

(SP–2) ← ×, ×, MBE, RBE

PC^13–0← addr, SP ← SP–6

4

● µPD753017A

(SP–6)(SP–3)(SP–4) ← PC^11–0

(SP–5) ← 0, PC14, 13, 12

(SP–2) ← ×, ×, MBE, RBE

PC¹⁴← 0, PC13–0 ← addr, SP ← SP–6

CALLF^Note

!faddr

2

2

3

(SP–4)(SP–1)(SP–2) ← PC11–0

(SP–3) ← MBE, RBE, PC¹³, PC12

PC13–0 ← 000+faddr, SP ← SP–4

*9

● µPD753012A, 753016A

(SP–6)(SP–3)(SP–4) ← PC11–0

(SP–5) ← 0, 0, PC13, 12

(SP–2) ← ×, ×, MBE, RBE

PC^13–0← 000+faddr, SP ← SP–6

3

● µPD753017A

(SP–6)(SP–3)(SP–4) ← PC11–0

(SP–5) ← 0, PC14, 13, 12

(SP–2) ← ×, ×, MBE, RBE

PC^14–0← 0000+faddr, SP ← SP–6

Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

Remark When the µPD753017A is set in the Mk I mode, PC14 is fixed to 0.

54

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

RET^Note

Operand

Operation

Skip Condition

Area

Subroutine

stack control

1

3

MBE, RBE, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2),

SP ← SP+4

● µPD753012A, 753016A

×, ×, MBE, RBE ← (SP+4)

0, 0, PC¹³, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2), SP ← SP+6

● µPD753017A

×, ×, MBE, RBE ← (SP+4)

0, PC¹⁴, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2), SP ← SP+6

RETS^Note

1

3+S

MBE, RBE, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2),

SP ← SP+4

Unconditional

then skip unconditionally

● µPD753012A, 753016A

×, ×, MBE, RBE ← (SP+4)

0, 0, PC¹³, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2), SP ← SP+6

then skip unconditionally

● µPD753017A

×, ×, MBE, RBE ← (SP+4)

0, PC¹⁴, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2), SP ← SP+6

then skip unconditionally

RETI^Note

!faddr

1

3

MBE, RBE, PC13, PC12 ← (SP+1)

PC11–0 ← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

● µPD753012A, 753016A

0, 0, PC¹³, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

● µPD753017A

0, PC¹⁴, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

Remark When the µPD753017A is set in the Mk I mode, PC14 is fixed to 0.

Data Sheet U11662EJ2V1DS00

55

µPD753012A, 753016A, 753017A

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

PUSH

Operand

Operation

Skip Condition

Area

Subroutine

stack control

rp

1

2

1

2

2

2

2

2

2

2

2

2

2

2

1

2

2

1

1

2

1

2

2

2

2

2

2

2

2

2

2

2

1

2

2

3

(SP–1)(SP–2) ← rp, SP ← SP–2

(SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2

rp ← (SP+1)(SP), SP ← SP+2

MBS ← (SP+1), RBS ← (SP), SP ← SP+2

IME(IPS.3) ← 1

BS

rp

POP

EI

BS

Interrupt

control

IEXXX

IEXXX ← 1

DI

IME(IPS.3) ← 0

IEXXX

IEXXX ← 0

Input/output

IN^{Note 1}

A, PORTn

XA, PORTn

PORTn, A

PORTn, XA

A ← PORTn

(n = 0-7)

(n = 4, 6)

(n = 2-7)

(n = 4, 6)

XA ← PORTn+1, PORTn

PORTn ← A

OUT^{Note 1}

PORTn+1, PORTn ← XA

Set HALT mode (PCC.2 ← 1)

Set STOP mode (PCC.3 ← 1)

No operation

CPU control HALT

STOP

NOP

Special

SEL

RBn

MBn

RBS ← n

MBS ← n

(n = 0-3)

(n = 0-3, 15)

GETI^{Notes 2, 3}taddr

• When TBR instruction

*10

PC^13–0← (taddr)5–0+(taddr+1)

• When TCALL instruction

(SP–4)(SP–1)(SP–2) ← PC^11–0

(SP–3) ← MBE, RBE, PC13, PC12

PC13–0 ← (taddr)5–0+(taddr+1)

SP ← SP–4

• When instruction other than TBR and

TCALL instructions

(taddr) (taddr+1) instruction is executed

Depending on

the reference

instruction

1

3

4

● µPD753017A

• When TBR instruction

PC^13–0← (taddr)5–0+(taddr+1)

PC14 ← 0

• When TCALL instruction

(SP–6)(SP–3)(SP–4) ← PC^11–0

(SP–5) ← 0, 0, PC13, 12

(SP–2) ← ×, ×, MBE, RBE

PC13–0 ← (taddr)5–0+(taddr+1)

SP ← SP–6, PC¹⁴← 0

3

• When instruction other than TBR and

TCALL instructions

(taddr) (taddr+1) instruction is executed

Depending on

the reference

instruction

Notes 1. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and

MBS must be set to 15.

2. The above operations in the shaded boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

3. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI

instruction.

Remark When the µPD753017A is set in the Mk I mode, PC14 is fixed to 0.

56

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

12. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter

Supply voltage

Symbol

VDD

Conditions

Ratings

–0.3 to +7.0

–0.3 to VDD + 0.3

–0.3 to VDD + 0.3

–0.3 to +14

–0.3 to VDD + 0.3

–10

Unit

V

Input voltage

VI1

Other than ports 4, 5

V

VI2

Ports Pull-up resistor provided

V

4, 5

N-ch open-drain

V

Output voltage

VO

IOH

V

High-level output current

Per pin

mA

mA

mA

mA

°C

Total of all pins

Per pin

–30

Low-level output current

IOL

30

Total of all pins

220

Operating ambient

temperature

T^A

–40 to +85

Storage temperature

Tstg

–65 to +150

°C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Capacitance (T^A= 25°C, VDD = 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

CIN

Conditions

MIN.

TYP.

MAX.

15

Unit

pF

f = 1 MHz

Unmeasured pins returned to 0 V

COUT

CIO

15

pF

15

pF

Data Sheet U11662EJ2V1DS00

57

µPD753012A, 753016A, 753017A

Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Recommended

Circuit

Resonator

Parameter

Conditions

MIN.

1.0

TYP. MAX.

Unit

Ceramic

resonator

Oscillation frequency

(fX)^{Note 1}

6.0^{Note 2}MHz

X1

X2

Oscillation

stabilization time^{Note 3}

After VDD has

4

ms

C1

C2

reached MIN. value of

oscillation voltage

range

V

DD

Crystal

resonator

Oscillation frequency

(fX)^{Note 1}

1.0

6.0^{Note 2}MHz

X1

X2

Oscillation

stabilization time^{Note 3}

VDD = 4.5 to 5.5 V

10

30

ms

C1

C2

V

DD

External

clock

X1 input frequency

(f^X)^{Note 1}

1.0

6.0^{Note 2}MHz

X1

X2

X1 input high-,

low-level width

(t^XH, tXL)

83.3

500

ns

Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator

only. For the instruction execution time, refer to AC Characteristics.

2. If the oscillation frequency is 4.19 MHz < f^X≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, do not set the processor

clock control register (PCC) to 0011. If PCC = 0011, one machine cycle time is less than 0.95 µs, falling

short of the rated value of 0.95 µs.

3. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been

applied or STOP mode has been released.

Caution When using the main system clock oscillator, wire the portion enclosed in the dotted line in

the above figure as follows to prevent adverse influence due to wiring capacitance:

· Keep the wiring length as short as possible.

· Do not cross the wiring with other signal lines.

· Do not route the wiring in the vicinity of a line through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillator at the same potential as V^DD.

· Do not ground to a power supply pattern through which a high current flows.

· Do not extract signals from the oscillator.

58

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Recommended Oscillator Constant

Ceramic resonator (T^A= –20 to +80°C)

Manufacturer

Part Number

Frequency Recommended Circuit

Oscillation Voltage

Range (V)

Remarks

(MHz)

Constant (pF)

C1

C2

100

–

MIN.

1.8

MAX.

5.5

TDK Corp.

CCR1000K2

1.0

2.0

100

–

–

CCR2.0MC33

CCR4.19MC3

FCR4.19MC5

CCR6.0MC3

On-chip capacitor

4.19

6.0

1.0

2.0

Murata Mfg.

Co., Ltd.

CSB1000J^Note

CSA2.00MG040

CST2.00MG040

CSA4.19MG

100

100

–

100

100

–

2.1

1.9

5.5

Rd = 5.6 kΩ

–

On-chip capacitor

4.19

6.0

30

–

30

–

1.8

2.3

1.8

–

CST4.19MGW

CSA6.00MG

On-chip capacitor

30

–

30

–

–

CST6.00MGW

On-chip capacitor

–

Kyocera Corp. KBR-1000F/Y

KBR-2.0MS

1.0

2.0

4.0

100

68

33

–

100

68

33

–

5.5

KBR-4.0MSA/MSB

KBR-4.0MKC

KBR-4.0MKD

KBR-4.0MKS

PBRC4.00A

On-chip capacitor

4.0

33

–

33

–

–

PBRC4.00B

On-chip capacitor

–

KBR-4.19MSA

KBR-4.19MSB

KBR-4.19MKC

KBR-4.19MKD

KBR-4.19MKS

PBRC4.19A

4.19

33

33

–

33

33

–

On-chip capacitor

33

–

33

–

–

PBRC4.19B

On-chip capacitor

–

KBR-6.0MSA/MSB

KBR-6.0MKC

KBR-6.0MKD

KBR-6.0MKS

PBRC6.00A

6.0

33

–

33

–

On-chip capacitor

33

–

33

–

–

PBRC6.00B

On-chip capacitor

Data Sheet U11662EJ2V1DS00

59

µPD753012A, 753016A, 753017A

Note When using the CSB1000J (1.0 MHz) by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor

(Rd = 5.6 kΩ) is necessary (refer to the figure below). The resistor is not necessary when using the other

recommended resonators.

X1

X2

Rd

CSB1000J

C1

C2

Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.

Oscillation frequency precision is not guaranteed. For applications requiring oscillation

frequency precision, the oscillation frequency must be adjusted on the implementation circuit.

For details, please contact directly the manufacturer of the resonator you will use.

60

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Recommended

Circuit

Resonator

Parameter

Conditions

MIN. TYP. MAX.

Unit

kHz

Crystal

resonator

Oscillation frequency

(fXT)^{Note 1}

32

32.768

35

XT1

XT2

R

Oscillation

stabilization time^{Note 2}

VDD = 4.5 to 5.5 V

1.0

2

s

C3

C4

VDD

10

External

clock

XT1 input frequency

(fXT)^{Note 1}

32

5

100

kHz

XT1

XT2

XT1 input high-,

low-level width

(t^XTH, tXTL)

15

µs

Notes 1. The oscillation frequency shown above indicates characteristics of the oscillator only. For the

instruction execution time, refer to AC Characteristics.

2. The oscillation stabilization time is the time required for oscillation to be stabilized after V^DDhas been

applied.

Caution When using the subsystem clock oscillator, wire the portion enclosed in the dotted line in the

above figure as follows to prevent adverse influence due to wiring capacitance:

· Keep the wiring length as short as possible.

· Do not cross the wiring with other signal lines.

· Do not route the wiring in the vicinity of a line through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillator at the same potential as V^DD.

· Do not ground to a power supply pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

The subsystem clock oscillator has a low amplification factor to reduce current consumption

and is more susceptible to noise than the main system clock oscillator. Therefore, exercise

utmost care in wiring the subsystem clock oscillator.

Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U11662EJ2V1DS00

61

µPD753012A, 753016A, 753017A

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

Low-level output

current

Symbol

Conditions

MIN.

TYP.

MAX.

15

Unit

mA

mA

V

IOL

Per pin

Total of all pins

Ports 2, 3

150

High-level input

voltage

VIH1

VIH2

VIH3

VDD = 2.7 to 5.5 V

VDD = 1.8 to 2.7 V

VDD = 2.7 to 5.5 V

VDD = 1.8 to 2.7 V

VDD = 2.7 to 5.5 V

VDD = 1.8 to 2.7 V

0.7 VDD

0.9 VDD

0.8 VDD

0.9 VDD

0.7 VDD

0.9 VDD

0.7 VDD

0.9 VDD

VDD–0.1

0

VDD

VDD

V

Ports 0, 1, 6, 7, RESET

VDD

V

VDD

V

Ports 4, 5 Pull-up resistor

provided

VDD

V

VDD

V

N-ch open-drain VDD = 2.7 to 5.5 V

VDD = 1.8 to 2.7 V

13

V

13

V

VIH4

VIL1

X1, XT1

VDD

V

Low-level input

voltage

Ports 2, 3, 4, 5

Ports 0, 1, 6, 7, RESET

X1, XT1

VDD = 2.7 to 5.5 V

VDD = 1.8 to 2.7 V

VDD = 2.7 to 5.5 V

VDD = 1.8 to 2.7 V

0.3 VDD

0.1 VDD

0.2 VDD

0.1 VDD

0.1

V

0

V

VIL2

0

V

0

V

VIL3

0

V

High-level output

voltage

V^OH

SCK, SO, Ports 2, 3, 6, 7, BP0-BP7 IOH = –1 mA

VDD–0.5

V

Low-level output

voltage

V^OL1

SCK, SO, Ports 2-7,

BP0-BP7

IOL = 15 mA

0.2

2.0

V

VDD = 5.0 V ±10%

IOL = 1.6 mA

0.4

V

V

V^OL2

SB0, SB1 N-ch open-drain

0.2 VDD

Pull-up resistor ≥ 1 kΩ

High-level input

leakage current

ILIH1

ILIH2

ILIH3

ILIL1

ILIL2

I^LIL3

VIN = VDD

Pins other than X1, XT1, ports 4, 5

X1, XT1

3

20

20

–3

–20

–3

µA

µA

µA

µA

µA

µA

VIN = 13 V Ports 4, 5 (N-ch open-drain)

Low-level input

leakage current

VIN = 0 V

Pins other than X1, XT1, ports 4, 5

X1, XT1

Ports 4, 5 (N-ch open-drain)

When input instruction is not executed

Ports 4, 5 (N-ch

–30

–27

–8

µA

µA

µA

open-drain)

When input

instruction is

executed

VDD = 5 V

VDD = 3 V

–10

–3

High-level output

leakage current

ILOH1

VOUT = VDD SCK, SO/SB0, SB1, ports 2, 3, 6, 7,

ports 4, 5 (pull-up resistor provided),

BP0-BP7

3

µA

ILOH2

ILOL

VOUT = 13 V Ports 4, 5 (N-ch open-drain)

VOUT = 0 V

20

–3

µA

µA

Low-level output

leakage current

Internal pull-up

resistor

RL1

RL2

VIN = 0 V

Ports 0, 1, 2, 3, 6, 7 (except P00 pin)

Ports 4, 5 (mask option selected)

50

15

100

30

200

60

kΩ

kΩ

62

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

LCD drive

Symbol

Conditions

MIN.

2.2

TYP.

MAX.

VDD

VDD

4

Unit

V

VLCD

VAC0 = 0

VAC0 = 1

voltage^{Note 1}

1.8

V

VAC current^{Note 2}

IVAC

VAC0 = 1, VDD = 2.0 V ±10%

1

µA

kΩ

kΩ

V

LCD split

RLCD1

RLCD2

VODC

50

5

100

10

200

20

resistor^{Note 3}

LCD output voltage

deviation^{Note 4}

(common)

IO =

VLCD0 = VLCD

0

±0.2

±1.0 µA

VLCD1 = VLCD × 2/3

VLCD2 = VLCD × 1/3

1.8 V ≤ VLCD ≤ VDD

LCD output voltage

deviation^{Note 4}

(segment)

VODS

IO =

0

±0.2

V

±0.5 µA

6

6.00 MHz^Note

crystal

Supply

IDD1

IDD2

IDD1

IDD2

IDD3

VDD = 5.0 V ±10%^{Note 7}

VDD = 3.0 V ±10%^{Note 8}

2.2

0.6

0.72

0.27

1.7

0.3

0.7

0.23

15

6.6

2.0

2.1

0.8

5.1

0.9

2.0

0.7

45

24

30

36

24

25

12

17

12

7

mA

mA

mA

mA

mA

mA

mA

mA

µA

µA

µA

µA

µA

µA

µA

µA

µA

µA

µA

µA

µA

current^{Notes 2, 5}

oscillation

C1 = C2

= 22 pF

HALT

mode

VDD = 5.0 V ±10%

VDD = 3.0 V ±10%

VDD = 5.0 V ±10%^{Note 7}

VDD = 3.0 V ±10%^{Note 8}

6

4.19 MHz^Note

crystal

oscillation

C1 = C2

= 22 pF

HALT

mode

VDD = 5.0 V ±10%

VDD = 3.0 V ±10%

VDD = 3.0 V ±10%

VDD = 2.0 V ±10%

VDD = 3.0 V, TA = 25°C

VDD = 3.0 V ±10%

VDD = 3.0 V, TA = 25°C

32.768

Low

voltage

mode^{Note 10}

kHz^{Note 9}

8

crystal

15

Low

12

oscillation

current

consumption

mode^{Note 11}

12

IDD4

HALT

mode

Low

V

V

V

V

V

DD = 3.0 V ±10%

DD = 2.0 V ±10%

8.5

4

voltage

mode^{Note 10}

DD = 3.0 V, T

A

= 25°C

8.5

3.5

3.5

0.05

0.02

0.02

Low

DD = 3.0 V ±10%

current

consumption

mode^{Note 11}

DD = 3.0 V, T = 25°C

A

IDD5

XT1 =

VDD = 5.0 V ±10%

VDD = 3.0 V ±10%

10

5

0 V^{Note 12}

STOP mode

TA = 25°C

3

Notes 1. When 1.8 V ≤ VDD < 2.7 V, TA = –10 to +85°C.

2. Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the

current increases by about 1 µA.

3. Either RLCD1 or RLCD2 can be selected by mask option.

4. Voltage deviation is the difference between the ideal values (V^LCDn; n = 0, 1, 2) of the segment and

common outputs and the output voltage.

5. The current flowing through the internal pull-up resistor and the LCD divider resistor is not included.

6. Including the case when the subsystem clock oscillates.

7. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011.

8. When the device operates in low-speed mode with PCC set to 0000.

9. When the device operates on the subsystem clock, with the system clock control register (SCC) set

to 1001 and oscillation of the main system clock stopped.

10. When the sub-oscillator control register (SOS) is set to 0000.

11. When SOS is set to 0010.

12. When SOS is set to 00X1, and the feedback resistor of the sub-oscillator is not used (X: don’t care).

Data Sheet U11662EJ2V1DS00

63

µPD753012A, 753016A, 753017A

AC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

CPU clock cycle time^{Note 1}

(minimum instruction

execution time = 1

Symbol

Conditions

MIN.

0.67

0.95

114

TYP.

122

MAX.

64

Unit

µs

tCY

Operates with

VDD = 2.7 to 5.5 V

main system clock

Operates with

64

µs

125

µs

machine cycle)

subsystem clock

VDD = 2.7 to 5.5 V

TI0, TI1, TI2 input frequency

fTI

0

0

1

MHz

kHz

µs

275

TI0, TI1, TI2 input high-,

low-level width

tTIH, tTIL

VDD = 2.7 to 5.5 V

INT0

0.48

1.8

Note 2

10

µs

Interrupt input high-,

low-level width

tINTH, tINTL

IM02 = 0

IM02 = 1

µs

µs

INT1, 2, 4

KR0-KR7

10

µs

10

µs

RESET low-level width

tRSL

10

µs

Notes 1. The cycle time of the CPU clock (Φ) is

determined by the oscillation frequency

of the connected resonator, the system

clock control register (SCC), and

processor clock control register (PCC).

The figure on the right shows the supply

voltage V^DDvs. cycle time tCY

characteristicswhenthedeviceoperates

with the main system clock.

t

CY vs VDD

(with main system clock)

64

60

6

5

Operation guaranteed range

4

3

µ

2. 2t^CYor 128/fX depending on the setting

of the interrupt mode register (IM0).

2

1

0.5

0

1

2

3

4

5

6

Supply voltage VDD [V]

64

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Serial transfer operation

2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (T^A= –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

SCK cycle time

Symbol

Conditions

VDD = 2.7 to 5.5 V

MIN.

1300

3800

tKCY1/2–50

tKCY1/2–150

150

TYP.

MAX.

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

tKCY1

SCK high-, low-level width

tKL1

tKH1

tSIK1

VDD = 2.7 to 5.5 V

VDD = 2.7 to 5.5 V

VDD = 2.7 to 5.5 V

SI^{Note 1}setup time

(to SCK ↑)

500

SI^{Note 1}hold time

tKSI1

400

(from SCK ↑)

600

Note 2

SCK ↓ → SO^{Note 1}

output delay time

tKSO1

RL = 1 kΩ,

VDD = 2.7 to 5.5 V

0

250

C^L= 100 pF

0

1000

Notes 1. Read as SB0 or SB1 when using the 2-wire serial I/O mode.

2. R^Land CL respectively indicate the load resistance and load capacitance of the SO output line.

2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

SCK cycle time

Symbol

Conditions

VDD = 2.7 to 5.5 V

MIN.

800

3200

400

1600

100

150

400

600

0

TYP.

MAX.

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

tKCY2

SCK high-, low-level width

tKL2

tKH2

tSIK2

VDD = 2.7 to 5.5 V

VDD = 2.7 to 5.5 V

VDD = 2.7 to 5.5 V

SI^{Note 1}setup time

(to SCK ↑)

SI^{Note 1}hold time

tKSI2

(from SCK ↑)

Note 2

SCK ↓ → SO^{Note 1}

output delay time

tKSO2

RL = 1 kΩ,

VDD = 2.7 to 5.5 V

300

CL = 100 pF

0

1000

Notes 1. Read as SB0 or SB1 when using the 2-wire serial I/O mode.

2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.

Data Sheet U11662EJ2V1DS00

65

µPD753012A, 753016A, 753017A

SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

SCK cycle time

Symbol

Conditions

VDD = 2.7 to 5.5 V

MIN.

1300

3800

tKCY3/2–50

tKCY3/2–150

150

TYP.

MAX.

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

tKCY3

SCK high-, low-level width

tKL3

tKH3

tSIK3

VDD = 2.7 to 5.5 V

VDD = 2.7 to 5.5 V

SB0, 1 setup time

(to SCK ↑)

500

SB0, 1 hold time (from SCK ↑) tKSI3

tKCY3/2

0

Note

SCK ↓ → SB0, 1 output

delay time

tKSO3

RL = 1 kΩ,

VDD = 2.7 to 5.5 V

250

CL = 100 pF

0

1000

SCK ↑ → SB0, 1 ↓

SB0, 1 ↓ → SCK ↓

SB0, 1 low-level width

SB0, 1 high-level width

tKSB

tSBK

tSBL

tSBH

tKCY3

tKCY3

tKCY3

tKCY3

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.

SBI mode (SCK ··· external clock input (slave)): (T^A= –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

SCK cycle time

Symbol

Conditions

VDD = 2.7 to 5.5 V

MIN.

800

3200

400

1600

100

150

tKCY4/2

0

TYP.

MAX.

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

tKCY4

SCK high-, low-level width

tKL4

tKH4

tSIK4

VDD = 2.7 to 5.5 V

VDD = 2.7 to 5.5 V

SB0, 1 setup time

(to SCK ↑)

SB0, 1 hold time (from SCK ↑) tKSI4

Note

SCK ↓ → SB0, 1 output

delay time

tKSO4

RL = 1 kΩ,

VDD = 2.7 to 5.5 V

300

CL = 100 pF

0

1000

SCK ↑ → SB0, 1 ↓

SB0, 1 ↓ → SCK ↓

SB0, 1 low-level width

SB0, 1 high-level width

tKSB

tSBK

tSBL

tSBH

tKCY4

tKCY4

tKCY4

tKCY4

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.

66

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

AC timing test points (except X1 and XT1 inputs)

V

V

IH (MIN.)

IL (MAX.)

V

IH (MIN.)

IL (MAX.)

V

V

OH (MIN.)

OL (MAX.)

V

OH (MIN.)

OL (MAX.)

V

V

Clock timing

1/fX

tXL

t

XH

VDD – 0.1 V

X1 input

0.1 V

1/fXT

tXTL

tXTH

VDD – 0.1 V

XT1 input

0.1 V

TI0, TI1, TI2 timing

1/fTI

t

TIL

t

TIH

TI0, TI1, TI2

Data Sheet U11662EJ2V1DS00

67

µPD753012A, 753016A, 753017A

Serial transfer timing

3-wire serial I/O mode

tKCY1,2

tKL1,2

tKH1,2

SCK

tSIK1,2

tKSI1,2

Input data

SI

tKSO1,2

Output data

SO

2-wire serial I/O mode

tKCY1,2

t

KL1,2

t

KH1,2

SCK

t

SIK1,2

tKSI1,2

SB0, 1

t

KSO1,2

68

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Serial transfer timing

Bus release signal transfer

t

KCY3, 4

t

KL3, 4

tKH3, 4

SCK

t

SIK3, 4

t

KSB

t

SBL

t

SBH

t

SBK

t

KSI3, 4

SB0, 1

t

KSO3, 4

Command signal transfer

t

KCY3, 4

t

KL3, 4

t

KH3, 4

SCK

t

SIK3, 4

t

KSB

t

SBK

t

KSI3, 4

SB0, 1

t

KSO3, 4

Interrupt input timing

t

INTL

t

INTH

INT0, 1, 2, 4

KR0-7

RESET input timing

t

RSL

RESET

Data Sheet U11662EJ2V1DS00

69

µPD753012A, 753016A, 753017A

Data retention characteristics of data memory in STOP mode and at low supply voltage

(T^A= –40 to +85°C)

Parameter

Symbol

V^DDDR

Conditions

MIN.

1.8

TYP.

MAX.

5.5

Unit

V

Data retention power supply

voltage

Release signal setup time

tSREL

tWAIT

0

µs

ms

ms

Oscillation stabilization

wait time^{Note 1}

Released by RESET

Note 2

Note 3

Released by interrupt request

Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent

unstable operation when oscillation is started.

2. Either 2¹⁷/fX or 2¹⁵/fX can be selected by mask option.

3. Set by the basic interval timer mode register (BTM). (Refer to the table below.)

Wait Time

BTM3

BTM2

BTM1

BTM0

fX = 4.19 MHz

fX = 6.0 MHz

–

–

–

–

0

0

1

1

0

1

0

1

0

1

1

1

2²⁰/fX (approx. 250 ms)

2¹⁷/fX (approx. 31.3 ms)

2¹⁵/fX (approx. 7.81 ms)

2¹³/fX (approx. 1.95 ms)

2²⁰/fX (approx. 175 ms)

2¹⁷/fX (approx. 21.8 ms)

2¹⁵/fX (approx. 5.46 ms)

2¹³/fX (approx. 1.37 ms)

Data retention timing (when STOP mode released by RESET)

Internal reset operation

HALT mode

STOP mode

Operation mode

Data retention mode

V

DD

V

DDDR

t

SREL

STOP instruction execution

RESET

t

WAIT

Data retention timing (standby release signal: when STOP mode released by interrupt signal)

HALT mode

STOP mode

Operation mode

Data retention mode

t

SREL

VDD

VDDDR

STOP instruction execution

Standby release signal

(interrupt request)

tWAIT

70

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

13. CHARACTERISTICS CURVES (REFERENCE VALUES)

I

DD vs VDD (f = 4.19 MHz, fXT = 32.768 kHz)

X

(TA = 25°C)

10

5.0

PCC = 0011

1.0

0.5

PCC = 0010

PCC = 0001

PCC = 0000

Main system clock HALT

mode + 32 kHz oscillation

0.1

0.05

Subsystem clock operation

mode (SOS.1 = 0)

Subsystem clock HALT

mode (SOS.1 = 1)

Main system clock STOP

mode + 32 kHz oscillation

(SOS.1 = 1)

0.01

0.005

X1

X2 XT1

Crystal

XT2

Crystal

resonator

4.19 MHz

resonator

32.768 MHz

330 kΩ

22 pF

22 pF

22 pF

22 pF

V

SS

V

SS

0.001

0

2

3

7

1

1.8

4

5

6

5.5

Supply voltage V^DD(V)

Data Sheet U11662EJ2V1DS00

71

µPD753012A, 753016A, 753017A

I

OH vs VDD–VOH (Ports 2, 3, 6, 7)

(T

A

= 25°C)

15

10

5

V

DD = 5 V

V

DD = 4 V

DD = 3 V

V

DD = 2.2 V

VDD = 5.5 V

V

V

DD = 1.8 V

0

0

0.5

1.0

2.0

1.5

2.5

3.0

V

DD–VOH [V]

I

OL vs VOL (Ports 2, 3, 6, 7)

(T = 25°C)

A

40

30

20

10

0

V

DD = 5 V V^DD= 4 V

V

DD = 5.5 V

VDD = 3 V

V

DD = 2.2 V

V

DD = 1.8 V

0

0.5

1.0

2.0

1.5

V

OL [V]

72

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

14. PACKAGE DRAWINGS

80-PIN PLASTIC QFP (14x14)

A

B

60

61

41

40

detail of lead end

S

C D

R

Q

21

20

80

1

F

G

J

M

H

I

K

P

S

N

S

L

M

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

A

B

C

D

F

G

H

I

17.2±0.4

14.0±0.2

14.0±0.2

17.2±0.4

0.825

0.825

0.30±0.10

0.13

J

0.65 (T.P.)

1.6±0.2

0.8±0.2

K

L

+0.10

0.15

M

−0.05

N

P

Q

R

S

0.10

2.7±0.1

0.1±0.1

5°±5°

3.0 MAX.

S80GC-65-3B9-6

Data Sheet U11662EJ2V1DS00

73

µPD753012A, 753016A, 753017A

80-PIN PLASTIC QFP (14x14)

A

B

60

61

41

40

detail of lead end

S

C

D

R

Q

80

21

20

1

F

J

M

G

H

I

P

K

S

N

S

L

M

NOTE

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

D

F

G

H

I

17.20±0.20

14.00±0.20

14.00±0.20

17.20±0.20

0.825

0.825

0.32±0.06

0.13

J

0.65 (T.P.)

1.60±0.20

0.80±0.20

K

L

+0.03

0.17

M

−0.07

N

P

0.10

1.40±0.10

0.125±0.075

Q

+7°

3°

R

S

−3°

1.70 MAX.

P80GC-65-8BT-1

74

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

80 PIN PLASTIC TQFP (FINE PITCH) (12x12)

A

B

60

41

61

40

detail of lead end

S

C

D

Q

R

80

21

1

20

F

P

M

G

H

I

J

K

M

S

N

S

L

NOTE

Each lead centerline is located within 0.10 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

D

F

14.00±0.20

12.00±0.20

12.00±0.20

14.00±0.20

1.25

G

1.25

+0.05

0.22

H

–0.04

I

0.10

J

0.50 (T.P.)

1.00±0.20

0.50±0.20

K

L

+0.055

0.145

M

–0.045

N

P

Q

R

S

0.10

1.05±0.07

0.10±0.05

5°±5°

1.27 MAX.

P80GK-50-BE9-6

Data Sheet U11662EJ2V1DS00

75

µPD753012A, 753016A, 753017A

80-PIN PLASTIC TQFP (FINE PITCH) (12x12)

A

B

60

41

61

40

detail of lead end

S

C

D

P

T

R

80

21

L

1

20

U

Q

F

M

G

J

H

I

K

S

M

N

S

NOTE

Each lead centerline is located within 0.08 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

D

F

G

H

I

14.0±0.2

12.0±0.2

12.0±0.2

14.0±0.2

1.25

1.25

0.22±0.05

0.08

J

0.5 (T.P.)

1.0±0.2

0.5

K

L

M

N

P

Q

0.145±0.05

0.08

1.0

0.1±0.05

+4°

3°

R

−3°

S

T

1.1±0.1

0.25

U

0.6±0.15

P80GK-50-9EU-1

76

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

15. RECOMMENDED SOLDERING CONDITIONS

Solder the µPD753017A under the following recommended conditions.

For the details on the recommended soldering conditions, refer to Information Document Semiconductor

Device Mounting Technology Manual (C10535E).

For the soldering methods and conditions other than those recommended, consult NEC.

Table 15-1. Soldering Conditions of Surface Mount Type (1/2)

(1) µPD753012AGC-XXX-3B9: 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

µPD753016AGC-XXX-3B9: 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

µPD753017AGC-XXX-3B9: 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

Soldering Method

Infrared reflow

Soldering Conditions

Symbol

Package peak temperature: 235°C, Reflow time: 30 seconds or below

(210°C or higher), Number of reflow processes: 3 max.

IR35-00-3

VPS

Package peak temperature: 215°C, Reflow time: 40 seconds or below

(200°C or higher), Number of reflow processes: 3 max.

VP15-00-3

WS60-00-1

Wave soldering

Solder temperature: 260°C or below, Time: 10 seconds or below,

Number of flow processes: 1

Preheating temperature: 120°C or below (package surface temperature)

Partial heating

Pin temperature: 300°C or below, Time: 3 seconds or below

–

(per side of device)

(2) µPD753012AGC-XXX-8BT: 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

µPD753016AGC-XXX-8BT: 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

µPD753017AGC-XXX-8BT: 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

Soldering Method

Infrared reflow

Soldering Conditions

Symbol

Package peak temperature: 235°C, Reflow time: 30 seconds or below

(210°C or higher), Number of reflow processes: 2 max.

IR35-00-2

VPS

Package peak temperature: 215°C, Reflow time: 40 seconds or below

(200°C or higher), Number of reflow processes: 2 max.

VP15-00-2

WS60-00-1

Wave soldering

Solder temperature: 260°C or below, Time: 10 seconds or below,

Number of flow processes: 1

Preheating temperature: 120°C or below (package surface temperature)

Partial heating

Pin temperature: 300°C or below, Time: 3 seconds or below

–

(per side of device)

Caution Do not use two or more soldering methods in combination (except the partial heating method).

Data Sheet U11662EJ2V1DS00

77

µPD753012A, 753016A, 753017A

Table 15-1. Soldering Conditions of Surface Mount Type (2/2)

(3) µPD753012AGK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)

µPD753016AGK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)

µPD753017AGK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)

Soldering Method

Infrared reflow

Soldering Conditions

Symbol

Package peak temperature: 235°C, Reflow time: 30 seconds or below

(210°C or higher), Number of reflow processes: 3 max., Exposure limit:

7 days^Note(After that, prebaking is necessary at 125°C for 10 hours.)

IR35-107-3

VPS

Package peak temperature: 215°C, Reflow time: 40 seconds or below

(200°C or higher), Number of reflow processes: 3 max., Exposure limit:

7 days^Note(After that, prebaking is necessary at 125°C for 10 hours.)

VP15-107-3

–

Partial heating

Pin temperature: 300°C or below, Time: 3 seconds or below

(per side of device)

Note The number of days for storage after the dry pack has been opened. The storage conditions are

25°C, 65% RH max.

(4) µPD753012AGK-XXX-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

µPD753016AGK-XXX-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

µPD753017AGK-XXX-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

Soldering Method

Infrared reflow

Soldering Conditions

Symbol

Package peak temperature: 235°C, Reflow time: 30 seconds or below

(210°C or higher), Number of reflow processes: 2 max., Exposure limit:

7 days^Note(After that, prebaking is necessary at 125°C for 10 hours.)

IR35-107-2

VPS

Package peak temperature: 215°C, Reflow time: 40 seconds or below

(200°C or higher), Number of reflow processes: 2 max., Exposure limit:

7 days^Note(After that, prebaking is necessary at 125°C for 10 hours.)

VP15-107-2

–

Partial heating

Pin temperature: 300°C or below, Time: 3 seconds or below

(per side of device)

Note The number of days for storage after the dry pack has been opened. The storage conditions are

25°C, 65% RH max.

Caution Do not use two or more soldering methods in combination (except the partial heating method).

78

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

APPENDIX A. µPD75316B, 753017A AND 75P3018A FUNCTION LIST

Parameter

Program memory

µPD75316B

µPD753017A

µPD75P3018A

Mask ROM

0000H-3F7FH

(16256 × 8 bits)

Mask ROM

0000H-5FFFH

(24576 × 8 bits)

One-time PROM

0000H-7FFFH

(32768 × 8 bits)

Data memory

CPU

000H-3FFH

(1024 × 4 bits)

75X Standard

75XL CPU

Instruction

execution

time

When main system

clock is selected

0.95, 1.91, 15.3 µs

(at 4.19 MHz operation)

•

•

0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz operation)

0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation)

When subsystem

clock is selected

122 µs (32.768 kHz operation)

Pin

connection

44

P12/INT2

P21

P12/INT2/TI1/TI2

P21/PTO1

47

48

P22/PCL

P30-P33

IC

P22/PCL/PTO2

50-53

P30/MD0-P33/MD3

57

V

PP

Stack

SBS register

None

SBS.3 = 1: Mk I mode selection

SBS.3 = 0: Mk II mode selection

Stack area

000H-0FFH

2-byte stack

n00H-nFFH (n = 0-3)

Subroutine call

instruction stack

operation

Mk I mode: 2-byte stack

Mk II mode: 3-byte stack

Instruction

BRA !addr1

CALLA !addr1

Unavailable

Mk I mode: unavailable

Mk II mode: available

MOVT XA, @BCDE

MOVT XA, @BCXA

BR BCDE

Available

BR BCXA

CALL !addr

3 machine cycles

2 machine cycles

Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles

Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles

CALLF !faddr

Timer

3 channels

5 channels

• Basic interval timer:

1 channel

• 8-bit timer/event counter:

1 channel

• Basic interval timer/watchdog timer: 1 channel

• 8-bit timer/event counter: 3 channels

(can be used as 16-bit timer/event counter,

carrier generator, timer with gate)

• Watch timer: 1 channel

• Watch timer: 1 channel

Data Sheet U11662EJ2V1DS00

79

µPD753012A, 753016A, 753017A

Parameter

Clock output (PCL)

µPD75316B

µPD753017A

µPD75P3018A

Φ, 524, 262, 65.5 kHz

(Main system clock:

at 4.19 MHz operation)

• Φ, 524, 262, 65.5 kHz

(Main system clock: at 4.19 MHz operation)

• Φ, 750, 375, 93.8 kHz

(Main system clock: at 6.0 MHz operation)

BUZ output

2 kHz

• 2, 4, 32 kHz

(Main system clock:

at 4.19 MHz operation)

(Main system clock: at 4.19 MHz operation or

subsystem clock: at 32.768 kHz operation)

• 2.93, 5.86, 46.9 kHz

(Main system clock: at 6.0 MHz operation)

Serial interface

3 modes are available

• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit

• 2-wire serial I/O mode

• SBI mode

SOS

register

Feedback resistor cut flag

(SOS.0)

None

None

Provided

Provided

Sub-oscillator current cut

flag (SOS.1)

Register bank selection register (RBS)

Standby release by INT0

Interrupt priority selection register (IPS)

Vectored interrupt

None

Yes

Unavailable

None

Available

Yes

External: 3, internal: 3

External: 3, internal: 5

Supply voltage

V

DD = 2.0 to 6.0 V

= –40 to +85˚C

VDD = 1.8 to 5.5 V

Operating ambient temperature

Package

T

A

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

• 80-pin plastic QFP (14 × 14 mm)

80

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are provided for system development using the µPD753017A. The 75XL series

uses a common relocatable assembler, in combination with a device file matching each machine.

Language processor

RA75X relocatable assembler

Part Number

Host Machine

(product name)

OS

Supply media

3.5-inch 2HD

PC-9800 series

MS-DOS^TM

Ver. 3.30 to

Ver. 6.2^Note

µS5A13RA75X

IBM PC/AT^TMand

compatible machines

Refer to

3.5-inch 2HC

µS7B13RA75X

OS for IBM PC

Device file

Part Number

(product name)

Host Machine

OS

Supply media

3.5-inch 2HD

PC-9800 series

MS-DOS

Ver. 3.30 to

Ver. 6.2^Note

µS5A13DF753017

3.5-inch 2HC

µS7B13DF753017

IBM PC/AT and

Refer to

compatible machines

OS for IBM PC

Note Ver. 5.00 or later is provided with a task swap function, but it does not work with this software.

Remark The operation of the assembler and device file is guaranteed only on the above host machines and

OSs.

Data Sheet U11662EJ2V1DS00

81

µPD753012A, 753016A, 753017A

PROM write tools

Hardware

PG-1500

PG-1500 is a PROM programmer which enables you to program single-chip microcontroller

containing PROM by stand-alone or host machine operation by connecting an attached

board and optional programmer adapter to PG-1500.

It also enables you to program typical PROM devices of 256K bits to 4M bits.

PA-75P316BGC

PA-75P316BGK

PROM programmer adapter common to µPD75P3018AGC-3B9. Connect the programmer

adapter to PG-1500 for use.

PROM programmer adapter common to µPD75P3018AGK-BE9. Connect the programmer

adapter to PG-1500 for use.

PA-75P3018AGC-8BT PROM programmer adapter common to µPD75P3018AGC-8BT. Connect the programmer

adapter to PG-1500 for use.

PA-75P3018AGK-9EU PROM programmer adapter common to µPD75P3018AGK-9EU. Connect the programmer

adapter to PG-1500 for use.

Software

PG-1500 controller

PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500

is controlled on the host machine.

Part number

(product name)

Host machine

OS

Supply media

3.5-inch 2HD

PC-9800 series

MS-DOS

Ver. 3.30 to

Ver. 6.2^Note

µS5A13PG1500

3.5-inch 2HD

µS7B13PG1500

IBM PC/AT and

compatible machines

Refer to

OS for IBM PC

Note Ver.5.00 or later is provided with a task swap function, but it does not work with this software.

Remark The operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.

82

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Debugging tool

The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the

µPD753017A.

The system configurations are described as follows.

Hardware

IE-75000-R^{Note 1}

In-circuitemulatorfordebuggingthehardwareandsoftwarewhendevelopingtheapplication

systems that use the 75X series and 75XL series. When developing a µPD753017

subseries, theemulationboardIE-75300-R-EMandemulationprobethataresoldseparately

must be used with the IE-75000-R.

By connecting with the host machine and the PROM programmer, efficient debugging can

be made.

It contains the emulation board IE-75000-R-EM which is connected.

IE-75001-R

In-circuitemulatorfordebuggingthehardwareandsoftwarewhendevelopingtheapplication

systems that use the 75X series and 75XL series. When developing a µPD753017

subseries, the emulation board IE-75300-R-EM and emulation probe which are sold

separately must be used with the IE-75001-R.

It can debug the system efficiently by connecting the host machine and PROM

programmer.

IE-75300-R-EM

EP-753017GC-R

Emulation board for evaluating the application systems that use the µPD753017 subseries.

It must be used with the IE-75000-R or IE-75001-R.

Emulation probe for the µPD753017AGC.

It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.

It is supplied with the 80-pin conversion socket EV-9200GC-80 which facilitates

connection to a target system.

EV-9200GC-80

EP-753017GK-R

Emulation probe for the µPD753017AGK.

It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.

It is supplied with the 80-pin conversion adapter TGK-080SDW which facilitates

TGK-080SDW^{Note 2}connection to a target system.

Software

IE control program Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix

I/F and controls the IE-75000-R or IE-75001-R on a host machine.

Host machine

Part number

(product name)

OS

Supply media

PC-9800 series

MS-DOS

3.5-inch 2HD

µS5A13IE75X

Ver. 3.30 to

Ver. 6.2^{Note 3}

3.5-inch 2HC

µS7B13IE75X

IBM PC/AT and

compatible machines

Refer to

OS for IBM PC

Notes 1. Maintenance parts

2. This is a product of TOKYO ELETECH CORPORATION.

For further information, contact: Daimaru Kogyo, Ltd.

Tokyo Electronics Department (TEL +81-3-3820-7112)

Osaka Electronics 2nd Department (TEL +81-6-6244-6672)

3. Ver.5.00 or later is provided with a task swap function, but it dose not work with this software.

Remarks 1. The operation of the IE control program is guaranteed only on the above host machines and OSs.

2. The µPD753012, 753016, 753017, 75P3018, 753012A, 753016A, 753017A, and 75P3018A are

commonly referred to as the µPD753017 subseries.

Data Sheet U11662EJ2V1DS00

83

µPD753012A, 753016A, 753017A

OS for IBM PC

The following IBM PC OS’s are supported.

OS

Version

PC DOS^TM

Ver. 5.02 to Ver. 6.3

J6.1/V^Noteto J6.3/V^Note

MS-DOS

Ver. 5.0 to Ver. 6.22

5.0/V^Noteto 6.2/V^Note

IBM DOS^TM

J5.02/V^Note

Note Only English version is supported.

Caution Ver. 5.0 or later is provided with a task swap function, but it does not work with this software.

84

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

APPENDIX C. RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

Device Related Documents

Document No.

Document Name

Japanese

U11662J

U11917J

U11282J

IEM-5598

U10453J

English

U11662E (this document)

U11917E

µPD753012A, 753016A, 753017A Data Sheet

µPD75P3018A Data Sheet

µPD753017 User’s Manual

U11282E

µPD753017 Instruction Table

75XL Series Selection Guide

—

U10453E

Development Tool Related Documents

Document No.

Document Name

Japanese

EEU-846

U11354J

EEU-967

U11940J

U12622J

U12385J

EEU-704

English

EEU-1416

U11354E

EEU-1494

U11940E

U12622E

U12385E

EEU-1291

Hardware IE-75000-R/IE-75001-R User’s Manual

IE-75300-R-EM User’s Manual

EP-753017GC/GK-R User’s Manual

PG-1500 User’s Manual

Software

RA75X Assembler Package

User’s Manual

Operation

Language

PG-1500 Controller User’s Manual

PC-9800 Series

(MS-DOS) Base

IBM PC Series

(PC DOS) Base

EEU-5008

U10540E

Other Related Documents

Document No.

X13769X

Document Name

Japanese

English

SEMICONDUCTOR SELECTION GUIDE Products & Package (CD-ROM)

Semiconductor Device Mounting Technology Manual

C10535J

C11531J

C10983J

C11892J

C10535E

C11531E

C10983E

C11892E

Quality Grades on NEC Semiconductor Devices

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic

Discharge (ESD)

Guide to Microcontroller-Related Products by Third Parties

U11416J

–

Caution The above related documents are subject to change without notice. For design purpose, etc.,

be sure to use the latest documents.

Data Sheet U11662EJ2V1DS00

85

µPD753012A, 753016A, 753017A

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

86

Data Sheet U11662EJ2V1DS00

µPD753012A, 753016A, 753017A

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, pIease contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

•

•

•

•

•

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.

Benelux Office

Hong Kong

Eindhoven, The Netherlands

Tel: 040-2445845

Tel: 2886-9318

Fax: 2886-9022/9044

Fax: 408-588-6130

800-729-9288

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 01-30-67 58 99

Fax: 0211-65 03 490

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore

Tel: 65-253-8311

NEC Electronics (France) S.A.

Madrid Office

Madrid, Spain

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 65-250-3583

Tel: 91-504-2787

Fax: 01908-670-290

Fax: 91-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

NEC Electronics Italiana s.r.l.

Milano, Italy

Tel: 02-66 75 41

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Fax: 02-2719-5951

Fax: 02-66 75 42 99

Tel: 08-63 80 820

NEC do Brasil S.A.

Electron Devices Division

Guarulhos-SP Brasil

Tel: 55-11-6462-6810

Fax: 55-11-6462-6829

Fax: 08-63 80 388

J00.7

Data Sheet U11662EJ2V1DS00

87

µPD753012A, 753016A, 753017A

MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States

and/or other countries.

IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited

without governmental license, the need for which must be judged by the customer. The export or re-export of this product

from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

•

The information in this document is current as of August, 2000. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or

data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all

products and/or types are available in every country. Please check with an NEC sales representative

for availability and additional information.

•

•

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

liability arising from the use of such products. No license, express, implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of NEC or others.

•

•

•

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third

parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not

intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness

to support a given application.

(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4

相关型号：

UPD753012AGK

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC

UPD753012AGK-XXX-9EU

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PQFP80, 12 X 12 MM, 1 MM HEIGHT, FINE PITCH, PLASTIC, TQFP-80

NEC

UPD753012AGK-XXX-9EU-A

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PQFP80, 12 X 12 MM, LEAD FREE, PLASTIC, TQFP-80

NEC

UPD753012AGK-XXX-BE9

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PQFP80, 14 X 14 MM, PLASTIC, QFP-80

NEC

UPD753012AGK-XXX-BE9-A

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PQFP80, 12 X 12 MM, 1.05 MM HEIGHT, FINE PITCH, PLASTIC, TQFP-80

NEC

UPD753012AGK-XXX-BE9-A

UPD753012AGK-XXX-BE9-A

RENESAS

UPD753012GC

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC

UPD753012GC-XXX-3B9

4-Bit Microcontroller

ETC

UPD753012GK

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC

UPD753012GK-XXX-BE9

4-Bit Microcontroller

ETC

UPD753016

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC

UPD753016A

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC

©2020 ICPDF网联系我们和版权申明