UPD78002BA [NEC]
8-BIT SINGLE-CHIP MICROCOMPUTER; 8位单片机
| 型号： | UPD78002BA |
| 厂家： | 
NEC |
| 描述： | 8-BIT SINGLE-CHIP MICROCOMPUTER |
| 文件： | 总62页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78001B(A), 78002B(A)
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD78001B(A)/78002B(A) are products in the µPD78002 subseries within the 78K/0 series.
The µPD78001B(A)/78002B(A) have various peripheral hardware such as timer, serial interface and interrupt
function.
A one-time PROM or EPROM product, the µPD78P014, capable of operating in the same power supply voltage
range as that of the mask ROM product and other development tools is provided.
Functions are described in detail in the following User's Manual, which should be read when carrying out design
work.
µPD78002, 78002Y Series User's Manual: IEU-1334
FEATURES
• The µPD78001B, in comparison with the 78002B, is a higher reliability device, as a result of a more comprehensive
quality assurance program (Refer to Quality Grade on NEC Semiconductor Devices (IEI-1209))
• Large on-chip ROM & RAM
Item
Program Memory
(ROM)
Data Memory
(Internal High-Speed RAM)
256 bytes
Package
Product Name
µPD78001B(A)
µPD78002B(A)
8K bytes
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP ( 14 mm)
16K byte
384 bytes
• External memory expansion space: 64K bytes
• Instruction execution time can be varied from high-speed (0.4 µs) to ultra-low-speed (122 µs)
• I/O ports: 53 (N-ch open-drain : 4)
• Serial interface : 1 channel
• Timer: 4 channels
• Operating voltage range : 2.7 to 6.0 V
APPLICATION
Transmission equipment control device, gas detector circuit breaker, safety devices, etc.
The information in this document is subject to change without notice.
Document No. IC-3599
(O.D. No. IC-9078)
Date Published February 1995 P
Printed in Japan
1995
©
µPD78001B(A), 78002B(A)
ORDERING INFORMATION
Part Number
Package
Quality Grade
µPD78001BCW (A)-×××
µPD78001BGC (A)-×××-AB8
µPD78002BCW (A)-×××
µPD78002BGC (A)-×××-AB8
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (■14 mm)
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (■14 mm)
Special
Special
Special
Special
Remark ××× indicates ROM code No.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Difference between the µPD78001B(A), 78002B(A) and the µPD78001B, 78002B.
Product Name
µPD78001B(A), 78002B(A)
µPD78001B, 78002B
Item
Quality Grade
Special
Standard
2
µPD78001B(A), 78002B(A)
78K/0 SERIES PRODUCT DEVELOPMENT
These products are a further development in the 78K/0 Series. The designations appearing inside the boxes
are subseries names.
Products in Volume Production
Products under Development
Y series products are compatible with I2C bus.
For control
µ
µ
µ
Timer added to the PD78054, external interface functions
PD78078
PD78054
µPD78078Y
100-pin
80-pin
64-pin
64-pin
64-pin
42/44-pin
µ
UART and D/A added to the PD78014, I/O enhanced
µ
PD78054Y
µPD78018FY
µ
Low-voltage (1.8 V) operation version of the PD78014, with enhanced ROM and RAM variations
µPD78018F
µ
µ PD78002
µ
A/D and 16-bit timer added to the µPD78002
Basic subseries for control
µ
PD78014
PD78014Y
µPD78002Y
PD78083
Internal UART, low-voltage (1.8 V) operation possible
78K/0
Series
For FIP® driving
µ
I/O, FIP C/D of the PD78044A enhanced, display output total: 53
100-pin
80-pin
64-pin
PD780208
µPD78044A
µ
6-bit U/D counter added to the PD78024, display output total: 34
µ
Basic subseries for FIP driving, display output total: 26
µ
PD78024
For LCD driving
100-pin
80-pin
µPD78064
µ
PD78064Y
Subseries for LCD driving, internal UART
For IEBusTM
µ
IEBus controller added to the PD78054
µPD78098
The major functional differences among the subseries are shown below.
Function
Timer
Watch
1ch
V
MIN.
DD
Serial
Interface
External
Expansion
A/D
D/A
I/O
88
Name
8-bit
16-bit
1ch
Watchdog
1ch
Value
µPD78078
4ch
2ch
8-bit × 8ch 8-bit × 2ch 3ch (UART: 1ch)
1.8 V
C
For Control
µPD78054
µPD78018F
µPD78014
µPD78002
µPD78083
µPD780208
µPD78044A
µPD78024
µPD78064
69
53
2.0 V
1.8 V
2.7 V
—
2ch
—
—
1ch
1ch (UART: 1ch)
2ch
—
8-bit × 8ch
8-bit × 8ch
33
74
68
54
57
1.8 V
2.7 V
—
—
For FIP
driving
2ch
1ch
1ch
1ch
—
—
2ch
2ch
1ch
1ch
1ch
1ch
1ch
1ch
8-bit × 8ch
2ch (UART: 1ch)
2.0 V
2.7 V
—
For LCD
driving
For IEBusTM
µPD78098
8-bit × 8ch 8-bit × 2ch 3ch (UART: 1ch)
69
C
3
µPD78001B(A), 78002B(A)
OVERVIEW OF FUNCTION
Product Name
Item
µPD78001B(A)
µPD78002B(A)
8K bytes
16K bytes
384 bytes
Internal
ROM
memory
Internal high-
speed RAM
256 bytes
64K bytes
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Memory space
General registers
Instruction cycle
On-chip instruction execution time cycle modification function
When main system
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 10.0 MHz operation)
clock selected
When subsystem
clock selected
122 µs (at 32.768 kHz operation)
• 16-bit operation
Instruction set
• Bit manipulation (set, reset, test, boolean operation)
• BCD correction, etc.
Total
: 53
: 02
: 47
I/O ports
• CMOS input
• CMOS I/O
• N-channel open-drain I/O
(15 V withstand voltage) : 04
• 3-wire/SBI/2-wire mode selectable
Serial interface
Timer
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
: 1 channel
• Watchdog timer
Timer output
Clock output
2
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock 10.0 MHz operation),
32.768 kHz (at subsystem clock 32.768 kHz operation)
Buzzer output
2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 10.0 MHz operation)
Vectored
interrupts interrupts
Maskable
Internal : 5
External: 4
Non-maskable
Internal : 1
interrupt
Software
interrupt
Internal : 1
Test input
Internal : 1
External : 1
Operating voltage range
VDD = 2.7 to 6.0 V
Operating ambient
temperature range
–40 to +85°C
• 64-pin plastic shrink DIP (750 mil)
Package
• 64-pin plastic QFP (■14 mm)
4
µPD78001B(A), 78002B(A)
CONTENTS
1. PIN CONFIGURATION (TOP VIEW).....................................................................................................
2. BLOCK DIAGRAM...................................................................................................................................
6
9
3. PIN FUNCTIONS ..................................................................................................................................... 10
3.1 PORT PINS ...................................................................................................................................................... 10
3.2 OTHER PINS ................................................................................................................................................... 12
3.3 PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS ...................................... 13
4. MEMORY SPACE.................................................................................................................................... 15
5. PERIPHERAL HARDWARE FUNCTION FEATURES............................................................................ 16
5.1 PORTS .............................................................................................................................................................. 16
5.2 CLOCK GENERATOR...................................................................................................................................... 17
5.3 TIMER/EVENT COUNTER.............................................................................................................................. 18
5.4 CLOCK OUTPUT CONTROL CIRCUIT ......................................................................................................... 20
5.5 BUZZER OUTPUT CONTROL CIRCUIT ....................................................................................................... 20
5.6 SERIAL INTERFACES ..................................................................................................................................... 21
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS .......................................................................... 22
6.1 INTERRUPT FUNCTIONS............................................................................................................................... 22
6.2 TEST FUNCTIONS.......................................................................................................................................... 25
7. EXTERNAL DEVICE EXPANSION FUNCTIONS ................................................................................. 26
8. STANDBY FUNCTIONS ......................................................................................................................... 26
9. RESET FUNCTION .................................................................................................................................. 26
10. INSTRUCTION SET ................................................................................................................................ 27
11. ELECTRICAL SPECIFICATIONS ............................................................................................................. 30
12. CHARACTERISTIC CURVE (REFERENCE VALUES) ........................................................................... 48
13. PACKAGE DRAWINGS........................................................................................................................... 52
14. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 56
APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 57
APPENDIX B. RELATED DOCUMENTS ...................................................................................................... 59
5
µPD78001B(A), 78002B(A)
1. PIN CONFIGURATION (TOP VIEW)
64-Pin Plastic Shrink DIP (750 mil)
P20
P21
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IC3
2
IC2
P22
3
P17
P16
P15
P14
P13
P12
P11
P10
IC1
P23
4
P24
5
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30
6
7
8
9
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P04/XT1
XT2
IC0
µ
µ
X1
X2
V
SS
V
DD
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0
RESET
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P63
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P62
P61
P60
P57/A15
P56/A14
V
SS
Remark
Always connect the IC0, IC1 and IC3 (Internally Connected) pins to VSS directly.
Always connect the IC2 pin to VDD directly.
6
µPD78001B(A), 78002B(A)
64-Pin Plastic QFP (■14 mm)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
P30
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
1
P11
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P10
3
IC1
4
µ
µ
P04/XT1
XT2
5
6
IC0
7
X1
8
X2
VSS
9
VDD
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
10
11
12
13
14
15
16
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0
RESET
P67/ASTB
P66/WAIT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Remark
Always connect the IC0, IC1 and IC3 (Internally Connected) pins to VSS directly.
Always connect the IC2 pin to VDD directly.
7
µPD78001B(A), 78002B(A)
P00 to P04
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
: Port 0
: Port 1
: Port 2
: Port 3
: Port 4
: Port 5
: Port 6
PCL
BUZ
AD0 to AD7
A8 to A15
RD
: Programmable Clock
: Buzzer Clock
: Address/Data Bus
: Address Bus
: Read Strobe
: Write Strobe
WR
WAIT
: Wait
INTP0 to INTP3 : Interrupt From Peripherals
ASTB
X1, X2
XT1, XT2
RESET
VDD
: Address Strobe
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
: Reset
: Power Supply
: Ground
TI1, TI2
TO1, TO2
SB0, SB1
SI0
: Timer Input
: Timer Output
: Serial Bus
: Serial Input
: Serial Output
: Serial Clock
SO0
VSS
IC0 to IC3
SCK0
: Internally Connected
8
µPD78001B(A), 78002B(A)
2. BLOCK DIAGRAM
TO1/P31
P00
P01-P03
P04
8-bit TIMER/
EVENT COUNTER 1
PORT0
PORT1
TI1/P33
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER 2
P10-P17
P20-P27
P30-P37
PORT2
PORT3
PORT4
WATCHDOG TIMER
WATCH TIMER
78K/0
CPU CORE
ROM
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SERIAL
INTERFACE 0
P40-P47
P50-P57
INTP0/P00 –
INTP3/P03
INTERRUPT
CONTROL
PORT5
PORT6
RAM
BUZ/P36
PCL/P35
BUZZER OUTPUT
P60-P67
CLOCK OUTPUT
CONTROL
AD0/P40-
AD7/P47
A8/P50-
A15/P57
EXTERNAL
ACCESS
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
X2
XT1/P04
XT2
SYSTEM
CONTROL
VDD
VSS
IC0-
IC3
Remark
Internal ROM & RAM capacity varies depending on the product.
9
µPD78001B(A), 78002B(A)
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
After
Dual-
Pin Name
I/O
Function
Input only
Reset
Function Pin
Port 0
Input
P00
Input
Input
INTP0
INTP1
INTP2
INTP3
XT1
5-bit I/O port
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can
be used by software.
Input/
P01
output
P02
P03
Input only
P04*
P10 to P17
Input
Input
Input
Port 1
Input/
–
8-bit input/output port.
output
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/
P20
Port 2
–
output
8-bit input/output port.
P21
–
Input/output can be specified bit-wise.
P22
–
When used as an input port, pull-up resistor can be used by software.
P23
–
–
P24
P25
SI0/SB0
SO0/SB1
SCK0
–
P26
P27
Input/
Port 3
P30
Input
output
8-bit input/output port.
P31
TO1
Input/output can be specified in bit-wise.
When used as an input port, pull-up resistor can be used by software.
P32
TO2
P33
TI1
P34
TI2
P35
PCL
P36
BUZ
–
P37
Input/
P40 to P47
Port 4
Input
AD0 to AD7
output
8-bit input/output port.
Input/output can be specified in 8-bit unit.
When used as an input port, pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
*
When using the P04/XT1 pins as an input port, set 1 to bit 6 (FRC) of the processor control register. (Do not use
the on-chip feedback register of the subsystem clock oscillator.)
10
µPD78001B(A), 78002B(A)
3.1 PORT PINS (2/2)
Dual-
After
Pin Name
P50 to P57
I/O
Function
Function Pin
Reset
Port 5
Input/
Input
A8 to A15
8-bit input/output port.
LED can be driven directly.
output
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/
Port 6
N-ch open-drain input/output port. On-
chip pull-up resistor can be specified by
mask option.
P60
P61
P62
P63
P64
P65
P66
P67
Input
output
8-bit input/output port.
Input/output can be specified
bit-wise.
LED can be driven directly.
When used as an input port, pull-up
resistor can be used by software.
RD
WR
WAIT
ASTB
Caution
When pull-up resistors are not used (specified by mask option), the low-level input leak current
increases with -200 µA (MAX.) under either of the following conditions.
1 When the external device expansion function is used and a low-level is input to the pin.
2 During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode
register (PM6).
11
µPD78001B(A), 78002B(A)
3.2
OTHER PINS
After
Dual-
I/O
Pin Name
Function
Reset
Function Pin
INTP0
INTP1
INTP2
INTP3
SI0
Input
Effective edge (rising edge, falling edge, or both rising edge and falling edge) Input
can be specified.
P00
P01
External interrupt input.
P02
Falling edge detection external interrupt input.
P03
Input
Output
Input
Serial interface serial data input.
Serial interface serial data output.
Serial interface serial data input/output.
Input
Input
Input
P25/SB0
P26/SB1
P25/SI0
P26/SO0
P27
SO0
SB0
SB1
/output
Input
SCK0
Serial interface serial clock input/output.
Input
Input
Input
/output
Input
TI1
External count clock input to 8-bit timer (TM1).
External count clock input to 8-bit timer (TM2).
8-bit timer (TM1) output.
P33
P34
TI2
TO1
Output
P31
TO2
8-bit timer (TM2) output.
P32
PCL
Output
Output
Input
Clock output (for main system clock, subsystem clock trimming).
Buzzer output.
Input
Input
Input
P35
BUZ
P36
AD0 to AD7
Low-order address/data bus at external memory expansion.
P40 to P47
/output
Output
Output
A8 to A15
RD
High-order address bus at external memory expansion.
External memory read operation strobe signal output.
External memory write operation strobe signal output.
Wait insertion at external memory access.
Input
Input
P50 to P57
P64
WR
P65
WAIT
ASTB
Input
Input
Input
P66
Output
Strobe output which latches the address information output at port 4 and
port 5 to access external memory.
P67
RESET
X1
Input
Input
—
System reset input.
—
—
—
—
Main system clock oscillation crystal connection.
X2
—
—
XT1
Input
—
Subsystem clock oscillation crystal connection.
Input
—
P04
—
XT2
VDD
—
Positive power supply.
—
—
VSS
—
Ground potential.
—
—
IC0 to IC3
—
Internal connection. IC0/IC1/IC3 and IC2 should be connected directly to VSS
VDD, respecitively.
—
—
12
µPD78001B(A), 78002B(A)
3.3 PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Fig. 3-1.
Table 3-1 Input/Output Circuit Type of Each Pin
Input/Output
Pin Name
P00/INTP0
I/O
Recommended Connection when Not Used
Connected to VSS .
Circuit Type
Input
2
Input/output
P01/INTP1
P02/INTP2
P03/INTP3
P04/XT1
8-A
Connected to VSS through resistor independently.
Input
16
Connected to VDD or VSS .
Input/output
P10 to P17
P20 to P24
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30
5-A
Connected to VDD or VSS through resistor independently.
10-A
5-A
P31/TO1
P32/TO2
P33/TI1
8-A
5-A
P34/TI2
P35/PCL
P36/BUZ
P37
P40/AD0 to P47/AD7
P50/A8 to P57/A15
P60 to P63
P64/RD
Connected to VDD through resistor independently.
Connected to VDD or VSS through resistor independently.
Connected to VDD through resistor independently.
Connected to VDD or VSS through resistor independently.
5-E
5-A
13-B
5-A
P65/WR
P66/WAIT
P67/ASTB
RESET
2
Input
—
—
XT2
16
—
Leave open.
Connected to VSS directly.
Connected to VDD directly.
IC0, IC1, IC3
IC2
13
µPD78001B(A), 78002B(A)
Fig. 3-1 Pin Input/Output Circuits
Type 10-A
VDD
Type 2
pullup
enable
P-ch
VDD
IN
data
P-ch
IN / OUT
open drain
N-ch
output disable
Schmitt-Triggered Input with Hysteresis Characteristic
Type 5-A
Type 13-B
VDD
VDD
Mask
Option
pullup
enable
P-ch
IN / OUT
data
VDD
P-ch
N-ch
VDD
output disable
data
IN / OUT
output
disable
N-ch
P-ch
RD
input
enable
Middle-High Voltage Input Buffer
Type 5-E
Type 16
VDD
feedback
cut-off
pullup
enable
P-ch
P-ch
VDD
P-ch
data
IN / OUT
output
disable
N-ch
XT1
XT2
Type 8-A
VDD
pullup
enable
P-ch
VDD
P-ch
data
IN / OUT
output
disable
N-ch
14
µPD78001B(A), 78002B(A)
4. MEMORY SPACE
The memory map of µPD78001B(A)/78002B(A) is shown in Fig. 4-1.
Fig. 4-1 Memory Map
FFFFH
Special Function Registers
(SFR) 256 × 8 Bits
FF00H
FEFFH
General Registers
32 × 8 Bits
FEE0H
FEDFH
Internal High-Speed RAM*
mmmmH
nnnnH
mmmmH–1
Program Area
CALLF Entry Area
Program Area
Data
1000H
0FFFH
Memory
Space
Use Prohibited
0800H
07FFH
FA80H
FA7FH
Program
Memory
Space
0080H
007FH
External Memory
nnnnH+1
nnnnH
CALLT Table Area
Vector Table Area
0040H
003FH
Internal ROM*
0000H
0000H
Remark
Shaded area indicates internal memory.
*
Intermal ROM and internal high-speed RAM capacities vary depending on the product (see the table below).
Internal ROM
End Address
nnnnH
Internal High-Speed
RAM Start Address
mmmmH
Product Name
µPD78001B(A)
µPD78002B(A)
1FFFH
3FFFH
FE00H
FD80H
15
µPD78001B(A), 78002B(A)
5
PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 PORTS
The I/O port has the following three types.
• CMOS input (P00, P04)
:
2
• CMOS input/output (P01 to P03,
port 1 to port 5, P64 to P67)
: 47
• N-ch open-drain input/output
(15V withstand voltage) (P60 to P63)
:
4
Total
: 53
Table 5-1 Functions of Ports
Port Name
Port 0
Pin Name
Function
P00, P04
Dedicated Input port
P01 to P03
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified in 8-bit units.
When used as an input port, pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
LED can be driven directly.
Port 1
Port 2
Port 3
Port 4
P10 to P17
P20 to P27
P30 to P37
P40 to P47
Port 5
Port 6
P50 to P57
P60 to P63
P64 to P67
N-ch open-drain input/output port. Input/output can be specified bit-wise.
On-chip pull-up resistor can be specified by mask option.
LED can be driven directly.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Caution
When pull-up resistors are not used (specified by mask option), low-level input leak current increases
with –200 µA (MAX.) under either of the following conditions.
1 When the external device expansion function is used and a low-level is input to the pin.
2 During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode
register (PM6).
16
µPD78001B(A), 78002B(A)
5.2 CLOCK GENERATOR
There are two types of clock generator: main system clock and subsystem clock.
The instruction exection time can be changed.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (mainsystem clock: at 10.0 MHz operation)
• 122 µs (subsystem clock: at 32.768 KHz operation)
Fig. 5-1 Clock Generator Block Diagram
XT1/P04
Watch Timer
Clock Output
Function
Subsystem
Clock
Osicillator
f
XT
XT2
Prescaler
Main
System
Clock
X1
X2
f
X
Clock to
Peripheral
Hardware
Prescaler
Osicillator
f
2
X
f
X
f
X
f
X
24
22 23
STOP
Standby
Control
Circuit
Wait
Control
Circuit
CPU Clock
Selector
(fCPU
)
INTP0
Sampling Clock
17
µPD78001B(A), 78002B(A)
5.3 TIMER/EVENT COUNTER
The following four channels are incorporated in the timer/event counter.
• 8-bit timer/event counter
• Watch timer
• Watchdog timer
: 2 channels
: 1 channel
: 1 channel
Table 5-2 Types and Features of Timer/Event Counter
8-bit Timer/Event Counter
Watch Timer
Watchdog Timer
Type
Interval timer
2 channels
2 channels
2 outputs
2 outputs
2
1 channel
1 channel
External event counter
–
–
–
2
–
–
–
1
Functions Timer output
Sqare wave output
Interrupt request
Fig. 5-2 8-Bit Timer/Enent Counter Block Diagram
Internal Bus
INTTM1
8-Bit Compare
Register (CR10)
8-Bit Compare
Register (CR20)
Output
Control
Circuit
TO2/P32
INTTM2
Selector
Match
Match
fX/2 – fX/210
8-Bit Timer
fX/212
Selector
Selector
Register 1 (TM1)
8-Bit Timer
Register 2 (TM2)
Selector
TI1/P33
Clear
Clear
fX/2 – fX/210
Selector
fX/212
TI1/P34
Output
Control
Circuit
TO1/P31
Internal Bus
18
µPD78001B(A), 78002B(A)
Fig. 5-3 Watch Timer Block Diagram
fW
214
Selector
5-Bit Counter
fX/28
fXT
fW
INTWT
Selector
Prescaler
Selector
fW
213
fW
fW
fW
fW
fW
fW
24 25 26 27 28
29
INTTM3
Selector
Fig. 5-4 Watchdog Timer Block Diagram
fW
Prescaler
24
fW
fW
fW
fW
fW
fW
fW
INTWDT
Maskable
Interrupt Request
25 26 27 28 29
212
210
Control
Circuit
Selector
RESET
8-Bit Counter
INTWDT
Non-Maskable
Interrupt Request
19
µPD78001B(A), 78002B(A)
5.4 CLOCK OUTPUT CONTROL CIRCUIT
The clock with the following frequencies can be output for clock output.
• 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation)
• 32.768 kHz (Subsystem clock: at 32.768 kHz operation)
Fig. 5-5 Clock Output Control Block Diagram
fX/23
fX/24
fX/25
Synchronization
Circuit
Output Control
Circuit
fX/26
fX/27
fX/28
fXT
Selector
PCL/P35
5.5 BUZZER OUTPUT CONTROL CIRCUIT
The clock with the following frequencies can be output for buzzer output.
• 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation)
Fig. 5-6 Buzzer Output Control Block Diagram
fX/210
fX/211
fX/212
Output Control
Circuit
BUZ/P36
Selector
20
µPD78001B(A), 78002B(A)
5.6 SERIAL INTERFACES
There is one on-chip clocked serial interface.
Serial Interface channel 0 has the following three modes.
• 3-wire serial I/O mode
• SBI (Serial Bus Interface) mode
• 2-wire serial I/O mode
: MSB/LSB-first switchable
: MSB-first
: MSB-first
Fig. 5-7 Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25
SO0/SB1/P26
Output
Latch
Serial I/O Shift
Selector
Selector
Register 0 (SIO0)
Busy/Acknowledge
Output Circuit
Bus Release/Command/
Acknowledge Detection
Circuit
Interrupt
Request
Signal
INTCSI0
SCK0/P27
Serial Counter
Generator
f
X
/22 – f
TO2
X
/29
Serial Clock
Control Circuit
Selector
21
µPD78001B(A), 78002B(A)
6. INTERRUPT FUNCTIONS AND DEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS
There are 11 interrupt functions of 3 different kinds as shown below.
• Non-maskable interrupt
• Maskable interrupt
• Software interrupt
:
:
:
1
9
1
Table 6-1 Interrrupt Source List
Basic
Interrupt Source
Trigger
Interrupt
Type
Default
Internal/
Vector Table
Adress
Configuration
Priority *1
External
Name
Type *2
Non-
INTWDT
Watchdog timer overflow (with non-
maskable interrupt selected)
Internal
0004H
A
B
maskable
Maskable
Watchdog timer overflow (with interval
timer selected)
0
INTWDT
Pin input edge detection
1
2
3
4
5
6
INTP0
INTP1
External
Internal
0006H
0008H
000AH
000CH
000EH
0012H
C
D
INTP2
INTP3
Serial interface channel 0 transfer end
INTCSI0
INTTM3
B
Reference time interval signal from
watch timer
8-bit timer/event counter 1 match signal
generation
7
8
INTTM1
INTTM2
BRK
0016H
0018H
003EH
8-bit timer/event counter 2 match signal
generation
Software
BRK instruction execution
Internal
E
*
1. The default priority is the priority applicable when more priority than one maskable interrupt is generated.
0 is the highest and 11, the lowest.
2. Basic configuration types A to E correspond to (A) to (E) on the next page.
22
µPD78001B(A), 78002B(A)
Fig. 6-1 Interrupt Function Basic Configuration (1/2)
(A) Internal Non-Maskable Interrupt
Internal Bus
Vector Table
Interrupt
Request
Priority Control
Circuit
Address
Generator
Standby Release
Signal
(B) Internal Maskable Interrupt
Internal Bus
PR
ISP
MK
IE
Vector Table
Priority Control
Circuit
Address
Interrupt
Request
IF
Generator
Standby Release
Signal
(C) External Maskable Interrupt (INTP0)
Internal Bus
MK
Sampling Clock
Select Register
(SCS)
External Interrupt
Mode Register
(INTM0)
PR
ISP
IE
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Edge
Detector
Sampling
Clock
IF
Standby Release
Signal
23
µPD78001B(A), 78002B(A)
Fig. 6-1 Interrupt Function Basic Configuration (2/2)
(D) External Maskable Interrupt (Except INTP0)
Internal Bus
MK
External Interrupt
Mode Register
(INTM0)
PR
ISP
IE
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Edge
Detector
IF
Standby Release
Signal
(E) Software Interrupt
Internal Bus
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Remarks 1. IF : Interrupt request flag
2. IE : Interrupt enable flag
3. ISP : In-service priority flag
4. MK : Interrupt mask flag
5. PR : Priority spcification flag
24
µPD78001B(A), 78002B(A)
6.2 TEST FUNCTIONS
There are two test functions as shown in Table 6-2.
Table 6-2 Test Source List
Test Source
Trigger
Internal/External
Name
INTWT
NTPT4
Watch timer overflow
Port 4 falling edge detection
Internal
External
Fig. 6-2 Test Function Basic Configuration
Internal Bus
MK
Standby Release
Signal
IF
Test Input
Remarks 1. IF : Test input flag
2. MK : Test mask flag
25
µPD78001B(A), 78002B(A)
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion function is used to connect external devices to areas other than the internal ROM,
RAM and SFR.
Ports 4 to 6 are used for connection with external devices.
8. STANDBY FUNCTIONS
There are the following two standby functions to reduce the current dissipation.
• HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by
intermittent operation in combination with the normal operating mode.
• STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is
stopped, so that the system operates with ultra-low power consumption using only the sub-
system clock.
Fig. 8-1 Standby Functions
CSS=1
Main System
Clock Operation
Subsystem Clock
Operation*
CSS=0
HALT
Instruction
STOP
Instruction
HALT
Instruction
Interrupt
Request
Interrupt
Request
Interrupt
Request
STOP Mode
(Main system clock
oscillation stopped)
HALT Mode
(Clock supply to CPU is
stopped, oscillation)
HALT Mode*
(Clock supply to CPU is
stopped, oscillation)
*
The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the
subsystem clock, set the MCC to stop the main system clock. The STOP instruction cannot be used.
Caution
When the main system clock is stopped and the system is operated by the subsystem clock, the
subsystem clock should be switched again to the main system clock after the oscillation stabilization
time is secured by the program by the program.
9. RESET FUNCTION
There are the following two reset methods.
• External reset input by RESET pin.
• Internal reset by watchdog timer runaway time detection.
26
µPD78001B(A), 78002B(A)
10. INSTRUCTION SET
(1) 8-Bit Instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH,
POP, DBNZ
2nd
[HL+byte]
Operand
#byte
A
r*
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL+B] $addr16
1
None
1st
Operand
[HL+C]
A
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROR
ROL
RORC
ROLC
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
r1
DBNZ
DBNZ
sfr
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL+byte]
[HL+B]
MOV
[HL+C]
*
Except r = A
27
µPD78001B(A), 78002B(A)
(2) 16-Bit Instruction
MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
#word
AX
rp*
sfrp
saddrp
!addr16
SP
None
1st Operand
AX
ADDW
MOVW
XCHW
MOVW
MOVW
MOVW
MOVW
SUBW
CMPW
rp
MOVW
MOVW*
INCW, DECW
PUSH, POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
*
Only when rp = BC, DE, HL.
(3) Bit Operation Instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
sfr.bit
saddr.bit
PWS.bit
[HL].bit
CY
$addr16
None
1st Operand
A.bit
MOV1
BT
BF
SET1
CLR1
BTCLR
sfr.bit
MOV1
MOV1
MOV1
MOV1
BT
SET1
CLR1
BF
BTCLR
saddr.bit
PSW.bit
[HL].bit
CY
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
MOV1
MOV1
MOV1
MOV1
AND1
OR1
MOV1
SET1
CLR1
NOT1
AND1
OR1
AND1
OR1
AND1
OR1
AND1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
28
µPD78001B(A), 78002B(A)
(4) Call Instruction/Branch Instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF,BTCLR, DBNZ
2nd Operand
AX
BR
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
1st Operand
Basic instruction
CALL, BR
BR, BC, BNC, BZ, BNZ
BT, BF, BTCLR, DBNZ
Compound instruction
(5) Other Instruction
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
29
µPD78001B(A), 78002B(A)
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Symbol
VDD
Test Conditions
Rating
Unit
V
Supply voltage
Input voltage
–0.3 to + 7.0
P00 to P04, P10 to P17, P20 to P27, P30 toP37
P40 to P47, P50 to P57, P64 to P67, X1, X2, XT2
–0.3 to VDD + 0.3
V
VI1
VI2
VO
P60 to P67
Open-drain
–0.3 to +16
V
Output voltage
–0.3 to VDD + 0.3
V
Output
1 pin
–10
–15
–15
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
current high
IOH
P10 to P17, P20 to P27, P30 to P37 total
P01 to P03, P40 to P47, P50 to P57, P60 to P67 total
Output
Peak value
1 pin
current low
Effective value
Peak value
15
100
70
P40 to P47, P50 to P55 total
Effective value
Peak value
P01 to P03, P56, P57,
P60 to P67 total
P01 to P03,
100
70
IOL*
Effective value
Peak value
50
P64 to P67 total
P10 to P17, P20 to P27, P30 to P37
total
Effective value
Peak value
20
50
Effective value
20
Operating ambient
temperature
TA
–40 to +85
°C
°C
Storage
Tstg
–65 to +150
temperature
*
Effective value should be calculated as follows:
[Effective value] = [Peak value] × √duty
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even
momentarily. That is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering
physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum
ratings are not exceeded.
30
µPD78001B(A), 78002B(A)
Capacitance (TA = 25 °C, VDD = VSS = 0 V)
Parameter
Symbol
CIN
Test Conditions
MIN.
TYP.
MAX.
15
Unit
pF
Input capacitance
I/O capacitance
f=1 MHz Unmeasured pins returned to 0 V
P01 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 toP47, P50 to P57,
P64 to P67
15
pF
pF
f=1 MHz Unmeasured
pins returned to 0 V
CIO
P60 to P63
20
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
Resonator
Parameter
Test Conditions
MIN.
1
TYP.
MAX.
10
Unit
MHz
Circuit
Ceramic
Oscillator
VDD = Oscillator
voltage range
X1
X2
V
SS
resonator
frequency (fX) *1
R1
C2
Oscillation
After VDD reaches oscil-
lator voltage range MIN.
C1
4
ms
stabilization time *2
Crystal
Oscillator
10
MHz
ms
8.38
1
X1
X2
V
SS
resonator
frequency (fX) *1
10
30
Oscillation
VDD = 4.5 to 6.0 V
C1
C2
stabilization time *2
External
clock
X1 input
MHz
ns
10.0
500
1.0
frequency (fX) *1
X2
X1
X1 input
µPD74HCU04
high/low level width
(tXH , tXL)
42.5
*
1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions
1. When using the main system clock oscillator, wiring the area enclosed with the broken line should be carried
out as follows to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as VSS.
Do not ground wiring to a ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem
clock should be switched again to the main system clock after the oscillation stabilization time is secured by
the program.
31
µPD78001B(A), 78002B(A)
Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
Circuit
Resonator
Parameter
Test Conditions
MIN.
32
TYP.
MAX.
35
Unit
kHz
Crystal
Oscillator
XT1 XT2
VSS
32.768
1.2
resonator
frequency (fXT) *1
R2
VDD = 4.5 to 6.0 V
2
C3
C4
Oscillation
s
stabilization time *2
10
External
clock
XT1 input
kHz
100
15
32
5
frequency (fXT) *1
XT2
XT1
XT1 input
high/low level width
(tXTH , tXTL)
µs
*
1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Cautions
1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried
out as follows to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as VSS.
Do not ground wiring to a ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
2. The subsystem clock oscillation circuit is a circuit with a low amplification level, more prone to misoperation
due to noise than the main system clock. When using the subsystem clock, special care is needed regarding
the wiring method.
32
µPD78001B(A), 78002B(A)
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
Main System Clock Ceramic Resonator (TA = –40 to +85 °C)
Recommended Oscillation Constant
Oscillation Voltage Range
Manufacturer
Murata m.f.g.
Products
CSB1000J
Frequency (MHz)
C1 (pF)
100
C2 (pF)
100
R1 (kΩ)
MIN. (V)
2.9
MAX. (V)
6.0
1.00
6.8
1.01-1.25
1.26-1.79
CSB ×××× J
100
100
4.7
0
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.9
2.9
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
100
CSA×. ××× MK
CSA×. ××MG
CST×. ××MG
CSA×. ××MG
CST×. ××MGW
CSA×. ××MG
CST×. ××MGW
CSA×. ××MT
CST×. ××MTW
KBR-4.19MWS
KBR-4.19MKS
KBR-4.19MSA
PBRC4.19A
100
100
0
100
1.80-2.44
2.45-4.18
4.19-6.00
6.01-10.0
4.19
On-chip
30
0
On-chip
30
0
On-chip
30
0
On-chip
30
0
On-chip
30
0
On-chip
30
0
On-chip
0
On-chip
Kyocera
–
–
2.7
6.0
–
4.19
10.0
1.00
33
33
–
–
2.7
2.8
2.7
6.0
6.0
6.0
33
33
KBR-10.0M
KBR-1000F
100
2.2
100
KBR-1000Y
Remark ××××, ×. ×××, ×. ×× indicates frequency.
Subsystem Clock: Crystal Resonator (TA = –40 to +60 °C)
Recommended Circuit Constant
Oscillation Voltage Range
Manufacturer
Products
Frequency (MHz)
32.768
C3 (pF)
C4 (pF)
R2 (kΩ)
MIN. (V)
MAX. (V)
DT-38 (1TA632E00,
Load capacitance 6.3pF)
Daishinku corp.
8
8
100
6.0
2.7
Caution
Regarding the oscillator circuit constant, operation is guaranteed, but reliability is not guaranteed. Customers who
require high reliability should directly consult the resonator manufacturer.
33
µPD78001B(A), 78002B(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
VDD
Unit
V
Input voltage
high
P10 to P17, P21, P23, P30 to P32, P35 to P37,
P40 to P47, P50 to P57, P64 to P67
VIH1
0.7 VDD
VIH2
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0.8 VDD
VDD
V
VIH3
VIH4
P60 to P63
X1, X2
Open-drain
0.7 VDD
VDD-0.5
VDD-0.5
VDD-0.3
15
V
V
V
V
VDD
VDD
VDD
VDD = 4.5 to 6.0 V
VIH5
XT1/P04, XT2
Input voltage
low
P10 to P17, P21, P23, P30 to P32, P35 to P37
P40 to P47, P50 to P57, P64 to P67
VIL1
0
0.3 VDD
V
VIL2
VIL3
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0
0.2 VDD
0.3 VDD
0.2 VDD
0.4
V
V
V
V
V
V
V
V
VDD = 4.5 to 6.0 V
0
P60 to P63
0
VIL4
VIL5
X1, X2
0
0
VDD = 4.5 to 6.0 V
0.4
XT1/P04, XT2
0
0.3
Output voltage
high
VDD = 4.5 to 6.0 V,IOH = –1 mA
VDD-1.0
VDD-0.5
VOH1
VOL1
IOH = –100 µA
Output voltage
low
VDD = 4.5 to 6.0 V,
IOL = 15 mA
P50 to P57, P60 to P63
0.4
2.0
0.4
V
V
P01 to P03, P10 to P17, P20 to P27, VDD = 4.5 to 6.0 V,
P30 to P37, P40 to P47, P64 to P67
IOL = 1.6 mA
VDD = 4.5 to 6.0 V,
open-drain
VOL2
SB0, SB1, SCK0
0.2 VDD
0.5
V
V
pulled-up (R = 1 KΩ )
VOL3
IOL = 400 µA
Input leakage
current high
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, RESET
X1, X2, XT1/P04, XT2
P60 to P63
ILIH1
3
µA
VIN = VDD
VIN = 15 V
ILIH2
ILIH3
20
80
µA
µA
Input leakage
current high
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, RESET
ILIL1
–3
µA
VIN = 0 V
ILIL2
ILIL3
X1, X2, XT1/P04, XT2
–20
–200
–3*2
µA
µA
µA
*1
P60 to
P63
Other than above
*
1. When memory expansion mode is used by the memory expansion mode register (MM) with no on-chip pull-up resistor
by mask option.
2. When pull-up resistors are not used (specified by mask option), the low-level input leakage current increases with –200
µA (MAX.) under either of the following conditions.
q
w
When the external device expansion function is used and a low level is input to the pin.
During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode registor (PM6).
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
34
µPD78001B(A), 78002B(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Symbol
ILOH1
Test Conditions
MIN.
TYP.
MAX.
3
Unit
Output leakage
current high
VOUT = VDD
µA
Output leakage
current low
ILOL
VOUT = 0 V
–3
90
µA
kΩ
Mask option pull-
up resister
R1
VIN = 0 V, P60 to P63
20
40
40
Software pull-
up resister
VIN = 0 V, P01 to P03,
P10 to P17, P20 to P27,
P30 to P37, P40 to P47,
P50 to P57, P64 to P67
4.5 V ≤ VDD < 6.0 V
15
20
90
kΩ
kΩ
R2
2.7 V ≤ VDD < 4.5 V
500
Power supply
current *3
VDD = 5.0 V ± 10 % *1
VDD = 3.0 V ± 10 % *2
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
7.5
0.8
1.4
550
60
22.5
2.4
4.2
1650
120
70
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
8.38 MHz
Crystal oscillation
operating mode
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
8.38 MHz
Crystal oscillation
HALT mode
32.768 kHz
Crystal oscillation
operating mode
35
25
50
32.768 kHz
Crystal oscillation
HALT mode
5
10
1
20
XT1 = 0 V STOP mode
When feedback resister
is used
0.5
0.1
0.05
10
XT1 = 0 V STOP mode
When feedback
resister is unused
20
10
*
1. Operating in high-speed mode (when set the processor clock control register to 00H).
2. Operating in low-speed mode (when set the processor clock control register to 04H).
3. Port current are excluded.
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
35
µPD78001B(A), 78002B(A)
AC Characteristics (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
(1) Basic Operation
Parameter
Cycle time
Symbol
TCY
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
122
MAX.
Unit
Operating on main
system clock
0.4
0.96
40
64
64
µs
µs
(Min. instruction
execution time)
TI input
Operationg on subsystem clock
VDD = 4.5 to 6.0 V
125
4
µs
0
MHz
kHz
ns
fTI
frequency
0
275
TI input high/
low-level width
Interrupt input
high/low-level
width
tTIH
tTIL
VDD = 4.5 to 6.0 V
100
1.8
8/fsam*
10
µs
INTP0
µs
tINTH
tINTL
INTP1 to INTP3
KR0 to KR7
µs
10
µs
RESET low
level width
tRSL
10
µs
*
In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of fsam is possible between fX/2N+1
fX/64 and fx/128 (when N = 0 to 4).
,
µPD78P014 (Reference)
µPD78001B(A), 78002B(A)
TCY vs VDD (At main system clock operation)
TCY vs VDD (At main system clock operation)
60
60
10
10
Operation Guaranteed
Range
Operation Guaranteed
Range
µ
µ
2.0
1.0
2.0
1.0
0.5
0.4
0.5
0.4
0
0
1
2
3
4
5
6
1
2
3
4
5
6
Supply Voltage VDD [V]
Supply Voltage VDD [V]
Remark
indicates TA=–40 to +40 °C
indicates TA=–40 to +85 °C
Caution
The operation guaranteed range of the µPD78001B(A), and 78002B(A) differs from that of the
µPD78P014.
36
µPD78001B(A), 78002B(A)
(2) Read/Write Operation (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Test Conditions
MIN.
0.5tCY
0.5tCY–30
10
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
Load resistor ≥ 5 kΩ
Data input time from address
tADD1
tADD2
tRDD1
tRDD2
tRDH
(2+2n)tCY–50
(3+2n)tCY–100
(1+2n)tCY–25
5
Data input time from RD↓
(2.5+2n)tCY–100
Read data hold time
RD low-level width
0
tRDL1
(1.5+2n)tCY–20
(2.5+2n)tCY–20
tRDL2
WAIT↓ input time from RD↓
tRDWT1
tRDWT2
tWRWT
tWTL
0.5tCY
1.5tCY
WAIT↓ input time from WR↓
WAIT low-level width
Write data setup time
Write data hold time
0.5tCY
(0.5+2n)tCY +10
100
(2+2n)tCY
tWDS
tWDH
5
WR low-level width
tWRL1
tASTRD
tASTWR
(2.5+2n)tCY –20
0.5tCY–30
1.5tCY –30
RD↓ delay time from ASTB↓
WR↓ delay time from ASTB↓
ASTB↑ delay time from
RD↑ in external fetch
tRDAST
tCY-10
tCY
tCY+40
tCY+50
ns
ns
Address hold time from
tRDADH
tRDWD
tWDWR
RD↑ in external fetch
Write data output time from RD↑
WR↓ delay time from write data
10
0.5tCY–120
0.5tCY–170
tCY
ns
ns
ns
ns
ns
ns
ns
VDD = 4.5 to 6.0 V
VDD =4.5 to 6.0 V
0.5tCY
0.5tCY
Address hold time from WR↑
tCY+60
tWRADH
tCY
tCY+100
2.5tCY+80
2.5tCY+80
RD↑ delay time from WAIT↑
WR↑ delay time from WAIT↑
tWTRD
tWTWR
0.5tCY
0.5tCY
Remarks
1. tCY = TCY/4
2. n indicates number of waits.
3. CL = 100 pF (CL indicates load capacitance of P40/AD0 to P47/AD7, P50/A8 to P57/A15, P64/RD, P65/WR,
P66/WAIT,P67/ASTB pins).
37
µPD78001B(A), 78002B(A)
(3) Serial Interface (TA = –40 to +85 °C, VDD = 2.7 to 6.0 V)
(a) 3-wire serial I/O mode (SCK... Internal clock output)
Parameter
SCK cycle time
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tKCY1
3200
SCK high/low-level width
tKH1
tKL1
VDD = 4.5 to 6.0 V
tKCY1/2-50
tKCY1/2-150
100
SI setup time (to SCK↑)
SI hold time (from SCK↑)
SO output delay time from
SCK↓
tSIK1
tKSI1
400
VDD = 4.5 to 6.0 V
300
tKSO1
C = 100 pF*
1000
*
C is the load capacitance of SO output line.
(b) 3-wire serial I/O mode (SCK... External clock input)
Parameter
SCK cycle time
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
800
3200
400
ns
ns
ns
ns
tKCY2
SCK high/low-level width
tKH2
tKL2
VDD = 4.5 to 6.0 V
1600
SI setup time (to SCK↑)
SI hold time (from SCK↑)
SO output delay time from
tSIK2
tKSI2
100
400
ns
ns
ns
VDD = 4.5 to 6.0 V
300
tKSO2
tR2
C = 100 pF*
SCK↓
1000
160
SCK rise, fall time
When external device expansion
function is used
ns
ns
When external device expansion
function is not used
1000
tF2
*
C is the load capacitance of SO output line.
38
µPD78001B(A), 78002B(A)
(c) SBI mode (SCK... Internal clock output)
Parameter
SCK cycle time
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
tKCY3
3200
ns
SCK high/low-level width
tKH3
tKL3
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
tKCY3/2-50
tKCY3/2-150
100
ns
ns
SB0, SB1 setup time
ns
tSIK3
(to SCK↑)
300
ns
SB0, SB1 hold time
tKSI3
tKCY3/2
ns
from SCK↓
SB0, SB1 output delay time
(from SCK↑)
R = 1 kΩ ,
VDD = 4.5 to 6.0 V
0
250
ns
ns
ns
ns
ns
ns
tKSO3
C = 100 pF*
0
1000
SB0, SB1↓ from SCK↑
SCK↓ from SB0, SB1↓
SB0, SB1 high-level width
SB0, SB1 low-level width
tKSB
tSBK
tSBH
tSBL
tKCY3
tKCY3
tKCY3
tKCY3
*
R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
(d) SBI mode (SCK... External clock input)
Parameter
SCK cycle time
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
tKCY4
3200
400
ns
SCK high/low-level width
tKH4
tKL4
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
ns
1600
100
ns
SB0, SB1 setup time
(to SCK↑)
ns
tSIK4
300
ns
SB0, SB1 hold time
(from SCK↓)
tKSI4
tKCY4/2
ns
SB0, SB1 output delay time
from SCK↑
R = 1 kΩ ,
VDD = 4.5 to 6.0 V
0
300
ns
ns
ns
ns
ns
ns
ns
tKSO4
C = 100 pF*
0
1000
SB0, SB1↓ from SCK↑
SCK↓ from SB0, SB1↓
SB0, SB1 high-level width
SB0, SB1 low-level width
SCK rise, fall time
tKSB
tSBK
tSBH
tSBL
tKCY4
tKCY4
tKCY4
tKCY4
When external device expansion
function is used
160
tR4
tF4
When external device expansion
function is not used
1000
ns
*
R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
39
µPD78001B(A), 78002B(A)
(e) 2-wire serial I/O mode (SCK... Internal clock output)
Parameter
SCK cycle time
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
1600
3800
ns
ns
ns
ns
tKCY5
SCK high-level width
SCK low-level width
SB0, SB1 setup time
(to SCK↑)
tKH5
tKL5
R = 1 kΩ, C = 100 pF*
tKCY5/2-50
tKCY5/2-50
tSIK5
tKSI5
tKSO5
300
600
ns
ns
SB0, SB1 hold time
(from SCK↑)
SB0, SB1 output delay time
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
0
250
ns
ns
from SCK↓
C = 100 pF*
1000
*
R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
(f) 2-wire serial I/O mode (SCK... External clock input)
Parameter
SCK cycle time
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
1600
3800
650
ns
ns
ns
ns
tKCY6
SCK high-level width
SCK low-level width
SB0, SB1 setup time
(to SCK↑)
tKH6
tKL6
800
tSIK6
tKSI6
tKSO6
100
ns
ns
SB0, SB1 hold time
tKCY6/2
(from SCK↑)
SB0, SB1 output delay time
from SCK↓
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
0
300
1000
160
ns
ns
ns
C = 100 pF*
SCK rise, fall time
When external device expansion
function is used
tR6
tF6
When external device expansion
function is not used
1000
ns
*
R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
40
µPD78001B(A), 78002B(A)
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
Clock Timing
1/fX
tXL
tXH
VDD - 0.5 V
0.4V
X1 Input
1/fXT
tXTL
tXTH
VDD - 0.5 V
0.4V
XT1 Input
TI Timing
1/fTI
tTIL
tTIH
TI1, TI2
41
µPD78001B(A), 78002B(A)
Read/Write Operation
External fetch (no wait):
A8-A15
Upper 8-Bit Address
Lower 8-Bit
Address
tADD1
Hi-z
Operation
Code
AD0-AD7
t
RDADH
t
ADS
t
RDD1
t
ADH
t
ASTH
t
RDAST
ASTB
RD
t
ASTRD
t
RDL1
tRDH
External fetch (wait insertion):
A8-A15
Upper 8-Bit Address
Lower 8-Bit
Address
tADD1
Hi-z
Operation
Code
AD0-AD7
tRDD1
tRDADH
tRDAST
tADS
tADH
tASTH
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tWTRD
tWTL
tRDWT1
42
µPD78001B(A), 78002B(A)
External data access (No wait):
A8-A15
Upper 8-Bit Address
Lower
8-Bit
Address
tADD2
Hi-z
Hi-z
AD0-AD7
Read Data
Write Data
tADS
tRDD2
tADH
tRDH
tASTH
ASTB
RD
tRDWD
tWDS
tWDH
tASTRD
tRDL2
tWDWR
tWRADH
WR
tASTWR
tWRL1
External data access (Wait insertion):
A8-A15
Lower
Upper 8-Bit Address
8-Bit
tADD2
Address
Hi-z
Hi-z
AD0-AD7
Read Data
Write Data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
tASTRD
RD
tWDH
tRDL2
tWDS
tWDWR
tRDWD
WR
tASTWR
tWRL1
tWRADH
WAIT
tRDWT2
tWTRD
tWTL
tWRWT
tWTL
tWTWR
43
µPD78001B(A), 78002B(A)
Serial Transfer Timing
3-wire serial I/O mode:
t
KCY 1,2
t
KL1,2
tKH1,2
t
R2
t
F2
SCK
t
SIK1,2
t
KSI1,2
SI
Input Data
t
KSO1,2
SO
Output Data
SBI mode (Bus release signal transfer):
t
KCY3,4
tKL3,4
tKH3,4
tR4
t
F4
SCK
t
KSB
tSBL
t
SBK
tSIK3,4
t
KSI3,4
t
SBH
SB0, SB1
tKSO3,4
SBI mode (Command signal transfer):
tKCY3,4
tKL3,4
tKH3,4
tR4
tF4
SCK
tSBK
tSIK3,4
tKSI3,4
t
KSB
SB0, SB1
tKSO3,4
44
µPD78001B(A), 78002B(A)
2-wire serial I/O mode:
tKCY5,6
tKL5,6
tR6
tKH5,6
tF6
SCK
tSIK5,6
tKSI5,6
tKSO5,6
SB0, SB1
45
µPD78001B(A), 78002B(A)
Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C)
Parameter
Data retention
Symbol
VDDDR
Test Conditions
MIN.
2.0
TYP.
MAX.
6.0
Unit
V
supply voltage
Data retention
supply
current
VDDDR = 2.0 V
IDDDR
tSREL
tWAIT
Subsystem clock stop and
feed-back resister disconnected
0.1
10
µA
µs
Release signal set time
0
Oscillation stabilization
wait time
Release by RESET
218/fx
µs
µs
Release by interrupt
*
*
In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 213/fx and 215/fx
to 218/fx is possible.
Data Retention Timing (STOP Mode Release by RESET)
HALT Mode
Operating Mode
STOP Mode
Data Retension Mode
V
DD
V
DDDR
t
SREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retension Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
46
µPD78001B(A), 78002B(A)
Interrupt Input Timing
tINTL
tINTH
INTP0-INTP2
tINTL
INTP3
RESET Input Timing
tRSL
RESET
47
µPD78001B(A), 78002B(A)
12. CHARACTERISTIC CURVE (REFERENCE VALUES)
IDD vs VDD (Main System Clock : 8.38 MHz)
(TA=25°C)
10.0
5.0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
PCC=30H
HALT (X1 Oscillation,
XT1 Oscillation)
1.0
0.5
0.1
PCC=B0H
0.05
(X1 Stop,
XT1 Oscillation)
(X1 Stop,
HALT
STOP
XT1 Oscillation)
0.01
f
f
X
=8.38MHz
0.005
XT=32.768kHz
0.001
0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
48
µPD78001B(A), 78002B(A)
IDD vs VDD (Main System Clock : 4.19 MHz)
(TA=25°C)
10.0
5.0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
PCC=30H
HALT
(X1 Oscillation,
XT1 Oscillation)
1.0
0.5
0.1
PCC=B0H
0.05
HALT
STOP
(X1 Stop,
XT1 Oscillation)
(X1 Stop,
XT1 Oscillation)
0.01
f
f
X
=4.19MHz
0.005
XT=32.768kHz
0.001
0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
49
µPD78001B(A), 78002B(A)
IDD vs fX
(VDD = 3 V, T = 25 °C)
A
5
4
PCC=00H
PCC=01H
3
2
1
0
PCC=02H
PCC=03H
PCC=04H
HALT
(X1 Oscilla-
tion)
0
1
2
3
4
5
6
7
8
9
10
11
12
Clock Oscillator Frequency f
X
[MHz]
IDD vs fX
(VDD = 5 V, T
A
= 25 °C)
12
11
10
9
8
7
6
5
4
3
2
1
0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
HALT
(X1 Oscilla-
tion)
0
1
2
3
4
5
6
7
8
9
10
11
12
Clock Oscillator Frequency f
X
[MHz]
50
µPD78001B(A), 78002B(A)
VOL vs IOL (Port 0, 2 to 5, P64 to P67)
(T =25 °C)
VOL vs IOL (P60 to P63)
(T
A
=25 °C)
A
VDD=5 V
V
DD= 6 V VDD=4 V
VDD=3 V
30
20
10
0
V
DD=6 V
V
DD=5 V
V
DD=4 V
30
20
10
0
V
DD=3 V
0
0.5
1.0
Output Voltage Low VOL [V]
0
0.5
1.0
Output Voltage Low VOL [V]
VOL vs IOL (Port 1)
VOH vs IOH (Port 0 to 5, P64 to P67)
(T
A
=25 °C)
(TA=25 °C)
V
DD=6 V VDD=5 V
30
V
DD=5 V
V
DD=4 V
V
V
DD=4 V
-10
V
DD=3 V
V
DD=6 V
DD=3 V
20
10
0
-5
0
0
0.5
1.0
0
0.5
1.0
Output Voltage High VDD – VOH [V]
Output Voltage Low VOL [V]
51
µPD78001B(A), 78002B(A)
13. PACKAGE DRAWINGS
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (1/2)
64-PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
L
F
D
M
R
B
C
M
N
NOTE
ITEM MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
58.68 MAX.
1.78 MAX.
1.778 (T.P.)
2.311 MAX.
0.070 MAX.
0.070 (T.P.)
2) Item "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
I
0.9 MIN.
3.2±0.3
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.750 (T.P.)
0.669
0.51 MIN.
4.31 MAX.
5.08 MAX.
19.05 (T.P.)
17.0
J
K
L
+0.004
0.010
+0.10
0.25
M
–0.003
–0.05
N
R
0.17
0.007
0~15°
0~15°
P64C-70-750A,C-1
Caution
Dimensions and materials of ES products are different from those of mass-production products. Refer
to DRAWINGS OF ES PRODUCT PACKAGES (1/2).
52
µPD78001B(A), 78002B(A)
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (2/2)
64-PIN PLASTIC QFP (■14)
A
B
48
49
33
32
detail of lead end
64
17
16
1
G
H
M
I
J
K
N
L
P64GC-80-AB8-3
NOTE
ITEM
A
MILLIMETERS
17.6 0.4
14.0 0.2
14.0 0.2
17.6 0.4
1.0
INCHES
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
0.693 0.016
+0.009
B
0.551
–0.008
+0.009
C
0.551
–0.008
D
F
0.693 0.016
0.039
G
H
I
1.0
0.039
+0.004
0.35 0.10
0.15
0.014
–0.005
0.006
J
0.8 (T.P.)
1.8 0.2
0.031 (T.P.)
K
0.071 0.008
+0.009
0.031
L
0.8 0.2
–0.008
+0.10
+0.004
0.15
M
N
P
0.006
–0.05
–0.003
0.10
0.004
2.55
0.100
Q
S
0.1 0.1
2.85 MAX.
0.004 0.004
0.112 MAX.
Caution
Dimensions and materials are different from those of mass-production products. Refer to DRAWINGS
OF ES PRODUCT PACKAGES (2/2).
53
µPD78001B(A), 78002B(A)
DRAWINGS OF ES PRODUCT PACKAGES (1/2)
64PIN CERAMIC SHRINK DIP (SEAM WELD) (750 mil)
64
33
32
1
K
L
A
F
D
B
M
N
M
0~15°
C
P64D-70-750A1
NOTES
ITEM
MILLIMETERS
58.16 MAX.
1.521 MAX.
1.778 (T.P.)
0.46 0.05
0.8 MIN.
3.5 0.3
INCHES
1) Each lead centerline is located within 0.25
mm (0.01 inch) of its true position (T.P.) at
maximum material condition.
A
B
C
D
F
2.290 MAX.
0.060 MAX.
0.070 (T.P.)
0.018 0.002
0.031 MIN.
0.138 0.012
0.040 MIN.
0.124
2) Item "K" to center of leads when formed
parallel.
G
H
I
1.02 MIN.
3.14
J
5.08 MAX.
19.05 (T.P.)
18.8
0.200 MAX.
0.750 (T.P.)
0.740
K
L
0.010+–0..00032
M
N
0.25 0.05
0.25
0.01
54
µPD78001B(A), 78002B(A)
DRAWINGS OF ES PRODUCT PACKAGES (2/2)
64 PIN CERAMIC QFP (14 × 14) (FOR ES)
A
B
48
49
33
32
64
17
16
1
G
H
J
K
X64B-80A-1
(Bottom View)
ITEM
A
MILLIMETERS
22.0 0.4
14.0
INCHES
0.866 0.016
0.551
B
C
14.0
0.551
D
22.0 0.4
1.0
0.866 0.016
0.039
F
G
1.0
0.039
H
0.32
0.013
U
V
J
0.8 (T.P.)
4.0 0.15
0.25
0.031 (T.P.)
+0.007
K
0.157
–0.006
M
Q
T
0.01
3.0 MAX.
0.55
0.119 MAX.
0.022
U
1.0
0.039
V
1.2
0.047
55
µPD78001B(A), 78002B(A)
14. RECOMMENDED SOLDERING CONDITIONS
The µPD78001B(A)/78002B(A) should be soldered and mounted under the conditions recommended in the table
below.
For detail of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our sales personnel.
Table 14-1 Surface Mounting Type Soldering Conditions
µPD78001BGC(A)-×××-AB8 :
µPD78002BGC(A)-×××-AB8 :
64-Pin Plastic QFP (■14 mm)
64-Pin Plastic QFP (■14 mm)
Soldering
Method
Recommended
Soldering Conditions
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
Number of times: Twice max.
IR35-00-2
VP15-00-2
—
< Points to note >
(1) Start the second reflow after the device temprature by the first reflow returns to normal.
(2) Flux washing by the water after the first reflow should be avoided.
VPS
Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above)
Number of times: Twice max.
< Points to note >
(1) Start the second reflow after the device temprature by the first reflow returns to normal.
(2) Flux washing by the water after the first reflow should be avoided.
Pin temperature: 300°C max., Duration: 3 sec. max. (per device side)
Pin part heating
Caution
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Table 14-2 Insertion Type Soldering Conditions
µPD78001BCW(A)-××× :
µPD78002BCW(A)-××× :
64-Pin Plastic Shrink DIP (750 mil)
64-Pin Plastic Shrink DIP (750 mil)
Soldering Method
Soldering Conditions
Wave soldering
(Pin only)
Solder bath temperature: 260°C max., Duration: 10 sec. max.
Pin temperature: 300°C max., Duration: 3 sec. max. (per pin)
Pin part heating
Caution
Wave soldering is only for the pins in order that jet solder can not contact with the chip
directly.
56
µPD78001B(A), 78002B(A)
APPENDIX A. DEVEROPMENT TOOLS
The following development tools are available for system development using the µPD78001B(A), 78002B(A).
Language Processing Software
RA78K/0*1, 2, 3
CC78K/0*1, 2, 3
DF78002*1, 2, 3
CC78K/0-L*1, 2, 3
78K/0 series common assembler package
78K/0 series common C compiler package
µPD78002 subseries device file
78K/0 series common C compiler library source file
PROM Programming Tools
PG-1500
PROM programmer
PA-78P014CW
PA-78P014GC
Programmer adapter connected to PG-1500
PG-1500 controller*1, 2
PG-1500 control program
Debugging Tools
IE-78000-R
78K/0 series common in-circuit emulator
78K/0 series common break board
IE-78000-R-BK
IE-78014-R-EM
µPD78002/78014 subseries evaluation emulation board
EP-78240CW-R
EP-78240GC-R
Emulation probe common to µPD78244 subseries
EV-9200GC-64
SD78K/0*1, 2
Socket to be mounted on user system board created for the 64-pin plastic QFP
IE-78000-R screen debugger
SM78K/0*4, 5, 6
DF78002*1, 2, 4, 5
78K/0 series common system simulator
µPD78002 subseries device file
Enbedded OS
MX78K/0*1, 2, 3, 6
78K/0 series common enbedded OS
Fuzzy Inference Development Support System
FE9000*1/FE9200*5
FT9080*1/FT9085*2
FI78K0*1, 2
Fuzzy knowledge data creation tool
Translator
Fuzzy inference module
Fuzzy inference debugger
FD78K0*1, 2
*
1. PC-9800 series (MS-DOSTM) based.
2. IBM PC/ATTM (PC DOSTM) based.
3. HP9000 series 300TM, HP9000 series 700TM (HP-UXTM) based, SPARCstationTM, (Sun OSTM) based, EWS-4800
series (EWS-UX/V) based.
4. PC-9800 series (MS-DOS + WindowsTM) based.
57
µPD78001B(A), 78002B(A)
5. IBM PC/AT (PC DOS + Windows) based.
6. Under development.
Remarks 1. For development tools manufactured by a third party, see the "78K/0 Series Selection Guide" (IF-
1185).
2. RA78K/0, CC78K/0, SD78K/0, and SM78K/0 are used in combination with DF78002.
58
µPD78001B(A), 78002B(A)
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
Document No. (Japanese)
Document No. (Engligh)
User's Manual
IEU-788
IEU-849
IEA-715
IEA-740
IEU-1334
IEU-1372
IEA-1288
IEA-1299
78K/0 Series User's Manual - Instruction
Application Note
Basic I
Basic II
Development Tools Documents (User's Manual)
Document Name
Document No. (Japanese)
Document No. (Engligh)
RA78K Series Assembler Package
Operation
EEU-809
EEU-815
EEU-817
EEU-656
EEU-655
EEU-651
EEU-704
EEU-810
EEU-867
EEU-805
EEU-986
EEU-852
EEU-816
EEU-1399
EEU-1404
EEU-1402
EEU-1280
EEU-1284
EEU-1335
EEU-1291
EEU-1398
EEU-1427
EEU-1400
In preparation
EEU-1414
EEU-1413
Language
RA78K Series Structured Assembler Preprocessor
CC78K Series C Compiler
Operation
Language
PG-1500 PROM Programmer
PG-1500 Controller
IE-78000-R
IE-78000-R-BK
IE-78014-R-EM
EP-78240
SD78K/0 Screen Debugger
Beginner's guide
Reference
Embedded Software Documents (User's Manual)
Document Name
Document No. (Japanese)
EEU-892
Document No. (Engligh)
EEU-1438
Fuzzy Knowledge Data Creation Tool
78K/0, 78K/II, 87AD Series
EEU-862
EEU-1444
Fuzzy Inference Development Support System - Translator
Caution These documents above are subject to change without notice. Besure to use the latest document for
designing your system.
59
µPD78001B(A), 78002B(A)
Other Documents
Document Name
Document No. (Japanese)
Document No. (Engligh)
IEI-1213
Package Manual
IEI-635
IEI-616
IEI-620
MEI-603
Semiconductor Device Mounting Technology Manual
Quality Grade on NEC Semiconductor Devices
Semiconductor Device Quality Guarantee Guide
IEI-1207
IEI-1209
MEI-1202
Caution These documents above are subject to change without notice. Besure to use the latest document for
designing your system.
60
µPD78001B(A), 78002B(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immedi-
ately after power-on for devices having reset function.
61
µPD78001B(A), 78002B(A)
[MEMO]
The export of this product from Japan is regulated by the Japanese government. To export this product may be
prohibited without governmental license, the need for which must be judged by the customer. The export or re-
export of this product from a country other than Japan may also be prohibited without a license from that country.
Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
FIP is a registered trademark of NEC Corporation.
IEBus is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
相关型号：
UPD78002BCW(A)-XXX
Microcontroller, 8-Bit, MROM, 10MHz, MOS, PDIP64, 0.750 INCH, SHRINK, PLASTIC, DIP-64
NEC
UPD780031ACW(A)-XXX
Microcontroller, 8-Bit, MROM, 8.38MHz, MOS, PDIP64, 0.750 INCH, PLASTIC, SDIP-64
NEC
©2020 ICPDF网 联系我们和版权申明