UPD78002BYCW-XXX [NEC]
Microcontroller, 8-Bit, MROM, MOS, PDIP64, 0.750 INCH, SHRINK, PLASTIC, DIP-64;
| 型号： | UPD78002BYCW-XXX |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 8-Bit, MROM, MOS, PDIP64, 0.750 INCH, SHRINK, PLASTIC, DIP-64 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总60页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78001BY, 78002BY
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD78001BY/78002BY are the products in the µPD78002Y subseries within 78K/0 series.
The µPD78001BY/78002BY have tim er, serial interface (I2C bus m ode com patibility), interrupt functions and m any
other peripheral hardware functions.
A one-tim e PROM or EPROM product µPD78P014Y capable of operating in the sam e power supply voltage range
as of the m ask ROM product and other developm ent tools are also provided.
Functions are described in detail in the follow ing User's Manual, w hich should be read w hen carrying out design
w ork.
µPD78002, 78002Y Series User's Manual: IEU-1334
FEATURES
• Large on-chip ROM & RAM
Item
Product Nam e
Program Mem ory
(ROM)
Data Mem ory
Package
(Internal High-Speed RAM)
µPD78001BY
µPD78002BY
8K bytes
256 bytes
384 bytes
•
•
64-pin plastic shrink DIP (750 m il)
64-pin plastic QFP ( 14 m m )
16K bytes
•
•
•
•
•
•
External m em ory expansion space : 64K bytes
Instruction execution tim e can be varied from high-speed (0.4 µs) to ultra-low-speed (122 µs)
I/O ports : 53 (N-ch open-drain : 4)
Serial interface (I2C bus m ode com patibility) : 1 channel
Tim er: 4 channels
Operating voltage range : 2.7 to 6.0 V
APPLICATION
Television, VCR, audio, etc.
The inform ation in this docum ent is subject to change w ithout notice.
The mark ★ shows major revised points.
Document No. IC-3173B
(O.D. No. IC-8571B)
Date Published December 1994 P
Printed in Japan
1994
©
µPD78001BY, 78002BY
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
µPD78001BYCW-×××
64-pin plastic shrink DIP (750 m il)
64-pin plastic QFP (■ 14 m m )
64-pin plastic shrink DIP (750 m il)
64-pin plastic QFP (■ 14 m m )
Standard
Standard
Standard
Standard
µPD78001BYGC-×××-AB8
µPD78002BYCW-×××
µPD78002BYGC-×××-AB8
Rem arks ××× indicates ROM code No.
Please refer to "Quality grade on NEC Sem iconductor Devices" (Docum ent num ber IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recom m ended applications.
78/ 0 SERIES PRODUCT DEVELOPMENT
µPD78078Y Subseries
Products in Volum e Production
µPD78078 Subseries
µPD78064Y Subseries
µPD78064 Subseries
100-pin package
8 bit-tim er/event
counter added
Products under Developm ent
100-pin package
LCD controller/driver,
UART added
Y series products are com patible with I2C bus.
External expansion
function enhanced
16-bit tim er/event
counter function
enhanced
µPD78098 Subseries
µPD78054Y Subseries
µPD78054 Subseries
80-pin pakage
IEBusTM controller added
80-pin package
µPD78014Y Subseries
µPD78014 Subseries
UART, D/A converter,
Real-tim e output port added
16-bit tim er/event counter
function enhanced
64-pin package
A/D converter,
16-bit tim er/event counter
function,
SIO with autom atic transm it/
receive function added
Multiplication/division
instruction added
µPD78044AY Subseries
µPD78044A Subseries
µPD78044 Subseries
µPD78024Y Subseries
µPD78024 Subseries
80-pin package
µPD78002Y Subseries
Au to m a tic tra n s m it/re ce ive
function added
64-pin package
µPD78002 Subseries
A/D converter,
6-bit up/down counter added
FIP controller/driver function
enhanced
16-bit tim er/event counter.
FIP controller/driver
Mu ltip lica tio n /d ivis io n
instrustion added
64-pin package
2
µPD78001BY, 78002BY
OVERVIEW OF FUNCTION
Product Nam e
Item
µPD78001BY
µPD78002BY
ROM
8K bytes
16K bytes
384 bytes
Internal
Internal high-
speed RAM
m em ory
256 bytes
Mem ory space
General registers
Instruction cycle
64K bytes
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
On-chip instruction execution tim e cycle m odification function
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 10.0 MHz operation)
When m ain system
clock selected
When subsystem
clock selected
122 µs (at 32.768 kHz operation)
Instruction set
• 16-bit operation
• Bit m anipulation (set, reset, test, boolean operation)
• BCD correction, etc.
I/O ports
Total
: 53
• CMOS input
• CMOS I/O
: 02
: 47
• N-channel open-drain I/O
(15 V withstand voltage) : 04
• 3-wire/SBI/2-wire/I2C m ode selectable
Serial interface
Tim er
• 8-bit tim er/event counter : 2 channels
• Watch tim er
• Watchdog tim er
: 1 channel
: 1 channel
2
Tim er output
Clock output
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at m ain system clock 10.0 MHz operation),
32.768 kHz (at subsystem clock 32.768 kHz operation)
2.4 kHz, 4.9 kHz, 9.8 kHz (at m ain system clock 10.0 MHz operation)
Buzzer output
Internal : 5
External: 4
Vectored
Maskable
interrupts interrupts
Internal : 1
Non-m askable
interrupt
Internal : 1
Software
interrupt
Internal : 1
External : 1
Test input
Operating voltage range
VDD = 2.7 to 6.0 V
Operating tem perature
range
–40 to +85°C
• 64-pin plastic shrink DIP (750 m il)
• 64-pin plastic QFP (■14 m m )
Package
3
µPD78001BY, 78002BY
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) .....................................................................................................
5
8
2. BLOCK DIAGRAM ...................................................................................................................................
3. PIN FUNCTIONS .....................................................................................................................................
9
9
3.1
3.2
3.3
PORT PINS ......................................................................................................................................................
OTHER PORTS ................................................................................................................................................ 10
PIN I/ O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS ...................................... 12
4. MEMORY SPACE.................................................................................................................................... 14
5. PERIPHEL HARDWARE FUNCTION FEATURES ................................................................................. 15
5.1
5.2
5.3
5.4
5.5
5.6
PORTS .............................................................................................................................................................. 15
CLOCK GENERATOR...................................................................................................................................... 16
TIMER/ EVENT COUNTER.............................................................................................................................. 17
CLOCK OUTPUT CONTROL CIRCUIT ......................................................................................................... 19
BUZZER OUTPUT CONTROL CIRCUIT ....................................................................................................... 19
SERIAL INTERFACES ..................................................................................................................................... 20
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS .......................................................................... 21
6.1
6.2
INTERRUPT FUNCTIONS ............................................................................................................................... 21
TEST FUNCTIONS .......................................................................................................................................... 24
7. EXTERNAL DEVICE EXPANTION FUNCTIONS. ................................................................................. 25
8. STANDBY FUNCTIONS ......................................................................................................................... 25
9. RESET FUNCTIONS ............................................................................................................................... 25
10. INSTRUCTION SET ................................................................................................................................ 26
11. ELECTRICAL SPECIFICATIONS ............................................................................................................. 28
12. CHARACTERISTIC CURVE (REFERENCE VALUES) ........................................................................... 47
13. PACKAGE INFORMATION ..................................................................................................................... 52
14. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 56
APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 57
APPENDIX B. RELATED DOCUMENTS ...................................................................................................... 58
4
µPD78001BY, 78002BY
1. PIN CONFIGURATION (TOP VIEW)
64-Pin Plastic Shrink DIP (750 m il)
P20
P21
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IC3
2
IC2
P22
3
P17
P16
P15
P14
P13
P12
P11
P10
IC1
P23
4
P24
5
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30
6
7
8
9
P31/TO1
P32/TO2
P33/TI1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P04/XT1
XT2
IC0
µ
µ
P34/TI2
P35/PCL
P36/BUZ
P37
X1
X2
VSS
V
DD
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0
RESET
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P63
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P62
P61
P60
P57/A15
P56/A14
VSS
Rem arks Always connect the IC0, 1, 3, (Internally Connected) pin to VSS directly.
Always connect the IC2 pin to VDD directly.
5
µPD78001BY, 78002BY
64-Pin Plastic QFP (■14 m m )
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
P30
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
1
P11
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P10
3
IC1
µ
µ
4
P04/XT1
XT2
5
6
IC0
7
X1
8
X2
VSS
9
VDD
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
10
11
12
13
14
15
16
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0
RESET
P67/ASTB
P66/WAIT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Rem arks Always connect the IC0, 1, 3, (Internally Connected) pin to VSS directly.
Always connect the IC2 pin to VDD directly.
6
µPD78001BY, 78002BY
P00 to P04
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
: Port 0
: Port 1
: Port 2
: Port 3
: Port 4
: Port 5
: Port 6
SDA0 and SDA1 : Serial Data 0 and 1
PCL
: Program m able Clock
BUZ
: Buzzer Clock
AD0 to AD7
A8 to A15
RD
: Address/Data Bus 0 to 7
: Address Bus 8 to 15
: Read Strobe
WR
: Write Strobe
INTP0 to INTP3 : Interrupt From Peripherals 0 to 3
WAIT
: Wait
TI1 and TI2
TO1 and TO2
SB0 and SB1
SI0
: Tim er Input 1 and 2
: Tim er Output 1 and 2
: Serial Bus 0 and 1
: Serial Input 0
ASTB
X1, X2
XT1, XT2
RESET
VDD
: Address Strobe
: Crystal1, 2 (Main System Clock)
: Crystal1, 2 (Subsystem Clock)
: Reset
SO0
: Serial Output 0
: Serial Clock 0
: Power Supply
SCK0
VSS
: Ground
SCL
: Serial Clock
IC0 to IC3
: Internally Connected
7
P00
PROGRAM COUNTER
P01-P03
P04
PORT0
PORT1
TO1/P31
TI1/P33
8-bit TIMER/
EVENT COUNTER 1
P10-P17
P20-P27
GENERAL REG.
ROM
PROGRAM
MEMORY
TO2/P32
TI2/P34
PORT2
PORT3
PORT4
DECODE
AND
CONTROL
8-bit TIMER/
EVENT COUNTER 2
RAM
DATA MEMORY
P30-P37
WATCHDOG TIMER
WATCH TIMER
P40-P47
P50-P57
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
PORT5
PORT6
PSW
SP
SERIAL
INTERFACE 0
ALU
P60-P67
CLOCK
CLOCK GENERATOR
AD0/P40-
AD7/P47
BUZZER
OUTPUT
CLOCK
DIVIDER
STAND BY
CONTROL
OUTPUT
CONTROL
SUB
MAIN
A8/P50-
A15/P57
EXTERNAL
ACCESS
RD/P64
µ
BUZ/P36
PCL/P35
P04/XT1 XT2
X1 X2
WR/P65
WAIT/P66
ASTB/P67
RESET
VDD
VSS
IC0-
IC3
INTP0/P00
-INTP3/P03
INTERRUPT
CONTROL
Rem arks
Internal ROM & RAM capacity varies depending on the product.
µPD78001BY, 78002BY
3. PIN FUNCTIONS
3.1 PORT PINS (1/ 2)
After
Reset
Dual-
Function Pin
Pin Nam e
P00
I/O
Function
INTP0
INTP1
INTP2
INTP3
XT1
Input
Port 0
5-bit I/O port
Input only
Input
P01
Input/
output
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be
used by software.
P02
P03
P04*
P10 to P17
Input
Input only
Input
Input
—
Input/
Port 1
output
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
—
P20
Input/
output
Port 2
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input
Input
Input
—
P21
—
P22
—
P23
—
P24
P25
SI0/SB0/SDA0
P26
SO0/SB1/SDA1
P27
SCK0/SCL
P30
—
TO1
Input/
output
Port 3
8-bit input/output port.
Input/output can be specified in 1-bit units.
When used as an input port, pull-up resistor can be used by software.
P31
P32
TO2
P33
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
P40 to P47
Input/
Port 4
AD0 to AD7
output
8-bit input/output port.
Input/output can be specified in 8-bit unit.
When used as an input port, pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
*
When using the P04/XT1 pins as an input port, set 1 to bit 6 (REC) of the processor clock control register. Do
not use the on-chip feedback register of the subsystem clock oscillator.
9
µPD78001BY, 78002BY
3.1 PORT PINS (2/ 2)
After
Reset
Dual-
Function Pin
Pin Nam e
P50 to P57
I/O
Function
A8 to A15
Input/
Port 5
Input
output
8-bit input/output port.
LED can be driven directly.
Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
P60
P61
P62
P63
P64
P65
P66
P67
N-ch open-drain input/output port.
On-chip pull-up resistor can be speci-
fied by m ask option.
Input/
output
Port 6
Input
8-bit input/output port.
Input/output can be specified bit-
wise
LED can be driven directly.
When used as an input port, pull-
up resistor can be used by soft-
ware.
RD
WR
WAIT
ASTB
Note
When pull-up resistors are not used (specified by m ask option), the low -level input leak current increases
w ith -200 µA (MAX.) under either of the follow ing conditions.
➀
➁
When the external device expansion function is used and a low -level is input to the pin.
During the 3-clock period w hen a read instruction is executed on port 6 (P6) and the port m ode register
(PM6).
3.2
OTHER PORTS(1/ 2)
After
Reset
Dual-
Function Pin
Pin Nam e
INTP0
Function
I/O
Input
Input
P00
External interrupt input by which the effective edge (rising edge, falling
edge, or both rising edge and falling edge) can be specified.
INTP1
INTP2
INTP3
SI0
P01
P02
Falling edge detection external interrupt input.
Serial interface serial data input.
P03
Input
Input
Input
P25/SB0/SDA0
P26/SB1/SDA1
P25/SI0/SDA0
P26/SO0/SDA1
P25/SI0/SB0
P26/SO0/SB1
P27/SCL
Input
SO0
Output
Serial interface serial data output.
Input
/output
SB0
Serial interface serial data input/output.
SB1
SDA0
SDA1
SCK0
SCL
Input
Input
/output
Serial interface serial clock input/output.
P22/SCK0
10
µPD78001BY, 78002BY
3.2 OTHER PORTS (2/ 2)
After
Reset
Dual-
Function Pin
Pin Nam e
TI1
Function
I/O
External count clock input to 8-bit tim er (TM1).
External count clock input to 8-bit tim er (TM2).
8-bit tim er (TM1) output.
Input
Input
Input
P33
P34
TI2
TO1
Output
P31
TO2
8-bit tim er (TM2) output.
P32
PCL
Clock output (for m ain system clock, subsystem clock trim m ing).
Buzzer output.
Output
Output
Input
Input
Input
P35
BUZ
P36
AD0 to AD7
Low-order address/data bus at external m em ory expansion.
P40 to P47
Input
/output
Output
Output
A8 to A15
RD
High-order address bus at external m em ory expansion.
External m em ory read operation strobe signal output.
External m em ory write operation strobe signal output.
Wait insertion at external m em ory access.
Input
Input
P50 to P57
P64
WR
P65
Input
WAIT
ASTB
Input
Input
P66
Strobe output which latches the address inform ation output at port 4 and
port 5 to access external m em ory.
Output
P67
System reset input.
Input
Input
—
RESET
X1
—
—
—
—
Main system clock oscillation crystal connection.
X2
—
—
Subsystem clock oscillation crystal connection.
Input
—
XT1
Input
—
P04
—
XT2
Positive power supply.
—
VDD
—
—
Ground potential.
VSS
—
—
—
Internal connection. Connect IC0, 1 and 3 to VSS, IC2 to VDD directly.
IC0 to IC3
—
—
—
11
µPD78001BY, 78002BY
3.3 PIN I/ O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recom m ended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Fig. 3-1.
Table 3-1 Input/ Output Circuit Type of Each Pin
Input/output
I/O
Pin Nam e
P00/INTP0
Recom m ended Connection when Not Used
Connected to VSS .
Circuit Type
2
Input
Input/output
8-A
Input
: Connected to VSS .
: Leave open.
P01/INTP1
P02/INTP2
P03/INTP3
P04/XT1
Output
Input
16
Connected to VSS .
Input/output
Input
: Connected to VDD or VSS .
5-A
P10 to P17
P20 to P24
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30
Output
: Leave open.
10-A
5-A
Input/output
Input
: Connected to VDD or VSS .
: Leave open.
Output
P31/TO1
P32/TO2
8-A
5-A
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
Input
: Connected to VDD or VSS .
: Leave open.
Input/output
Input/output
5-E
P40/AD0 to P47/AD7
Output
5-A
13-B
5-A
Input
: Connected to VDD or VSS .
: Leave open.
P50/A8 to P57/A15
P60 to P63
P64/RD
Output
P65/WR
P66/WAIT
P67/ASTB
RESET
2
Input
—
—
16
—
Leave open.
XT2
Connected to VSS .
Connected to VDD .
IC0, 1, 3
IC2
12
µPD78001BY, 78002BY
Fig. 3-1 Pin Input/ Output Circuits
Type 10-A
Type 2
VDD
pullup
enable
P-ch
VDD
IN
data
P-ch
IN / OUT
open drain
output disable
N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
Type 5-A
Type 13-B
VDD
VDD
Mask
Option
pullup
enable
P-ch
IN / OUT
VDD
P-ch
data
N-ch
VDD
output disable
data
IN / OUT
output
disable
N-ch
P-ch
RD
input
enable
Middle-High Voltage Input Buffer
Type 16
Type 5-E
VDD
feedback
cut-off
pullup
enable
P-ch
P-ch
VDD
P-ch
data
IN / OUT
output
disable
N-ch
XT1
XT2
Type 8-A
VDD
pullup
enable
P-ch
VDD
P-ch
data
IN / OUT
output
disable
N-ch
13
µPD78001BY, 78002BY
4. MEMORY SPACE
The m em ory m ap of µPD78001BY/78002BY is shown in Fig. 4-1.
Fig. 4-1 Mem ory Map
FFFFH
Special Function Registers
(SFR) 256 × 8 Bits
FF00H
FEFFH
General Registers
32 × 8 Bits
FEE0H
FEDFH
Internal High-Speed RAM*
mmmmH
nnnnH
mmmmH–1
Program Area
CALLF Entry Area
Program Area
Data
1000H
0FFFH
Memory
Space
Use Prohibited
0800H
07FFH
FA80H
FA7FH
Program
Memory
Space
0080H
007FH
External Memory
nnnnH+1
nnnnH
CALLT Table Area
Vector Table Area
0040H
003FH
Internal ROM*
0000H
0000H
Rem arks Shaded area indicates internal m em ory.
*
Interm al ROM and internal high-speed RAM capacities vary depending on the product (see the table below).
Internal High-Speed
RAM Start Address
m m m m H
Intenal ROM End Address
Product Nam e
nnnnH
1FFFH
3FFFH
µPD78001BY
µPD78002BY
FE00H
FD80H
14
µPD78001BY, 78002BY
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 PORTS
The I/O port has the following three types
• CMOS input (P00, P04)
: 2
• CMOS input/output (P01 to P03, port 1 to port 5, P64 to P67)
: 47
• N-ch open-drain input/output (15V withstand voltage) (P60 to P63) : 4
Total
: 53
Table 5-1 Functions of Ports
Port Nam e
Port 0
Pin Nam e
P00, P04
Function
Dedicated Input port
P01 to P03
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified in 8-bit units.
When used as an input port, pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
LED can be driven directly.
P10 to P17
P20 to P27
P30 to P37
P40 to P47
Port 1
Port 2
Port 3
Port 4
P50 to P57
P60 to P63
P64 to P67
Port 5
Port 6
N-ch open-drain input/output port. Input/output can be specified bit-wise.
On-chip pull-up resistor can be specified by m ask option.
LED can be driven directly.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Caution
When pull-up resistors are not used (specified by m ask option), low -level input leak current increases
w ith –200 m A (MAX.) under either of the follow ing conditions.
➀
➁
When the external device expansion function is used and a low -level is input to the pin.
During the 3-clock period w hen a read instruction is executed on port 6 (P6) and the port m ode register
(PM6).
15
µPD78001BY, 78002BY
5.2 CLOCK GENERATOR
There are two types of clock generator: m ain system clock and subsystem clock.
The instruction exection tim e can be changed.
• 0.4µs/0.8µs/1.6µs/3.2µs/6.4µs (m ainsystem clock: at 10.0 MHz operation)
• 122µs (subsystem clock: at 32.768 KHz operation)
Fig. 5-1 Clock Generator Block Diagram
XT1
/P04
Watch Timer
Clock Output
Function
Subsystem
Clock
Osicillator
fXT
XT2
Prescaler
Main
System
Clock
X1
fX
Clock to
Peripheral
Hardware
Prescaler
X2
Osicillator
fX
2
fX
22
fX
24
fX
23
STOP
CPU
Clock
(fCPU)
Standby
Control
Circuit
Wait
Control
Circuit
Selector
INTP0
Sampling Clock
16
µPD78001BY, 78002BY
5.3 TIMER/ EVENT COUNTER
The following four channels are incorporated in the tim er/event counter.
• 8-bit tim er/event counter
• Watch tim er
: 2 channels
: 1 channel
: 1 channel
• Watchdog tim er
Table 5-2 Types and Features of Tim er/ Event Counter
8-bit Tim er/Event
Watch Tim er
Watchdog Tim er
Counter
Type
Interval tim er
2 channels
2 channels
2 outputs
2 outputs
2
1channel
1 channel
Externanal event counter
–
–
–
2
–
–
–
1
Functions Tim er output
Sqare wave output
Interrupt request
Fig. 5-2 8-bit Tim er/ Enent Counter Block Diagram
Internal Bus
INTTM1
8-Bit Compare
Register (CR10)
8-Bit Compare
Register (CR20)
Output
Control
Circuit
Selector
Match
TO2/P32
INTTM2
Match
fX/22–fX/210
8-Bit Timer
Selector
Selector
fX/212
Register 1 (TM1)
8-Bit Timer
Selector
TI1/P33
Register 2 (TM2)
Clear
Clear
fX/22–fX/210
Selector
fX/212
TI2/P34
Output
Control
Circuit
TO1/P31
Internal Bus
17
µPD78001BY, 78002BY
Fig. 5-3 Watch Tim er Block Diagram
fW
214
Selector
5-Bit Counter
fX/28
fXT
fw
Selector
INTWT
Prescaler
Selector
fW
213
fW
24
fW
25
fW
26
fW
29
fW
27
fW
28
Selector
INTTM3
Fig. 5-4 Watchdog Tim er Block Diagram
fX
24
Prescaler
fX
25
fX
26
fX
27
fX
28
fX
29
fX
fX
210 212
INTWDT
Maskable
Interrupt Request
Control
Circuit
Selector
8-Bit Counter
RESET
INTWDT
Non-Maskable
Interrupt Request
18
µPD78001BY, 78002BY
5.4 CLOCK OUTPUT CONTROL CIRCUIT
The clock with the following frequencies can be output for clock output.
• 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation)
• 32.768 kHz (Subsystem clock: at 32.768 kHz operation)
Fig. 5-5 Clock Output Control Block Diagram
fX/23
fX/24
fX/25
Synchronization
Circuit
Output Control
Circuit
fX/26
PCL/P35
Selector
fX/27
fX/28
fXT
5.5 BUZZER OUTPUT CONTROL CIRCUIT
The clock with the following frequencies can be output for buzzer output.
• 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation)
Fig. 5-6 Buzzer Output Control Block Diagram
fX/210
Output Control
Circuit
fX/211
fX/212
BUZ/P36
Selector
19
µPD78001BY, 78002BY
5.6 SERIAL INTERFACES
There is an on-chip clocked serial interface as follows.
•
Serial Interface channel 1
The serial interface channel 0 has four kinds of m odes as follows.
• 3-wire serial I/O m ode
: MSB/LSB-first switchable
• SBI (Serial Bus Interface) m ode : MSB-first
• 2-wire serial I/O m ode
• I2C (Inter IC) Bus Mode
: MSB-first
: MSB-first
Fig. 5-7 Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/
SDA0/P25
Output
Latch
Serial I/O Shift
Register 0 (SIO0)
Selector
Selector
SO0/SB1/
SDA1/P26
Busy/Acknowledge
Output Circuit
Bus Release/Command/
Acknowledge Detection
Circuit
Interrupt
Request
Signal
INTCSI0
SCK0/SCL/P27
Serial Counter
Generator
fX/22–fX/29
TO2
Serial Clock
Control Circuit
Selector
20
µPD78001BY, 78002BY
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS
There are 11 interrupt Functions of 3 different kinds as shown below.
• Non-m askable interrupt
• Maskable interrupt
• Software interrupt
:
:
:
1
9
1
Table. 6-1 Interrupt Source LIst
*1
Default
Priority
*2
Interrupt Source
Trigger
Vector
Table
Address
Basic
Configuration
Type
Interrupt
Type
Internal/
External
Nam e
Non-
m askable
Watchdog tim er overflow
(with non-m askable interrupt selected)
—
INTWDT
A
Internal
External
004H
Watchdog tim er overflow
(with interval tim er selected)
Maskable
0
1
2
3
4
5
6
INTWDT
INTP0
INTP1
INTP2
INTP3
B
C
D
Pin input edge detection
0006H
0008H
000AH
000CH
000EH
0012H
INTCSI0 Serial interface channel 0 transfer end
Internal
B
INTTM3 Reference tim e intervalsignalfrom watch tim er
8-bit tim er/event counter 1 m atch signal
generation
INTTM1
7
0016H
8-bit tim er/event counter 2 m atch signal
generation
INTTM2
8
0018H
003EH
BRK instruction execution
Internal
BRK
Software
—
E
*
1. The default priority is the priority applicable when m ore than one m askable interrupt is generated.
0 is the highest priority and 11, the lowest.
2. Basic configuration types A to E correspond to A to E on the next page.
21
µPD78001BY, 78002BY
Fig. 6-1 Basic Interrupt Function Configuration (1/ 2)
(A) Internal Non-Maskable Interrupt
Internal Bus
Vector Table
Address
Generator
Interrupt
Request
Priority Control
Circuit
Standby Release
Signal
(B) Internal Maskable Interrupt
Internal Bus
PR
ISP
MK
IE
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
IF
Standby Release
Signal
(C) External Maskable Interrupt (INTP0)
Internal Bus
MK
Sampling Clock
Select Register
(SCS)
External Interrupt
Mode Register
(INTM0)
PR
ISP
IE
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Edge
Detector
Sampling
Clock
IF
Standby Release
Signal
22
µPD78001BY, 78002BY
Fig. 6-1 Basic Interrupt Function Configuration (2/ 2)
(D) External Maskable Interrupt (Except INTP0)
Internal Bus
MK
External Interrupt
Mode Register
(INTM0)
PR
ISP
IE
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Edge
Detector
IF
Standby Release
Signal
(E) Softw are Interrupt
Internal Bus
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Rem arks 1. IF : Interrupt request flag
2. IE : Interrupt enable flag
3. ISP : In-service priority flag
4. MK : Interrupt m ask flag
5. PR : Priority spcification flag
23
µPD78001BY, 78002BY
6.2 TEST FUNCTIONS
There are two test functinos as shown in Table 6-2.
Table. 6-2 Test Source List
Test Source
Trigger
Internal/External
Nam e
INTWT
INTPT4
Watch tim er overflow
Interna
Port 4 falling edge detection
External
Fig. 6-2 Test Function Basic Configuration
Internal Bus
MK
Standby Release
Signal
Test Input Signal
IF
Rem arks 1. IF
: Test input flag
2. MK : Test m ask flag
24
µPD78001BY, 78002BY
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion function is used to connect external devices to areas other than the internal ROM,
RAM and SFR.
Ports 4 to 6 are used for connection with external devices.
8. STANDBY FUNCTIONS
There are the following two standby functions to reduce the current dissipation.
• HALT m ode
• STOP m ode
:
:
The CPU operating clock is stopped. The average consum ption current can be reduced by
interm ittent operation in com bination with the norm al operating m ode.
The m ain system clock oscillation is stopped. The whole operation by the m ain system clock
is stopped, so that the system operates withultra-low power consum ption using only the
subsystem clock.
Fig. 8-1 Standby Functions
CSS=1
Main System
Subsystem Clock
Clock Operation
Operation*
CSS=0
HALT
Instruction
STOP
Instruction
HALT
Instruction
Interrupt
Request
Interrupt
Request
Interrupt
Request
STOP Mode
HALT Mode
HALT Mode*
(Main system clock
oscillation stopped)
(Clock supply to CPU is
stopped, oscillation)
(Clock supply to CPU is
stopped, oscillation)
*
The power consum ption can be reduced by stopping the m ain system clock. When the CPU is operating on the
subsystem clock, set the MCC to stop the m ain system clock. The STOP instruction cannot be used.
Note
When the m ain system clock is stopped and the system is operated by the subsystem clock, the subsystem
clock should be sw itched again to the m ain system clock after the oscillation stabilization tim e is secured
by the program by the program .
9. RESET FUNCTIONS
There are the following two reset m ethods.
• External reset input by RESET pin.
• Internal reset by watchdog tim er runaway tim e detection.
25
µPD78001BY, 78002BY
10. INSTRUCTION SET
(1) 8-Bit Instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH,
POP, DBNZ
2nd Operand
1st Operand
[HL+byte]
[HL+B]
[HL+C]
#byte
A
r*
sfr
saddr !addr16
PSW
MOV
[DE]
[HL]
$adder16
1
None
A
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROR
ROL
RORC
ROLC
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
r1
DBNZ
DBNZ
sfr
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
sadder
INC
DEC
XOR
CMP
!adder16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL+byte]
[HL+B]
MOV
[HL+C]
*
Except r=A
26
µPD78001BY, 78002BY
(2) 16-Bit Instruction
MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
#word
AX
rp*
sfrp
saddrp
!addr16
SP
None
1st Operand
AX
ADDW
SUBW
CMPW
MOVW
XCHW
MOVW
MOVW
MOVW
MOVW
rp
MOVW
MOVW*
INCW, DECW
PUSH, POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
sadderp
!adder16
SP
MOVW
*
Only when rp=BC, DE, HL.
(3) Bit Manipulation Instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
sfr.bit
saddr.bit
PWS.bit
[HL].bit
CY
$addr16
None
1st Operand
A.bit
MOV1
BT
BF
SET1
CLR1
BTCLR
sfr.bit
MOV1
MOV1
MOV1
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BT
BF
BTCLR
SET1
CLR1
BT
BF
BTCLR
SET1
CLR1
BT
BF
BTCLR
SET1
CLR1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
AND1
OR1
SET1
CLR1
NOT1
XOR1
XOR1
XOR1
XOR1
XOR1
(4) CALL INSTRUCTION/ BRANCH INSTRUCTION
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
AX
!addr16
!addr11
[addr5]
$addr16
1st Operand
Basic instruction
BR
CALL, BR
CALLF
CALLT
BR, BC, BNC,
BZ, BNZ
Com pound
instruction
BT, BF,
BTCLR,
DBNZ
(5) Other Instruction
ADJ BA, ADJ BS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
27
µPD78001BY, 78002BY
11. ELECTRICAL SPECIFICATIONS
Absolute Maxim um Ratings (Ta = 25 °C)
Param eter
Supply voltage
Input voltage
Sym bol
Test Conditions
Rating
Unit
V
VDD
–0.3 to + 7.0
P00 to P04, P10 to P17,P20 to P27, P30 toP37
P40 toP47, P50 to P57, P64 to P67, X1, X2, XT2
VI1
–0.3 to VDD + 0.3
V
VI2
P60 to P63
Open-drain
–0.3 to +16
V
Output voltage
VO
–0.3 to VDD + 0.3
V
Output current
high
1 pin
–10
–15
–15
30
m A
m A
m A
m A
m A
m A
m A
m A
m A
m A
m A
m A
m A
IOH
P10 to P17, P20 to P27, P30 to P37 total
P01 to P03, P40 to P47, P50 to P57, P60 to P67 total
Output current
low
Peak value
1 pin
R.m .s. value
15
Peak value
P40 to P47, P50 to P55 total
R.m .s. value
100
70
P01 to P03, P56, P57,
P60 to P67 total
Peak value
R.m .s. value
Peak value
R.m .s. value
Peak value
R.m .s. value
100
70
IOL*
50
P01 to P03, P64 to P67 total
20
P10 to P17, P20 to P27, P30 to P37
total
50
20
Operating
-40 to +85
°C
°C
Topt
tem perature
Storage
-65 to +150
Tstg
tem perature
*
R.m .s. value should be calculated as follows: [R.m .s.] = [Peak value] × √
duty
Caution
Product quality m ay suffer if the absolute m axim um rating is exceeded for even a single param eter or
even m om entarily. That is, the absolute m axim uam ratings are rated values at w hich the product is on
the verge of suffering physical dam age, and therefore the product m ust be used under conditions w hich
ensure that the absolute m axim um ratings are not exceeded.
Capacitance (Ta = 25 °C, VDD = VSS = 0 V)
Param eter
Sym bol
Test Conditions
MIN.
TYP.
MAX.
15
Unit
pF
Input capacitance
I/O capacitance
CIN
f = 1 MHz Unm easured pins returned to 0 V
P01 to P03, P10 to P17,
P20 to P27, P30 toP37,
P40 toP47, P50 to P57,
P64 to P67
15
20
pF
pF
f = 1 MHz Unm easured
pins returned to 0 V
CIO
P60 to P63
Rem arks The characteristics of a dual-function pin and a port pin are the sam e unless specified otherwise.
28
µPD78001BY, 78002BY
Main System Clock Oscillator Circuit Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recom m ended
Circuit
Resonator
Ceram ic
Param eter
Test Conditions
MIN.
1
TYP.
MAX.
10
Unit
MHz
Oscillator frequency
VDD = Oscillator
voltage range
resonator
X1
X2
V
SS
(fX)*1
R1
C2
After VDD reaches
oscillator voltage
range MIN.
Oscillation
C1
m s
4
stabilization tim e*2
Crystal
Oscillator frequency
resonator
1
10
MHz
8.38
(fX)*1
X1
X2
V
SS
VDD = 4.5 to 6.0 V
C1
C2
10
30
Oscillation
m s
stabilization tim e*2
External clock
X1 input frequency
10.0
500
MHz
ns
1.0
(fX)*1
X2
X1
X1 input high/low
level width
42.5
µPD74HCU04
(tXH , tXL)
*
1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution tim e.
2. Tim e required to stabilize oscillation after reset or STOP m ode release.
Note
1. When using the m ain system clock oscillator, w iring the area enclosed w ith the dotted line should be
carried out as follow s to avoid an adverse effect from w iring capacitance.
•
•
•
•
•
•
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the sam e as VSS.
Do not ground w iring to a ground pattern in w hich a high current flow s.
Do not fetch a signal from the oscillator.
2. When the m ain system clock is stopped and the system is operated by the subsystem clock, the
subsystem clock should be sw itched again to the m ain system clock after the oscillation stabilization
tim e is secured by the program .
29
µPD78001BY, 78002BY
Subsystem Clock Oscillator Circuit Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recom m ended
Circuit
Resonator
Crystal
Param eter
Test Conditions
MIN.
32
TYP.
MAX.
35
Unit
kHz
resonator
Oscillator frequency
32.768
(fXT)*1
XT1 XT2
VSS
R2
C4
VDD = 4.5 to 6.0 V
1.2
2
C3
Oscillation stabiliza-
s
tion tim e*2
10
External clock
XT1 input frequency
32
5
kHz
100
15
(fXT)*1
XT2
XT1
XT1 input high/low
level width
µs
(tXTH , tXTL)
*
1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution tim e.
2. Tim e required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Note
1. When using the subsystem clock oscillator, w iring in the area enclosed w ith the dotted line should be
carried out as follow s to avoid an adverse effect from w iring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the sam e as VSS.
• Do not ground w iring to a ground pattern in w hich a high current flow s.
• Do not fetch a signal from the oscillator.
2. The subsystem clock oscillation circuit is a circuit w ith a low am plification level,m ore prone to
m isoperation due to noise than the m ain system clock. Particular care is therefore required w ith the
w iring m ethod w hen the subsystem clock is used.
30
µPD78001BY, 78002BY
Recom m ended Oscillation Circuit Constant
Main system clock: Ceram ic resonator (Ta = –40 to +85 °C)
Oscillator Voltage
Range
Recom m ended Circuit Constant
Frequency
(MHz)
Manufacturer
Product Nam e
C1 (pF)
C2 (pF)
R1 (kΩ)
MIN. (V)
MAX. (V)
Murata Mfg.
Co., Ltd.
CSB1000J
1.00
100
100
100
100
6.8
4.7
0
2.9
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.9
2.9
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
CSB××××J
1.01 to 1.25
1.26 to 1.79
CSA×. ×××MK
CSA×. ××MG
CST×. ××MG
CSA×. ××MG
CST×. ××MGW
CSA×. ××MG
CST×. ××MGW
CSA×. ××MT
CST×. ××MTW
KBR-4.19MWS
KBR-4.19MKS
KBR-4.19MSA
PBRC4.19A
100
100
100
100
0
1.80 to 2.44
2.45 to 4.18
Built-in
30
Built-in
30
0
0
Built-in
30
Built-in
30
0
0
4.19 to 6.00
6.01 to 10.0
Built-in
30
Built-in
30
0
0
Built-in
Built-in
0
Kyocera
4.19
–
–
–
2.7
6.0
4.19
10.0
1.00
33
33
33
33
–
–
2.7
2.8
2.7
6.0
6.0
6.0
KBR-10.0M
KBR-1000F
100
100
2.2
KBR-1000Y
Rem arks ××××, ×. ×××, ×. ×× indicate frequency.
Subsystem clock: Cristal resonator (Ta = –40 to + 60 °C)
Oscillator Voltage
Range
Recom m ended Circuit Constant
Frequency
Manufacturer
Daishinku
Product Nam e
(MHz)
C1 (pF)
8
C2 (pF)
8
R1 (kΩ)
MIN. (V)
MAX. (V)
DT-38
(1TA632 E00, load
capacitance 6.3 pF)
32.768
100
2.7
6.0
31
µPD78001BY, 78002BY
DC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Param eter
Sym bol
Test Conditions
MIN.
TYP.
MAX.
Unit
V
Input voltage
high
P10 to P17, P21, P23, P30 to P32, P35 to P37,
P40 to P47, P50 to P57, P64 to P67
VIH1
0.7 VDD
VDD
VIH2
VIH3
VIH4
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0.8 VDD
0.7 VDD
VDD-0.5
VDD-0.5
VDD-0.3
VDD
15
V
V
V
V
V
P60 to P63
X1, X2
Open-drain
VDD
VDD
VDD
VDD = 4.5 to 6.0 V
VIH5
XT1/P04, XT2
Input voltage
low
P10 to P17, P21, P23, P30 to P32, P35 to P37,
P40 to P47, P50 to P57, P64 to P67
VIL1
VIL2
VIL3
0
0.3 VDD
V
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0
0.2 VDD
0.3 VDD
0.2 VDD
0.4
V
V
V
V
V
V
V
V
VDD = 4.5 to 6.0 V
P60 to P63
0
0
VIL4
X1, X2
0
VDD = 4.5 to 6.0 V
XT1/P04, XT2
0
0.4
VIL5
0
0.3
Output voltage
high
VDD = 4.5 to 6.0 V,IOH = –1 m A
VDD-1.0
VDD-0.5
VOH1
IOH = –100 µA
Output voltage
low
VDD = 4.5 to 6.0 V,
P50 to P57, P60 to P63
0.4
2.0
0.4
V
IOL = 15 m A
VOL1
P01 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P64 to P67
VDD = 4.5 to 6.0 V,
IOL = 1.6 m A
V
VDD = 4.5 to 6.0 V,
open-drain pulled-up
(R = 1 KΩ )
VOL2
VOL3
SB0, SB1, SCK0
0.2 VDD
0.5
V
V
IOL = 400 µA
Input leakage
current high
P01 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67 RESET
ILIH1
3
µA
VIN = VDD
ILIH2
X1, X2, XT1/P04, XT2
P60 to P63
20
80
µA
µA
ILIH3
VIN = 15 V
Input leakage
current high
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67 RESET
ILIL1
–3
µA
VIN = 0 V
ILIL2
ILIL3
X1, X2, XT1/P04, XT2
–20
µA
µA
*1
–200
P60
to
Other than
above
–3*2
µA
P63
32
µPD78001BY, 78002BY
DC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Param eter
Sym bol
Test Conditions
MIN.
TYP.
MAX.
3
Unit
Output leakage
current high
ILOH1
VOUT = VDD
VOUT = 0 V
µA
Output leakage
current low
–3
90
µA
kΩ
ILOL
Mask option
R1
VIN = 0 V, P60 to P63
VIN = 0 V, P01 to P03,
20
40
40
pull-up resistor
Software pull-
up resistor
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
15
20
90
kΩ
kΩ
P10 to P17, P20 to P27,
P30 to P37, P40 to P47,
P50 to P57, P60 to P67
R2
500
Power supply
8.38 MHz Crystal oscillation
operating m ode
VDD = 5.0 V ± 10 %*3
VDD = 3.0 V ± 10 %*4
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
7.5
0.8
1.4
550
60
35
25
5
22.5
2.4
4.2
1650
120
70
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
IDD1
IDD2
IDD3
IDD4
IDD5
current*5
8.38 MHz Crystal oscillation
HALT m ode
32.768 kHz Crystal oscillation
operating m ode
32.768 kHz Crystal oscillation
HALT m ode
50
10
XT1 = 0 V STOP m ode
1
20
When feedback resistor is used
0.5
0.1
10
XT1 = 0 V STOP m ode
When feedback resistor is
unused
20
IDD6
VDD = 3.0 V ± 10 %
0.05
10
µA
*
1. When m em ory expansion m ode is used by the m em ory expansion m ode register (MM) with no on-chip pull-
up resistor by m ask option.
2. When pull-up resistors are not used (specified by m ask option), the low-level input leakage current increases
with –200 µA (MAX.) under either of the following conditions.
1 When the external device expansion function is used and a low level is input to the pin.
2 During the 3-clock period when a read instruction is executed on port 6 (P6) and the port m ode registor
(PM6).
3. Operating in high-speed m ode (when set the processor clock control register to 00H).
4. Operating in low-speed m ode (when set the processor clock control register to 04H).
5. Port current are excluded.
Rem arks The characteristics of a dual-function pin and a port pin are the sam e unless specified otherwise.
33
µPD78001BY, 78002BY
AC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
(1) Basic Operation
Param eter
Cycle tim e
Sym bol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
0.4
0.96
40
TYP.
122
MAX.
64
Unit
µs
Operating on m ain
system clock
(Min. instruction
execution tim e)
TI input
TCY
64
µs
Operationg on subsystem clock
VDD = 4.5 to 6.0 V
125
4
µs
0
MHz
kHz
ns
fTI
frequency
0
275
TI input high/
low-level width
Interrupt input
high/low-level
width
tTIH
VDD = 4.5 to 6.0 V
100
1.8
8/fsam *
10
tTIL
µs
INTP0
µs
tINTH
tINTL
INTP1 to INTP3
KR0 to KR7
µs
10
µs
RESET low
tRSTL
10
µs
level width
*
In com bination with bits 0 (SCS0) and 1 (SCS1) of sam pling clock select register, selection of fsam is possible
between fX/2N+1, fX/64 and fX/128 (when N = 0 to 4).
µPD78P014Y (Reference)
µPD78001BY, 78002BY
TCY vs VDD (At m ain system clock operation)
TCY vs VDD (At m ain system clock operation)
60
10
60
10
µ
Operation Guaranteed
µ
Operation Guaranteed
Range
Range
2.0
1.0
2.0
1.0
0.5
0.4
0.5
0.4
0
0
1
2
3
4
5
6
1
2
3
4
5
6
Supply Voltage VDD [V]
Supply Voltage VDD [V]
Rem arks
indicates Ta = –40 to +40 °C
indicates Ta= – 40 to +80 °C
Note
The operation guaranteed range of the µPD78001BY and 78002BY differs from that of the µPD78P014Y.
34
µPD78001BY, 78002BY
(2) Read/ Write Operation (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Param eter
ASTB high-level width
Address setup tim e
Sym bol
tASTH
tADS
Test Conditions
MIN.
0.5 tCY
0.5 tCY–30
10
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold tim e
tADH
Load resistor ≥ 5 kΩ
Data input tim e from address
tADD1
tADD2
tRDD1
tRDD2
tRDH
(2+2n)tCY–50
(3+2n)tCY–100
(1+2n)tCY–25
5
Data input tim e from RD↓
(2.5+2n)tCY–100
Read data hold tim e
RD low-level width
0
tRDL1
(1.5+2n)tCY–20
(2.5+2n)tCY–20
tRDL2
WAIT↓ input tim e from RD↓
tRDWT1
tRDWT2
tWRWT
tWTL
0.5tCY
1.5tCY
WAIT↓ input tim e from WR↓
WAIT low-level width
0.5tCY
(0.5+2n)tCY +10
100
(2+2n)tCY
Write data setup tim e
tWDS
Write data hold tim e
tWDH
5
WR low-level width
tWRL1
tASTRD
tASTWR
(2.5+2n)tCY –20
0.5tCY–30
1.5tCY –30
RD↓ delay tim e from ASTB↓
WR↓ delay tim e from ASTB↓
ASTB↑ delay tim e from
RD↑ in external fetch
tRDAST
tCY–10
tCY
tCY+40
tCY+50
ns
ns
Address hold tim e from
tRDADH
tRDWD
tWDWR
RD↑ in external fetch
Write data output tim e from RD↑
WR↓ delay tim e from write data
10
0.5tCY–120
0.5tCY–170
tCY
ns
ns
ns
ns
ns
ns
ns
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
0.5tCY
0.5tCY
Address hold tim e from WR↑
tCY+60
tWRADH
tCY
tCY+100
2.5tCY+80
2.5tCY+80
RD↑ delay tim e from WAIT↑
WR↑ delay tim e from WAIT↑
tWTRD
tWTWR
0.5tCY
0.5tCY
Rem arks 1. tCY = TCY/4
2. n indicates num ber of waits.
3. CL = 100 pF (CL indicates load capacitance of P40/AD0 to P47/AD7, P50/A8 to P57/A15, P64/RD, P65/
WR, P66/WAIT,P67/ASTB pins).
35
µPD78001BY, 78002BY
(3) Serial Interface (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
(a) 3-w ire serial I/ O m ode (SCK... Internal clock output)
Param eter
Sym bol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
SCK cycle tim e
tKCY1
3200
ns
SCK high/low-level
width
tKH1
tKL1
tSIK1
VDD = 4.5 to 6.0 V
tKCY1/2-50
tKCY1/2-150
100
ns
ns
SI setup tim e (to SCK↑)
ns
SI setup tim e
tKSI1
400
ns
(from SCK↑)
SI hold tim e
VDD = 4.5 to 6.0 V
300
ns
ns
tKSO1
C = 100 pF*
(from SCK↑)
1000
*
C is the load capacitance of SO output line.
(b) 3-w ire serial I/ O m ode (SCK... External clock input)
Param eter
Sym bol
tKCY2
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
SCK cycle tim e
3200
400
ns
SCK high/low-level
width
tKH2
tKL2
tSIK2
VDD = 4.5 to 6.0 V
ns
1600
100
ns
SI setup tim e (to SCK↑)
ns
SI hold tim e
tKSI2
400
ns
(from SCK↑)
SO output delay tim e
VDD = 4.5 to 6.0 V
300
1000
160
ns
ns
ns
tKSO2
C = 100 pF*
from SCK↓
★
SCK rise, fall tim e
tR1
When external device expansion
functions are used
tF1
When external device expansion
functions are not used
1000
ns
*
C is the load capacitance of SO output line.
36
µPD78001BY, 78002BY
(c) SBI m ode (SCK... Internal clock output)
Param eter
Sym bol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
SCK cycle tim e
tKCY3
3200
ns
SCK high/low-level
width
tKH3
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
tKCY3/2-50
tKCY3/2-150
100
ns
tKL3
ns
SB0, SB1 setup tim e
ns
tSIK3
(to SCK↑)
300
ns
SB0, SB1 hold tim e
tKSI3
tKCY3/2
ns
(from SCK↑)
SB0, SB1 output delay
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
250
ns
ns
ns
ns
tKSO3
tim e from SCK↓
C = 100 pF*
0
1000
SB0, SB1↓ from SCK↑
SCK↓ from SB0, SB1↓
tKSB
tKCY3
tKCY3
tSBK
SB0, SB1 high-level
width
tSBH
tKCY3
tKCY3
ns
ns
SB0, SB1 low-level
width
tSBL
*
R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
(d) SBI m ode (SCK... External clock input)
Param eter
Sym bol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
SCK cycle tim e
tKCY4
3200
400
ns
SCK high/low-level
width
tKH4
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
ns
tKL4
1600
100
ns
SB0, SB1 setup tim e
ns
tSIK4
(to SCK↑)
300
ns
SB0, SB1 hold tim e
tKSI4
tKCY4/2
ns
(from SCK↑)
SB0, SB1 output delay
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
300
ns
ns
ns
ns
tKSO4
tim e from SCK↓
C = 100 pF*
0
1000
SB0, SB1↓ from SCK↑
SCK↓ from SB0, SB1↓
tKSB
tSBK
tKCY4
tKCY4
SB0, SB1 high-level
width
tSBH
tKCY4
tKCY4
ns
SB0, SB1 low-level
width
tSBL
tR2
ns
ns
SCK rise, fall tim e
When external device expansion
functions are used
160
★
tF2
When external device expansion
functions are not used
1000
ns
*
R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
37
µPD78001BY, 78002BY
(e) 2-w ire serial I/ O m ode (SCK... Internal clock output)
Param eter
Sym bol
tKCY5
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
1600
TYP.
MAX.
Unit
ns
SCK cycle tim e
3800
ns
SCK high-level width
SCK high-level width
tKH5
R = 1 kΩ, C = 100 pF*
tKCY5/2-50
tKCY5/2-50
ns
tKL5
ns
SB0, SB1 setup tim e
tSIK5
tKSI5
tKSO5
300
600
ns
ns
(to SCK↑)
SB0, SB1 hold tim e
(from SCK↑)
SB0, SB1 output delay
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
0
250
ns
ns
tim e from SCK↓
C = 100 pF*
1000
*
R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
(f) 2-w ire serial I/ O m ode (SCK... External clock input)
Param eter
Sym bol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
1600
3800
650
TYP.
MAX.
Unit
ns
SCK cycle tim e
tKCY6
ns
SCK high-level width
SCK high-level width
tKH6
ns
tKL6
800
ns
SB0, SB1 setup tim e
tSIK6
tKSI6
100
ns
ns
(to SCK↑)
SB0, SB1 hold tim e
tKCY6/2
(from SCK↑)
SB0, SB1 output delay
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
0
300
1000
160
ns
ns
ns
tKSO6
tim e from SCK↓
C = 100 pF*
★
SCK rise, fall tim e
tR3
When external device expansion
functions are used
tF3
When external device expansion
functions are not used
1000
ns
*
R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
38
µPD78001BY, 78002BY
(g) I2C bus interface
Param eter
Sym bol
Test Conditions
MIN.
0
TYP.
MAX.
100
Unit
kHz
SCL input clock
frequency
tSCL
Bus release tim e
tBUF
4.7
4.0
µs
µs
before transfer start
Start condition hold
tim e
tHDSTA
SCL low-level tim e
SCL high-level tim e
tLOW
tHIGH
4.7
4.0
µs
µs
Start condition setup
tim e
tSUSTA
tHDDAT
tSUDAT
4.7
µs
Data hold tim e
Data setup tim e
Data retention during SCL fall tim e
VDD = 4.5 to 6.0 V
0
µs
ns
ns
ns
ns
250
700
*1
*3
SDA0, SDA1, SCL
signal rise tim e
tR4
R = 2 kΩ, C = 100 pF
1000
160
★
*2
tR4
When external device expansion
functions are used
When external device expansion
functions are not used
1000
300
ns
SDA0, SDA1, SCL
signal fall tim e
tF4
R = 2 kΩ, C = 100 pF*3
ns
Stop condition setup
tim e
tSUSTO
4.7
µs
*1 When the serial clock is used as the internal clock output.
*2 When the serial clock is used as the external clock input.
*3 R and C are the load resistors and load capacitance of the SCL, SDA0 and SDA1 output line.
39
µPD78001BY, 78002BY
AC Tim ing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
Clock Tim ing
1/fX
tXL
tXH
VDD - 0.5 V
0.4V
X1 Input
1/fXT
tXTL
tXTH
VDD - 0.5 V
0.4V
XT1 Input
TI Tim ing
1/fTI
tTIL
tTIH
TI1, TI2
40
µPD78001BY, 78002BY
Read/ Write Operation
External fetch (No w ait):
A8-A15
Upper 8-Bit Address
Lower 8-Bit
Address
tADD1
Hi-z
Operation
Code
AD0-AD7
tRDADH
tADS
tRDD1
tADH
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
External fetch (Wait insertion):
A8-A15
Upper 8-Bit Address
Lower 8-Bit
Address
tADD1
Hi-z
Operation
Code
AD0-AD7
tRDD1
tRDADH
tRDAST
tADS
tADH
tASTH
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tWTRD
tWTL
tRDWT1
41
µPD78001BY, 78002BY
External data access (No w ait):
A8-A15
Upper 8-Bit Address
Lower
8-Bit
Address
tADD2
Hi-z
Hi-z
AD0-AD7
Read Data
Write Data
tADS
tRDD2
tADH
tRDH
tASTH
ASTB
RD
tRDWD
tWDS
tWDH
tASTRD
tRDL2
tWDWR
tWRADH
WR
tASTWR
tWRL1
External data access (Wait insertion):
A8-A15
Lower
Upper 8-Bit Address
8-Bit
tADD2
Address
Hi-z
Hi-z
AD0-AD7
Read Data
Write Data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
tASTRD
RD
tWDH
tRDL2
tWDS
tWDWR
tRDWD
WR
tASTWR
tWRL1
tWRADH
WAIT
tRDWT2
tWTRD
tWTL
tWRWT
tWTL
tWTWR
42
µPD78001BY, 78002BY
Serial Transfer Tim ing
3-w ire serial I/ O m ode:
tKCY 1,2
tKL1,2
tKH1,2
tR1
tF1
★
SCK
tSIK1,2
tKSI1,2
SI
Input Data
tKSO1,2
SO
Output Data
SBI m ode (Bus release signal transfer):
tKCY3,4
tKL3,4
tR2
tKH3,4
tF2
★
SCK
tKSB
tSBL
tSBK
tSIK3,4
tKSI3,4
tSBH
SB0, SB1
tKSO3,4
SBI m ode (Com m and signal transfer):
tKCY3,4
tKL3,4
tR2
tKH3,4
tF2
★
SCK
tSBK
tSIK3,4
tKSI3,4
tKSB
SB0, SB1
tKSO3,4
43
µPD78001BY, 78002BY
2-w ire serial I/ O m ode:
tKCY5,6
tKL5,6
tKH5,6
tR3
tF3
★
SCK
tSIK5,6
tKSI5,6
tKSO5,6
SB0, SB1
I2C bus m ode:
SCL
t
HIGH
t
SUDAT
t
SUSTA
t
LOW
t
HDDAT
t
R4
t
HDSTA
t
F4
SDA0, SDA1
t
BUF
t
HDSTA
t
SUSTO
44
µPD78001BY, 78002BY
Data Mem ory STOP Mode Low Supply Voltage Data Retention Characteristics (Ta = –40 to +85 °C)
Param eter
Sym bol
Test Conditions
MIN.
2.0
TYP.
MAX.
6.0
Unit
V
Data retention supply
voltage
VDDDR
Data retention
supply current
VDDDR = 2.0 V
IDDDR
Subsystem clock stop and feed-back
resister disconnected
0.1
10
µs
Release signal set time
Oscillation stabilization
wait tim e
tSREL
0
µs
m s
m s
Release by RESET
Release by interrupt
218/fX
tWAIT
*
*
In com bination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization tim e select register, selection of 213
fX and 215/fX to 218/fX is possible.
/
Data Retention Tim ing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retension Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Tim ing (Standby Release Signal: STOP Mode Release By Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retension Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
45
µPD78001BY, 78002BY
Interrupt Input Tim ing
tINTL
tINTH
INTP0-INTP2
tINTL
INTP3
RESET Input Tim ing
tRSL
RESET
46
µPD78001BY, 78002BY
12. CHARACTERISTIC CURVE (REFERENCE VALUES)
IDD vs VDD (Main System Clock : 8.38 MHz)
(Ta=25°C)
10.0
5.0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
PCC=30H
HALT (X1 Oscillation,
XT1 Oscillation)
1.0
0.5
0.1
PCC=B0H
0.05
HALT (X1 Stop,
XT1 Oscillation)
STOP (X1 Oscillation,
XT1 Oscillation)
0.01
fX=8.38MHz
fXT=32.768kHz
0.005
0.001
0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
47
µPD78001BY, 78002BY
IDD vs VDD (Main System Clock : 4.19 MHz)
(Ta=25˚C)
10.0
5.0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
PCC=30H
(X1 Oscillation,
HALT
1.0
0.5
XT1 Oscillation)
0.1
PCC=B0H
0.05
HALT
STOP
(X1 Stop,
XT1 Oscillation)
(X1 Stop,
XT1 Oscillation)
0.01
fX=4.19MHz
fXT=32.768kHz
0.005
0.001
0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
48
µPD78001BY, 78002BY
IDD vs fX
(VDD=3V, Ta=25°C)
5
4
3
2
1
0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
HALT
(X1Oscillation)
0
1
2
3
4
5
6
7
8
9
10
11
12
Clock Oscillator Frequency fx [MHz]
IDD vs fX
(VDD=5V, Ta=25°C)
12
11
10
9
PCC=00H
PCC=01H
8
7
6
5
4
PCC=02H
PCC=03H
3
2
1
0
PCC=04H
HALT
(X1Oscillation)
0
1
2
3
4
5
6
7
8
9
10
11
12
Clock Oscillator Frequency fx [MHz]
49
µPD78001BY, 78002BY
VOL vs IOL (Port 0, 2 to 5, P64 to P67)
(Ta=25˚C)
VDD=5V
VDD=6V VDD=4V VDD=3 V
30
20
10
0
0
0.5
1.0
Output Voltage Low VOL [V]
VOL vs IOL (Port 1)
(Ta=25˚C)
VDD=3V
VDD=6V VDD=5V
VDD=4V
30
20
10
0
0
0.5
1.0
Output Voltage Low VOL [V]
50
µPD78001BY, 78002BY
VOL vs IOL (P60 to P63)
(Ta=25˚C)
VDD=6V VDD=5V
VDD=4V
30
20
10
VDD=3 V
0
1.0
0.5
0
Output Voltage Low VOL [V]
VOH vs IOH (Port 0 to 5, P64 to P67)
(Ta=25˚C)
VDD=5V VDD=4V
-10
VDD=6V
VDD=3 V
-5
0
0
0.5
1.0
Output Voltage High VDD – VOH [V]
51
µPD78001BY, 78002BY
13. PACKAGE INFORMATION
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (1/ 2)
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
L
F
D
M
R
B
C
M
N
NOTE
ITEM MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
58.68 MAX.
1.78 MAX.
1.778 (T.P.)
2.311 MAX.
0.070 MAX.
0.070 (T.P.)
2) Item "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
I
0.9 MIN.
3.2±0.3
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.750 (T.P.)
0.669
0.51 MIN.
4.31 MAX.
5.08 MAX.
19.05 (T.P.)
17.0
J
K
L
+0.004
0.010
+0.10
0.25
M
–0.003
–0.05
N
R
0.17
0.007
0~15°
0~15°
P64C-70-750A,C-1
Caution
Dim ensions and m aterials of ES products are different from those of m ass-production products. Refer
to DRAWINGS OF ES PRODUCT PACKAGES (1/ 2).
52
µPD78001BY, 78002BY
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES
64 PIN PLAS TIC QFP ( 14)
A
B
48
49
33
32
detail of lead end
64
1
17
16
G
H
M
I
J
K
N
L
P64GC-80-AB8-3
NOTE
ITEM
A
B
MILLIMETERS
INCHES
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
±
±
17.6 0.4
0.693 0.016
+0.009
–0.008
±
14.0 0.2
0.551
+0.009
–0.008
±
C
14.0 0.2
0.551
±
±
D
F
0.693 0.016
17.6 0.4
1.0
1.0
0.039
G
H
I
0.039
+0.004
–0.005
±
0.35 0.10
0.014
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
±
±
K
L
1.8 0.2
0.071 0.008
+0.009
–0.008
±
0.031
0.8 0.2
+0.10
–0.05
+0.004
–0.003
0.15
M
N
P
0.006
0.10
2.55
0.004
0.100
±
Q
S
0.1 0.1
±
0.004 0.004
2.85 MAX.
0.112 MAX.
Caution
Dim ensions and m aterials are different from those of m ass-production products. Refer to DRAWINGS
OF ES PRODUCT PACKAGES (2/ 2).
53
µPD78001BY, 78002BY
DRAWINGS OF ES PRODUCT PACKAGES (1/ 2)
64PIN CERAMIC SHRINK DIP (SEAM WELD) (750 m il)
64
33
1
32
K
L
A
F
D
B
M
N
M
0~15°
C
P64D-70-750A1
NOTES
ITEM
A
B
MILLIMETERS
58.16 MAX.
1.521 MAX.
1.778 (T.P.)
INCHES
1) Each lead centerline is located within 0.25
mm (0.01 inch) of its true position (T.P.) at
maximum material condition.
2.290 MAX.
0.060 MAX.
0.070 (T.P.)
C
2) Item "K" to center of leads when formed
parallel.
±
±
D
F
0.46 0.05
0.018 0.002
0.8 MIN.
0.031 MIN.
±
±
G
H
I
3.5 0.3
0.138 0.012
1.02 MIN.
3.14
0.040 MIN.
0.124
J
5.08 MAX.
19.05 (T.P.)
18.8
0.200 MAX.
0.750 (T.P.)
K
L
0.740
+0.002
–0.003
±
M
N
0.25 0.05
0.010
0.25
0.01
54
µPD78001BY, 78002BY
DRAWINGS OF ES PRODUCT PACKAGES (2/ 2)
64 PIN CERAMIC QFP (14 × 14) (FOR ES)
A
B
48
49
33
32
64
G
17
16
1
H
J
K
X64B-80A-1
(Bottom View)
ITEM
A
MILLIMETERS
INCHES
±
±
22.0 0.4
0.866 0.016
B
14.0
14.0
0.551
0.551
C
±
±
D
22.0 0.4
0.866 0.016
F
1.0
0.039
0.039
0.013
G
1.0
H
0.32
U
V
J
0.8 (T.P.)
0.031 (T.P.)
+0.007
±
K
4.0 0.15
0.157
–0.006
M
Q
0.25
0.01
3.0 MAX.
0.55
0.119 MAX.
0.022
T
U
1.0
0.039
V
1.2
0.047
55
µPD78001BY, 78002BY
14. RECOMMENDED SOLDERING CONDITIONS
The µPD78001BY/78002BY should be soldered and m ounted under the conditions recom m ended in the table
below.
For detail of recom m ended soldering conditions, refer to the inform ation docum ent “Sem iconductor Device
Mounting Technology Manual” (IE-1207).
For soldering m ethods and conditions other than those recom m ended below, contact our sales personnel.
Table 14-1 Surface Mounting Type Soldering Conditions
µPD78001BYGC-×××-AB8 : 64-Pin Plastic QFP (■14 m m )
µPD78002BYGC-×××-AB8 : 64-Pin Plastic QFP (■14 m m )
Recom m ended
Condition Sym bol
Soldering Method
Infrared reflow
Soldering Conditions
Package peak tem perature: 235°C, Duration: 30 sec. m ax. (at 210°C or above),
Num ber of tim es: Twice m ax.
IR35-00-2
< Points to note >
(1) Start the second reflow after the device tem prature by the first reflow returns
to norm al.
(2) Flux washing by the water after the first reflow should be avoided.
Package peak tem perature: 215°C, Duration: 40 sec. m ax. (at 200°C or above)
Num ber of tim es: Twice m ax.
VPS1
VP15-00-2
< Points to note >
(1) Start the second reflow after the device tem prature by the first reflow returns
to norm al.
(2) Flux washing by the water after the first reflow should be avoided.
Pin tem perature: 300°C m ax., Duration: 3 sec. m ax. (per device side)
Pin part heating
—
Caution
Use m ore than one soldering m ethod should be avoided (except in the case of pin part heating).
Table 14-2 Insertion Type Soldering Conditions
µPD78001BYCW-××× : 64-Pin Plastic Shrink DIP (750 m il)
µPD78001BYCW-××× : 64-Pin Plastic Shrink DIP (750 m il)
Soldering Conditions
Soldering Method
Solder bath tem perature: 260°C m ax., Duration: 10 sec. m ax.
Wave soldering
(lead part only)
Pin tem perature: 300°C m ax., Duration: 3 sec. m ax. (per pin)
Pin heating
★
Caution
Wave soldering is only for the pins in order that jet solder can not contact w ith the chip directly.
56
µPD78001BY, 78002BY
APPENDIX A. DEVEROPMENT TOOLS
The following developm ent tools are available for system developm ent using the µPD78001BY and 78002BY.
Language Processing Softw are
RA78K/0*1, 2, 3
CC78K/0*1, 2, 3
DF78002*1, 2, 3
CC78K/0-L*1, 2, 3
78K/0 series com m on assem bler package
78K/0 series com m on C com piler package
µPD78002 sub-series com m on device file
78K/0 series com m on C com piler library source file
★
PROM Program m ing Tools
PG-1500
PROM program m er
PA-78P014CW
PA-78P014GC
Program m er adapter connected to PG-1500
PG-1500 controller*1, 2
PG-1500 control program
Debugging Tool
IE-78000-R
78K/0 series com m on in-circuit em ulator
IE-78000-R-BK
IE-78014-R-EM
78K/0 series com m on break board
Evaluation em ulation board com m on to µPD78002/78014 subseries
Em ulation probe com m on to µPD78244 subseries
EP-78240CW-R
EP-78240GC-R
EV-9200GC-64
SD78K/0*1, 2
Socket to be m ounted on user system board created for the 64-pin plastic QFP
IE-78000-R screen debugger
SM78K/0*3, 4, 5, 6
DF78002*1, 2, 3, 4, 5
78K/0 series com m on system sim ulator
★
Device file com m on to µPD78002 subseries
Fuzzy Inference Devleopm ent Support System
FE9000*1/FE9200*5
FT9080*1/FT9085*2
FI78K0*1, 2
Fuzzy knowledge data creation tool
Translator
Fuzzy inference m odule
Fuzzy inference debugger
FD78K0*1, 2
*
1. PC-9800 series (MS-DOSTM) based.
2. IBM PC/ATTM (PC DOS TM) based.
3. HP9000 series 300TM, HP9000 series 700TM (HP-UXTM) based, SPARCstationTM, (Sun OSTM) based, EWS-4800
seriesTM (EWS-UX/VTM) based.
★
4. PC-9800 series (MS-DOS + WindowsTM base)
5. IBM PC/AT (PC DOS + Windows) based.
6. Under developm ent
Rem arks 1. For developm ent tools m anufactured by a third party, see the "78K/ 0 Series Selection Guide" (IF-
1185).
★
2. RA78K/0, CC78K/0, SD78K/0, and SM78K/0 are used in com bination with DF78002.
57
µPD78001BY, 78002BY
★
APPENDIX B. RELATED DOCUMENTS
Device Related Docum ents
Docum ent Nam e
User's Manual
Docum ent No. (J apanese) Docum ent No. (English)
IEU-788
IEU-849
IEA-715
IEA-740
IEU-1334
IEM-1372
IEA-1288
IEA-1299
78K/0 Series User's Manual - Instruction
Application Note
Basic I
Basic II
Developm ent Tools Docum ents (User's Manual)
Docum ent Nam e
Docum ent No. (J apanese) Docum ent No. (English)
RA78K Series Assem bler Package
Operation
Language
EEU-809
EEU-815
EEU-817
EEU-656
EEU-655
EEU-651
EEU-704
EEU-810
EEU-867
EEU-805
EEU-852
EEU-816
EEU-1399
EEU-1404
EEU-1402
EEU-1280
EEU-1284
EEU-1335
EEU-1291
EEU-1398
EEU-1427
EEU-1400
EEU-1414
EEU-1413
RA78K Series Structured Assem bler Preprocessor
CC78K Series C Com piler
Operation
Language
PG-1500 PROM Program m er
PG-1500 Controller
IE-78000-R
IE-78000-R-BK
IE-78014-R-EM
SD78K/0 Screen Debugger
Basic
Reference
Em bedded Softw are Docum ents (User's Manual)
Docum ent Nam e
Docum ent No. (J apanese) Docum ent No. (English)
Fuzzy Knowledge Data Creation Tool
EEU-829
EEU-862
EEU-1438
EEU-1444
78K/0, 78K/II, 87AD Series
Fuzzy Inference Developm ent Support System - Translator
Caution
These docum ents above are subject to change w ithout notice. Be sure to use the latest docum ent for
designing your system .
Other Docum ents
Docum ent Nam e
Docum ent No. (J apanese) Docum ent No. (English)
Package Manual
IEI-635
IEI-616
IEI-620
MEI-603
IEI-1213
IEI-1207
IEI-1209
MEI-1202
Sem iconductor Device Mounting Technology Manual
Quality Grade on NEC Sem iconductor Devices
Sem iconductor Device Quality Guarantee Guide
Caution
These docum ents above are subject to change w ithout notice. Be sure to use the latest docum ent for
designing your system .
58
µPD78001BY, 78002BY
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, w hen exposed to a MOS device, can cause destruction of
the gate oxide and ultim ately degrade the device operation. Steps m ust be
taken to stop generation of static electricity as m uch as possible, and quickly
dissipate it once, w hen it has occurred. Environm ental control m ust be
adequate. When it is dry, hum idifier should be used. It is recom m ended to
avoid using insulators that easily build static electricity. Sem iconductor
devices m ust be stored and transported in an anti-static container, static
shielding bag or conductive m aterial. All test and m easurem ent tools including
w ork bench and floor should be grounded. The operator should be grounded
using w rist strap. Sem iconductor devices m ust not be touched w ith bare
hands. Sim ilar precautions need to be taken for PW boards w ith sem iconductor
devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of m alfunction. If no
connection is provided to the input pins, it is possible that an internal input
level m ay be generated due to noise, etc., hence causing m alfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices m ust be fixed high or low by using a pull-up or pull-dow n circuitry. Each
unused pin should be connected to VDD or GND w ith a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins m ust be judged device by device and related specifications governing the
devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Pow er-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Im m ediately after the pow er source is turned ON, the devices w ith reset
function have not yet been initialized. Hence, pow er-on does not guarantee
out-pin levels, I/ O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation m ust be executed im m edi-
ately after pow er-on for devices having reset function.
59
µPD78001BY, 78002BY
Purchase of NEC I2C com ponents conveys a license under the Philips I2C Patent Rights to use these com ponents
in an I2C system , provided that the system conform s to the I2C Standard Specification as defined by Philips.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92.6
FIP is a registered tradem ark of NEC Corporation.
EWS-4800 Series, EWS-UX/V, and IEBus are tradem arks of NEC Corporation.
MS-DOS and Windows are tradem arks of Microsoft Corporation.
PC/AT and PC DOS are tradem arks of IBM Corporation.
HP9000 Series 300, HP9000 Series 700, and HP-UX are tradem arks of Hewlett-Packard Com pany.
SPARCstation is a tradem ark of SPARC International Inc.
SunOS is a tradem ark of Sun Microsystem s, Inc.
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