UPD78053GK-XXX-BE9 [NEC]
Microcontroller, 8-Bit, MROM, MOS, PQFP80, 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80;
| 型号： | UPD78053GK-XXX-BE9 |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 8-Bit, MROM, MOS, PQFP80, 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80 时钟 微控制器 外围集成电路 |
| 文件： | 总78页 (文件大小：580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78052,78053,78054,78055,78056,78058
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD78052, 78053, 78054, 78055, 78056 and 78058 are µPD78054 Subseries products of the 78K/0 Series.
A variety of peripheral functions such as an 8-bit resolution A/D converter, 8-bit resolution D/A converter, timer,
serial interface, real-time output port and interrupt functions are included on chip.
The µPD78P054 and 78P058, one-time PROM or EPROM products that can be operated in the same supply voltage
range as the mask ROM versions, and various development tools are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD78054, 78054Y Subseries User’s Manual: U11747E
78K/0 Series User’s Manual Instructions:
U12326E
FEATURES
• High-capacity on-chip ROM & RAM
Item
Data Memory
Internal
Program
Internal High-
Internal
Package
Memory (ROM)
Part Number
µPD78052
µPD78053
µPD78054
µPD78055
µPD78056
µPD78058
Speed RAM
512 bytes
Buffer RAM Expansion RAM
16 KB
24 KB
32 KB
40 KB
48 KB
60 KB
32 bytes
None
• 80-pin plastic QFP (14 × 14 mm)
• 80-pin plastic TQFP (fine pitch)
(12 × 12 mm)
1024 bytes
1024 bytes
• External memory expansion space: 64 KB
• Minimum instruction execution time can be changed from high-speed (0.4 µs) to ultra-low-speed (122 µs)
• I/O ports: 69 (N-ch open drain: 4)
• 8-bit resolution A/D converter: 8 channels
• 8-bit resolution D/A converter: 2 channels
• Serial interface: 3 channels
• Timer: 5 channels
• Supply voltage: VDD = 2.0 to 6.0 V
APPLICATIONS
Cellular phones, pagers, printers, AV equipment, air-conditioners, cameras, PPCs, fuzzy-logic home appliances,
vending machines, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12327EJ5V0DS00 (5th edition)
Date Published February 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1994, 2000
µPD78052, 78053, 78054, 78055, 78056, 78058
ORDERING INFORMATION
Part Number
Package
µPD78052GC-×××-8BT
µPD78052GK-×××-BE9
µPD78053GC-×××-8BT
µPD78053GK-×××-BE9
µPD78054GC-×××-8BT
µPD78054GK-×××-BE9
µPD78055GC-×××-8BT
µPD78055GK-×××-BE9
µPD78056GC-×××-8BT
µPD78056GK-×××-BE9
µPD78058GC-×××-8BT
µPD78058GK-×××-BE9
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Remark ××× indicates ROM code suffix.
2
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
µ
EMI-noise reduced version of the PD78078
PD78075B
PD78078
µ
µ
100-pin
100-pin
100-pin
100-pin
80-pin
µPD78054 with timer added and enhanced external interface
µPD78078Y
PD78070AY
µPD78070A
µ
µ
ROM-less version of the PD78078
µPD78078Y with enhanced serial I/O and limited functions
µPD78054 with enhanced serial I/O
PD780018AY
µ
PD780058
PD780058Y
PD78058FY
µ
µ
µ
EMI-noise reduced version of theµPD78054
µPD78058F
80-pin
PD78054
µ
µ
PD78018F with added UART and D/A converter and enhanced I/O
PD780024A with increased RAM capacity
80-pin
PD78054Y
µ
PD780065
µ
80-pin
µ
PD780078Y
PD780034AY
PD780024AY
A timer added to the PD780034A and serial I/O enhanced
µ
µ
µ
PD780078
64-pin
µ
µ
µ
µ
µ
µ
PD780034A
µ
µ
64-pin
64-pin
PD780024A with enhanced A/D converter
PD78018F with enhanced serial I/O
PD780024A
PD78014H
PD78018F
PD78083
µ
EMI-noise reduced version of the µPD78018F
64-pin
Basic subseries for control
PD78018FY
64-pin
µ
On-chip UART, capable of operating at low voltage (1.8 V)
42/44-pin
Inverter control
PD780988
64-pin
On-chip inverter controller and UART. EMI-noise reduced.
µ
FIPTM drive
µ
µ
PD78044F with enhanced I/O and FIP C/D. Display output total: 53
100-pin
100-pin
80-pin
80-pin
80-pin
PD780208
PD780228
PD780232
PD78044H
PD78044F
µ
µ
µ
µ
µ
78K/0
Series
PD78044H with enhanced I/O and FIP C/D. Display output total: 48
For panel control. On-chip FIP C/D. Display output total: 53
PD78044F with added N-ch open drain I/O. Display output total: 34
µ
Basic subseries for driving FIP. Display output total: 34
LCD drive
100-pin
100-pin
100-pin
PD780308
µ
PD780308Y
PD78064Y
µ
PD78064 with enhanced SIO, and increased ROM, RAM capacity.
µ
µ
EMI-noise reduced version of the PD78064
PD78064B
PD78064
µ
µ
µ
Basic subseries for driving LCDs, on-chip UART
Call ID supported
µPD780841
80-pin
On-chip Call ID function, simple DTMF. EMI-noise reduced.
On-chip D-CAN controller
Bus interface supported
100-pin
80-pin
µPD780948
µPD78098B
µ
PD78054 with IEBusTM controller added. EMI-noise reduced.
80-pin
80-pin
PD780701Y
µ
µ
On-chip D-CAN/IEBus controller
PD780833Y
On-chip controller compliant with J1850 (Class 2)
Meter control
100-pin
For industrial meter control
PD780958
µ
µ
µ
Ultra-low power consumption. On-chip UART.
On-chip automobile meter controller/driver
80-pin
80-pin
PD780955
PD780973
Data Sheet U12327EJ5V0DS00
3
µPD78052, 78053, 78054, 78055, 78056, 78058
The major functional differences among the subseries are listed below.
Function
Subseries Name
Timer
ROM
Capacity
8-Bit 10-Bit 8-Bit
A/D A/D D/A
VDD MIN. External
Value Expansion
Serial Interface
I/O
8-bit 16-bit Watch WDT
Control µPD78075B 32K to 40K 4 ch 1 ch 1 ch 1 ch 8 ch
–
2 ch 3 ch (UART: 1 ch)
88 1.8 V
61 2.7 V
√
µPD78078
48K to 60K
—
µPD78070A
µPD780058 24K to 60K 2 ch
µPD78058F 48K to 60K
3 ch (time division UART: 1 ch) 68 1.8 V
3 ch (UART: 1 ch)
69 2.7 V
2.0 V
µPD78054
16K to 60K
µPD780065 40K to 48K
µPD780078 48K to 60K
µPD780034A 8K to 32K
—
4 ch (UART: 1 ch)
3 ch (UART: 2 ch)
3 ch (UART: 1 ch)
60 2.7 V
52 1.8 V
51
2 ch
1 ch
—
8 ch
—
µ
PD780024A
8 ch
µPD78014H
2 ch
53
µPD78018F 8K to 60K
µPD78083
8K to 16K
—
—
—
1 ch (UART: 1 ch)
3 ch (UART: 2 ch)
33
—
Inverter µPD780988 16K to 60K 3 ch Note
1 ch
—
8 ch
—
—
—
47 4.0 V
√
control
FIP
µPD780208 32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch
2 ch
1 ch
2 ch
1 ch
2 ch
74 2.7 V
72 4.5 V
40
—
drive
µPD780228 48K to 60K 3 ch
µPD780232 16K to 24K
—
—
4 ch
8 ch
µPD78044H 32K to 48K 2 ch 1 ch 1 ch
µPD78044F 16K to 40K
68 2.7 V
LCD
drive
µPD780308 48K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch
µPD78064B 32K
—
—
—
3 ch (time division UART: 1 ch) 57 2.0 V
2 ch (UART: 1 ch)
—
—
µPD78064
16K to 32K
Call ID µPD780841 24K to 32K 2 ch
—
1 ch 1 ch 2 ch
—
—
2 ch (UART: 1 ch)
3 ch (UART: 1 ch)
61 2.7 V
supported
Bus
interface
µPD780948 60K
2 ch 2 ch 1 ch 1 ch 8 ch
1 ch
—
2 ch
—
79 4.0 V
69 2.7 V
69 2.2 V
50 2.2 V
56 4.5 V
√
µPD78098B 40K to 60K
—
—
supported
Meter
µPD780958 48K to 60K 4 ch 2 ch
µPD780955 40K 6 ch 1 ch
µPD780973 24K to 32K 3 ch
—
1 ch
—
—
2 ch (UART: 1 ch)
2 ch (UART: 2 ch)
2 ch (UART: 1 ch)
control
1 ch
5 ch
1 ch
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
4
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
OVERVIEW OF FUNCTIONS
Part Number
µPD78052
µPD78053
µPD78054
µPD78055
µPD78056
µPD78058
Item
Internal
Memory
ROM
16 KB
24 KB
32 KB
40 KB
48 KB
60 KB
High-speed RAM
Buffer RAM
Expansion RAM
512 bytes
32 bytes
None
1024 bytes
1024 bytes
Memory space
64 KB
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
On-chip minimum instruction execution time variable function
Minimum instruction execution time
When main system clock is selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0 MHz operation)
When subsystem clock is selected
Instruction set
122 µs (@ 32.768 kHz operation)
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD correction, etc.
I/O ports
Total:
69
02
63
4
• CMOS input :
• CMOS I/O :
• N-ch open-drain I/O:
A/D converter
D/A converter
Serial interface
• 8-bit resolution × 8 channels
• 8-bit resolution × 2 channels
• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable: 1 channel
•
3-wire serial I/O mode (automatic data transmit/receive function for up to 32 bytes
provided on chip): 1 channel
• 3-wire serial I/O/UART mode selectable: 1 channel
Timer
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer:
1 channel
1 channel
• Watchdog timer:
Timer outputs
Clock output
3 (14-bit PWM output × 1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz
(@ 5.0 MHz operation with main system clock)
32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0 MHz operation with main system clock)
Vectored
interrupt
sources
Maskable
Internal: 13, external: 7
Internal: 1
Non-maskable
Software
1
Test inputs
Internal: 1, external: 1
VDD = 2.0 to 6.0 V
TA = –40 to +85°C
Supply voltage
Operating ambient temperature
Package
• 80-pin plastic QFP (14 × 14 mm)
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Data Sheet U12327EJ5V0DS00
5
µPD78052, 78053, 78054, 78055, 78056, 78058
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................
2. BLOCK DIAGRAM ...........................................................................................................................
7
9
3. PIN FUNCTIONS ............................................................................................................................... 10
3.1 Port Pins .................................................................................................................................................... 10
3.2 Non-Port Pins ............................................................................................................................................ 12
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................................ 14
4. MEMORY SPACE .............................................................................................................................. 18
5. PERIPHERAL HARDWARE FUNCTION FEATURES ...................................................................... 19
5.1 Ports ........................................................................................................................................................... 19
5.2 Clock Generator ........................................................................................................................................ 20
5.3 Timer/Event Counter ................................................................................................................................. 20
5.4 Clock Output Controller ........................................................................................................................... 23
5.5 Buzzer Output Controller ......................................................................................................................... 23
5.6 A/D Converter ............................................................................................................................................ 24
5.7 D/A Converter ........................................................................................................................................... 25
5.8 Serial Interface .......................................................................................................................................... 25
5.9 Real-Time Output Port .............................................................................................................................. 27
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS........................................................................ 28
6.1 Interrupt Functions ................................................................................................................................... 28
6.2 Test Functions ........................................................................................................................................... 32
7. EXTERNAL DEVICE EXPANSION FUNCTION................................................................................ 33
8. STANDBY FUNCTION ...................................................................................................................... 33
9. RESET FUNCTION ........................................................................................................................... 33
10. INSTRUCTION SET .......................................................................................................................... 34
11. ELECTRICAL SPECIFICATIONS ..................................................................................................... 36
12. CHARACTERISTICS CURVES (REFERENCE VALUES)................................................................ 64
13. PACKAGE DRAWINGS .................................................................................................................... 66
14. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 68
APPENDIX A. DEVELOPMENT TOOLS................................................................................................. 70
APPENDIX B. RELATED DOCUMENTS ................................................................................................ 73
6
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
1. PIN CONFIGURATION (TOP VIEW)
• 80-pin plastic QFP (14 × 14 mm)
µPD78052GC-×××-8BT, 78053GC-×××-8BT, 78054GC-×××-8BT, 78055GC-×××-8BT,
µPD78056GC-×××-8BT, 78058GC-×××-8BT
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD78052GK-×××-BE9, 78053GK-×××-BE9, 78054GK-×××-BE9, 78055GK-×××-BE9,
µPD78056GK-×××-BE9, 78058GK-×××-BE9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RESET
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P15/ANI5
P16/ANI6
P17/ANI7
1
2
3
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
4
5
6
AVSS
P130/ANO0
P131/ANO1
AVREF1
P123/RTP3
P122/RTP2
7
8
P121/RTP1
P120/RTP0
P37
P70/SI2/R
XD
9
P71/SO2/T
XD
10
P72/SCK2/ASCK
P20/SI1
P36/BUZ
P35/PCL
P34/TI2
11
12
13
P21/SO1
P22/SCK1
P33/TI1
14
15
P23/STB
P32/TO2
P31/TO1
P30/TO0
P24/BUSY
16
17
P25/SI0/SB0
P26/SO0/SB1
P67/ASTB
P66/WAIT
P65/WR
18
P27/SCK0
P40/AD0
19
20
21
P41/AD1
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
22
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
Data Sheet U12327EJ5V0DS00
7
µPD78052, 78053, 78054, 78055, 78056, 78058
A8 to A15:
AD0 to AD7:
ANI0 to ANI7:
ANO0, ANO1:
ASCK:
Address Bus
P130, P131:
PCL:
Port13
Address/Data Bus
Analog Input
Programmable Clock
Read Strobe
Reset
RD:
Analog Output
RESET:
Asynchronous Serial Clock
Address Strobe
RTP0 to RTP7: Real-Time Output Port
ASTB:
RXD:
Receive Data
Serial Bus
AVDD:
Analog Power Supply
SB0, SB1:
AVREF0, AVREF1: Analog Reference Voltage
SCK0 to SCK2: Serial Clock
AVSS:
BUSY:
BUZ:
IC:
Analog Ground
Busy
SI0 to SI2:
SO0 to SO2:
STB:
Serial Input
Serial Output
Strobe
Buzzer Clock
Internally Connected
TI00, TI01:
TI1, TI2:
TO0 to TO2:
TXD:
Timer Input
INTP0 to INTP6: External Interrupt Input
Timer Input
P00 to P07:
P10 to P17:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P67:
P70 to P72:
P120 to P127:
Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port12
Timer Output
Transmit Data
Power Supply
Ground
VDD:
VSS:
WAIT:
Wait
WR:
Write Strobe
Crystal (Main System Clock)
Crystal (Subsystem Clock)
X1, X2:
XT1, XT2:
8
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
2. BLOCK DIAGRAM
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
P00
16-bit timer/
event counter
Port 0
P01 to P06
P07
TO1/P31
TI1/P33
8-bit timer/
event counter 1
P10 to P17
P25 to P27
Port 1
Port 2
TO2/P32
TI2/P34
8-bit timer/
event counter 2
Port 3
Port 4
Port 5
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
Watchdog timer
Watch timer
78K/0
CPU
core
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
ROM
Serial
interface 0
Port 6
Port 7
SI1/P20
SO1/P21
SCK1/P22
STB/P23
Serial
interface 1
BUSY/P24
RAM
Port 12
Port 13
P120 to P127
P130, P131
SI2/RxD/P70
SO2/TxD/P71
Serial
interface 2
SCK2/ASCK/P72
ANI0/P10 to
ANI7/P17
Real-time
output port
RTP0/P120 to
RTP7/P127
AVDD
AVSS
AVREF0
A/D converter
D/A converter
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
ANO0/P130,
ANO1/P131
External
access
AVSS
RD/P64
WR/P65
AVREF1
WAIT/P66
ASTB/P67
INTP0/P00 to
INTP6/P06
Interrupt
control
RESET
X1
BUZ/P36
PCL/P35
Buzzer output
System
control
X2
XT1/P07
XT2
Clock output
control
V
DD
V
SS
IC
Remark The internal ROM and RAM capacity varies depending on the product.
Data Sheet U12327EJ5V0DS00
9
µPD78052, 78053, 78054, 78055, 78056, 78058
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
After
Alternate
Function
Pin Name
P00
I/O
Input
Function
Reset
Port 0
Input only
Input
Input
INTP0/TI00
INTP1/TI01
INTP2
8-bit I/O port
P01
P02
P03
P04
P05
P06
P07
I/O
Input/output can be specified in 1-bit units.
When used as an input port, a pull-up resistor can be
specified by means of software.
INTP3
INTP4
INTP5
INTP6
Note 1
Input
I/O
Input only
Input
Input
XT1
P10 to P17
Port 1
ANI0 to ANI7
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, a pull-up resistor can be specified by means
Note 2
of software
.
P20
I/O
I/O
I/O
Port 2
Input
Input
Input
SI1
8-bit I/O port.
P21
SO1
Input/output can be specified in 1-bit units.
When used as an input port, a pull-up resistor can be specified by means
of software.
P22
SCK1
STB
P23
P24
BUSY
SI0/SB0
SO0/SB1
SCK0
TO0
P25
P26
P27
P30
Port 3
8-bit I/O port.
P31
TO1
Input/output can be specified in 1-bit units.
When used as an input port, a pull-up resistor can be specified by means
of software.
P32
TO2
P33
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
P40 to P47
Port 4
AD0 to AD7
8-bit I/O port.
Input/output can be specified in 8-bit units.
When used as an input port, a pull-up resistor can be specified by means
of software.
The test input flag (KRIF) is set to 1 by falling edge detection.
Notes 1. When using the P07/XT1 pin as an input port, set bit 6 (FRC) of the processor clock control register (PCC)
to 1. Do not use the on-chip feedback resistor of the subsystem clock oscillator.
2. When using the P10/ANI0 to P17/ANI7 pins as A/D converter analog input pins, set port 1 to the input mode.
At this time, pull-up resistors are automatically disconnected.
10
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
3.1 Port Pins (2/2)
After
Alternate
Function
Pin Name
I/O
Function
Reset
P50 to P57
I/O
I/O
Port 5
Input
A8 to A15
8-bit I/O port.
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
When used as an input port, a pull-up resistor can be specified by
means of software.
P60
P61
P62
P63
P64
P65
P66
P67
P70
Port 6
N-ch open-drain I/O port.
Input
Input
Input
—
8-bit I/O port.
An on-chip pull-up resistor can be
specified by the mask option.
LEDs can be driven directly.
Input/output can be specified in
1-bit units.
When used as an input port, a
pull-up resistor can be specified by
means of software.
RD
WR
WAIT
ASTB
SI2/RxD
Port 7
I/O
3-bit I/O port.
P71
P72
SO2/TxD
Input/output can be specified in 1-bit units.
When used as an input port, a pull-up resistor can be specified by
means of software.
SCK2/ASCK
P120 to P127 I/O
Port 12
Input
Input
RTP0 to RTP7
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, a pull-up resistor can be specified by
means of software.
P130, P131
I/O
Port 13
ANO0, ANO1
2-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, a pull-up resistor can be specified by
means of software.
Data Sheet U12327EJ5V0DS00
11
µPD78052, 78053, 78054, 78055, 78056, 78058
3.2 Non-Port Pins (1/2)
After
Alternate
Function
Pin Name
INTP0
I/O
Input
Function
Reset
External interrupt request input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified.
Input
P00/TI00
P01/TI01
P02
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
SI0
P03
P04
P05
P06
Input
Serial interface serial data input
Serial interface serial data output
Input
Input
P25/SB0
P20
SI1
SI2
P70/RxD
P26/SB1
P21
SO0
SO1
SO2
SB0
Output
P71/TxD
P25/SI0
P26/SO0
P27
I/O
I/O
Serial interface serial data input/output
Serial interface serial clock input/output
Input
Input
SB1
SCK0
SCK1
SCK2
STB
P22
P72/ASCK
P23
Output
Input
Serial interface automatic transmit/receive strobe output
Serial interface automatic transmit/receive busy input
Asynchronous serial interface serial data input
Asynchronous serial interface serial data output
Asynchronous serial interface serial clock input
External count clock input to the 16-bit timer (TM0)
Capture trigger signal input to the capture register (CR00)
External count clock input to the 8-bit timer (TM1)
External count clock input to the 8-bit timer (TM2)
16-bit timer (TM0) output (also used for 14-bit PWM output)
8-bit timer (TM1) output
Input
Input
Input
Input
Input
Input
BUSY
RxD
P24
Input
P70/SI2
P71/SO2
P72/SCK2
P00/INTP0
P01/INTP1
P33
TxD
Output
Input
ASCK
TI00
TI01
TI1
Input
TI2
P34
TO0
Output
Input
P30
TO1
P31
TO2
8-bit timer (TM2) output
P32
PCL
Output
Output
Clock output (for trimming of main system clock and subsystem clock)
Buzzer output
Input
Input
Input
P35
BUZ
P36
RTP0 to RTP7 Output
Real-time output port from which data is output in synchronization with
a trigger
P120 to P127
AD0 to AD7
A8 to A15
RD
I/O
Lower address/data bus for expanding memory externally
Higher address bus for expanding memory externally
Strobe signal output for reading from external memory
Strobe signal output for writing to external memory
Input
Input
Input
P40 to P47
P50 to P57
P64
Output
Output
WR
P65
12
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
3.2 Non-Port Pins (2/2)
After
Alternate
Function
Pin Name
I/O
Function
Reset
WAIT
ASTB
Input
Output
Wait insertion at external memory access
Input
Input
P66
Strobe output that externally latches address information output to
ports 4 and 5 to access external memory
P67
ANI0 to ANI7 Input
ANO0, ANO1 Output
A/D converter analog input
Input
Input
—
P10 to P17
D/A converter analog output
P130, P131
AVREF0
AVREF1
AVDD
AVSS
RESET
X1
Input
Input
A/D converter reference voltage input
—
—
D/A converter reference voltage input
—
—
A/D converter analog power supply. Connect to VDD.
Ground potential of A/D converter and D/A converter. Connect to VSS.
System reset input
—
—
—
—
—
Input
Input
—
—
Connecting crystal resonator for main system clock oscillation
—
—
X2
—
—
—
XT1
Input
Connecting crystal resonator for subsystem clock oscillation
Input
—
P07
—
XT2
—
VDD
—
—
—
Positive power supply
—
—
VSS
Ground potential
—
—
IC
Internally connected. Connect directly to VSS.
—
—
Data Sheet U12327EJ5V0DS00
13
µPD78052, 78053, 78054, 78055, 78056, 78058
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Types of Pin Input/Output Circuits (1/2)
Input/Output
Pin Name
I/O
Recommended Connection of Unused Pins
Connect to VSS .
Circuit Type
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
P07/XT1
2
Input
I/O
8-A
Input: Independently connect to VSS via a resistor.
Output: Leave open.
16
11
Input
I/O
Connect to VDD.
P10/ANI0 to P17/ANI7
P20/SI1
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
8-A
5-A
8-A
5-A
8-A
10-A
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30/TO0
5-A
P31/TO1
P32/TO2
P33/TI1
8-A
5-A
P34/TI2
P35/PCL
P36/BUZ
P37
P40/AD0 to P47/AD7
5-E
5-A
Input: Independently connect to VDD via a resistor.
Output: Leave open.
P50/A8 to P57/A15
P60 to P63
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
13-B
5-A
Input: Independently connect to VDD via a resistor.
Output: Leave open.
P64/RD
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P65/WR
P66/WAIT
P67/ASTB
14
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Table 3-1. Types of Pin Input/Output Circuits (2/2)
Input/Output
Pin Name
P70/SI2/RxD
I/O
I/O
Recommended Connection of Unused Pins
Circuit Type
8-A
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P71/SO2/TxD
5-A
P72/SCK2/ASCK
8-A
P120/RTP0 to P127/RTP7
P130/ANO0, P131/ANO1
5-A
I/O
I/O
12-A
Input: Independently connect to VSS via a resistor.
Note
Output: Leave open
.
RESET
XT2
2
Input
—
—
16
—
Leave open.
AVREF0
AVREF1
AVDD
AVSS
IC
Connect to VSS .
Connect to VDD .
Connect to VSS .
Connect directly to VSS.
Note Output a low level.
Data Sheet U12327EJ5V0DS00
15
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2
Type 8-A
VDD
Pull-up
enable
P-ch
IN
VDD
Data
P-ch
IN/OUT
Output
disable
N-ch
Schmitt-triggered input with hysteresis characteristics
VDD
Type 5-A
VDD
Type 10-A
Pull-up
enable
Pull-up
enable
P-ch
P-ch
VDD
VDD
Data
Data
P-ch
P-ch
IN/OUT
IN/OUT
Output
disable
Open drain
Output disable
N-ch
N-ch
Input
enable
V
Type 5-E
Type 11
VDD
DD
Pull-up
enable
P-ch
Pull-up
enable
P-ch
VDD
Data
VDD
P-ch
P-ch
IN/OUT
Data
N-ch
Output
disable
Comparator
IN/OUT
P-ch
N-ch
Output
disable
N-ch
+
-
V
REF (Threshold Voltage)
Input
enable
16
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 3-1. Pin Input/Output Circuits (2/2)
VDD
Type 12-A
Type 16
Pull-up
enable
Feed back
cut-off
P-ch
VDD
P-ch
Data
P-ch
IN/OUT
Output
disable
N-ch
Input
enable
P-ch
XT1
XT2
Analog output
voltage
N-ch
Type 13-B
VDD
Mask
option
IN/OUT
Data
Output disable
N-ch
VDD
P-ch
RD
Middle voltage input buffer
Data Sheet U12327EJ5V0DS00
17
µPD78052, 78053, 78054, 78055, 78056, 78058
4.
MEMORY SPACE
Figure 4-1 shows the µPD78052/78053/78054/78055/78056/78058 memory map.
Figure 4-1. Memory Map
FFFFH
Special function registers
(SFRs) 256 × 8 bits
FF00H
FEFFH
FA7FH
General-purpose
registers
Reserved
32 × 8 bits
FEE0H
FEDFH
F800H
F7FFH
Internal expanded RAM
1024 × 8 bits
Note 1
Internal high-speed
RAMNote 3
F400H
F3FFH
mmmmH
mmmmH – 1
ReservedNote 2
F000H
nnnnH
Reserved
FAE0H
FADFH
Data memory
space
Internal buffer RAM 32 × 8 bits
Program area
FAC0H
FABFH
1000H
0FFFH
Reserved
CALLF entry area
FA80H
FA7FH
0800H
07FFH
Program area
CALLT table area
Vector table area
External memory
0080H
007FH
Program memory
space
nnnnH + 1
nnnnH
0040H
003FH
Internal ROMNote 3
0000H
0000H
Notes 1. µPD78058 only
2. If external device expansion functions are to be employed for the µPD78058, set the size of internal ROM
to 56 KB or below using the memory size switching register (IMS).
3. The internal ROM capacity and internal high-speed RAM capacity differ depending on the product (see
the following table).
Last Address of Internal ROM
nnnnH
First Address of Internal High-Speed RAM
mmmmH
Part Number
µPD78052
µPD78053
µPD78054
µPD78055
µPD78056
µPD78058
3FFFH
5FFFH
7FFFH
9FFFH
BFFFH
EFFFH
FD00H
FB00H
18
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following three types of I/O ports are available.
•
•
•
CMOS input (P00, P07):
2
CMOS I/O (P01 to P06, port 1 to port 5, P64 to P67, port 7, port 12, port 13): 63
N-ch open-drain I/O (P60 to P63):
4
Total:
69
Table 5-1. Port Functions
Name
Pin Name
P00, P07
Function
Port 0
Input-only
I/O port. Input/output can be specified in 1-bit units.
P01 to P06
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 1
Port 2
Port 3
Port 4
P10 to P17
P20 to P27
P30 to P37
P40 to P47
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
I/O port. Input/output can be specified in 8-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
The test flag (KRIF) is set to 1 by falling edge detection.
Port 5
Port 6
P50 to P57
P60 to P63
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
LEDs can be driven directly.
N-ch open-drain I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by the mask option.
LEDs can be driven directly.
P64 to P67
P70 to P72
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 7
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Port 12
Port 13
P120 to P127 I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
P130, P131
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by means of software.
Data Sheet U12327EJ5V0DS00
19
µPD78052, 78053, 78054, 78055, 78056, 78058
5.2 Clock Generator
Two types of generators, a main system clock generator and a subsystem clock generator, are available.
The minimum instruction execution time can also be changed.
•
•
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0 MHz operation with main system clock)
122 µs (@32.768 kHz operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1/P07
XT2
Subsystem
clock
oscillator
f
XT
Watch timer, clock
output function
Prescaler
1
2
f
X
X1
X2
Main system
clock
oscillator
Clock to peripheral
hardware
Selector
Prescaler
f
XX
f
XX
f
XX
f
XX
f
XX
Scaler
f
XT
2
22 23 24
2
f
X
Standby
controller
Wait
controller
STOP
2
Selector
CPU clock
(fCPU
)
To INTP0
sampling clock
5.3 Timer/Event Counter
The µPD78052/78053/78054/78055/78056/78058 incorporate a 5-channel timer/event counter.
•
•
•
•
16-bit timer/event counter: 1 channel
8-bit timer/event counter: 2 channels
Watch timer:
1 channel
1 channel
Watchdog timer:
Table 5-2. Operation of Timer/Event Counter
16-Bit Timer/Event Counter 8-Bit Timer/Event Counter Watch Timer Watchdog Timer
Operation mode
Interval timer
1 channel
1 channel
2 channels
2 channels
1 channel
—
1 channel
—
External event counter
Function
Timer output
1 output
1 output
2 inputs
1 output
1 output
2
2 outputs
—
—
—
—
—
PWM output
Pulse amplitude measurement
Square wave output
One-shot pulse output
Interrupt source
Test input
2 outputs
—
—
—
—
1
—
2
1
—
—
1 input
—
20
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter
Internal bus
INTP1
TI01/P01/INTP1
16-bit capture/
compare register
(CR00)
Selector
INTTM00
PWM pulse
output
controller
Match
Output
controller
Watch Timer
Output
TO0/P30
2fXX
f
XX
16-bit timer register
(TM0)
Selector
f
XX/2
f
XX/22
Clear
Selector
Edge
detector
TI00/P00/INTP0
Match
INTTM01
INTP0
16-bit capture/
compare register
(CR01)
Internal bus
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter
Internal bus
INTTM1
8-bit compare
register (CR10)
8-bit compare
register (CR20)
Output
controller
Selector
TO2/P32
INTTM2
Match
Match
f
xx/2 to fxx/29
8-bit timer
register 1 (TM1)
/211
TI1/P33
Selector
Selector
f
x
8-bit timer
Selector
register 2 (TM2)
Clear
Clear
f
xx/2 to fxx/29
Selector
f
x
/211
TI2/P34
Output
TO1/P31
controller
Internal bus
Data Sheet U12327EJ5V0DS00
21
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 5-4. Watch Timer Block Diagram
fW
214
Selector
5-bit counter
fXX/27
fW
Selector
INTWT
Prescaler
Selector
fXT
fW
213
fW
24
fW
fW
fW
fW
fW
25
26
27
28
29
INTTM3
Selector
To 16-bit timer/
event counter
Figure 5-5. Watchdog Timer Block Diagram
f
XX
23
Prescaler
f
XX
24
f
XX
25
f
XX
26
f
XX
27
f
XX
28
f
XX
29
f
XX
211
INTWDT
maskable
interrupt request
Selector
8-bit counter
RESET
Controller
INTWDT
non-maskable
interrupt request
22
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
5.4 Clock Output Controller
Clocks with the following frequencies can be output as clock output.
•
19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (@5.0 MHz operation with
main system clock)
•
32.768 kHz (@32.768 kHz operation with subsystem clock)
Figure 5-6. Block Diagram of Clock Output Controller
f
XX
f
XX/2
f
f
f
f
XX/22
XX/23
XX/24
Synchronization
circuit
Selector
Output controller
PCL/P35
XX/25
f
f
XX/26
XX/27
f
XT
5.5 Buzzer Output Controller
Clocks with the following frequencies can be output as buzzer output.
1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (@5.0 MHz operation with main system clock)
•
Figure 5-7. Block Diagram of Buzzer Output Controller
f
XX/29
XX/210
XX/211
BUZ/P36
f
Selector
Output controller
f
Data Sheet U12327EJ5V0DS00
23
µPD78052, 78053, 78054, 78055, 78056, 78058
5.6 A/D Converter
An A/D converter consisting of eight 8-bit resolution channels is incorporated.
The following two A/D conversion operation start-up methods are available.
•
•
Hardware start
Software start
Figure 5-8. A/D Converter Block Diagram
Series resistor string
AVDD
Sample & hold circuit
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
AVREF0
Voltage comparator
Tap
selector
Selector
Succesive approxmation
register (SAR)
AVSS
Edge
detector
INTAD
INTP3
Controller
INTP3/P03
A/D conversion
result register (ADCR)
Internal bus
24
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
5.7 D/A Converter
A D/A converter consisting of two 8-bit resolution channels is available.
The conversion method is the R-2R resistor ladder method.
Figure 5-9. D/A Converter Block Diagram
AVREF1
ANOn
Selector
DACSn
write
AVSS
INTTM
X
D/A conversion value set register n
(DACSn)
DAMm
D/A converter
mode register
Internal bus
n = 0, 1
m = 4, 5
x = 1, 2
5.8 Serial Interface
Three clocked serial interface channels are incorporated.
•
•
•
Serial interface channel 0
Serial interface channel 1
Serial interface channel 2
Table 5-3. Types and Functions of Serial Interface
Function
Serial Interface Channel 0
Serial Interface Channel 1
Serial Interface Channel 2
3-wire serial I/O mode
(MSB/LSB first switching
possible)
(MSB/LSB first switching
possible)
(MSB/LSB first switching
possible)
3-wire serial I/O mode with auto-
matic transmit/receive function
—
(MSB/LSB first switching
possible)
—
SBI (serial bus interface) mode
2-wire serial I/O mode
(MSB first)
(MSB first)
—
—
—
—
—
—
Asynchronous serial interface
(UART) mode
(On-chip dedicated baud
rate generator)
Data Sheet U12327EJ5V0DS00
25
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 5-10. Block Diagram of Serial Interface Channel 0
Internal bus
SI0/SB0/P25
SO0/SB1/P26
Output
latch
Serial I/O shift
register 0 (SIO0)
Selector
Selector
Busy/acknowledge
output circuit
Bus release/command/
acknowledge detector
Interrupt
request
signal
INTCSI0
Serial clock counter
SCK0/P27
generator
f
XX/2 to fXX/28
Serial clock controller
Selector
TO2
Figure 5-11. Block Diagram of Serial Interface Channel 1
Internal bus
Automatic data transmit/
receive address pointer
(ADTP)
Automatic data
transmit/receive
interval specification
register (ADTI)
Buffer RAM
Match
SI1/P20
Serial I/O shift register 1 (SIO1)
SO1/P21
STB/P23
5-bit counter
Handshake
controller
BUSY/P24
Interrupt request
signal generator
Serial counter
INTCSI1
SCK1/P22
f
XX/2 to fXX/28
Selector
Serial clock controller
TO2
26
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 5-12. Block Diagram of Serial Interface Channel 2
Internal bus
Receive buffer register
(RXB/SIO2)
Direction controller
Transmit shift register
(TXS/SIO2)
Direction controller
Receive shift register
(RXS)
Transmit controller
RxD/SI2/P70
TxD/SO2/P71
INTST
INTSER
INTSR/INTCSI2
Receive controller
SCK output
controller
ASCK/SCK2/P72
Baud rate
generator
f
XX to fXX/210
5.9 Real-Time Output Port
Data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently
with timer interrupt or external interrupt generation in order to output off-chip. This is a real-time output function. Pins
used to output off-chip are called real-time output ports.
By using a real-time output port, a signal with no jitter can be output. This is most applicable to control of stepper
motors, etc.
Figure 5-13. Block Diagram of Real-Time Output Port
Internal bus
Real-time output Real-time output
INTP2
INTTM1
Output trigger
controller
buffer register
higher 4 bits
(RTBH)
buffer register
lower 4 bits
(RTBL)
INTTM2
Real-time output port mode
register (RTPM)
Output latch
P127
P120
Data Sheet U12327EJ5V0DS00
27
µPD78052, 78053, 78054, 78055, 78056, 78058
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 Interrupt Functions
A total of 22 interrupt sources are provided, divided into the following three types.
•
•
•
Non-maskable: 1
Maskable:
Software:
20
1
The following table shows the interrupt source list.
Table 6-1. Interrupt Source List (1/2)
Vector
Table
Basic
Interrupt Source
Trigger
Default
Internal/
External
Interrupt Type
Non-maskable
Maskable
Configuration
Note 1
Priority
Note 2
Name
Address
Type
—
0
INTWDT Watchdog timer overflow
(with watchdog timer mode 1 selected)
INTWDT Watchdog timer overflow
(with interval timer mode selected)
Pin input edge detection
Internal
0004H
(A)
(B)
1
2
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
External
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
(C)
(D)
3
4
5
6
7
8
INTCSI0 End of serial interface channel 0 transfer
INTCSI1 End of serial interface channel 1 transfer
Internal
(B)
9
10
INTSER Occurrence of serial interface channel 2
UART reception error
11
12
INTSR
End of serial interface channel 2 UART
reception
001AH
INTCSI2 End of serial interface channel 2 3-wire
transfer
INTST
End of serial interface channel 2 UART
transmission
001CH
Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same
time. 0 is the highest and 18 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
28
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Table 6-1. Interrupt Source List (2/2)
Vector
Table
Basic
Interrupt Source
Trigger
Default
Internal/
External
Interrupt Type
Maskable
Configuration
Note 1
Priority
Note 2
Name
Address
Type
13
14
INTTM3 Reference time interval signal from
watch timer
Internal
001EH
0020H
(B)
INTTM00 Generation of match signal of 16-bit
timer register and capture/compare
register (CR00)
15
INTTM01 Generation of match signal of 16-bit
timer register and capture/compare
register (CR01)
0022H
16
17
INTTM1 Generation of match signal of 8-bit
timer/event counter 1
0024H
0026H
INTTM2 Generation of match signal of 8-bit
timer/event counter 2
18
—
INTAD
BRK
End of A/D conversion
0028H
003EH
Software
BRK instruction execution
—
(E)
Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same
time. 0 is the highest and 18 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
Data Sheet U12327EJ5V0DS00
29
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 6-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Vector table
Priority
controller
Interrupt
request
address
generator
Standby release
signal
(B) Internal maskable interrupt
Internal bus
PR
ISP
MK
IE
Vector table
address
generator
Priority
controller
Interrupt
request
IF
Standby release
signal
(C) External maskable interrupt (INTP0)
Internal bus
MK
Sampling clock
select register
(SCS)
External interrupt
mode register
(INTM0)
PR
ISP
IE
Vector table
address
generator
Priority
controller
Interrupt
request
Edge
detector
Sampling
clock
IF
Standby release
signal
30
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Figure 6-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (except INTP0)
Internal bus
MK
External interrupt
mode register
(INTM0, INTM1)
PR
ISP
IE
Vector table
address
generator
Priority
controller
Interrupt
request
Edge
detector
IF
Standby release
signal
(E) Software interrupt
Internal bus
Vector table
address
generator
Interrupt
request
Priority
controller
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-service priority flag
MK: Interrupt mask flag
PR: Priority specification flag
Data Sheet U12327EJ5V0DS00
31
µPD78052, 78053, 78054, 78055, 78056, 78058
6.2 Test Functions
Table 6-2 shows the two test functions available.
Table 6-2. Test Input Source List
Test Input Source
Trigger
Internal/External
Name
INTWT
INTPT4
Watch timer overflow
Port 4 falling edge detection
Internal
External
Figure 6-2. Basic Configuration of Test Function
Internal bus
MK
Standby release
Interrupt
IF
signal
request
IF: Test input flag
MK: Test mask flag
32
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
7. EXTERNAL DEVICE EXPANSION FUNCTION
The external device expansion function is for the connection of external devices to areas other than the internal
ROM, RAM and SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
The following two standby functions are available for further reduction of system current consumption.
•
•
HALT mode: In this mode, the CPU operating clock is stopped.
The average current consumption can be reduced by intermittent operation by combining this mode
with the normal operation mode.
STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on the
main system clock are suspended, and only the subsystem clock is used, resulting in extremely
small power consumption.
Figure 8-1. Standby Function
CSS=1
Main system
clock operation
Subsystem clock
operationNote
CSS=0
HALT
instruction
STOP
instruction
HALT
instruction
Interrupt
request
Interrupt
request
Interrupt
request
HALT mode
HALT modeNote
STOP mode
(Main system clock
oscillation stopped)
(Clock supply to CPU halted,
oscillation maintained)
(Clock supply to CPU halted,
oscillation maintained)
Note The current consumption can be reduced by stopping the main system clock. When the CPU is operating on
the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC) to stop the main system clock.
The STOP instruction cannot be used.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back to the
main system clock.
9. RESET FUNCTION
The following two reset methods are available.
•
•
External reset by RESET signal input
Internal reset by watchdog timer runaway time detection
Data Sheet U12327EJ5V0DS00
33
µPD78052, 78053, 78054, 78055, 78056, 78058
10. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd
Operand
[HL + Byte]
[HL + B]
[HL + C]
#byte
A
rNote
sfr
saddr !addr16 PSW
[DE]
[HL]
$addr16
1
None
1st
Operand
A
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
ROR
ROL
ADDC
SUB
XCH
ADD
RORC
ROLC
ADDC
SUB
ADDC ADDC
ADDC ADDC
SUB SUB
SUBC SUBC
SUBC
AND
OR
SUB
SUB
SUBC
AND
OR
SUBC
AND
OR
SUBC
AND
OR
XOR
AND
OR
AND
OR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV
MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
DBNZ
DBNZ
B, C
sfr
MOV
MOV
MOV
saddr
MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
MOV
MOV
[DE]
[HL]
ROR4
ROL4
[HL + Byte]
MOV
[HL + B]
[HL + C]
X
C
MULU
DIVUW
Note Except r = A
34
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
(2) 16-bit instructions
MOV, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
ADDW
AX
rpNote
sfrp
saddrp
MOVW
!addr16
MOVW
SP
None
MOVW
XCHW
MOVW
MOVW
AX
SUBW
CMPW
MOVW
MOVWNote
rp
INCW, DECW
PUSH, POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note Only when rp = BC, DE or HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
1st Operand
A.bit
MOV1
BT
SET1
CLR1
BF
BTCLR
SET1
CLR1
BT
MOV1
MOV1
MOV1
MOV1
sfr.bit
BF
BTCLR
BT
SET1
CLR1
saddr.bit
PSW.bit
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
[HL].bit
CY
BF
BTCLR
MOV1
MOV1
MOV1
AND1
MOV1
AND1
MOV1
AND1
SET1
CLR1
NOT1
AND1
AND1
OR1
OR1
OR1
OR1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
AX
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
1st Operand
Basic instruction
BR
CALL
BR
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
Compound
instruction
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Data Sheet U12327EJ5V0DS00
35
µPD78052, 78053, 78054, 78055, 78056, 78058
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD
Conditions
Ratings
Unit
V
Supply voltage
–0.3 to +7.0
AVDD
AVREF0
AVREF1
AVSS
VI1
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +0.3
V
V
V
V
Input voltage
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P64 to P67, P70 to P72,
P120 to P127, P130, P131, X1, X2, XT2, RESET
–0.3 to VDD + 0.3
V
VI2
VO
P60 to P63
N-ch open drain
–0.3 to +16
–0.3 to VDD + 0.3
AVSS – 0.3 to AVREF0 + 0.3
–10
V
V
Output voltage
Analog input voltage VAN
P10 to P17
Per pin
Analog input pin
V
Output
IOH
mA
mA
current, high
Total for P01 to P06, P30 to P37, P56, P57,
P60 to P67, P120 to P127
–15
Total for P10 to P17, P20 to P27, P40 to P47,
P50 to P55, P70 to P72, P130, P131
–15
mA
Note
Output
IOL
Per pin
Peak value
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
current, low
rms value
Peak value
rms value
Peak value
rms value
Peak value
rms value
Peak value
rms value
15
Total for P50 to P55
Total for P56, P57, P60 to P63
100
70
100
70
Total for P10 to P17, P20 to P27,
50
P40 to P47, P70 to P72, P130, P131
20
50
Total for P01 to P06, P30 to P37,
P64 to P67, P120 to P127
20
Operating ambient
temperature
TA
–40 to +85
Storage
Tstg
–65 to +150
°C
temperature
Note The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
36
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Resonator
Recommended Circuit
X1 X2
Parameter
Oscillation
frequency (fX)Note 1
Conditions
MIN. TYP. MAX. Unit
Ceramic
VDD = Oscillation voltage range 1.0
5.0
MHz
IC
resonator
Oscillation
After VDD reaches oscillation
4
ms
C2
C1
stabilization timeNote 2 voltage range MIN.
Crystal
Oscillation
frequency (fX)Note 1
1.0
5.0
10
MHz
ms
X1
X2
IC
resonator
R1
Oscillation
stabilization timeNote 2
VDD = 4.5 to 6.0 V
C1
C2
30
External
clock
X1 input
frequency (fX)Note 1
1.0
85
5.0
MHz
ns
X2
X1
X1 input
500
µ
PD74HCU04
high-/low-level width
(tXH , tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back
to the main system clock.
Data Sheet U12327EJ5V0DS00
37
µPD78052, 78053, 78054, 78055, 78056, 78058
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Resonator
Recommended Circuit
Parameter
Oscillation
frequency (fXT)Note 1
Conditions
MIN. TYP. MAX. Unit
Crystal
32 32.768 35
kHz
XT1 XT2
IC
resonator
R2
Oscillation
stabilization timeNote 2
VDD = 4.5 to 6.0 V
1.2
2
s
C3
C4
10
External
clock
XT1 input
frequency (fXT)Note 1
32
5
100
kHz
µs
XT2
XT1
XT1 input
15
high-/low-level width
(tXTH , tXTL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem clock
is used.
38
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Recommended Oscillator Constant
(1) µPD78052, 78053, 78054, 78055, 78056
Main system clock: Ceramic resonator (TA = –40 to +85°C)
Recommended
Frequency
Oscillation
Manufacturer
Product Name
Circuit Constant
Voltage Range
Remarks
(MHz)
C1 (pF)
30
C2 (pF) MIN. (V) MAX. (V)
Murata Mfg.
Co., Ltd.
CSA5.00MG
CST5.00MGW
KBR-5.0MSA
KBR-5.0MKS
5.00
5.00
5.00
5.00
30
2.0
2.0
2.0
2.0
6.0
6.0
6.0
6.0
On-chip On-chip
33 33
On-chip capacitor
Lead type
Kyocera
Corp.
On-chip On-chip
On-chip capacitor,
lead type
KBR-5.0MWS
5.00
On-chip On-chip
2.0
6.0
On-chip capacitor,
lead type
PBRC 5.00A
CCR4.0MC3
CCR5.0MC3
5.00
4.00
5.00
33
33
2.0
2.0
2.0
6.0
6.0
6.0
Chip type
TDK Corp.
On-chip On-chip
On-chip On-chip
On-chip capacitor
On-chip capacitor
Main system clock: Crystal resonator (TA = –10 to +70°C)
Recommended
Circuit Constant
C4 (pF) R2 (kΩ)
27 1.5
Oscillation
Frequency
(MHz)
Manufacturer
Product Name
SMD-49
Voltage Range
C3 (pF)
27
MIN. (V) MAX. (V)
Daishinku
Corp.
3.579545
2.0
6.0
Subsystem clock: Crystal resonator (TA = –10 to +70°C)
Recommended
Circuit Constant
C2 (pF) R1 (kΩ)
20 330
Oscillation
Frequency
(MHz)
Manufacturer
Product Name
Voltage Range
C1 (pF)
27
MIN. (V) MAX. (V)
Daishinku
Corp.
DT-38
32.768
2.0
6.0
(1TA252E00)
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
However, oscillation frequency precision is not guaranteed. For applications requiring oscillation
frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For
details, please contact directly the manufacturer of the resonator you will use.
Data Sheet U12327EJ5V0DS00
39
µPD78052, 78053, 78054, 78055, 78056, 78058
(2) µPD78058
Main system clock: Ceramic resonator (TA = –40 to +85°C)
Recommended
Frequency
Oscillation
Manufacturer Product Name
Circuit Constant
Voltage Range
Remarks
(MHz)
C1 (pF)
33
C2 (pF) MIN. (V) MAX. (V)
Kyocera
Corp.
PBRC4.19A
4.19
4.19
4.19
4.19
4.91
4.91
4.91
4.91
33
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
PBRC4.19B
On-chip On-chip
33 33
On-chip On-chip
33 33
On-chip On-chip
33 33
On-chip On-chip
On-chip capacitor
On-chip capacitor
On-chip capacitor
On-chip capacitor
KBR-4.19MSA
KBR-4.19MKS
PBRC4.91A
PBRC4.91B
KBR-4.91MSA
KBR-4.91MKS
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
However, oscillation frequency precision is not guaranteed. For applications requiring oscillation
frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For
details, please contact directly the manufacturer of the resonator you will use.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input
Symbol
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
CIN
f = 1 MHz
capacitance
Unmeasured pins returned to 0 V.
f = 1 MHz
I/O
CIO
P01 to P06, P10 to P17,
15
pF
capacitance
Unmeasured pins returned to 0 V. P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, P70 to P72,
P120 to P127, P130, P131
P60 to P63
20
pF
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
40
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
Input voltage,
high
VIH1
P10 to P17, P21, P23, P30 to P32,
P35 to P37, P40 to P47, P50 to P57,
P64 to P67, P71, P120 to P127,
P130, P131
VDD = 2.7 to 6.0 V
0.7VDD
VDD
0.8VDD
VDD
V
VIH2
VIH3
VIH4
VIH5
P00 to P06, P20, P22, P24 to P27,
P33, P34, P70, P72, RESET
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
0.8VDD
0.85VDD
0.7VDD
VDD
VDD
15
V
V
V
V
V
V
V
V
V
V
P60 to P63
(N-ch open drain)
0.8VDD
15
X1, X2
VDD – 0.5
VDD – 0.2
0.8VDD
VDD
VDD
VDD
VDD
VDD
0.3VDD
XT1/P07, XT2
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
0.9VDD
2.0 V ≤ VDD < 2.7 VNote 0.9VDD
Input voltage,
low
VIL1
P10 to P17, P21, P23, P30 to P32,
P35 to P37, P40 to P47, P50 to P57,
P64 to P67, P71, P120 to P127,
P130, P131
VDD = 2.7 to 6.0 V
0
0
0.2VDD
V
VIL2
VIL3
P00 to P06, P20, P22, P24 to P27,
P33, P34, P70, P72, RESET
VDD = 2.7 to 6.0 V
0
0.2VDD
0.15VDD
0.3VDD
0.2VDD
0.1VDD
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
0
P60 to P63
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
0
0
0
VIL4
VIL5
X1, X2
VDD = 2.7 to 6.0 V
0
0
0.2
XT1/P07, XT2
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 VNote
0
0.2VDD
0.1VDD
0.1VDD
0
0
Output voltage, VOH
high
VDD = 4.5 to 6.0 V, IOH = –1 mA
IOH = –100 µA
VDD – 1.0
VDD – 0.5
Output voltage, VOL1
low
P50 to P57, P60 to P63
VDD = 4.5 to 6.0 V,
IOL = 15 mA
0.4
2.0
0.4
P01 to P06, P10 to P17, P20 to P27, VDD = 4.5 to 6.0 V,
P30 to P37, P40 to P47, P64 to P67, IOL = 1.6 mA
P70 to P72, P120 to P127, P130,
P131
V
VOL2
SB0, SB1, SCK0
VDD = 4.5 to 6.0 V,
open drain,
0.2VDD
0.5
V
V
pulled-up (R = 1 KΩ)
VOL3
IOL = 400 µA
Note When using the P07/X1 pin as P07, the inverse phase of P07 should be input to XT2.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U12327EJ5V0DS00
41
µPD78052, 78053, 78054, 78055, 78056, 78058
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Conditions
P00 to P06, P10 to P17,
MIN.
TYP.
MAX.
3
Unit
Input leakage
current, high
ILIH1
VIN = VDD
µA
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, P70 to P72,
P120 to P127, P130, P131,
RESET
ILIH2
ILIH3
ILIL1
X1, X2, XT1/P07, XT2
P60 to P63
20
80
–3
µA
µA
µA
VIN = 15 V
VIN = 0 V
Input leakage
current, low
P00 to P06, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, P70 to P72,
P120 to P127, P130, P131,
RESET
ILIL2
ILIL3
X1, X2, XT1/P07, XT2
P60 to P63
–20
–3Note 1
3
µA
µA
µA
Output leakage ILOH
current, high
VOUT = VDD
Output leakage ILOL
current, low
VOUT = 0 V
–3
90
90
µA
kΩ
kΩ
Mask option
R1
VIN = 0 V, P60 to P63
20
15
40
40
pull-up resistor
Software
pull-up
R2
VIN = 0 V, P01 to P06,
P10 to P17, P20 to P27,
P30 to P37, P40 to P47,
P50 to P57, P64 to P67,
P70 to P72, P120 to
P127, P130, P131
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
resistorNote 2
20
500
kΩ
Notes 1. When pull-up resistors are not connected to P60 to P63 (specifiable by the mask option), a low-level input
leakage current of –200 µA (MAX.) flows only for 1.5 clocks (without wait) after a read instruction has been
executed to port 6 (P6) or port mode register 6 (PM6). At times other than this 1.5-clock interval, a –3 µA
(MAX.) current flows.
2. A software pull-up resistor can be used only in the range of VDD = 2.7 to 6.0 V.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
42
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
4
MAX.
12
Unit
mA
mA
mA
mA
mA
mA
mA
µA
Power supply
currentNote 1
IDD1
5.0 MHz crystal oscillation operating VDD = 5.0 V ±10%Note 5
mode (fXX = 2.5 MHz)Note 2
VDD = 3.0 V ±10%Note 6
VDD = 2.2 V ±10%Note 6
0.6
0.35
6.5
0.8
1.4
0.5
280
1.6
0.65
60
1.8
1.05
19.5
2.4
4.2
1.5
840
4.8
1.95
120
64
5.0 MHz crystal oscillation operating VDD = 5.0 V ±10%Note 5
mode (fXX = 5.0 MHz)Note 3
VDD = 3.0 V ±10%Note 6
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.2 V ±10%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.2 V ±10%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.2 V ±10%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.2 V ±10%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.2 V ±10%
IDD2
5.0 MHz crystal oscillation HALT
mode (fXX = 2.5 MHz)Note 2
5.0 MHz crystal oscillation HALT
mode (fXX = 5.0 MHz)Note 3
mA
mA
µA
IDD3
IDD4
IDD5
IDD6
32.768 kHz crystal oscillation
operating modeNote 4
32
µA
24
48
µA
32.768 kHz crystal oscillation
HALT modeNote 4
25
55
µA
5
15
µA
2.5
1
12.5
30
µA
XT1 = VDD
µA
STOP mode
0.5
0.3
0.1
0.05
0.05
10
µA
When feedback resistor used
10
µA
XT1 = VDD
30
µA
STOP mode
10
µA
When feedback resistor not used
10
µA
Notes 1. Refers to the current flowing to the VDD and AVDD pins. The current flowing to the A/D converter, D/A
converter, and on-chip pull-up resistors are not included.
2. Operation with main system clock fXX = fX/2 (when the oscillation mode selection register (OSMS) is set
to 00H)
3. Operation with main system clock fXX = fX (when OSMS is set to 01H)
4. When the main system clock operation is stopped.
5. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
6. Low-speed mode operation (when PCC is set to 04H).
Data Sheet U12327EJ5V0DS00
43
µPD78052, 78053, 78054, 78055, 78056, 78058
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
TYP.
MAX.
64
Unit
µs
TCY
Operating with main system clock VDD = 2.7 to 6.0 V
(fXX = 2.5 MHz)Note 1
0.8
(minimum
2.2
64
µs
instruction
Operating with main system clock 4.5 V ≤ VDD ≤ 6.0 V
0.4
32
µs
execution time)
(fXX = 5.0 MHz)Note 2
2.7 V ≤ VDD < 4.5 V
0.8
32
µs
Operating with subsystem clock
VDD = 4.5 to 6.0 V
40Note 3
122
125
4
µs
TI00, TI01, TI1, TI2 fTI
input frequency
0
MHz
kHz
µs
0
2/fsam + 0.1Note 4
2/fsam + 0.2Note 4
2/fsam + 0.5Note 4
10
275
TI00 input high-/
low-level width
tTIH,
3.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 3.5 V
tTIL
µs
µs
TI01 input high-/
low-level width
tTIH,
tTIL
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
µs
20
µs
TI1, TI2 input high-/ tTIH,
100
ns
low-level width
tTIL
1.8
µs
Interrupt request
input high-/
tINTH,
tINTL
INTP0
3.5 V ≤ VDD ≤ 6.0 V 2/fsam + 0.1Note 4
2.7 V ≤ VDD < 3.5 V 2/fsam + 0.2Note 4
2/fsam + 0.5Note 4
µs
µs
low-level width
µs
INTP1 to INTP6, KR0 to KR7
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
10
20
10
20
µs
µs
RESET
tRSL
µs
low-level width
µs
Notes 1. Operation with main system clock fXX = fX/2 (when the oscillation mode selection register (OSMS) is set
to 00H)
2. Operation with main system clock fXX = fX (when OSMS is set to 01H)
3. Value when an external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
4. Selection of fsam = fXX/2N, fXX/32, fXX/64, fXX/128 is possible with bits 0 and 1 (SCS0, SCS1) of the sampling
clock selection register (SCS) (when N= 0 to 4).
44
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
TCY vs. VDD (fXX = fX/2 main system clock operation)
TCY vs. VDD (fXX = fX main system clock operation)
60
10
60
10
µ
µ
Guaranteed operation
range
Guaranteed
operation
range
2.0
1.0
2.0
1.0
0.5
0.4
0.5
0.4
0
0
1
2
3
4
5
6
1
2
3
4
5
6
Supply voltage VDD [V]
Supply voltage VDD [V]
Data Sheet U12327EJ5V0DS00
45
µPD78052, 78053, 78054, 78055, 78056, 78058
(2) Read/write operation
(a) When MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 4.5 to 6.0 V)
Parameter
ASTB high-level width
Address setup time
Symbol
Conditions
MIN.
0.85tCY – 50
0.85tCY – 50
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tASTH
tADS
Address hold time
tADH
Data input time from address
tADD1
tADD2
tRDD1
tRDD2
tRDH
(2.85 + 2n)tCY – 80
(4 + 2n)tCY – 100
(2 + 2n)tCY – 100
(2.85 + 2n)tCY – 100
Data input time from RD↓
Read data hold time
RD low-level width
0
tRDL1
tRDL2
tRDWT1
tRDWT2
tWRWT
tWTL
(2 + 2n)tCY – 60
(2.85 + 2n)tCY – 60
Input time from RD↓ to WAIT↓
0.85tCY – 50
2tCY – 60
Input time from WR↓ to WAIT↓
WAIT low-level width
2tCY – 60
(1.15 + 2n)tCY
(2.85 + 2n)tCY – 100
20
(2 + 2n)tCY
Write data setup time
tWDS
Write data hold time
tWDH
WR low-level width
tWRL
(2.85 + 2n)tCY – 60
25
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
tASTRD
tASTWR
tRDAST
0.85tCY + 20
0.85tCY – 10
Delay time from RD↑ to ASTB↑ at
1.15tCY + 20
1.15tCY + 50
external fetch
Address hold time from RD↑ at
tRDADH
0.85tCY – 50
ns
external fetch
Write data output time from RD↑
Write data output time from WR↓
Address hold time from WR↑
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
tRDWD
tWRWD
tWRADH
tWTRD
tWTWR
40
0
ns
ns
ns
ns
ns
50
0.85tCY
1.15tCY + 40
3.15tCY + 40
3.15tCY + 30
1.15tCY + 40
1.15tCY + 30
Remarks 1. MCS: Bit 0 of the oscillation mode selection register (OSMS)
2. PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
3. tCY = TCY/4
4. n indicates the number of waits.
46
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
(b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
tCY – 80
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASTB high-level width
tASTH
VDD = 2.7 to 6.0 V
tCY – 150
tCY – 80
Address setup time
tADS
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
tCY – 150
0.4tCY – 10
0.37tCY – 40
Address hold time
tADH
Data input time from address
tADD1
tADD2
tRDD1
tRDD2
(3 + 2n)tCY – 160
(3 + 2n)tCY – 320
(4 + 2n)tCY – 200
(4 + 2n)tCY – 300
(1.4 + 2n)tCY – 70
(1.37 + 2n)tCY – 120
(2.4 + 2n)tCY – 70
(2.37 + 2n)tCY – 120
Data input time from RD↓
Read data hold time
RD low-level width
tRDH
0
tRDL1
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
(1.4 + 2n)tCY – 20
(1.37 + 2n)tCY – 20
(2.4 + 2n)tCY – 20
(2.37 + 2n)tCY – 20
tRDL2
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tRDWT2
tWRWT
tCY – 100
tCY – 200
2tCY – 100
2tCY – 200
2tCY – 100
2tCY – 200
(2 + 2n)tCY
WAIT low-level width
Write data setup time
tWTL
tWDS
(1 + 2n)tCY
(2.4 + 2n)tCY – 60
(2.37 + 2n)tCY – 100
20
VDD = 2.7 to 6.0 V
Write data hold time
WR low-level width
tWDH
tWRL
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
(2.4 + 2n)tCY – 20
(2.37 + 2n)tCY – 20
0.4tCY – 30
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
tASTRD
tASTWR
0.37tCY – 50
1.4tCY – 30
1.37tCY – 50
Remarks 1. MCS: Bit 0 of the oscillation mode selection register (OSMS)
2. PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
3. tCY = TCY/4
4. n indicates the number of waits.
Data Sheet U12327EJ5V0DS00
47
µPD78052, 78053, 78054, 78055, 78056, 78058
(b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
Delay time from RD↑ to ASTB↑ at
tRDAST
tCY – 10
tCY + 20
external fetch
Address hold time from RD↑ at
tRDADH
tRDWD
tCY – 50
tCY + 50
ns
external fetch
Write data output time from RD↑
Write data output time from WR↓
Address hold time from WR↑
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
0.4tCY – 20
0.37tCY – 40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWRWD
tWRADH
tWTRD
60
0
120
tCY
tCY + 60
tCY
tCY + 120
0.6tCY + 180
0.63tCY + 350
0.6tCY + 120
0.63tCY + 240
2.6tCY + 180
2.63tCY + 350
2.6tCY + 120
2.63tCY + 240
tWTWR
Remarks 1. MCS: Bit 0 of the oscillation mode selection register (OSMS)
2. PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
3. tCY = TCY/4
4. n indicates the number of waits.
48
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
(3) Serial interface (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY1
2.7 V ≤ VDD < 4.5 V
1600
3200
SCK0 high-/low-level
width
tKH1,
tKL1
VDD = 4.5 to 6.0 V
tKCY1/2 – 50
tKCY1/2 – 100
100
SI0 setup time (to
tSIK1
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
SCK0↑)
150
300
SI0 hold time (from
tKSI1
400
SCK0↑)
SO0 output delay time tKSO1
C = 100 pFNote
300
ns
from SCK0↓
Note C is the load capacitance of the SO0 output line.
(ii) 3-wire serial I/O mode (SCK0 ... External clock input)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY2
2.7 V ≤ VDD < 4.5 V
1600
3200
400
SCK0 high-/low-level
width
tKH2,
tKL2
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
800
1600
100
SI0 setup time
tSIK2
(to SCK0↑)
SI0 hold time
tKSI2
400
ns
ns
ns
ns
(from SCK0↑)
Delay time from
tKSO2
C = 100 pFNote
300
160
SCK0↓ to SO0 output
SCK0 rise, fall time
tR2, tF2
When using external device
expansion function
When not using external device
expansion function
1000
Note C is the load capacitance of the SO0 output line.
Data Sheet U12327EJ5V0DS00
49
µPD78052, 78053, 78054, 78055, 78056, 78058
(iii) SBI mode (SCK0 ... Internal clock output)
Parameter
Symbol
Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY3
3200
SCK0 high-/low-level
width
tKH3,
tKL3
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
tKCY3/2 – 50
tKCY3/2 – 150
100
SB0, SB1 setup time
tSIK3
(to SCK0↑)
300
SB0, SB1 hold time
tKSI3
tKCY3/2
(from SCK0↑)
Delay time from SCK0↓
tKSO3
R = 1 kΩ,
C = 100 pFNote
VDD = 4.5 to 6.0 V
0
250
ns
ns
ns
ns
ns
to SB0, SB1 output
0
1000
SB0, SB1↓ from SCK0↑ tKSB
SCK0↓ from SB0, SB1↓ tSBK
tKCY3
tKCY3
tKCY3
SB0, SB1 high-level
width
tSBH
SB0, SB1 low-level
width
tSBL
tKCY3
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(iv) SBI mode (SCK0 ... External clock input)
Parameter
Symbol
Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY4
3200
400
SCK0 high-/low-level
width
tKH4,
tKL4
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
1600
100
SB0, SB1 setup time
tSIK4
(to SCK0↑)
300
SB0, SB1 hold time
tKSI4
tKCY4/2
(from SCK0↑)
Delay time from SCK0↓
tKSO4
R = 1 kΩ,
C = 100 pFNote
VDD = 4.5 to 6.0 V
0
300
ns
ns
ns
ns
ns
to SB0, SB1 output
0
1000
SB0, SB1↓ from SCK0↑ tKSB
SCK0↓ from SB0, SB1↓ tSBK
tKCY4
tKCY4
tKCY4
SB0, SB1 high-level
width
tSBH
SB0, SB1 low-level
width
tSBL
tKCY4
ns
ns
ns
SCK0 rise, fall time
tR4, tF4
When using external device
expansion function
160
When not using external device
expansion function
1000
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
50
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
(v) 2-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter
Symbol
Conditions
MIN.
1600
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY5
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 4.5 to 6.0 V
3200
SCK0 high-level width tKH5
tKCY5/2 – 160
tKCY5/2 – 190
tKCY5/2 – 50
tKCY5/2 – 100
300
SCK0 low-level width
tKL5
SB0, SB1 setup time
tSIK5
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
(to SCK0↑)
350
400
SB0, SB1 hold time
tKSI5
600
(from SCK0↑)
Delay time from SCK0↓ tKSO5
0
300
ns
to SB0, SB1 output
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(vi) 2-wire serial I/O mode (SCK0 ... Internal clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 6.0 V
MIN.
1600
3200
650
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY6
SCK0 high-level width tKH6
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
1300
800
SCK0 low-level width
tKL6
1600
100
SB0, SB1 setup time
tSIK6
tKSI6
(to SCK0↑)
SB0, SB1 hold time
tKCY6/2
ns
(from SCK0↑)
Delay time from SCK0↓ tKSO6
R = 1 kΩ,
C = 100 pFNote
VDD = 4.5 to 6.0 V
0
0
300
500
160
ns
ns
ns
to SB0, SB1 output
SCK0 rise, fall time
tR6, tF6
When using external device
expansion function
When not using external device
expansion function
1000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
Data Sheet U12327EJ5V0DS00
51
µPD78052, 78053, 78054, 78055, 78056, 78058
(b) Serial interface channel 1
(i) 3-wire serial I/O mode (SCK1 ... Internal clock output)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
tKCY7
2.7 V ≤ VDD < 4.5 V
1600
3200
SCK1 high-/low-level
width
tKH7,
tKL7
VDD = 4.5 to 6.0 V
tKCY7/2 – 50
tKCY7/2 – 100
100
SI1 setup time
tSIK7
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
(to SCK1↑)
150
300
SI1 hold time
tKSI7
400
(from SCK1↑)
Delay time from SCK1↓ tKSO7
C = 100 pFNote
300
ns
to SO1 output
Note C is the load capacitance of the SO1 output line.
(ii) 3-wire serial I/O mode (SCK1 ... External clock input)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
tKCY8
2.7 V ≤ VDD < 4.5 V
1600
3200
400
SCK1 high-/low-level
width
tKH8,
tKL8
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
800
1600
100
SI1 setup time
tSIK8
tKSI8
(to SCK1↑)
SI1 hold time
400
ns
ns
ns
ns
(from SCK1↑)
Delay time from SCK1↓ tKSO8
C = 100 pFNote
300
160
to SO1 output
SCK1 rise, fall time
tR8, tF8
When using external device
expansion function
When not using external device
expansion function
1000
Note C is the load capacitance of the SO1 output line.
52
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... Internal clock output)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
tKCY9
2.7 V ≤ VDD < 4.5 V
1600
3200
SCK1 high-/low-level
width
tKH9,
tKL9
VDD = 4.5 to 6.0 V
tKCY9/2 – 50
tKCY9/2 – 100
100
SI1 setup time
tSIK9
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
(to SCK1↑)
150
300
SI1 hold time
tKSI9
400
(from SCK1↑)
SO1 output delay time tKSO9
C = 100 pFNote
300
ns
from SCK1↓
STB↑ from SCK1↑
tSBD
tSBW
tKCY9/2 – 100
tKCY9 – 30
tKCY9 – 60
100
tKCY9/2 + 100
tKCY9 + 30
ns
ns
ns
ns
Strobe signal
VDD = 2.7 to 6.0 V
high-level width
tKCY9 + 60
Busy signal setup time tBYS
(to busy signal
detection timing)
Busy signal hold time
(from busy signal
detection timing)
tBYH
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
100
150
200
ns
ns
ns
ns
SCK1↓ from busy
tSPS
2tKCY9
inactive
Note C is the load capacitance of the SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... External clock input)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
tKCY10
2.7 V ≤ VDD < 4.5 V
1600
3200
400
SCK1 high-/low-level
width
tKH10,
tKL10
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
800
1600
100
SI1 setup time
tSIK10
tKSI10
(to SCK1↑)
SI1 hold time
400
ns
ns
ns
ns
(from SCK1↑)
Delay time from SCK1↓ tKSO10
C = 100 pFNote
300
160
to SO1 output
SCK1 rise, fall time
tR10, tF10 When using external device
expansion function
When not using external device
expansion function
1000
Note C is the load capacitance of the SO1 output line.
Data Sheet U12327EJ5V0DS00
53
µPD78052, 78053, 78054, 78055, 78056, 78058
(c) Serial interface channel 2
(i) 3-wire serial I/O mode (SCK2 ... Internal clock output)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK2 cycle time
tKCY11
2.7 V ≤ VDD < 4.5 V
1600
3200
SCK2 high-/low-level
width
tKH11,
tKL11
VDD = 4.5 to 6.0 V
tKCY7/2 – 50
tKCY7/2 – 100
100
SI2 setup time
tSIK11
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
(to SCK2↑)
150
300
SI2 hold time
tKSI11
400
(from SCK2↑)
Delay time from SCK2↓ tKSO11
C = 100 pFNote
300
ns
to SO2 output
Note C is the load capacitance of the SO2 output line.
(ii) 3-wire serial I/O mode (SCK2 ... External clock input)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
SCK2 cycle time
tKCY12
2.7 V ≤ VDD < 4.5 V
1600
3200
400
ns
ns
ns
ns
ns
ns
SCK2 high-/low-level
width
tKH12,
tKL12
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
800
1600
100
SI2 setup time
tSIK12
tKS1I2
(to SCK2↑)
SI2 hold time
400
ns
ns
ns
ns
(from SCK2↑)
Note
Delay time from SCK2↓ tKSO12
C = 100 pF
300
160
to SO2 output
SCK2 rise, fall time
tR12,
tF12
When using external device
expansion function
When not using external
device expansion function
1000
Note C is the load capacitance of the SO2 output line.
54
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
MIN.
TYP.
MAX.
78125
39063
19531
Unit
bps
bps
bps
(iv) UART mode (External clock input)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK cycle time
tKCY13
2.7 V ≤ VDD < 4.5 V
1600
3200
400
ns
ns
ASCK high-/low-level
width
tKH13,
tKL13
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
ns
800
ns
1600
ns
Transfer rate
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
39063
19531
9766
bps
bps
bps
ns
ASCK rise, fall time
tR13,
tF13
VDD = 4.5 to 6.0 V,
1000
when not using external
device expansion function.
160
ns
Data Sheet U12327EJ5V0DS00
55
µPD78052, 78053, 78054, 78055, 78056, 78058
AC Timing Measurement Points (Excluding X1, XT1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Point of measurement
Clock Timing
1/fX
t
XL
t
XH
V
IH4 (MIN.)
IL4 (MAX.)
X1 Input
V
1/fXT
t
XTL
t
XTH
V
IH5 (MIN.)
IL5 (MAX.)
XT1 Input
V
TI Timing
1/fTI
t
TIL
t
TIH
TI00, TI01,
TI1, TI2
56
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
Lower 8-bit
address
t
ADD1
Hi-z
Operation
code
AD0 to AD7
t
RDADH
t
ADS
t
RDD1
t
ADH
t
ASTH
t
RDAST
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
Lower 8-bit
address
t
ADD1
Hi-z
Operation
code
AD0 to AD7
t
RDD1
t
RDADH
t
ADS
t
ADH
t
ASTH
t
RDAST
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
WAIT
t
WTRD
t
WTL
t
RDWT1
Data Sheet U12327EJ5V0DS00
57
µPD78052, 78053, 78054, 78055, 78056, 78058
External data access (no wait):
A8 to A15
Higher 8-bit address
Lower
8-bit
address
t
ADD2
Hi-z
Hi-z
Hi-z
AD0 to AD7
Read data
Write data
t
RDD2
t
ADS
t
ADH
t
RDH
t
ASTH
ASTB
RD
t
ASTRD
t
WDH
t
RDWD
t
RDL2
t
WDS
t
WRWD
WR
t
ASTWR
t
WRL
t
WRADH
External data access (wait insertion):
A8 to A15
Lower
Higher 8-bit address
8-bit
tADD2
address
Hi-z
Hi-z
Hi-z
AD0 to AD7
Read data
Write data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
tASTRD
RD
tWDH
tRDWD
tRDL2
tWDS
tWRWD
WR
tASTWR
tWRL
tWRADH
WAIT
tRDWT2
tWTRD
tWTL
tWRWT
tWTL
tWTWR
58
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
t
Fn
t
Rn
SCK0 to SCK2
t
SIKm
t
KSIm
SI0 to SI2
Input data
t
KSOm
SO0 to SO2
Output data
m = 1, 2, 7, 8, 11, 12
n = 2, 8, 12
SBI mode (bus release signal transfer):
t
KCY3, 4
t
KL3, 4
t
KH3, 4
t
F4
t
R4
SCK0
t
KSB
t
SBL
t
SBK
t
SIK3, 4
t
KSI3, 4
t
SBH
SB0, SB1
t
KSO3, 4
SBI mode (command signal transfer):
tKCY3,4
tKL3, 4
tR4
t
KH3, 4
tF4
SCK0
tSIK3, 4
tSBK
tKSI3, 4
tKSB
SB0, SB1
tKSO3, 4
Data Sheet U12327EJ5V0DS00
59
µPD78052, 78053, 78054, 78055, 78056, 78058
2-wire serial I/O mode:
t
KCY5, 6
t
KL5, 6
t
KH5, 6
t
F6
t
R6
SCK0
t
SIK5, 6
t
KSI5, 6
t
KSO5, 6
SB0, SB1
3-wire serial I/O mode with automatic transmit/receive function:
SO1
SI1
D2
D1
D0
D7
D2
D1
D0
D7
t
SIK9, 10
t
KSI9, 10
t
KH9, 10
t
KSO9, 10
tF10
SCK1
STB
t
R10
t
SBD
t
SBW
t
KL9, 10
t
KCY9, 10
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9Note
10Note
10+nNote
1
t
BYS
t
BYH
t
SPS
BUSY
(Active high)
Note The signal is not actually driven low here; it is shown as such to indicate the timing.
60
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
UART mode (external clock input):
KCY13
t
t
KL13
tKH13
t
R13
t
F13
ASCK
A/D Converter Characteristics (TA = –40 to +85°C, AVDD = VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
bit
%
Overall errorNote
2.7 V ≤ AVREF0 ≤ AVDD
2.0 V ≤ AVREF0 < 2.7 V
±0.6
±1.4
200
%
Conversion time
Sampling time
tCONV
19.1
12/fXX
AVSS
2.0
µs
µs
V
tSAMP
Analog input voltage
Reference voltage
VIAN
AVREF0
AVDD
AVREF0
RAIREF0
V
Resistance between
AVREF0 and AVSS
4
14
kΩ
Note Excludes quantization error (±1/2 LSB). This value is indicated as a ratio to the full-scale value.
Remark fXX: Main system clock frequency (fX or fX/2)
fX: Main system clock oscillation frequency
D/A Converter Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
TYP.
MAX.
8
Unit
bit
%
Note 1
Note 1
Note 1
Overall error
R = 2 MΩ
R = 4 MΩ
1.2
0.8
0.6
10
%
R = 10 MΩ
%
Note 1
Settling time
C = 30 pF
4.5 V ≤ AVREF1 ≤ 6.0 V
2.7 V ≤ AVREF1 < 4.5 V
µs
µs
µs
kΩ
V
15
2.0 V ≤ AVREF1 < 2.7 V
20
Note 2
Output resistance
RO
DACS0, DACS1 = 55H
10
8
Analog reference voltage AVREF1
2.0
4
VDD
Note 2
Resistance between
AVREF1 and AVSS
RAIREF1
DACS0, DACS1 = 55H
kΩ
Notes 1. R and C are the D/A converter output pin load resistance and load capacitance, respectively.
2. Value for one D/A converter channel
Remark DACS0 and DACS1: D/A conversion value setting registers 0 and 1
Data Sheet U12327EJ5V0DS00
61
µPD78052, 78053, 78054, 78055, 78056, 78058
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
6.0
Unit
V
Data retention power
supply voltage
VDDDR
Data retention power
supply current
IDDDR
VDDDR = 1.8 V
0.1
10
µA
When the subsystem clock is unused (XT1 = VDD)
and the feed-back resistor is disconnected
Release signal set time
tSREL
tWAIT
0
µs
ms
ms
Oscillation stabilization
wait time
Release by RESET
217/fX
Release by interrupt request
Note
Note Selection of 212/fXX and 214/fXX to 217/fXX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time selection register (OSTS).
Remark fXX: Main system clock frequency (fX or fX/2)
fX: Main system clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retension mode
V
DD
VDDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
Operating mode
STOP mode
Data retension mode
V
DD
VDDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
62
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Interrupt Request Input Timing
t
INTL
t
INTH
INTP0 to INTP6
RESET Input Timing
t
RSL
RESET
Data Sheet U12327EJ5V0DS00
63
µPD78052, 78053, 78054, 78055, 78056, 78058
12. CHARACTERISTICS CURVES (REFERENCE VALUES)
IDD vs. VDD (fX = fXX = 5.0 MHz)
(TA = 25°C)
10.0
5.0
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT
(X1 oscillating, XT1 oscillating)
1.0
0.5
0.1
PCC = B0H
0.05
HALT (X1 stopped, XT1 oscillating)
0.01
0.005
0.001
0
2
3
4
5
6
7
8
9
Supply voltage VDD (V)
64
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
I
DD vs. VDD (f
X
= 5.0 MHz, fXX = 2.5 MHz)
(TA = 25°C)
10.0
5.0
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT
(X1 oscillating, XT1 oscillating)
1.0
0.5
0.1
PCC = B0H
0.05
HALT (X1 stopped, XT1 oscillating)
0.01
0.005
0.001
0
2
3
4
5
6
7
8
9
Supply voltage VDD (V)
Data Sheet U12327EJ5V0DS00
65
µPD78052, 78053, 78054, 78055, 78056, 78058
13. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
M
G
P
H
I
K
L
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
17.20±0.20
14.00±0.20
0.677±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
D
14.00±0.20
17.20±0.20
–0.008
0.677±0.008
F
0.825
0.825
0.032
0.032
G
+0.002
0.013
H
0.32±0.06
–0.003
I
0.13
0.005
J
K
0.65 (T.P.)
1.60±0.20
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.80±0.20
–0.008
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.10
0.004
1.40±0.10
0.125±0.075
0.055±0.004
0.005±0.003
+7°
3°
+7°
3°
R
S
–3°
–3°
1.70 MAX.
0.067 MAX.
P80GC-65-8BT
Remark Dimensions and materials of ES product are the same as those of mass-production products.
66
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
80 PIN PLASTIC TQFP (FINE PITCH) (12x12)
A
B
60
41
61
40
detail of lead end
S
C
D
Q
R
80
21
1
20
F
P
M
G
H
I
J
K
M
S
N
S
L
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
14.00±0.20
12.00±0.20
12.00±0.20
14.00±0.20
1.25
G
1.25
+0.05
0.22
H
–0.04
I
0.10
J
0.50 (T.P.)
1.00±0.20
0.50±0.20
K
L
+0.055
0.145
M
–0.045
N
P
Q
R
S
0.10
1.05±0.07
0.10±0.05
5°±5°
1.27 MAX.
P80GK-50-BE9-6
Remark Dimensions and materials of ES product are the same as those of mass-production products.
Data Sheet U12327EJ5V0DS00
67
µPD78052, 78053, 78054, 78055, 78056, 78058
14. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales represen-
tative.
Table 14-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD78052GC-×××-8BT: 80-pin plastic QFP (14 × 14 mm)
µPD78053GC-×××-8BT: 80-pin plastic QFP (14 × 14 mm)
µPD78054GC-×××-8BT: 80-pin plastic QFP (14 × 14 mm)
µPD78055GC-×××-8BT: 80-pin plastic QFP (14 × 14 mm)
µPD78056GC-×××-8BT: 80-pin plastic QFP (14 × 14 mm)
µPD78058GC-×××-8BT: 80-pin plastic QFP (14 × 14 mm)
Soldering
Method
Recommended
Soldering Conditions
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), IR35-00-2
Count: Twice max.
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), VP15-00-2
Count: Twice max.
Wave soldering
Partial Heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
—
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
68
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Table 14-1. Surface Mounting Type Soldering Conditions (2/2)
(2) µPD78052GK-×××-BE9: 80-pin plastic TQFP (12 × 12 mm)
µPD78053GK-×××-BE9: 80-pin plastic TQFP (12 × 12 mm)
µPD78054GK-×××-BE9: 80-pin plastic TQFP (12 × 12 mm)
µPD78055GK-×××-BE9: 80-pin plastic TQFP (12 × 12 mm)
µPD78056GK-×××-BE9: 80-pin plastic TQFP (12 × 12 mm)
µPD78058GK-×××-BE9: 80-pin plastic TQFP (12 × 12 mm)
Soldering
Recommended
Soldering Conditions
Method
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Three times max., Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 hours)
Infrared reflow
IR35-107-3
VP15-107-3
—
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times max., Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 hours)
VPS
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Partial Heating
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U12327EJ5V0DS00
69
µPD78052, 78053, 78054, 78055, 78056, 78058
APPENDIX A. DEVELOPMENT TOOLS
The following support tools are available for system development using the µPD78054 Subseries.
Refer to (5) Cautions on Using Development Tools.
(1) Language Processing Software
RA78K/0
CC78K/0
DF78054
CC78K/0-L
Assembler package common to 78K/0 Series
C compiler package common to 78K/0 Series
µPD78054 Subseries device file
C compiler library source file common to 78K/0 Series
(2) PROM Writing Tools
PG-1500
PROM programmer
PA-78P054GC
PA-78P054GK
PA-78P054KK-T
Programmer adapter connected to a PG-1500
PG-1500 controller
PG-1500 control program
(3) Debugging Tools
• When using in-circuit emulator IE-78K0-NS
IE-78K0-NS
IE-70000-MC-PS-B
In-circuit emulator common to 78K/0 Series
Power supply unit for IE-78K0-NS
IE-78K0-NS-PANote
IE-70000-98-IF-C
Performance board to enhance and expand the functions of IE-78K0-NS
Interface adapter when using PC-9800 series PC (except notebook type) as the host machine (C
bus supported)
IE-70000-CD-IF-A
PC card and interface cable when using notebook type PC as the host machine (PCMCIA socket
supported)
IE-70000-PC-IF-C
IE-70000-PCI-IF
Interface adapter when using IBM PC/AT™ or compatible as the host machine
Adapter necessary when using PC including PCI bus as the host machine
Emulation board common to µPD780308 Subseries
IE-780308-NS-EM1
NP-80GC
Emulation probe for 80-pin plastic QFP (GC-8BT type)
NP-80GC-TQ
NP-80GK
Emulation probe for 80-pin plastic TQFP (GK-BE9 type)
EV-9200GC-80
Conversion socket to connect the NP-80GC and a target system board on which an 80-pin plastic
QFP (GC-8BT type) can be mounted
TGC-080SBP
TGK-080SDW
Conversion socket to connect the NP-80GC-TQ and a target system board on which an 80-pin
plastic QFP (GC-8BT type) can be mounted
Conversion adapter to connect the NP-80GK and a target system board on which an 80-pin plastic
TQFP (GK-BE9 type) can be mounted
ID78K0-NS
SM78K0
Integrated debugger for IE-78K0-NS
System simulator common to 78K/0 Series
Device file for µPD78054 Subseries
DF78054
Note Under development
70
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
IE-70000-98-IF-C
In-circuit emulator common to 78K/0 Series
Interface adapter when using PC-9800 series PC (except notebook type) as the host machine (C
bus supported)
IE-70000-PC-IF-C
IE-70000-PCI-IF
IE-78000-R-SV3
Interface adapter when using IBM PC/AT or compatible as the host machine (ISA bus supported)
Adapter necessary when using PC including PCI bus as the host machine
Interface adapter and cable when using EWS as the host machine
Emulation board common to µPD780308 Subseries
IE-780308-NS-EM1
IE-780308-R-EM
IE-78K0-R-EX1
EP-78230GC-R
EP-78054GK-R
EV-9200GC-80
Emulation probe conversion board necessary when using IE-780308-NS-EM1 on IE-78001-R-A
Emulation probe for 80-pin plastic QFP (GC-8BT type)
Emulation probe for 80-pin plastic TQFP (GK-BE9 type)
Conversion socket to connect the EP-78230GC-R and a target system board on which an 80-pin
plastic QFP (GC-8BT type) can be mounted
TGK-080SDW
Conversion adapter to connect the EP-78054GK-R and a target system board on which an 80-pin
plastic TQFP (GK-BE9 type) can be mounted
ID78K0
Integrated debugger for IE-78001-R-A
System simulator common to 78K/0 Series
Device file for µPD78054 Subseries
SM78K0
DF78054
(4) Real-Time OS
RX78K/0
MX78K0
Real-time OS for 78K/0 Series
OS for 78K/0 Series
Data Sheet U12327EJ5V0DS00
71
µPD78052, 78053, 78054, 78055, 78056, 78058
(5) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF78054.
• The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and DF78054.
• The NP-80GC, NP-80GC-TQ, and NP-80GK are products of Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-
822-3813). Consult an NEC sales representative regarding purchase of these products.
• The TGK-080SDW and TGC-080SBP are products of TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo Ltd. Tokyo Electronics Department (TEL+81-3-3820-7112)
Osaka Electronic Department (TEL+81-6-6244-6672)
• For third party development tools, refer to 78K/0 Series Selection Guide (U11126E).
• The host machines and operating systems suitable for each software are as follows.
Host Machine
[OS]
PC
EWS
PC-9800 series [Windows™]
IBM PC/AT compatibles
HP9000 series 700™ [HP-UX™]
SPARCstation™ [SunOS™, Solaris™]
NEWS™ (RISC) [NEWS-OS™]
Software
RA78K/0
CC78K/0
[Japanese/English Windows]
Note
√
√
√
Note
√
Note
PG-1500 controller
ID78K0-NS
ID78K0
√
—
—
√
√
√
√
SM78K0
—
√
Note
RX78K/0
√
Note
MX78K0
√
√
Note DOS-based software
72
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Name
Document No.
(English)
Document No.
(Japanese)
µPD78054, 78054Y Subseries User’s Manual
µPD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet
µPD78P054, 78P058 Data Sheet
U11747E
This document
U10417E
U12326E
—
U11747J
U12327J
U10417J
U12326J
U10904J
U10903J
U10102J
U10182J
U13482J
78K/0 Series User’s Manual Instructions
78K/0 Series Instruction Set
78K/0 Series Instruction Table
—
µPD78054 Subseries Special Function Register Table
—
78K/0 Series Application Note
Basic (III)
U10182E
Floating Point Arithmetic Programs IEA-1289
Documents Related to Development Tools (User’s Manuals)
Document Name
Document No.
(English)
Document No.
(Japanese)
RA78K0 Assembler Package
Operation
U11802E
U11802J
Assembly Language
Structured Assembly Language
U11801E
U11801J
U11789E
U11789J
RA78K Series Structured Assembler Preprocessor
CC78K0 C Compiler
EEU-1402
U11517E
U12323J
Operation
U11517J
Language
U11518E
U11518J
CC78K0 C Compiler Application Note
PG-1500 PROM Programmer
Programming Know-how
U13034E
U13034J
U11940E
U11940J
PG-1500 Controller PC-9800 Series (MS-DOS™) based
EEU-1291
U10540E
EEU-704
PG-1500 Controller IBM PC Series (PC DOS™) based
EEU-5008
To be prepared
To be prepared
To be prepared
U11362J
IE-78K0-NS
To be prepared
To be prepared
To be prepared
U11362E
IE-78001-R-EM
IE-780308-NS-EM1
IE-780308-R-EM
EP-78230
EEU-1515
EEU-1468
U10181E
EEU-985
EP-78054GK-R
EEU-932
SM78K0 System Simulator Windows based
SM78K Series System Simulator
Reference
U10181J
External Part User Open
Interface Specifications
U10092E
U10092J
ID78K0-NS Integrated Debugger Windows based
ID78K0 Integrated Debugger EWS based
ID78K0 Integrated Debugger PC based
Reference
Reference
Reference
Guide
U12900E
—
U12900J
U11151J
U11539J
U11649J
U11539E
U11649E
ID78K0 Integrated Debugger Windows based
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Data Sheet U12327EJ5V0DS00
73
µPD78052, 78053, 78054, 78055, 78056, 78058
Documents Related to Embedded Software (User’s Manuals)
Document Name
Document No.
(English)
Document No.
(Japanese)
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
Other Related Documents
Basics
U11537E
U11536E
U12257E
U11537J
U11536J
U12257J
Installation
Basics
Document Name
Document No.
(English)
Document No.
(Japanese)
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
Semiconductor Device Mounting Technology Manual
X13769X
C10535E
C11531E
C10983E
C11892E
—
C10535J
C11531J
C10983J
C11892J
U11416J
Quality Grades on NEC Semiconductor Devices
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Microcomputer Product Series Guide
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
74
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
[MEMO]
Data Sheet U12327EJ5V0DS00
75
µPD78052, 78053, 78054, 78055, 78056, 78058
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
76
Data Sheet U12327EJ5V0DS00
µPD78052, 78053, 78054, 78055, 78056, 78058
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
NEC Electronics (Germany) GmbH
Scandinavia Office
Tel: 02-66 75 41
Fax: 02-2719-5951
Taeby, Sweden
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U12327EJ5V0DS00
77
µPD78052, 78053, 78054, 78055, 78056, 78058
FIP and IEBus are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation
in the United States and/or other countries.
PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8
相关型号：
UPD78053YGC-XXX-8BT
8-BIT, MROM, 5MHz, MICROCONTROLLER, PQFP80, 14 X 14 MM, PLASTIC, LQFP-80
RENESAS
UPD78053YGC-XXX-8BT
Microcontroller, 8-Bit, MROM, 5MHz, MOS, PQFP80, 14 X 14 MM, PLASTIC, LQFP-80
NEC
UPD78054GC-XXX-3B9
Microcontroller, 8-Bit, MROM, 5MHz, CMOS, PQFP80, 14 X 14 MM, 2.70 MM HEIGHT, PLASTIC, QFP-80
NEC
©2020 ICPDF网 联系我们和版权申明