UPD789167GB-XXX-8ES [NEC]

Microcontroller, 8-Bit, MROM, 10MHz, MOS, PQFP44, 10 X 10 MM, PLASTIC, LQFP-44;

UPD789167GB-XXX-8ES


型号：	UPD789167GB-XXX-8ES
厂家：	NEC
描述：	Microcontroller, 8-Bit, MROM, 10MHz, MOS, PQFP44, 10 X 10 MM, PLASTIC, LQFP-44 控制器微控制器微控制器和处理器
文件：	总68页 (文件大小：847K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

MOS INTEGRATED CIRCUITS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),

176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

8-BIT SINGLE-CHIP MICROCONTROLLERS

The µPD789166, 789167, 789176, and 789177 (hereafter, represented as µPD78916x and µPD78917x) are

µPD789167, 789177 Subseries (small, general-purpose) in the 78K/0S Series. The µPD789166Y, 789167Y,

789176Y, and 789177Y (hereafter, represented as µPD78916xY and µPD78917xY) are µPD789167Y, 789177Y

Subseries (small, general-purpose) in the 78K/0S Series.

A stricter quality assurance program (called special grade in NEC’s grade classification) is applied to the

µPD789166(A), 789167(A), 789176(A), 789177(A) (hereafter, represented as µPD78916x(A) and µPD78917x(A)),

and µPD789166Y(A), 789167Y(A), 789176Y(A), 789177Y(A) (hereafter, represented as µPD78916xY(A) and

µPD78917xY(A)), compared to the µPD78916x, 78917x, 78916xY, and 78917xY, which are classified as standard

grade.

In addition, a flash memory version (µPD78F9177, 78F9177Y) that can operate within the same power supply

voltage range as the mask ROM version, and a range of development tools are also being prepared.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

µPD789167, 789177, 789167Y, 789177Y Subseries User’s Manual: U14186E

78K/0S Series User's Manual Instruction: U11047E

FEATURES

• ROM and RAM sizes

Item

Data Memory

(Internal High-Speed RAM)

Program Memory (ROM)

16 Kbytes

Part Number

µPD789166, 789176, 789166Y, 789176Y,

512 bytes

789166(A), 789176(A), 789166Y(A), 789176Y(A)

µPD789167, 789177, 789167Y, 789177Y,

24 Kbytes

789167(A), 789177(A), 789167Y(A), 789177Y(A)

• Minimum instruction execution time can be changed • Serial interface: 2 channels

from high-speed (0.2 µs @10.0-MHZ operation with • 3-wire serial I/O mode / UART mode: 1 channel

main system clock, V^DD= 4.5 to 5.5 V) to ultra-low- • SMB(µPD78916xY, 78917xY, 78916xY(A), and

speed (122 µs

@

32.768-kHz operation with

78917xY(A) only): 1 channel

• Timers: 6 channels

subsystem clock)

• 8-bit resolution A/D converter: 8 channels

(µPD78916x, 78916xY, 78916x(A), 78916xY(A))

• 10-bit resolution A/D converter: 8 channels

(µPD78917x, 78917xY, 78917x(A), 78917xY(A))

• On chip 16-bit multiplier

• 16-bit timer: 1 channel

• 8-bit timer/event counter: 2 channels

• 8-bit timer: 1 channel

• Watchdog timer: 1 channel

• Watch timer: 1 channel

• I/O ports: 31

• Power supply voltage: V^DD= 1.8 to 5.5 V

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. U14017EJ3V0DS00 (3rd edition)

Date Published April 2002 N CP(K)

Printed in Japan

The mark

shows major revised points.

2000

©

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

APPLICATIONS

Power windows, keyless entry, battery management unit, side air bags, etc

ORDERING INFORMATION

(1) µPD78916x, 78917x, 78916x(A), 78917x(A)

Part Number

Package

Quality grade

Standard

44-pin plastic LQFP (10 × 10 mm)

µPD789166GB-×××-8ES

µPD789167GB-×××-8ES

µPD789176GB-×××-8ES

µPD789177GB-×××-8ES

µPD789166GB(A)-×××-8ES

µPD789167GB(A)-×××-8ES

µPD789176GB(A)-×××-8ES

µPD789177GB(A)-×××-8ES

44-pin plastic LQFP (10 × 10 mm)

44-pin plastic LQFP (10 × 10 mm)

44-pin plastic LQFP (10 × 10 mm)

44-pin plastic LQFP (10 × 10 mm)

44-pin plastic LQFP (10 × 10 mm)

44-pin plastic LQFP (10 × 10 mm)

44-pin plastic LQFP (10 × 10 mm)

Standard

Standard

Standard

Special

Special

Special

Special

Remark ××× indicates ROM code suffix.

(2) µPD78916xY, 78917xY, 78916xY(A), 78917xY(A)

Part Number

Package

Quality grade

Standard

44-pin plastic LQFP (10 × 10 mm)

µPD789166YGB-×××-8ES

µPD789166YGA-×××-9EU

µPD789167YGB-×××-8ES

µPD789167YGA-×××-9EU

µPD789176YGB-×××-8ES

µPD789176YGA-×××-9EU

µPD789177YGB-×××-8ES

µPD789177YGA-×××-9EU

µPD789166YGA(A)-×××-9EU

µPD789167YGA(A)-×××-9EU

µPD789176YGA(A)-×××-9EU

µPD789177YGA(A)-×××-9EU

48-pin plastic TQFP (fine pitch) (7 × 7 mm)

44-pin plastic LQFP (10 × 10 mm)

Standard

Standard

Standard

Standard

Standard

Standard

Standard

Special

48-pin plastic TQFP (fine pitch) (7 × 7 mm)

44-pin plastic LQFP (10 × 10 mm)

48-pin plastic TQFP (fine pitch) (7 × 7 mm)

44-pin plastic LQFP (10 × 10 mm)

48-pin plastic TQFP (fine pitch) (7 × 7 mm)

48-pin plastic TQFP (fine pitch) (7 × 7 mm)

48-pin plastic TQFP (fine pitch) (7 × 7 mm)

48-pin plastic TQFP (fine pitch) (7 × 7 mm)

48-pin plastic TQFP (fine pitch) (7 × 7 mm)

Special

Special

Special

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

2

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

78K/0S SERIES LINEUP

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products in mass production

Products under development

Y Subseries products support SMB.

Small-scale package, general-purpose applications

µ

µ

µ

µ

PD789074 with added subsystem clock

44-pin

µ

µ

µ

µ

µ

µ

µ

PD789046

PD789026

PD789088

PD789074

PD789014

PD789062

PD789052

42/44-pin

30-pin

30-pin

28-pin

20-pin

20-pin

PD789014 with enhanced timer and increased ROM and RAM capacity

PD789074 with enhanced timer and increased ROM and RAM capacity

PD789026 with enhanced timer

On-chip UART and capable of low voltage (1.8 V) operation

RC oscillation version of PD789026 with enhanced timer

µ

µ

PD789060 without EEPROM^TM, POC, and LVI

Small-scale package, general-purpose applications and A/D converter

µ

µ

µ

µ

µ

PD789167 with enhanced A/D converter (10 bits)

PD789104A with enhanced timer

µ

PD789177

µ

µ

PD789177Y

PD789167Y

44-pin

44-pin

30-pin

30-pin

30-pin

30-pin

30-pin

30-pin

µ

µ

µ

µ

µ

µ

µ

PD789167

PD789156

PD789146

PD789134A

PD789124A

PD789114A

PD789104A

PD789146 with enhanced A/D converter (10 bits)

PD789104A with added EEPROM

PD789124A with enhanced A/D converter (10 bits)

RC oscillation version of the

µ

PD789104A

PD789104A with enhanced A/D converter (10 bits)

PD789026 with added A/D converter and multiplier

µ

µ

LCD drive

144-pin

88-pin

80-pin

µ

µ

PD789835

PD789830

UART, 8-bit A/D converter, and dot LCD (Display output total: 96)

UART and dot LCD (40 × 16)

SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4)

SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)

µ

µ

µ

µ

µ

µ

µ

µ

PD789488

PD789478

PD789417A

PD789407A

PD789456

PD789446

PD789436

PD789426

PD789316

PD789306

PD789467

80-pin

80-pin

µ

PD789407A with enhanced A/D converter (10 bits)

78K/0S

Series

SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)

80-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

52-pin

52-pin

µ

PD789446 with enhanced A/D converter (10 bits)

SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (15 × 4)

µ

PD789426 with enhanced A/D converter (10 bits)

SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (5 × 4)

µ

µ

µ

µ

RC oscillation version of the PD789306

SIO and on-chip voltage booster type LCD (24 × 4)

8-bit A/D converter and on-chip voltage booster type LCD (23 × 4)

SIO and resistance division type LCD (24 × 4)

µ

PD789327

USB

64-pin

44-pin

µ

µ

For PC keyboard, on-chip USB HUB function

For PC keyboard, on-chip USB function

PD789803

PD789800

Inverter control

µ

44-pin

30-pin

PD789842

On-chip inverter controller and UART

On-chip CAN controller

On-chip bus controller

µ

PD789850

Keyless entry

30-pin

20-pin

20-pin

PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity

µ

PD789862

PD789861

PD789860

µ

µ

µ

µ

RC oscillation version of the PD789860

On-chip POC and key return circuit

VFD drive

PD789871

On-chip VFD controller (display output total: 25)

52-pin

64-pin

µ

Meter control

PD789881

µ

UART and resistance division type LCD (26 × 4)

Remark VFD (Vacuum Fluorescent Display) is referred to as FIP^TM(Fluorescent Indicator Panel) in some

documents, but the functions of the two are the same.

3

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

The major differences between subseries are shown below.

Series for LCD drive, general-purpose applications

ROM

Capacity

Timer

8-Bit 10-Bit

Serial

Interface

I/O V^DD

Remarks

Function

Subseries Name

A/D

A/D

8-Bit 16-Bit Watch WDT

MIN.

Value

Small-scale µPD789046

16 KB

1 ch

3 ch

1 ch

1 ch

1 ch

−

−

1 ch (UART: 34 1.8 V

1 ch)

−

package,

µPD789026

4KB to16KB

−

general-

purpose

µPD789088

16 KB to

32 KB

24

applications

µPD789074

2KB to8KB 1 ch

2KB to4KB 2 ch

4 KB

µPD789014

µPD789062

−

22

−

14

RC oscillation

version

µPD789052

−

−

Small-scale µPD789177

16 KB to

24 KB

3 ch

1 ch

1 ch

1 ch

1 ch

−

8 ch

−

8 ch 1 ch (UART: 31 1.8 V

package,

general-

purpose

applications

and A/D

1 ch)

µPD789167

−

µPD789156

8 KB to

16 KB

−

4 ch

−

20

On-chip

EEPROM

µPD789146

4 ch

−

µPD789134A 2 KB to

4 ch

−

RC oscillation

version

converter

8 KB

µPD789124A

4 ch

−

µPD789114A

µPD789104A

4 ch

−

−

4 ch

LCD drive µPD789835

24 KB to

60 KB

6 ch

–

1 ch

1 ch 3 ch

–

1 ch (UART: 37 1.8 V Dot LCD

Note

1 ch)

supported

µPD789830

µPD789488

µPD789478

24 KB

32 KB

1 ch

3 ch

1 ch

–

30 2.7 V

8 ch 2 ch (UART: 45 1.8 V

−

1 ch)

24 KB to

32 KB

8 ch

−

µPD789417A 12 KB to

−

7 ch

−

7 ch 1 ch (UART: 43

24 KB

1 ch)

µPD789407A

−

µPD789456

µPD789446

µPD789436

µPD789426

µPD789316

12 KB to

16 KB

2 ch

6 ch

–

30

40

6 ch

–

6 ch

–

6 ch

–

8 KB to

16 KB

2 ch (UART: 23

1 ch)

RC oscillation

version

µPD789306

µPD789467

µPD789327

–

4 KB to

24 KB

–

1 ch

–

–

18

21

1 ch

Note Flash memory version: 3.0 V

4

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Series for ASSP

Subseries Name

Function

ROM

Capacity

Timer

8-Bit 10-Bit

Serial

Interface

I/O V^DD

Remarks

A/D

A/D

8-Bit 16-Bit Watch WDT

MIN.

Value

USB

µPD789803

µPD789800

2 ch

–

−

1 ch

–

–

2 ch

(USB: 1 ch)

41 3.6 V

31 4.0 V

−

8 KB to 16 KB

8 KB

Inverter

control

µPD789842

8 KB to

16 KB

3 ch Note 1 1 ch

1 ch 8 ch

1 ch 4 ch

−

−

1 ch (UART: 30 4.0 V

1 ch)

−

−

On-chip

bus

controller

µPD789850

16 KB

1 ch

2 ch

1 ch

−

−

2 ch (UART: 18 4.0 V

1 ch)

Keyless

entry

µPD789861

4 KB

−

1 ch

−

−

–

14 1.8 V RC oscillation

version,

on-chip

EEPROM

µPD789860

µPD789862

On-chip

EEPROM

1 ch

2 ch

1 ch (UART: 22

1 ch)

16 KB

VFD drive µPD789871

3 ch

2 ch

–

1 ch

–

1 ch

1 ch

–

–

–

–

1 ch

33 2.7 V

–

–

4 KB to 8 KB

16 KB

Meter

µPD789881

1 ch

1 ch (UART: 28 2.7 V

1 ch)

Note 2

control

Notes 1. 10-bit timer: 1 channel

2. Flash memory version: 3.0 V

5

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

OVERVIEW OF FUNCTIONS

Item

µPD789166,789176

µPD789167,789177

µPD789166Y,789176Y

µPD789166(A),789176(A)

µPD789166Y(A), 789176Y(A)

µPD789167Y,789177Y

µPD789167(A),789177(A)

µPD789167Y(A), 789177Y(A)

Internal memory

ROM

High-speed RAM

16 KB

512 bytes

24 KB

Minimum instruction execution time

•

•

0.2/0.8 µ s (@ 10.0-MHz operation with main system clock, V^DD= 4.5 to 5.5 V)

122 µ s (@ 32.768-kHz operation with subsystem clock)

General-purpose registers

Instruction set

8 bits × 8 registers

•

•

16-bit operations

Bit manipulations (set, reset, and test)

8 bits × 8 bits = 16 bits

Multiplier

I/O ports

Total:

31

•

•

•

CMOS input:

8

CMOS I/O:

17

6

N-ch open-drain (12-V withstand voltage):

A/D converters

Serial interfaces

•

•

8-bit resolution × 8 channels (µPD78916x, 78916xY, 78916x(A), 78916xY(A))

10-bit resolution × 8 channels (µPD78917x, 78917xY, 78917x(A), 78917xY(A))

•

•

3-wire serial I/O / UART: 1 channel

SMB: 1 channel (µPD78916xY, 78917xY, 78916xY(A), 78917xY(A))

•

•

•

•

16-bit timer: 1 channel

Timers

8-bit timer/event counter: 2 channels

8-bit timer: 1 channel

Watchdog timer: 1 channel

•

Watch timer: 1 channel

Timer output

4 output (16-bit/8-bit timer alternate function: 1)

Vectored interrupt

sources

Maskable

Internal: 10, External: 4 (µPD78916x, 78917x, 78916x(A), 78917x(A))

Internal: 12, External: 4 (µPD78916xY, 78917xY, 78916xY(A), 78917xY(A))

Non-maskable

Internal: 1

Power supply voltage

V^DD= 1.8 to 5.5 V

T^A= –40 to +85°C

Operating ambient temperature

Package

•

•

44-pin plastic LQFP (10 × 10 mm)

48-pin plastic TQFP (fine pitch) (7 × 7 mm)

(µPD78916xY, 78917xY, 78916xY(A), 78917xY(A) only)

6

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) .............................................................................................8

2. BLOCK DIAGRAM ..........................................................................................................................11

3. PIN FUNCTIONS.............................................................................................................................12

3.1 Port Pins................................................................................................................................................ 12

3.2 Non-Port Pins........................................................................................................................................ 13

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.................................................... 14

4. MEMORY SPACE ...........................................................................................................................16

5. PERIPHERAL HARDWARE FUNCTIONS.....................................................................................17

5.1 Ports ...................................................................................................................................................... 17

5.2 Clock Generator.................................................................................................................................... 18

5.3 Timer...................................................................................................................................................... 18

5.4 A/D Converter ....................................................................................................................................... 22

5.5 Serial Interface...................................................................................................................................... 23

5.6 Multiplier ............................................................................................................................................... 26

6. INTERRUPT FUNCTION.................................................................................................................27

7. STANDBY FUNCTION....................................................................................................................29

8. RESET FUNCTION ..........................................................................................................................29

9. MASK OPTION.................................................................................................................................29

10. INSTRUCTION SET OVERVIEW...................................................................................................30

10.1 Conventions.......................................................................................................................................... 30

10.1.1 Operand identifiers and description methods ........................................................................... 30

10.1.2 Descriptions of operation fields................................................................................................. 31

10.1.3 Description of flag operation fields............................................................................................ 31

10.2 Operations............................................................................................................................................. 32

11. ELECTRICAL SPECIFICATIONS....................................................................................................37

12. CHARACTERISTICS CURVES........................................................................................................54

13. PACKAGE DRAWING......................................................................................................................57

14. RECOMMENDED SOLDERING CONDITIONS...............................................................................59

APPENDIX A. DEVELOPMENT TOOLS..............................................................................................61

APPENDIX B. RELATED DOCUMENTS .............................................................................................63

7

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

1. PIN CONFIGURATION (TOP VIEW)

• 44-pin plastic LQFP (10 × 10 mm)

µPD789166GB-×××-8ES

µPD789167GB-×××-8ES

µPD789176GB-×××-8ES

µPD789177GB-×××-8ES

µPD789166YGB-×××-8ES

µPD789167YGB-×××-8ES

µPD789176YGB-×××-8ES

µPD789177YGB-×××-8ES

µPD789166GB(A)-×××-8ES

µPD789167GB(A)-×××-8ES

µPD789176GB(A)-×××-8ES

µPD789177GB(A)-×××-8ES

44 43 42 41 40 39 38 37 36 35 34

P60/ANI0

P61/ANI1

P62/ANI2

P63/ANI3

P64/ANI4

P65/ANI5

P66/ANI6

P67/ANI7

AV^SS

P01

1

33

P00

2

32

31

30

29

28

27

26

25

24

23

P26/TO80

P25/TI80/SS20

3

4

V

V

DD0

5

SS0

6

X1

7

X2

8

RESET

XT1

XT2

9

P10

10

11

P11

12 13 14 15 16 17 18 19 20 21 22

Note The SCL0 and SDA0 pins are available in µPD78916xY and 78917xY products only.

Cautions 1. Connect the IC0 (Internally Connected) pin directly to V^SS0or V^SS1.

2. Connect the AV^DDpin to V^DD0.

3. Connect the AV^SSpin to V^SS0.

8

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

• 48-pin plastic TQFP (fine pitch) (7 × 7 mm)

µPD789166YGA-×××-9EU

µPD789167YGA-×××-9EU

µPD789176YGA-×××-9EU

µPD789177YGA-×××-9EU

µPD789166YGA(A)-×××-9EU

µPD789167YGA(A)-×××-9EU

µPD789176YGA(A)-×××-9EU

µPD789177YGA(A)-×××-9EU

48 47 46 45 44 43 42 41 40 39 38 37

1

2

3

4

5

6

7

8

9

P60/ANI0

P61/ANI1

P62/ANI2

P63/ANI3

P64/ANI4

P65/ANI5

P66/ANI6

P67/ANI7

AV^SS

36

35

34

33

32

31

30

29

28

27

26

25

P01

P00

P26/TO80

P25/Tl80/SS20

V

DD0

IC2

VSS0

X1

X2

RESET

XT1

XT2

10

11

12

P10

P11

IC2

13 14 15 16 17 18 19 20 21 22 23 24

Cautions 1. Connect the IC0 (Internally Connected) pin directly to V^SS0or V^SS1.

2. Leave the IC2 pin open.

3. Connect the AV^DDpin to V^DD0.

4. Connect the AV^SSpin to V^SS0.

9

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

ANI0 to ANI7:

ASCK20:

AV^DD:

Analog input

RESET:

RxD20:

SCK20:

SCL0^Note

Reset

Asynchronous serial input

Analog power supply

Analog reference voltage

Analog ground

Receive data

Serial clock (for SIO20)

Serial clock (for SMB0)

Serial data

:

AV^REF:

SDA0^Note

:

AV^SS:

BZO90:

CPT90:

IC0, IC2^Note

Buzzer output

SI20:

Serial input

Capture trigger input

Internally connected

SO20:

SS20:

Serial output

:

Chip select input

Timer input

INTP0 to INTP3: Interrupt from peripherals

TI80, TI81:

P00 to P05:

P10, P11:

Port 0

Port 1

Port 2

Port 3

Port 5

Port 6

TO80 to TO82, TO90: Timer output

TxD20:

Transmit data

P20 to P26:

P30 to P33:

P50 to P53:

P60 to P67:

V^DD0, V^DD1:

V^SS0, V^SS1:

X1, X2:

Power supply

Ground

Crystal (main system clock)

Crystal (subsystem clock)

XT1, XT2:

Note The IC2, SCL0, and SDA0 pins are available in µPD78916xY, 78917xY, 78916xY(A), and 78917xY(A)

products only.

10

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

2. BLOCK DIAGRAM

TI80/SS20/P25

TO80/P26

8-BIT TIMER/

EVENT COUNTER80

P00 to P05

P10, P11

PORT0

PORT1

PORT2

PORT3

PORT5

PORT6

TI81/INTP0/CPT90/P30

TO81/INTP1/P31

8-BIT TIMER/

EVENT COUNTER81

TO82/INTP3/BZO90/P33

8-BIT TIMER82

16-BIT TIMER90

P20 to P26

P30 to P33

P50 to P53

P60 to P67

CPT90/INTP0/TI81/P30

TO90/INTP2/P32

BZO90/INTP3/TO82/P33

78K/0S

CPU CORE

WATCH TIMER

ROM

WATCHDOG TIMER

RESET

X1

SCK20/ASCK20/P20

SO20/T^XD20/P21

SI20/RXD20/P22

SS20/TI80/P25

SIO20

SYSTEM

CONTROL

X2

RAM

XT1

XT2

SCL0/P23

SDA0/P24

SMB^{Note 1}

INTP0/TI81/CPT90/P30

INTP1/TO81/P31

INTERRUPT

CONTROL

ANI0/P60-

ANI7/P67

INTP2/TO90/P32

A/D

CONVERTER

INTP3/TO82/BZO90/P33

AV^DD

AVSS

AVREF

MULTIPLIER

VDD0

VDD1

VSS0

VSS1

IC0

IC2^{Note 2}

Notes 1. SMB is available in µPD78916xY, 78917xY, 78916xY(A), and 78917xY(A) products only.

2. The IC2 pin is available in µPD78916xY, 78917xY, 78916xY(A), and 78917xY(A) products only.

Remark The internal ROM capacity varies depending on the product.

11

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

3. PIN FUNCTIONS

3.1 Port Pins

Pin Name

I/O

I/O

Function

After Reset

Input

Alternate Function

P00 to P05

Port 0

−

6-bit input/output port

Input/output mode can be specified in 1-bit units

When used as an input port, an on-chip pull-up resistor can

be used by setting software.

P10, P11

I/O

I/O

Port 1

Input

Input

−

2-bit input/output port

Input/output mode can be specified in 1-bit units

When used as an input port, an on-chip pull-up resistor can

be used by setting software.

P20

Port 2

SCK20/ASCK20

SO20/TxD20

SI20/RxD20

7-bit input/output port

P21

Input/output mode can be specified in 1-bit units

For P20 to P22, P25, and P26, an on-chip pull-up resistor

can be used by setting software.

Only P23 and P24 can be used as N-ch open-drain

input/output port pins.

P22

Note

SCL0

P23

Note

SDA0

P24

P25

TI80/SS20

TO80

P26

P30

I/O

Port 3

Input

INTP0/TI81/CPT90

INTP1/TO81

INTP2/TO90

INTP3/TO82/BZO90

−

4-bit input/output port

P31

Input/output mode can be specified in 1-bit units

An on-chip pull-up resistor can be used by setting software.

P32

P33

P50 to P53

I/O

Port 5

Input

Input

4-bit N-ch open-drain input/output port

Input/output mode can be specified in 1-bit units

An on-chip pull-up resistor can be specified by the mask

option.

P60 to P67

Input

Port 6

ANI0 to ANI7

8-bit input-only port

Note µPD78916xY, 78917xY, 78916xY(A), and 78917xY(A) only

12

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

3.2 Non-Port Pins

Pin Name

INTP0

INTP1

INTP2

INTP3

SI20

I/O

Function

After Reset

Input

Alternate Function

P30/TI81/CPT90

P31/TO81

Input

External interrupt input for which the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified

P32/TO90

P33/TO82/BZO90

P22/RxD20

P21/TxD20

P20/ASCK20

P25/TI80

Input

Output

I/O

Serial data input to serial interface

Serial data output from serial interface

Serial clock input/output for serial interface

Chip select input to serial interface

Serial clock input for asynchronous serial interface

Serial data input for asynchronous serial interface

Serial data output for asynchronous serial interface

SMB0 clock input/output

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

SO20

SCK20

SS20

Input

ASCK20

RxD20

TxD20

SCL0^Note

SDA0^Note

TI80

Input

Input

Output

I/O

P20/SCK20

P22/SI20

P21/SO20

P23

I/O

SMB0 data input/output

P24

Input

Input

Output

Output

Output

Output

Output

Input

Input

External count clock input to 8-bit timer/event counter (TM80)

External count clock input to 8-bit timer/event counter (TM81)

8-bit timer/event counter (TM80) output

8-bit timer/event counter (TM81) output

8-bit timer (TM82) output

P25/SS20

TI81

P30/INTP0/CPT90

P26

TO80

TO81

P31/INTP1

P33/INTP3/BZO90

P32/INTP2

P33/INTP3/TO82

P30/INTP0/TI81

P60 to P67

TO82

TO90

16-bit timer (TM90) output

BZO90

CPT90

16-bit timer Buzzer output

Capture edge input

ANI0 to

ANI7

A/D converter analog input

AV^REF

AV^SS

AV^DD

X1

−

A/D converter reference voltage

A/D converter ground potential

A/D converter analog power supply

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

Input

Connecting crystal resonator for main system clock

oscillation

−

X2

−

−

XT1

XT2

V^DD0

V^DD1

V^SS0

V^SS1

RESET

IC0

Input

Connecting crystal resonator for subsystem clock oscillation

−

−

−

−

Positive power supply

−

−

−

Positive power supply (other than ports)

Ground potential

−

−

−

Ground potential (other than ports)

System reset input

−

Input

−

Input

−

Internally connected. Connect this pin directly to the V^SS0or

V^SS1pin.

IC2^Note

−

Internally connected. Leave this pin open.

−

−

Note µ PD78916xY, 78917xY, 78916xY(A), 78917xY(A) only.

13

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins is shown in Table 3-1.

For the input/output circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Types of Pin Input/Output Circuits

Pin Name

I/O Circuit Type

5-H

I/O

I/O

Recommended Connection of Unused Pins

P00 to P05

P10, P11

Input:

Independently connects to V^DD0, V^DD1, V^SS0, or V^SS1

via a resistor.

Output: Leave open.

P20/SCK20/ASCK20

P21/SO20/TxD20

P22/SI20/RxD20

P23/SCL0^Note

8-C

13-X

8-C

Input:

Independently connects to VDD0 or VDD1 via a

resistor.

Output: Leave open.

P24/SDA0^Note

P25/TI80/SS20

P26/TO80

Input: Independently connects to VDD0, VDD1, VSS0, or VSS1

via a resistor.

Output: Leave open.

Input: Independently connects to VSS0 or VSS1 via a

resistor.

Output: Leave open.

P30/INTP0/TI81/CPT90

P31/INTP1/TO81

P32/INTP2/TO90

P33/INTP3/TO82/BZO90

P50 to P53

13-U

Input:

Independently connects to VDD0 or VDD1 via a

resistor.

Output: Leave open.

P60/ANI0 to P67/ANI7

9-C

Input

Connect directly to V^DD0, V^DD1, V^SS0, or V^SS1.

Connect directly to V^DD0, V^DD1, V^SS0, or V^SS1.

Connect directly to V^DD0or V^DD1.

Connect directly to V^SS0or V^SS1.

Connect to V^SS0or V^SS1.

Leave open.

AV^REF

AV^DD

AV^SS

XT1

−

−

Input

−

XT2

RESET

2

Input

−

−

IC0

−

Connect directly to V^SS0or V^SS1.

Leave open.

IC2^Note

Note The IC2, SCL0, and SDA0 pins are available in µPD78916xY, 78917xY, 78916xY(A), and 78917xY(A) products

only.

14

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Figure 3-1. Pin Input/Output Circuits

Type 2

Type 9-C

Comparator

P-ch

+

IN

N-ch

IN

−

AV^SS

VREF

(Threshold voltage)

Schmitt-triggered input with hysteresis characteristics

Input

enable

Type 13-U

Type 5-H

V

DD0

VDD0

Pull-up resistor

(mask option)

Pull-up

enable

P-ch

IN/OUT

VDD0

Output data

Output disable

N-ch

Data

P-ch

IN/OUT

VSS0

Output

disable

N-ch

Input enable

VSS0

Input buffer with intermediate withstand voltage

Input

enable

Type 13-X

Type 8-C

VDD0

Pull-up

enable

P-ch

IN/OUT

VDD0

Output data

N-ch

Output disable

Data

P-ch

VSS0

IN/OUT

Input buffer with 5-V

Output

disable

N-ch

withstand voltage

VSS0

Comparator

15

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

4. MEMORY SPACE

Products in the µ PD78916x, 78917x, 78916xY, 78917xY, 78916x(A), 78917x(A), 78916xY(A), and 78917xY(A)

can access up to 64 Kbytes of memory space.

Figure 4-1 shows the memory map.

Figure 4-1. Memory Map

F F F F H

Special function registers

256 × 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

512 × 8 bits

F D 0 0 H

F C F F H

Data memory space

n n n n H

Reserved

n n n n H + 1

n n n n H

Program area

0 0 8 0 H

0 0 7 F H

Program memory

space

Internal ROM^Note

CALLT table area

0 0 4 0 H

0 0 3 F H

Program area

0 0 2 4 H

0 0 2 3 H

Vector table area

0 0 0 0 H

0 0 0 0 H

Note The internal ROM capacity depends on the product. (See the following table.)

Last Address of Internal ROM

Part Number

nnnnH

µPD789166, 789176, 789166Y, 789176Y,

789166(A), 789176(A), 789166Y(A), 789176Y(A)

3FFFH

5FFFH

µPD789167, 789177, 789167Y, 789177Y,

789167(A), 789177(A), 789167Y(A), 789177Y(A)

16

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 Ports

The following three types of I/O ports are available:

• CMOS Input:

8

• CMOS input/output:

• N-ch open-drain input/output:

17

6

Total:

31

Table 5-1. Port Functions

Port Name

Port 0

Pin Name

Function

P00 to P05

Input/output port. Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be specified by means of software.

Port 1

Port 2

P10, P11

Input/output port. Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be specified by means of software.

P20 to P26

Input/output port. Input/output can be specified in 1-bit units.

For P20 to P22, P25, and P26, an on-chip pull-up resistor can be specified by means of

software.

(P23 and P24 are N-ch open-drain I/O ports (with 5-V withstand voltage).)

Port 3

Port 5

Port 6

P30 to P33

P50 to P53

P60 to P67

Input/output port. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by means of software.

N-channel open-drain input/output port. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by the mask option.

Input-only port

17

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

5.2 Clock Generator

An on-chip system clock generator is provided.

The minimum instruction execution time can be changed.

•

•

0.2 µs/0.8 µs (@ 10.0-MHz operation with Main system clock, V^DD= 4.5 to 5.5 V)

122 µs (@ 32.768-kHz operation with Subsystem clock)

Figure 5-1. Clock Generator Block Diagram

XT1

XT2

Subsystem

clock

oscillator

16-bit timer 90

8-bit timer/counter 82

Watch timer

Prescaler

Clock to

peripheral hardware

X1

X2

Main system

clock oscillator

1/2

Prescaler

fX

fX

2²

Standby

controller

Wait

controller

CPU clock

(f^CPU)

STOP

5.3 Timer

Six on-chip timers are provided.

•

•

•

•

•

16-bit timer 90 (TM90):

1 channel

8-bit timer/event counters 80, 81 (TM80, TM81): 2 channels

8-bit timer 82 (TM82):

Watch timer (WT):

1 channel

1 channel

1 channel

Watchdog timer (WDT):

Table 5-2. Timer Operation

TM90

TM80

1 channel

1 channel

1 output

1 output

1 output

–

TM81

1 channel

1 channel

1 output

1 output

1 output

–

TM82

WT

WTM

Operation mode Interval timer

External event counter

Timer output

–

1 channel

1 channel

1 channel

–

–

–

–

–

–

–

–

1

–

–

–

–

–

–

1

Function

1 output

1 output

Square wave output

PWM output

–

–

1 output

1 output

Buzzer output

Capture

1 output

1 input

1

–

–

1

–

–

Interrupt request

1

1

18

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Figure 5-2. Block Diagram of 16-Bit Timer

Internal bus

Output

controller

16-bit compare

register 90 (CR90)

TO90/INTP2

/P32

Match

INTTM90

f

X

/2²

/2⁶

fX

Output

controller

16-bit timer

counter 90 (TM90)

f

/2⁷

X

BZO90/INTP3

/TO82/P33

OVF

fXT

CPT90/INTP0

/TI81/P30

16-bit capture

register 90 (TCP90)

16-bit counter

read buffer

Edge

detector

Internal bus

Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter 80

Internal bus

8-bit compare

register 80 (CR80)

Match

INTTM80

fX

Output

OVF

TO80/P26

8-bit timer counter

80 (TM80)

controller

f

/2³

X

TI80/P25/

SS20

Clear

Internal bus

19

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter 81

Internal bus

8-bit compare register

81 (CR81)

Match

INTTM81

f

X

/2⁴

/2⁸

Output

controller

OVF

TO81/P31

/INTP1

8-bit timer counter

81 (TM81)

fX

TI81/CPT90/

P30/INTP0

Clear

Internal bus

Figure 5-5. Block Diagram of 8-Bit Timer 82

Internal bus

8-bit compare

register 82 (CR82)

Match

INTTM82

f

f

X

/2⁵

/2⁷

Output

controller

OVF

Clear

8-bit timer counter

82 (TM82)

TO82/BZO90

/P33/INTP3

X

f

XT

Internal bus

Figure 5-6. Block Diagram of Watch timer

Clear

f

X

/2⁷

5-bit counter

Clear

INTWT

9-bit prescaler

f

W

fW

f

W

fW

fW

f

W

f

W

2⁹

2⁴2⁵2⁶2⁷2⁸

f

XT

INTWTI

WTM0^Note

Note Bit 0 of the Watch timer mode control register (WTM)

20

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Figure 5-7. Watchdog Timer Block Diagram

f

X

2⁴

Prescaler

f

X

2⁶

f

X

2⁸

f

X

2¹⁰

RUN^Note

Clear

7-bit counter

INTWDT

Maskable

interrupt request

Controller

RESET

INTWDT

Non-maskable

interrupt request

Note Bit 7 of the Watchdog timer mode control register (WDTM)

21

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

5.4 A/D Converter

The conversion resolution of the A/D converter differs depending on the product as shown below.

•

•

8-bit A/D converter × 8 channels ....µPD78916x, 78916xY, 78916x(A), 78916xY(A)

10-bit A/D converter × 8 channels ..µPD78917x, 78917xY, 78917x(A), 78917xY(A)

A/D conversion can only be started by software.

Figure 5-8. A/D Converter Block Diagram

ANI0/P60

ANI1/P61

INTAD0

ANI2/P62

ANI3/P63

ANI4/P64

ANI5/P65

A/D conversion

result register 0

(ADCR0)

A/D converter

(8/10 bits)

Sample &

hold circuit

ANI6/P66

ANI7/P67

Internal bus

22

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

5.5 Serial Interface

Two serial interface channels are incorporated.

• Serial interface SIO20: 1 channel

• Serial interface SMB^Note: 1 channel

Note The SMB0 is available in µPD78916xY, 78917xY, 78916xY(A), and 78917xY(A) products only.

(1) Serial Interface SIO20

Serial interface 20 has the following three modes:

• Operation stop mode:

• Asynchronous serial interface (UART) mode: A dedicated baud rate generator is incorporated.

• 3-wire serial I/O mode: A function to select the clock phase or data phase is incorporated.

Power consumption can be reduced.

Figure 5-9. Block Diagram of Serial Interface 20

Internal bus

Transmit shift register

20 (TXS20/SIO20)

Receive buffer register

20 (RXB20/SIO20)

Receive shift register

Selector

SI20/P22/RXD20

Data

phase control

20 (RXS20)

SO20/P21/TXD20

Transmit

data counter

INTST20

Transmit

data counter

INTSR20/INTCSI20

SS20/P25

/TI80

Baud rate generator

ASCK20/P20

/SCK20

Clock

phase control

fX

/2-f

/2⁸

X

23

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

(2) Serial Interface SMB0

SMB0 has following two modes:

• Operation stop mode: Power consumption can be reduced.

• SMB mode:

Supporting multi-master.

Figure 5-10 shows the block diagram of Serial Interface SMB0.

24

Data Sheet U14017EJ3V0DS

Figure 5-10. Block Diagram of SMB0

Internal bus

µ

µ

SMB clock selection

register 0 (SMBCL0)

SMB control register 0 (SMBC0)

SCLCTL0

AWTIM0

CLD0 DAD0 SMC0 DFC0 CL01 CL00

WTIM0 ACKE0

SPIE0

SMBE0 LREL0 WREL0

STT0

SPT0

f

X

Serial clock

controller

Serial clock wait

controller

Prescaler

fX/2

SMB slave address register 0

(SMBSVA0)

CL00,

CL01

EXC0

N-ch open-drain output

INTSMB0

Data hold

time correc-

tion circuit

D

Q

SMB shift register 0 (SMB0)

+

-

Acknowledge

detector

Noise

eliminator

SCL0/

P23

Serial clock counter

+

-

Noise

eliminator

f

f

X

/2⁶

/2⁷

/2⁸

SDA0/

P24

Timeout count

&

controller

X

INTSMBOV0

Reference

generator

fX

Start condi-

tion detector

Stop condi-

tion detector

Acknowledge

detector

fXT

N-ch open-drain output

SCL

CTL0

ACKD0 STD0 SPD0

TOS02 TOS01 TOS00 SVIN0 LVL01 LVL00

MSTS0 ALD0 EXC0 COI0 TRC0

STIE0 TOEN0 TOCL01 TOCL00

SMB mode register 0 (SMBM0)

AWTIM0

SMB status register 0 (SMBS0)

SMB input level setting register 0 (SMBVI0)

Internal bus

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

5.6 Multiplier

The calculation of 8 bits × 8 bits = 16 bits can be performed.

Figure 5-11. Multiplier Block Diagram

Internal bus

Multiplication data

register A0

Multiplication data

register B0

(MRA0)

(MRB0)

Multiplier

16-bit multiplication result

storing register (MUL0)

Internal bus

26

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

6. INTERRUPT FUNCTION

A total of 17 interrupt sources are provided, divided into the following two types.

•

•

Non-maskable interrupts:

Maskable interrupts:

1 source

16 sources

Table 6-1. Interrupt Source List

Interrupt Source

Trigger

Vector

Table

Basic

Internal/

External

Interrupt Type Priority^{Note 1}

Configuration

Type^{Note 2}

Name

Address

Non-

−

INTWDT

Watchdog timer overflow

(with watchdog timer mode 1

selected)

Internal

0004H

(A)

(B)

(C)

maskable

Maskable

0

INTWDT

Watchdog timer overflow

(with the interval timer mode

selected)

1

2

3

4

5

INTP0

INTP1

INTP2

INTP3

INTSR20

Pin input edge detection

External

Internal

0006H

0008H

000AH

000CH

000EH

End of serial interface 20 UART

reception

(B)

INTCSI20

INTST20

End of serial interface 20 3-wire

SIO transfer reception

6

End of serial interface 20 UART

transmission

0010H

7

8

9

INTWT

Watch timer interrupt

Interval timer interrupt

0012H

0014H

0016H

INTWTI

INTTM80

Generation of matching signal of

8-bit timer/event counter 80

10

11

12

INTTM81

INTTM82

INTTM90

Generation of matching signal of

8-bit timer/event counter 81

0018H

001AH

001CH

Generation of matching signal of

8-bit timer 82

Generation of matching signal of

16-bit timer 90

13

14

15

INTSMB0^{Note 3}

INTSMBOV0^{Note 3}

INTAD0

SMB interrupt

001EH

0020H

0022H

SMB timeout interrupt

A/D conversion completion signal

Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time. 0

is the highest order and 15 is the lowest order.

2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 6-1.

3. µ PD78916xY, 78917xY, 78916xY(A), 78917xy(A) only.

Remark As the interrupt source of the watchdog timer (INTWDT), either a non-maskable interrupt or a maskable

interrupt (internal) can be selected.

27

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Figure 6-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Internal bus

Vector table address

generator

Interrupt request

Standby release signal

(B) Internal maskable interrupt

Internal bus

MK

IE

Vector table address

generator

IF

Interrupt request

Standby release signal

(C) External maskable interrupt

Internal bus

External interrupt mode

registers (INTM0, INTM1)

MK

IE

Vector table address

generator

Interrupt

Edge detector

request

IF

Standby release

signal

IF: Interrupt request flag

IE: Interrupt enable flag

MK: Interrupt mask flag

28

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

7. STANDBY FUNCTION

The following two standby functions are available for further reduction of system current consumption.

•

•

HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be

reduced by intermittent operation by combining this mode with the normal operation mode.

STOP mode: In this mode, oscillation of the system clock is stopped. All the operations performed on the

system clock are suspended, resulting in extremely small power consumption.

Figure 7-1. Standby Function

CSS0^{Note 1}= 1

Subsystem clock

operation^{Note 2}

Main system clock operation

STOP

CSS0^{Note 1}= 0

HALT instruction

HALT instruction

Interrupt

request

instruction

Interrupt

request

Interrupt

request

STOP mode

HALT mode

HALT mode

Clock supply for CPU

is stopped, oscillation

is maintained

Clock supply for CPU

is stopped, oscillation

is maintained

Main system clock

oscillation is stopped

Notes 1. Bit 4 of the sub-clock control register (CSS)

2. The current consumption can be reduced by stopping the main system clock.

When the CPU is operating on the subsystem clock, set bit 7 (MCC) of the processor clock control

register (PCC) to stop the main system clock. The STOP instruction cannot be used.

Caution When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

8. RESET FUNCTION

The following two reset methods are available.

(1) External reset by the RESET pin

(2) Internal reset by watchdog timer detection runaway time.

9. MASK OPTION

The µ PD78916x, 78917x, 78916xY, 78917xY, 78916x(A), 78917x(A) 78916xY(A), and 78917xY(A) have the

following mask options.

•P50 to P53 mask options

On-chip pull-up resistors can be selected.

<1>Specify on-chip pull-up resistors in bit units

<2>Do not specify on-chip pull-up resistors

29

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

10. INSTRUCTION SET OVERVIEW

This section lists the µPD78916x, 78917x, 78916xY, 78917xY, 78916x(A), 78917x(A) , 78916xY(A), and

78917xY(A) instruction set.

10.1 Conventions

10.1.1 Operand identifiers and description methods

Operands are described in the “Operand” column of each instruction in accordance with the description method of

the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more

description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords

and must be described as they are. Each symbol has the following meaning.

•

•

#: Immediate data specification

!: Absolute address specification

•

•

$:

Relative address specification

[ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to

describe the #,!, $, or [ ] symbols.

For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in

parentheses in the table below, R0, R1, R2, etc.) can be used for description.

Table 10-1. Operand Identifiers and Description Methods

Identifier

Description Method

r

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special function register symbol

rp

sfr

saddr

FE20H to FF1FH immediate data or label

saddrp

FE20H to FF1FH immediate data or label (even address only)

addr16

0000H to FFFFH immediate data or label

(Only even addresses for 16-bit data transfer instructions)

0040H to 007FH immediate data or label (even address only)

addr5

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

30

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

10.1.2 Descriptions of operation fields

A:

A register; 8-bit accumulator

X:

X register

B:

B register

C:

C register

D:

D register

E:

E register

H:

H register

L:

L register

AX:

BC:

DE:

HL:

PC:

SP:

PSW:

CY:

AC:

Z:

AX register pair; 16-bit accumulator

BC register pair

DE register pair

HL register pair

Program counter

Stack pointer

Program status word

Carry flag

Auxiliary carry flag

Zero flag

IE:

Interrupt request enable flag

NMIS:

( ):

X^H, X^L:

∧:

Non-maskable interrupt servicing flag

Memory contents indicated by address or register contents in parentheses

Higher 8 bits and lower 8 bits of 16-bit register

Logical product (AND)

∨:

Logical sum (OR)

∨:

Exclusive OR

:

Inverted data

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

10.1.3 Description of flag operation fields

(Blank): Not affected

0:

1:

×:

R:

Cleared to 0

Set to 1

Set/cleared according to the result

Previously saved value is restored

31

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

10.2 Operations

Flags

Mnemonic

Operand

Bytes

Clock

Operation

Z

AC CY

MOV

r. #byte

saddr, #byte

3

3

3

2

2

2

2

2

2

3

3

3

2

2

1

1

1

1

2

2

1

2

2

2

1

1

2

3

2

2

1

1

6

6

6

4

4

4

4

4

4

8

8

6

4

4

6

6

6

6

6

6

4

6

6

6

8

8

8

6

6

8

4

4

r ← byte

(saddr) ← byte

sfr ← byte

A ← r

sfr, #byte

A, r^{Note 1}

r, A^{Note 1}

A, saddr

saddr, A

A, sfr

r ← A

A ← (saddr)

(saddr) ← A

A ← sfr

sfr, A

sfr ← A

A, !addr16

!addr16, A

PSW, #byte

A, PSW

A ← (addr16)

(addr16) ← A

PSW ← byte

A ← PSW

PSW ← A

A ← (DE)

×

×

×

×

×

×

PSW, A

A, [DE]

[DE], A

(DE) ← A

A, [HL]

A ← (HL)

[HL], A

(HL) ← A

A, [HL + byte]

[HL + byte], A

A, X

A, r^{Note 2}

A, saddr

A, sfr

A ← (HL + byte)

(HL + byte) ← A

A ←→ X

XCH

A ←→ r

A ←→ (saddr)

A ←→ (sfr)

A ←→ (DE)

A ←→ (HL)

A ←→ (HL+byte)

rp ← word

AX ← (saddrp)

(saddrp) ← AX

AX ← rp

A, [DE]

A, [HL]

A, [HL + byte]

rp, #word

AX, saddrp

saddrp, AX

AX, rp^{Note 3}

rp, AX^{Note 3}

MOVW

rp ← AX

Notes 1. Except r = A

2. Except r = A, X

3. Only when rp = BC, DE, HL

Remark One clock of an instruction is one clock of the CPU clock (f^CPU) selected using the processor clock

control register (PCC).

32

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Flags

Mnemonic

Operand

AX, rp^Note

Bytes

Clock

Operation

Z

AC CY

XCHW

ADD

1

2

3

2

2

3

1

2

2

3

2

2

3

1

2

2

3

2

2

3

1

2

2

3

2

2

3

1

2

8

4

6

4

4

8

6

6

4

6

4

4

8

6

6

4

6

4

4

8

6

6

4

6

4

4

8

6

6

AX ←→ rp

A, #byte

saddr, #byte

A, r

A, CY ← A + byte

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

(saddr), CY ← (saddr) + byte

A, CY ← A + r

A, saddr

A, !addr16

A, [HL]

A, CY ← A + (saddr)

A, CY ← A + (addr16)

A, CY ← A + (HL)

A, [HL + byte]

A, #byte

saddr, #byte

A, r

A, CY ← A + (HL + byte)

A, CY ← A + byte + CY

(saddr), CY ← (saddr) + byte + CY

A, CY ← A + r + CY

ADDC

A, saddr

A, !addr16

A, [HL]

A, CY ← A+ (saddr) + CY

A, CY ← A+ (addr16) +CY

A, CY ← A + (HL) + CY

A, CY ← A+ (HL + byte) + CY

A, CY ← A – byte

A, [HL + byte]

A, #byte

saddr, #byte

A, r

SUB

(saddr), CY ← (saddr) – byte

A, CY ← A – r

A, saddr

A, !addr16

A, [HL]

A, CY ← A – (saddr)

A, CY ← A – (addr16)

A, CY ← A – (HL)

A, [HL + byte]

A, #byte

A, CY ← A – (HL + byte)

A, CY ← A – byte – CY

(saddr), CY ← (saddr) – byte – CY

A, CY ← A – r – CY

SUBC

saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, CY ← A – (saddr) – CY

A, CY ← A – (addr16) – CY

A, CY ← A – (HL) – CY

A, CY ← A – (HL + byte) – CY

A, [HL + byte]

Note Only when rp = BC, DE, HL

Remark One clock of an instruction is one clock of the CPU clock (f^CPU) selected using the processor clock

control register (PCC).

33

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Flags

Mnemonic

AND

Operand

A, #byte

Bytes

Clock

Operation

Z

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

AC CY

2

3

2

2

3

1

2

2

3

2

2

3

1

2

2

3

2

2

3

1

2

2

3

2

2

3

1

2

3

3

3

2

2

2

2

4

6

4

4

8

6

6

4

6

4

4

8

6

6

4

6

4

4

8

6

6

4

6

4

4

8

6

6

6

6

6

4

4

4

4

A ← A ∧ byte

saddr, #byte

A, r

(saddr) ← (saddr) ∧ byte

A ← A ∧ r

A, saddr

A, !addr16

A, [HL]

A ← A ∧ (saddr)

A ← A ∧ (addr16)

A ← A ∧ (HL)

A, [HL + byte]

A, #byte

saddr, #byte

A, r

A ← A ∧ (HL + byte)

A ← A ∨ byte

OR

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A, [HL + byte]

A, #byte

saddr, #byte

A, r

A ← A ∨ (HL + byte)

A ← A ∨ byte

XOR

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A, [HL + byte]

A, #byte

saddr, #byte

A, r

A ← A ∨ (HL + byte)

A – byte

CMP

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

(saddr) – byte

A – r

A, saddr

A, !addr16

A, [HL]

A – (saddr)

A – (addr16)

A – (HL)

A, [HL + byte]

AX, #word

AX, #word

AX, #word

r

A – (HL + byte)

AX, CY ← AX + word

AX, CY ← AX – word

AX – word

ADDW

SUBW

CMPW

INC

r ← r + 1

saddr

(saddr) ← (saddr) + 1

r ← r– 1

DEC

r

saddr

(saddr) ← (saddr) – 1

Remark One clock of an instruction is one clock of the CPU clock (f^CPU) selected using the processor clock

control register (PCC).

34

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Flags

Mnemonic

Operand

Bytes

Clock

Operation

Z

AC CY

INCW

DECW

ROR

rp

1

1

1

1

1

1

3

3

2

3

2

3

3

2

3

2

1

1

1

3

4

4

rp ← rp + 1

rp ← rp – 1

rp

A, 1

A, 1

A, 1

A, 1

2

(CY, A⁷← A⁰, A^m-1← A^m) × 1

(CY, A⁰← A⁷, A^m+1← A^m) × 1

(CY ← A⁰, A⁷← CY, A^m-1← A^m) × 1

(CY ← A⁷, A⁰← CY, A^m+1← A^m) × 1

(saddr.bit) ← 1

sfr.bit ← 1

×

×

×

×

ROL

2

RORC

ROLC

SET1

2

2

saddr.bit

sfr.bit

6

6

A.bit

4

A.bit ← 1

PSW.bit

[HL].bit

saddr.bit

sfr.bit

6

PSW.bit ← 1

×

×

×

×

×

10

6

(HL).bit ← 1

CLR1

(saddr.bit) ← 0

sfr.bit ← 0

6

A.bit

4

A.bit ← 0

PSW.bit

[HL].bit

CY

6

PSW.bit ← 0

×

10

2

(HL).bit ← 0

SET1

CLR1

NOT1

CALL

CY ← 1

1

0

×

CY

2

CY ← 0

CY

2

CY ← CY

!addr16

6

(SP – 1) ← (PC + 3)^H, (SP – 2) ← (PC + 3)^L,

PC ← addr16, SP ←SP – 2

CALLT

[addr5]

1

8

(SP – 1) ← (PC + 1)^H, (SP – 2) ← (PC + 1)^L,

PC^H← (00000000, addr5 + 1)

PC^L← (00000000, addr5)

SP ← SP – 2

RET

1

1

6

8

PC^H← (SP + 1), PC^L← (SP),

SP ← SP + 2

RETI

PC^H← (SP + 1), PC^L← (SP),

PSW ← (SP + 2), SP ← SP + 3,

NMIS ← 0

R

R

R

R

R

R

PUSH

POP

PSW

rp

1

1

2

4

(SP – 1) ← PSW, SP ← SP – 1

(SP – 1) ← rp^H, (SP – 2) ← rp^L,

SP ← SP -– 2

PSW

rp

1

1

4

6

PSW ← (SP), SP ← SP + 1

rp^H← (SP + 1), rp^L← (SP),

SP ← SP + 2

MOVW

SP, AX

AX, SP

2

2

8

6

SP ← AX

AX ← SP

Remark One clock of an instruction is one clock of the CPU clock (f^CPU) selected using the processor clock

control register (PCC).

35

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Flags

Mnemonic

Operand

Bytes

Clock

Operation

Z

AC CY

BR

!addr16

3

2

1

2

2

2

2

4

6

6

PC ← addr16

$addr16

PC ← PC + 2 + jdisp8

PC^H← A, PC^L← X

AX

6

BC

$addr16

6

PC ← PC + 2 + jdisp8 if CY = 1

PC ← PC + 2 + jdisp8 if CY = 0

PC ← PC + 2 + jdisp8 if Z = 1

PC ← PC + 2 + jdisp8 if Z = 0

BNC

BZ

$addr16

6

$addr16

6

BNZ

BT

$addr16

6

saddr.bit, $saddr16

10

PC ← PC + 4 + jdisp8

if (saddr. bit) = 1

sfr.bit, $addr16

A.bit, $saddr16

PSW.bit $addr16

saddr.bit, $addr16

4

3

4

4

10

8

PC ← PC + 4 + jdisp8 if sfr. bit = 1

PC ← PC + 3 + jdisp8 if A. bit = 1

PC ← PC + 4 + jdisp8 if PSW. bit = 1

10

10

BF

PC ← PC + 4 + jdisp8

if (saddr. bit) = 0

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

B, $addr16

4

3

4

2

10

8

PC ← PC + 4 + jdisp8 if sfr. bit = 0

PC ← PC + 3 + jdisp8 if A. bit = 0

PC ← PC + 4 + jdisp8 if PSW. bit = 0

10

6

DBNZ

B ← B – 1, then

PC ← PC + 2 + jdisp8 if B ≠ 0

C, $addr16

2

3

6

8

C ← C – 1, then

PC ← PC + 2 + jdisp8 if C ≠ 0

saddr, $addr16

(saddr) ← (saddr) – 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

NOP

EI

1

3

3

1

1

2

6

6

2

2

No Operation

IE ← 1 (Enable Interrupt)

IE ← 0 (Disable Interrupt)

Set HALT Mode

DI

HALT

STOP

Set Stop Mode

Remark One clock of an instruction is one clock of the CPU clock (f^CPU) selected using the processor clock

control register (PCC).

36

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

11. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T^A= 25°C)

Parameter

Supply voltage

Symbol

Conditions

Ratings

Unit

V

V^DD

AV^DD

AV^REF

V^I1

AV^DD− 0.3 V ≤ V^DD≤ AV^DD+ 0.3 V

AV^REF≤ AV^DD+ 0.3 V

−0.3 to +6.5

V

AV^REF≤ V^DD+ 0.3 V

V

Input voltage

Pins other than P50 to P53, P23, P24

P23, P24

−0.3 to V^DD+ 0.3

−0.3 to +5.5

−0.3 to +13

−0.3 to V^DD+ 0.3

−0.3 to V^DD+ 0.3

−10

V

V^I2

V

V^I3

P50 to P53

N-ch open drain

V

On-chip pull-up resistor

V

Output voltage

V^O

I^OH

V

Output current, high

Per pin

µ PD78916x, 78917x,

78916xY, 78917xY

mA

mA

mA

mA

Total for all pins

Per pin

−30

µ PD78916x(A),

78917x(A), 78916xY(A),

78917xY(A)

−7

Total for all pins

−22

Output current, low

I^OL

Per pin

µ PD78916x, 78917x,

78916xY, 78917xY

30

160

10

mA

mA

mA

mA

Total for all pins

Per pin

µ PD78916x(A),

78917x(A), 78916xY(A),

78917xY(A)

Total for all pins

120

Operating ambient temperature

Storage temperature

T^A

−40 to +85

°C

°C

T^stg

−65 to +150

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on

the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

37

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Main System Clock Oscillator Characteristics (T^A= −40 to +85°C, V^DD= 1.8 to 5.5 V)

Resonator

Recommended

Circuit

Parameter

Conditions

MIN. TYP. MAX. Unit

Ceramic

Oscillation frequency (f^X)^{Note 1}

V^DD= 4.5 to 5.5 V

V^DD= 3.0 to 5.5 V

V^DD= 1.8 to 5.5 V

1.0

1.0

1.0

10.0 MHz

resonator

V

SS0 X1

X2

6.0

5.0

4

MHz

MHz

ms

Oscillation stabilization time^{Note 2}

Oscillation frequency (f^X)^{Note 1}

After V^DDreaches

oscillation voltage

range MIN.

C1

C2

Crystal

V^DD= 4.5 to 5.5 V

V^DD= 3.0 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 4.5 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 4.5 to 5.5 V

V^DD= 3.0 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 4.5 to 5.5 V

V^DD= 3.0 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

1.0

1.0

1.0

10.0 MHz

V

SS0 X1

X2

resonator

6.0

5.0

10

MHz

MHz

ms

C1

C2

Oscillation stabilization time^{Note 2}

X1 input frequency (f^X)^{Note 1}

30

ms

External

clock

1.0

1.0

1.0

45

10.0 MHz

X2

X1

6.0

5.0

MHz

MHz

ns

X1 input high-/low-level width

(t^XH, t^XL)

500

500

500

5.0

75

ns

85

ns

X1 input frequency (f^X)^{Note 1}

1.0

MHz

X1

X2

X1 input high-/low-level width

(t^XH, t^XL)

V^DD= 2.7 to 5.5 V

85

500

ns

OPEN

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator that stabilizes

oscillation within the oscillation wait time.

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS0.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before

switching back to the main system clock.

Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

38

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Subsystem Clock Oscillator Characteristics (T^A= −40 to +85°C, V^DD= 1.8 to 5.5 V)

Resonator Recommended Circuit

Crystal

Parameter

Conditions

MIN. TYP. MAX. Unit

Oscillation frequency (f^XT)^{Note 1}

32

32.768

35

kHz

IC0XT1

XT2

resonator

R

Oscillation stabilization time^{Note 2}V^DD= 4.5 to 5.5 V

V^DD= 1.8 to 5.5 V

1.2

2

s

s

C4

C3

10

35

External

clock

XT1 input frequency (f^XT)^{Note 1}

32

kHz

XT2

XT1

XT1 input high-/low-level width

(t^XTH, t^XTL)

14.3

15.6

µs

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator that stabilizes

oscillation within the oscillation wait time.

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

•

•

•

•

•

•

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines.

Do not route the wiring near a signal line through which a high fluctuating current flows.

Always make the ground point of the oscillator capacitor the same potential as V^SS0.

Do not ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current

consumption, and is more prone to malfunction due to noise than the main system clock

oscillator. Particular care is therefore required with the wiring method when the subsystem

clock is used.

Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

39

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

DC Characteristics (T^A= −40°C to +85°C, V^DD= 1.8 to 5.5 V) (1/3)

Parameter

Symbol

I^OH

Conditions

MIN.

TYP.

MAX.

Unit

Per pin

Total for all pins

−1

−15

mA

mA

Output current,

µ PD78916x, 78917x, 78916xY,

78917xY

high

Per pin

Total for all pins

−1

−11

mA

mA

µ PD78916x(A), 78917x(A),

78916xY(A), 78917xY(A)

Output current, low

Input voltage, high

I^OL

Per pin

Total for all pins

10

80

mA

mA

µ PD78916x, 78917x, 78916xY,

78917xY

Per pin

Total for all pins

3

60

mA

mA

µ PD78916x(A), 78917x(A),

78916xY(A), 78917xY(A)

V^IH1

V^IH2

P00 to P05, P10, P11,

P60 to P67

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 4.5 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 4.5 to 5.5 V

V^DD= 1.8 to 5.5 V

0.7 V^DD

0.9 V^DD

0.7 V^DD

0.9 V^DD

0.7 V^DD

0.9 V^DD

0.8 V^DD

0.9 V^DD

V^DD

V^DD

12

12

V^DD

V^DD

V^DD

V^DD

V^DD

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

P50 to

P53

N-ch open

drain

On-chip pull-

up resistor

V^IH3

V^IH4

V^IL1

V^IL2

V^IL3

V^IL4

V^OH

RESET,

P20 to P26, P30 to P33

X1, X2, XT1, XT2

V^DD− 0.5

V^DD− 0.1

V^DD

Input voltage, low

P00 to P05, P10, P11,

P60 to P67

0

0

0

0

0

0

0

0

0.3 V^DD

0.1 V^DD

0.3 V^DD

0.1 V^DD

0.2 V^DD

0.1 V^DD

0.4

P50 to P53

RESET,

P20 to P26, P30 to P33

X1, X2, XT1, XT2

0.1

Output voltage,

high

Pins other

than P23,

P24, P50 to

P53

V^DD= 4.5 to 5.5 V, I^OH= −1 mA

V^DD− 1.0

V^DD= 1.8 to 5.5 V, I^OH= −100 µA

V^DD− 0.5

V

V

Output voltage,

low

V^OL1

Pins other

than P50 to

P53

V^DD= 4.5 to 5.5 V, I^OL= 10 mA

(µ PD78916x, 78917x, 78916xY,

78917xY)

V^DD= 4.5 to 5.5 V, I^OL= 3 mA

(µ PD78916x(A), 78917x(A),

78916xY(A), 78917xY(A))

1.0

1.0

V

V^DD= 1.8 to 5.5 V, I^OL= 400 µA

0.5

1.0

V

V

V^OL2

P50 to P53 V^DD= 4.5 to 5.5 V, I^OL= 10 mA

(µ PD78916x, 78917x, 78916xY,

78917xY)

V^DD= 4.5 to 5.5 V, I^OL= 3 mA

(µ PD78916x(A), 78917x(A),

78916xY(A), 78917xY(A))

1.0

0.4

V

V

V^DD= 1.8 to 5.5 V, I^OL= 1.6 mA

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

40

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

DC Characteristics (T^A= −40 to +85°C, V^DD= 1.8 to 5.5 V) (2/3)

Parameter

Symbol

I^LIH1

Conditions

MIN.

TYP.

MAX.

3

Unit

Input current

leakage, high

V^I= V^DD

Pins other than P50 to P53 (N-ch open-

drain) X1, X2, XT1, and XT2

µA

I^LIH2

I^LIH3

X1, X2, XT1, XT2

20

20

µA

µA

V^I= 12 V^{Note 1}P50 to P53

(N-ch open drain)

Input current

leakage, low

I^LIL1

V^I= 0 V

Pins other than P50 to P53 (N-ch open-

drain) X1, X2, XT1, and XT2

−3

µA

I^LIL2

I^LIL3

X1, X2, XT1, XT2

P50 to P53

(N-ch open drain)

−20

µA

µA

−3^{Note 2}

Output current

leakage, high

I^LOH

I^LOL

R¹

V^O= V^DD

V^O= 0 V

3

µA

µA

kΩ

kΩ

Output current

leakage, low

−3

Software pull-up

resistor

V^I= 0 V, for pins other than P23, P24, and P50 to

P53

50

15

100

30

200

60

Mask option pull-

up resistor

R²

V^I= 0 V, P50 to P53

Notes 1. When pull-up resistors are not connected to P50 to P53 (specified by the mask option).

2. A low-level input leakage current of −60 µA(MAX.) flows only during the 1-cycle time after a read

instruction is executed to P50 to P53 when on-chip pull-up resistors are not connected to P50 to P53

(specified by the mask option) and P50 to P53 are set to input mode. At times other than this, −3µA

(MAX.) current flows.

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

41

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

DC Characteristics (T^A= −40 to +85°C, V^DD= 1.8 to 5.5 V) (3/3)

Parameter

Symbol

Conditions

MIN.

TYP.

3.2

MAX.

8.0

Unit

mA

Note 1

Power supply

current

I^DD1

10.0-MHz crystal oscillation V^DD= 5.0 V 10%^{Note 4}

operating mode

6.0-MHz crystal oscillation

operating mode

V^DD= 5.0 V 10%^{Note 4}

2.0

4.7

mA

5.0-MHz crystal oscillation

operating mode

(C1 = C2 = 22pF)

V^DD= 5.0 V 10%^{Note 4}

V^DD= 3.0 V 10%^{Note 5}

V^DD= 2.0 V 10%^{Note 5}

1.8

0.6

4.0

1.2

0.7

3.0

mA

mA

mA

mA

0.35

1.5

Note 1

I^DD2

10.0-MHz crystal oscillation V^DD= 5.0 V 10%^{Note 4}

HALT mode

6.0-MHz Crystal oscillation V^DD= 5.0 V 10%^{Note 4}

HALT mode

0.9

1.8

mA

5.0-MHz crystal oscillation

HALT mode

(C1 = C2 = 22pF)

V^DD= 5.0 V 10%^{Note 4}

V^DD= 3.0 V 10%^{Note 5}

V^DD= 2.0 V 10%^{Note 5}

V^DD= 5.0 V 10%

0.75

0.4

0.25

25

1.5

0.8

0.5

90

mA

mA

mA

µA

Note 1

I^DD3

32.768-kHz crystal

oscillation operating

mode^{Note 3}

(C3 = C4 = 22pF,

R = 220kΩ)

7.0

3.5

50

µA

V^DD= 3.0 V 10%

30

µA

V^DD= 2.0 V 10%

Note 1

I^DD4

32.768-kHz crystal

oscillation HALT mode^{Note 3}

(C3 = C4 = 22pF,

R = 220kΩ)

16

4.5

2.3

75

35

18

µA

µA

µA

V^DD= 5.0 V 10%

V^DD= 3.0 V 10%

V^DD= 2.0 V 10%

Note 1

I^DD5

32.768-kHz crystal stop

STOP mode

0.1

0.05

0.05

4.0

10

5.0

µA

µA

µA

mA

V^DD= 5.0 V 10%

V^DD= 3.0 V 10%

3.0

V^DD= 2.0 V 10%

Note 2

Note 4

I^DD6

10.0-MHz crystal oscillation

A/D operating mode

V^DD= 5.0 V ± 10%

10.0

Note 4

6.0-MHz crystal oscillation

A/D operating mode

V^DD= 5.0 V ± 10%

2.8

6.7

mA

Note 4

Note 4

Note 4

5.0-MHz crystal oscillation

A/D operating mode

(C1 = C2 = 22pF)

V^DD= 5.0 V ± 10%

V^DD= 3.0 V ± 10%

V^DD= 2.0 V ± 10%

2.6

1.4

6.0

3.2

2.7

mA

mA

mA

1.15

Notes 1. The AV^REFON (ADCS0 (bit 7 of ADM0; A/D converter mode register 0) = 1), AV^DD, and the port current

(including the current flowing through the internal pull-up resistors) are not included.

2. The AV^REFOn (ADCS0 =1) and port current (including the current flowing through the internal pull-up

resistors) are not included. Refer to the A/D converter characteristics for the current flowing through

AV^REF.

3. When the main system clock is stopped.

4. During high-speed mode operation (when the processor clock control register (PCC) is set to 00H.)

5. During low-speed mode operation (when PCC is set to 02H)

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

42

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

AC Characteristics

(1) Basic operation (T^A= −40°C to +85°C, V^DD= 1.8 to 5.5 V)

Parameter

Cycle time

Symbol

T^CY

Conditions

Operation based on the

main system clock

MIN.

0.2

0.33

0.4

1.6

114

0

TYP.

MAX.

8

Unit

V^DD= 4.5 to 5.5 V

V^DD= 3.0 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

µs

µs

(minimum instruction

execution time)

8

8

µs

8

µs

Operation based on the subsystem clock

V^DD= 2.7 to 5.5 V

122

125

4

µs

MHz

kHz

TI80 and TI81 input

frequency

f^TI

V^DD= 1.8 to 5.5 V

0

275

TI80 and TI81 input

high-/low-level width

t^TIH, t^TIL

V^DD= 2.7 to 5.5 V

0.1

1.8

10

µs

µs

µs

V^DD= 1.8 to 5.5 V

Interrupt input high-

/low-level width

t^INTH, t^INTLINTP0 to INTP3

RESET input low-

level width

t^RSL

10

10

µs

µs

CPT90 input high-

/low-level width

t^CPH,

t^CPL

T^CYvs V^DD(main system clock)

60

10

µ

Operation

guaranteed range

1.0

0.4

0.1

1

2

3

4

5

6

Supply voltage VDD [V]

43

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

(2) Serial interface (T^A= −40 to +85°C, VDD = 1.8 to 5.5 V)

(a) 3-wire serial I/O mode (SCK20...Internal clock)

Parameter

Symbol

t^KCY1

Conditions

MIN.

800

TYP.

MAX.

Unit

SCK20 cycle time

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

ns

ns

ns

ns

ns

ns

3200

t^KCY1/2−50

t^KCY1/2−150

150

SCK20 high-/low-

level width

t^KH1, t^KL1V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

SI20 setup time

t^SIK1

t^KSI1

t^KSO1

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

(to SCK20 ↑)

500

SI20 hold time

400

ns

ns

ns

ns

(from SCK20 ↑)

600

SO20 output delay

R = 1 kΩ,

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

0

250

time from SCK20↓

C = 100 pF^Note

0

1000

Note R and C are the load resistance and load capacitance of the SO20 output line.

(b) 3-wire serial I/O mode (SCK20...External clock)

Parameter

Symbol

t^KCY2

Conditions

MIN.

900

3500

400

1600

100

150

400

600

0

TYP.

MAX.

Unit

SCK20 cycle time

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

ns

ns

ns

ns

ns

ns

SCK20 high-/low-

level width

t^KH2, t^KL2V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

SI20 setup time

t^SIK2

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

(to SCK20 ↑)

SI20 hold time

t^KSI2

ns

ns

ns

ns

(from SCK20 ↑)

SO20 output delay

t^KSO2

R = 1 kΩ,

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

300

time from SCK20 ↓

C = 100 pF^Note

0

1000

SO20 setup time

(when using SS20,

to SS20 ↓)

t^KAS2

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

120

400

240

800

ns

ns

ns

ns

SO20 disable time

(when using SS20,

from SS20 ↑)

t^KDS2

Note R and C are the load resistance and load capacitance of the SO20 output line.

(c) UART mode (dedicated baud rate generator output)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

78125

19531

Unit

bps

bps

Transfer rate

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

44

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

(d) UART mode (external clock input)

Parameter

Symbol

t^KCY3

Conditions

MIN.

900

TYP.

MAX.

Unit

ASCK20 cycle

time

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

ns

ns

3500

400

ASCK20 high-/low- t^KH3, t^KL3V^DD= 2.7 to 5.5 V

ns

level width

V^DD= 1.8 to 5.5 V

1600

ns

bps

bps

Transfer rate

V^DD= 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

39063

9766

1

ASCK20 rise time,

fall time

t^R, t^F

µs

45

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

(3) Serial interface SMB0 (T^A= −40 to +85°C, VDD = 1.8 to 5.5 V)

(µPD78916xY, 78917xY, 78916xY(A), 78917xY(A) only)

(a) DC Characteristics

Parameter

Symbol

Conditions

MIN.

0.8 V^DD

0.9 V^DD

0

TYP.

MAX.

V^DD

Unit

Input voltage, high

V^IH

SCL0, SDA0 V^DD= 2.7 to 5.5 V

V

V

V

V

V

(at hysteresis)

V^DD= 1.8 to 5.5 V

V^DD

Input voltage, low

V^IL

SCL0, SDA0 V^DD= 2.7 to 5.5 V

0.2 V^DD

0.1 V^DD

1.0

(at hysteresis)

V^DD= 1.8 to 5.5 V

0

Output voltage,

high

V^OL

SCL0, SDA0 V^DD= 4.5 to 5.5 V, I^OL= 10 mA

(µPD78916xY, 78917xY)

V

V^DD= 4.5 to 5.5 V, I^OL= 3 mA

(µPD78916xY(A), 78917xY(A))

V^DD= 1.8 to 5.5 V, I^OL= 400 µ A

SCL0, SDA0 V^I= V^DD

1.0

V

0.5

3

Input current

leakage, high

I^LIH

µA

Input current

leakage, low

I^LIL

SCL0, SDA0 V^I= 0 V

−3

µA

(b) DC Characteristics (When using comparator)

Parameter

Symbol

Conditions

MIN.

0

TYP.

MAX.

5.5

Unit

V

Input range

V^SDA,

V^SCL

V^DD= 1.8 to 5.5 V

Transfer level

V^ISDA,

V^ISCL

4.5 ≤ V^DD≤ 5.5 V

3.3 ≤ V^DD< 4.5 V

2.7 ≤ V^DD< 3.3 V

1.8 ≤ V^DD< 2.7 V

0.72 V^ISMB

0.78 V^ISMB

0.75 V^ISMB

0.90 V^ISMB

V^ISMB

V^ISMB

1.28 V^ISMB

1.22 V^ISMB

1.25 V^ISMB

1.45 V^ISMB

V

V

V

V

V

V

V

V^ISMB

V^ISMB

Input level

V^ISMB

LVL01, LVL00 = 0, 1

LVL01, LVL00 = 1, 0

LVL01, LVL00 = 1, 1

0.25× V^DD

0.375 ×V^DD

0.5 × V^DD

threshold value

Note V^ISMBis an input level threshold value selected by bits LVL00 and LVL01 (bits 0 and 1 of SMB input level

setting register 0 (SMBVI0)).

According to the SMB standard (V1.1), the maximum value of low-level input voltage is 0.8 V, and the

minimum value of high-level input voltage, 2.1 V. To satisfy these conditions, set LVL01 and LVL00 as

follows;

• When V^DD= 1.8 to 3.3 V: LVL01, LVL00 = 1, 1 (0.5 × V^DD)

• When V^DD= 3.3 to 4.5 V: LVL01, LVL00 = 1, 0 (0.375 × V^DD)

• When V^DD= 4.5 to 5.5 V: LVL01, LVL00 = 0, 1 (0.25 × V^DD)

"LVL01, LVL00 = 0, 0" is not available since this setting does not satisfy the SMB standard (V1.1).

46

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

(c) AC Characteristics

SMB Mode

Standard Mode I²C

Bus

High-speed Mode I²C

Bus

Parameter

Symbol

Unit

MIN.

MAX.

100

−

MIN.

0

MAX.

100

−

MIN.

0

MAX.

400

−

SCL0 clock frequency

f^CLK

t^BUF

10

kHz

Bus free time

4.7

4.7

1.3

µs

(between stop and start condition)

Hold time^Note1

t^HD:STA

t^SU:STA

t^SU:STO

t^HD:DAT

4.0

4.7

4.0

−

−

−

−

−

4.0

4.7

4.0

5

−

−

−

−

0.6

0.6

0.6

−

−

−

−

−

µs

µs

µs

µs

Start/restart condition setup time

Stop condition setup time

Data hold When using CBUS-

compatible master

time

0^{Note 2}

900^{Note 3}

When using SMB/IIC

bus

300

−

−

−

ns

100^{Note 4}

Data setup time

t^SU:DAT

t^LOW

t^HIGH

t^F

250

4.7

4.0

−

−

−

250

4.7

4.0

−

−

−

−

−

ns

µs

µs

ns

ns

ns

SCL0 clock low-level width

SCL0 clock high-level width

SCL0 and SDA0 signal fall time

SCL0 and SDA0 signal rise time

1.3

0.6

−

50

−

−

300

1000

−

300

1000

−

300

300

50

t^R

−

−

−

Spike pulse width controlled by

input filter

t^SP

−

−

0

Timeout

t^TIMEOUT

25

35

25

−

−

−

−

−

−

−

−

ms

ms

Total extended time of SCL0 clock

low-level period (slave)

t^LOW:SEXT

−

Total extended time of cumulative

clock low-level period (master)

t^LOW:MEXT

−

−

10

−

−

−

−

−

−

ms

pF

Capacitive load per each bus line

Cb

−

400

400

Notes 1. In the start condition, the first clock pulse is generated after this hold time.

2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally

provide at least 300 ns of hold time for the SDA0 signal (which is V^IHmin. of the SCL0 signal).

3. If the device does not extend the SCL0 signal low hold time (t^LOW), only maximum data hold time

t^HD:DATneeds to be fulfilled.

4. The high-speed mode I²C bus is available in the SMB mode and the standard mode I²C bus

system. At this time, the conditions described below must be satisfied.

If the device extends the SCL0 signal low state hold time

t

^SU:DAT≥ 250 ns

If the device extends the SCL0 signal low state hold time

Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (t^Rmax.+

t^SU:DAT= 1000 + 250 = 1250 ns by the SMB mode or the standard mode I²C bus specification).

47

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

AC Timing Measurement Points (excluding the X1 and XT1 inputs)

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

Point of

measurement

Clock Timing

1/f

X

tXL

tXH

V

IH4 (MIN.)

IL4 (MAX.)

X1 input

V

1/fXT

t

XTL

t

XTH

V

IH4 (MIN.)

IL4 (MAX.)

XT1 input

V

TI Timing

1/fTI

t

TIL

t

TIH

TI80, TI81

48

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Interrupt Input Timing

t

INTL

t

INTH

INTP0 to INTP3

RESET Input Timing

t

RSL

RESET

CPT90 Input Timing

tCPL

tCPH

CPT90

49

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Serial Transfer Timing

3-wire serial I/O mode:

t

KCYm

t

KLm

t

KHm

SCK20

t

SIKm

t

KSIm

SI20

Input data

t

KSOm

Output data

SO20

Remark m = 1, 2

3-wire serial I/O mode (when using SS20):

SS20

t

KAS2

tKDS2

SO20

Output data

UART mode (external clock input):

tKCY3

tKL3

tKH3

tR

tF

ASCK20

50

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

SMB mode:

t

LOW

t

R

SCL0

t

F

t

HD:DAT

t

HIGH

SU:DAT

t

SU:STA

t

HD:STA

t

SP

t

SU:STO

t

HD:STA

t

SDA0

t

BUF

Stop condition Start condition

Restart condition

Stop condition

8-Bit A/D Converter Characteristics (µPD78916x, 78916xY, 78916x(A), 78916xY(A))

(T^A= −40 to +85°C, 1.8 ≤ AV^REF≤ AV^DD= V^DD≤ 5.5 V, AV^SS= V^SS= 0 V)

Parameter

Symbol

Conditions

MIN.

8

TYP.

8

MAX.

8

Unit

Resolution

bit

%FSR

%FSR

µs

Overall error^Note

Conversion time

2.7 ≤ AV^REF≤ AV^DD≤ 5.5 V

1.8 ≤ AV^REF≤ AV^DD≤ 5.5 V

4.5 ≤ AV^REF≤ AV^DD≤ 5.5 V

2.7 ≤ AV^REF≤ AV^DD≤ 5.5 V

1.8 ≤ AV^REF≤ AV^DD≤ 5.5 V

0.4

0.8

0.6

1.2

t^CONV

12

14

28

0

100

100

100

AV^REF

AV^DD

µs

µs

V

Analog input voltage

Reference voltage

V^IAN

AV^REF

R^ADREF

1.8

20

V

Resistance between

AV^REFand AV^SS

40

kΩ

Note Excludes quantization error ( 0.2%FSR).

Remark FSR: Full scale range

51

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

10-Bit A/D Converter Characteristics (µPD78917x, 78917xY, 78917x(A), 78917xY(A))

(T^A= −40 to +85°C, 1.8 ≤ AV^REF≤ AV^DD= V^DD≤ 5.5 V, AV^SS= V^SS= 0 V)

Parameter

Symbol

Conditions

MIN.

10

TYP.

MAX.

Unit

Resolution

10

10

0.4

bit

Note

Overall error

4.5 V ≤ AV^REF≤ AV^DD≤ 5.5 V

2.7 V ≤ AV^REF≤ AV^DD≤ 5.5 V

1.8 V ≤ AV^REF≤ AV^DD≤ 5.5 V

4.5 V ≤ AV^REF≤ AV^DD≤ 5.5 V

2.7 V ≤ AV^REF≤ AV^DD≤ 5.5 V

1.8 V ≤ AV^REF≤ AV^DD≤ 5.5 V

4.5 V ≤ AV^REF≤ AV^DD≤ 5.5 V

2.7 V ≤ AV^REF≤ AV^DD≤ 5.5 V

1.8 V ≤ AV^REF≤ AV^DD≤ 5.5 V

4.5 V ≤ AV^REF≤ AV^DD≤ 5.5 V

2.7 V ≤ AV^REF≤ AV^DD≤ 5.5 V

1.8 V ≤ AV^REF≤ AV^DD≤ 5.5 V

4.5 V ≤ AV^REF≤ AV^DD≤ 5.5 V

2.7 V ≤ AV^REF≤ AV^DD≤ 5.5 V

1.8 V ≤ AV^REF≤ AV^DD≤ 5.5 V

4.5 V ≤ AV^REF≤ AV^DD≤ 5.5 V

2.7 V ≤ AV^REF≤ AV^DD≤ 5.5 V

1.8 V ≤ AV^REF≤ AV^DD≤ 5.5 V

0.2

0.4

0.8

%FSR

%FSR

%FSR

µs

0.6

1.2

Conversion time

t^CONV

12

14

28

100

100

100

0.4

µs

µs

Note

Zero-scale error

%FSR

%FSR

%FSR

%FSR

%FSR

%FSR

LSB

0.6

1.2

Note

Full-scale error

0.4

0.6

1.2

Integral linearity

INL

2.5

Note

error

LSB

4.5

LSB

8.5

LSB

Differential linearity

DNL

1.5

Note

error

LSB

2.0

LSB

3.5

V

Analog input voltage

Reference voltage

V^IAN

0

AV^REF

AV^DD

AV^REF

R^AIREF

1.8

20

V

Resistance between

AV^REFand AV^SS

40

kΩ

Note Excludes quantization error ( 0.05%FSR).

Remark FSR: Full scale range

52

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Data Memory Stop Mode Low Power Supply Voltage Data Retention Characteristics (T = −40 to +85°C)

A

Parameter

Symbol

V^DDDR

Conditions

MIN.

1.8

TYP.

MAX.

5.5

Unit

V

Data retention power

supply voltage

Release signal set time

t^SREL

t^WAIT

0

µs

s

Oscillation stabilization

wait time^{Note 1}

Release by RESET

Release by interrupt request

2¹⁵/f^X

Note 2

s

Notes 1.

2.

The oscillation stabilization time is the time the CPU operation is stopped to prevent unstable

operation when oscillation starts.

By using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time selection register (OSTS),

2¹²/f^X, 2¹⁵/f^X, or 2¹⁷/f^Xcan be selected.

Remark f^X: Main system clock oscillation frequency

Data Retention Timing (STOP Mode Release by RESET)

Internal reset operation

HALT mode

Operating mode

STOP mode

Data retention mode

VDD

VDDDR

tSREL

STOP instruction execution

RESET

tWAIT

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

HALT mode

STOP mode

Operating mode

Data retention mode

VDD

VDDDR

tSREL

STOP instruction execution

Standby release signal

(interrupt request)

tWAIT

53

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

12. CHARACTERISTICS CURVES

I

DD vs. VDD (f = 5.0 MHz, fXT = 32.768 kHz)

X

(TA = 25˚C)

10.0

Main system clock operating

mode

(PCC1 = 0, CSS0 = 0)

Main system clock operating

mode

(PCC1 = 1, CSS0 = 0)

Main system clock operation

HALT mode

1.0

0.5

(PCC1 = 0, CSS0 = 0)

Main system clock

operation HALT mode

(PCC1 = 1, CSS0 = 0)

0.1

0.05

Subsystem clock operating

mode (CSS0 = 1, MCC = 1)

Subsystem clock operation

HALT mode (CSS0 = 1, MCC = 1)

0.01

XT1

X1

X2

XT2

0.005

Crystal

resonator

5.0 MHz

Crystal

resonator

220 kΩ

32.768 kHz

22 pF

22 pF

33 pF

33 pF

VSS

VSS

0.001

0

1

2

3

4

5

6

7

8

Supply voltage V^DD(V)

54

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

IDD vs. VDD (fX = 4.19 MHz, fXT = 32.768 kHz)

(T^A= 25˚C)

10.0

Main system clock operating

mode (PCC1 = 0, CSS0 = 0)

1.0

0.5

Main system clock operating

mode (PCC1 = 1, CSS0 = 0)

Main system clock operation

HALT mode (PCC1 = 0, CSS0 = 0)

Main system clock operation

HALT mode (PCC1 = 1, CSS0 = 0)

0.1

0.05

Subsystem clock operating

mode (CSS0 = 1, MCC = 1)

Subsystem clock operation

HALT mode (CSS0 = 1, MCC = 1)

0.01

XT1

X1

X2

XT2

0.005

Crystal

Crystal

resonator

4.19 MHz

resonator

220 kΩ

32.768 kHz

22 pF

22 pF

33 pF

V^SS

33 pF

VSS

0.001

0

1

2

3

4

5

6

7

8

Supply voltage V^DD(V)

55

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

I

DD vs. VDD (f = 1.0 MHz, fXT = 32.768 kHz)

X

(TA = 25˚C)

10.0

1.0

0.5

Main system clock operating

mode (PCC1 = 0, CSS0 = 0)

Main system clock operating

mode (PCC1 = 1, CSS0 = 0)

Main system clock operation

HALT mode (PCC1 = 0, CSS0 = 0)

Main system clock operation

HALT mode (PCC1 = 1, CSS0 = 0)

0.1

0.05

Subsystem clock operating

mode (CSS0 = 1, MCC = 1)

Subsystem clock operation

HALT mode (CSS0 = 1,

MCC = 1)

0.01

XT1

X1

X2

XT2

Crystal

0.005

Crystal

resonator

1.0 MHz

resonator

32.768 kHz

220 kΩ

100 pF

100 pF

33 pF

33 pF

V

SS

V

SS

0.001

0

1

2

3

4

5

6

7

8

Supply voltage V^DD(V)

56

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

13. PACKAGE DRAWING

44 PIN PLASTIC QFP (10x10)

A

B

detail of lead end

23

22

33

34

S

P

T

C

D

R

L

12

11

44

1

U

Q

F

J

M

G

H

I

K

M

N

S

S

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.16 mm of

its true position (T.P.) at maximum material condition.

A

B

C

D

F

12.0 0.2

10.0 0.2

10.0 0.2

12.0 0.2

1.0

G

1.0

+0.08

H

0.37

−0.07

I

0.2

J

K

L

0.8 (T.P.)

1.0 0.2

0.5

+0.03

0.17

M

−0.06

N

P

Q

0.10

1.4 0.05

0.1 0.05

+4°

3°

R

−3°

S

U

1.6 MAX.

0.6 0.15

S44GB-80-8ES-1

57

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

48-PIN PLASTIC TQFP (FINE PITCH) (7x7)

A

B

detail of lead end

36

37

25

24

S

P

T

C

D

R

L

U

48

13

12

Q

1

F

G

J

M

H

I

K

S

M

N

S

NOTE

Each lead centerline is located within 0.10 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

9.0 0.2

7.0 0.2

7.0 0.2

9.0 0.2

0.75

A

B

C

D

F

G

0.75

+0.05

0.22

H

−0.04

I

0.10

J

K

L

0.5 (T.P.)

1.0 0.2

0.5 0.2

+0.03

0.17

M

−0.07

N

P

Q

0.08

1.0 0.1

0.1 0.05

+4°

3°

R

S

−3°

1.27 MAX.

P48GA-50-9EU

58

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

14. RECOMMENDED SOLDERING CONDITIONS

The µPD78916x, 78917x, 78916xY, 78917xY, 78916x(A), 78917x(A), 78916xY(A), and 78917xY(A) should be

soldered and mounted under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 14-1. Surface Mounting Type Soldering Conditions (1/2)

µPD789166GB-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789167GB-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789176GB-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789177GB-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789166YGB-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789167YGB-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789176YGB-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789177YGB-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789166GB(A)-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789167GB(A)-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789176GB(A)-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

µPD789177GB(A)-×××-8ES: 44-pin plastic LQFP (10 × 10 mm)

Recommended Condition

Soldering Method

Infrared reflow

Soldering Conditions

Symbol

Package peak temperature: 235°C, Time: 30 seconds max.

(at 210°C or higher), Count: Twice or less

IR35-00-2

VPS

Package peak temperature: 215°C, Time: 40 seconds max.

(at 200°C or higher), Count: Twice or less

VP15-00-2

Wave soldering

Solder bath temperature: 260°C max., Time: 10 seconds max., Count:

Once, Preheating temperature: 120°C max. (package surface

temperature)

WS60-00-1

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

−

Caution Do not use different soldering methods together (except for partial heating).

59

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Table 14-1. Surface Mounting Type Soldering Conditions (2/2)

µPD789166YGA-×××-9EU: 48-pin plastic TQFP (7 × 7 mm)

µPD789167YGA-×××-9EU: 48-pin plastic TQFP (7 × 7 mm)

µPD789176YGA-×××-9EU: 48-pin plastic TQFP (7 × 7 mm)

µPD789177YGA-×××-9EU: 48-pin plastic TQFP (7 × 7 mm)

µPD789166YGA(A)-×××-9EU: 48-pin plastic TQFP (7 × 7 mm)

µPD789167YGA(A)-×××-9EU: 48-pin plastic TQFP (7 × 7 mm)

µPD789176YGA(A)-×××-9EU: 48-pin plastic TQFP (7 × 7 mm)

µPD789177YGA(A)-×××-9EU: 48-pin plastic TQFP (7 × 7 mm)

Recommended Condition

Symbol

Soldering Method

Infrared reflow

Soldering Conditions

Package peak temperature: 235°C, Time: 30 seconds max.

(at 210°C or higher), Count: Twice or less, Number of days:3^Note(After

that, prebaking is necessary at 125°C for 10 hours)

IR35-103-2

VP15-103-2

−

VPS

Package peak temperature: 215°C, Time: 40 seconds max.

(at 200°C or higher), Count: Twice or less, Number of days:3

that, prebaking is necessary at 125°C for 10 hours)

Note

(After

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note The number of days for storage at 25°C, 65% RH MAX after the dry pack has been opened.

Caution Do not use different soldering methods together (except for partial heating).

60

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for developing systems using the µPD78916x, 78917x, 78916xY,

78917xY, 78916x(A), 78917x(A), 78916xY(A), and 78917xY(A).

Language Processing Software

RA78K0S^{Notes 1, 2, 3}

CC78K0S^{Notes 1, 2, 3}

DF789177^{Notes 1, 2, 3}

Assembler package common to 78K/0S Series

C compiler package common to 78K/0S Series

Device file for µPD78916x, 78917x, 78916xY, 78917xY, 78916x(A), 78917x(A),

78916xY(A), and 78917xY(A)

CC78K0S-L^{Notes 1, 2, 3}

C compiler library source file common to 78K/0S Series

Flash Memory Writing Tools

Flashpro lIl

Flash programmer dedicated for on-chip flash memory microcontrollers

Flash memory programming adapter for 44-pin plastic LQFP (GB-8ES type)

(Part No.: FL-PR3^{Note 4}, PG-FP3)

FA-44GB-8ES^{Note 4}

FA-48GA

Flash memory programming adapter for 48-pin plastic TQFP (fine pitch) (GA-9EU

type)

Debugging Tools (1/2)

IE-78K0S-NS

In-circuit emulator used to debug hardware or software when application systems which

use the 78K/0S Series are developed. The IE-78K0S-NS supports an integrated

debugger (ID78K0S-NS). The IE-78K0S-NS is used in combination with an interface

adapter for connection to an AC adapter, emulation probe, or host machine.

In-circuit emulator

IE-78K0S-NS-A

The debugging function is enhanced by the addition of a coverage function and the

tracer function and timer function are also enhanced.

In-circuit emulator

IE-70000-MC-PS-B

AC adapter

Adapter used to supply power from a 100- to 240-V AC outlet

IE-70000-98-IF-C

Interface adapter

Adapter required when using the PC-9800 series (excluding notebook PCs) as the host

machine (C bus supported)

IE-70000-CD-IF-A

PC card/interface

PC card and interface cable required when using a notebook PC as the host machine

(PCMCIA socket supported)

IE-70000-PC-IF-C

Interface adapter

Adapter required when using an IBM PC/AT^TMor compatible as the host machine (ISA

bus supported)

IE-70000-PCI-IF-A

Interface adapter

Adapter required when using a PC equipped with a PCI bus as the host machine

IE-789177-NS-EM1

Emulation board

Emulation board used to emulate the peripheral hardware specific to the device. This

is used in combination with the in-circuit emulator.

NP-44GB-TQ^{Note 4}

Board to connect an in-circuit emulator to the target system. This is used in

combination with the TGB-044SAP.

Emulation probe

TGB-044SAP^{Note 5}

conversion socket

Conversion socket to connect the target system board on which a 44-pin plastic LQFP

can be mounted and the NP-44GB-TQ

61

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Debugging Tools (2/2)

NP-48GA^{Note 4}

Board to connect an in-circuit emulator to the target system. This is used in

combination with the TGA-048SDP.

Emulation probe

TGA-048SDP^{Note 5}

conversion socket

Conversion socket to connect the target system board on which a 48-pin plastic TQFP

(fine pitch) can be mounted and the NP-48GA

SM78K0S^{Notes 1, 2}

ID78K0S-NS^{Notes 1, 2}

DF789177^{Notes 1, 2}

System simulator common to 78K/0S Series

Integrated debugger common to 78K/0S Series

Device file for µPD78916x, 78917x, 78916xY, 78917xY, 78916x(A), 78917x(A),

78916xY(A), and 78917xY(A)

Notes 1. Based on the PC-9800 series (MS-DOS^TM+ Windows^TM

)

2. Based on IBM PC/AT and compatibles (Japanese Windows/English Windows)

3. Based on the HP9000 series 700^TM(HP-UX^TM), and SPARCstation^TM(SunOS^TM, Solaris^TM

)

4. Product made by and available from Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191).

5. Product made by TOKYO ELETECH CORPORATION.

Refer to: Daimaru Kogyo, Ltd.

Tokyo Electronic Division (+81-3-3820-7112)

Osaka Electronic Division (+81-6-6244-6672)

Remark The RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S can be used in combination with the

DF789177.

62

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

APPENDIX B. RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

Documents Related to Devices

Document Name

Document No.

This manual

µPD789166, 167, 176, 177, 166Y, 167Y, 176Y, 177Y, 166(A), 167(A), 176(A), 177(A), 166Y(A), 167Y(A),

176Y(A), 177Y(A) Data Sheet

µPD78F9177, 78F9177Y Data Sheet

U14022E

U14186E

U11047E

µPD789167, 789177, 789167Y, 789177Y Subseries User’s Manual

78K/0S Series Instruction User’s Manual

Document Related to Development Tools (User’s Manuals)

Document Name

Document No.

U14876E

RA78K0S Assembler Package

CC78K0S C Compiler

Operation

Language

U14877E

Structured Assembly Language

Operation

U11623E

U14871E

Language

U14872E

SM78K0S, SM78K0 System Simulator Ver. 2.10 or

Later

Operation (Windows Based)

U14611E

SM78K Series System Simulator Ver. 2.10 or Later

External Part User Open Interface Specifications

Operation (Windows Based)

U15006E

U14910E

ID78K0-NS, ID78K0S-NS Integrated Debugger Ver.

2.20 or Later

Project Manager Ver. 3.12 or later (Windows-based)

U14610E

Documents Related to Embedded Software (User’s Manuals)

Document Name

Document No.

U13549E

IE-78K0S-NS In-Circuit Emulator

IE-78K0S-NS-A In-Circuit Emulator

IE-789177-NS-EM1 Emulation Board

U15207E

U14621E

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

63

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Other Documents

Document Name

Document No.

X13769E

SEMICONDUCTOR SELECTION GUIDE -Products & Packages-

Semiconductor Device Mounting Technology Manual

C10535E

Quality Grades on NEC Semiconductor Device

C11531E

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

C10983E

C11892E

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

64

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

[MEMO]

65

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Purchase of NEC I²C components conveys a license under the Philips I²C Patent Rights to use these components in

an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

FIP and EEPROM are trademarks of NEC Corporation.

MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United

States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

66

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, pIease contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

•

•

•

•

•

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics (France) S.A.

Vélizy-Villacoublay, France

Tel: 01-3067-58-00

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 01-3067-58-99

Fax: 2886-9022/9044

Fax: 408-588-6130

800-729-9288

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Representación en España

Madrid, Spain

Tel: 091-504-27-87

Fax: 091-504-28-60

NEC do Brasil S.A.

Electron Devices Division

Guarulhos-SP, Brasil

Tel: 11-6462-6810

NEC Electronics Shanghai, Ltd.

Shanghai, P.R. China

Tel: 021-6841-1138

Fax: 11-6462-6829

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

NEC Electronics (Europe) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 01

Fax: 021-6841-1137

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Fax: 0211-65 03 327

•

Tel: 02-2719-2377

Branch The Netherlands

Fax: 02-2719-5951

Eindhoven, The Netherlands

Tel: 040-244 58 45

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore

Tel: 253-8311

Fax: 040-244 45 80

•

Branch Sweden

Fax: 250-3583

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

•

Filiale Italiana

Milano, Italy

Tel: 02-667541

Fax: 02-66754299

J02.3-1

67

Data Sheet U14017EJ3V0DS

µPD789166,167,176,177,166Y,167Y,176Y,177Y,166(A),167(A),176(A),177(A),166Y(A),167Y(A),176Y(A),177Y(A)

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited

without governmental license, the need for which must be judged by the customer. The export or re-export of this product

from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

•

The information in this document is current as of January, 2002. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or

data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all

products and/or types are available in every country. Please check with an NEC sales representative

for availability and additional information.

•

•

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

liability arising from the use of such products. No license, express, implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of NEC or others.

•

•

•

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third

parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not

intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness

to support a given application.

(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4

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