UPD789489GC-XXX-8BT-A [NEC]
Microcontroller, 8-Bit, MROM, 5MHz, CMOS, PQFP80, 14 X 14 MM, PLASTIC, QFP-80;
| 型号： | UPD789489GC-XXX-8BT-A |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 8-Bit, MROM, 5MHz, CMOS, PQFP80, 14 X 14 MM, PLASTIC, QFP-80 微控制器 |
| 文件： | 总388页 (文件大小：3633K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
User’s Manual
µPD789489 Subseries
8-Bit Single-Chip Microcontrollers
µPD789488
µPD789489
µPD78F9488
µPD78F9489
Document No. U15331EJ4V1UD00 (4th edition)
Date Published July 2005 NS CP(K)
©
Printed in Japan
[MEMO]
2
User’s Manual U15331EJ4V1UD
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U15331EJ4V1UD
3
EEPROM and FIP are trademarks of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
4
User’s Manual U15331EJ4V1UD
•
The information in this document is current as of July, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
User’s Manual U15331EJ4V1UD
5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
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Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
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Tel: 08-63 87 200
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J05.6
6
User’s Manual U15331EJ4V1UD
Major Revisions in This Edition
Page
Description
Throughout
Change of descriptions of µPD789489, 78F9489
• Change of status from under development to development completed
• Change of the subseries name to “µPD789489 subseries”
pp.31 to 33
p.123
Update of 1.5 78K/0S Series Lineup to latest version
Modification of Figure 7-2 Block Diagram of Timer 50
p.124
Modification of Figure 7-3 Block Diagram of Timer 60
p.126
Modification of Figure 7-5 Block Diagram of Output control circuit (Timer 60)
Addition of descriptions in 7.2 (2) 8-bit compare register 60
p.127
p.136
p.137
Addition of descriptions in 7.2 (4) 8-bit H width compare registers 60 and 61
Modification of Figure 7-11 8-bit Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
Modification of Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Is Set to
FFH)
p.140
p.150
p.151
p.152
p.153
Modification of Figure 7-17. Timing of Operation of External Event Counter with 8-Bit Resolution
Addition of descriptions of setting sequence in 7.4.3 Operation as carrier generator
Modification of Figure 7-22. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N))
Modification of Figure 7-23. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N))
Modification of Figure 7-24. Timing of Carrier Generator Operation (When CR60 = CRH60 = N)
Modification of the mode name in 7.4.4 PWM output mode operation (timer 50)
pp.154 to
157
pp.158, 159
p.160
Modification of the mode name in 7.4.5 PPG output mode operation (timer 60 and 61)
Modification of (1) Error on starting timer in 7.5 Cautions on Using 8-Bit Timers 50, 60, and 61
Modification of Figure 10-1. Block Diagram of 10-bit A/D converter
p.174
p.182
Modification of (1) Current consumption in standby mode in 10.5 Cautions Related to 10-Bit A/D Converter
Modification of Figure 11-1. Block Diagram of Serial Interface 20
p.187
p.190
Addition of Caution in Figure 11-3 Format of Serial Operation Mode Register 20
Modification of Cautions in Figure 11-6 Format of Baud Rate Generator Control Register 20
p.194
pp.195, 203
Modification of Caution in Table 11-3 and 11-5. Example of Relationship Between System Clock and Baud
Rate
p.222
Modification of descriptions in Figure 12-4. Format of Automatic Data Transmit/Receive Interval
Specification Register 0
pp.342 to
361
Addition of formal specifications of µPD789489 and 78F9489 in CHAPTER 22 ELECTRICAL SPECIFICATIONS
(µPD789488, 78F9488, 789489, 78F9489)
pp.366, 367
Addition of recommended conditions for µPD789489 and 78F9489 in CHAPTER 25 RECOMMENDED
SOLDERING CONDITIONS
Major Revisions in Modified Edition (U15331EJ4V1UD00)
Addition of the lead-free products
Throughout
pp.254, 257
pp.328
Modification of descriptions of the voltage boost wait time in CHAPTER 13 LCD CONTROLLER/DRIVER
Modification of Figure 19-9. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O with
Handshake
The mark shows major revised points.
User’s Manual U15331EJ4V1UD
7
INTRODUCTION
Target Readers
This manual is intended for user engineers who wish to understand the functions of
the µPD789489 Subseries and design and develop application systems and programs
for these devices.
Target products:
• µPD789489 Subseries:
µPD789488, 789489, 78F9488, 78F9489
Purpose
This manual is intended to give users an understanding of the functions described in
the Organization below.
Organization
Two manuals are available for the µPD789489 Subseries:
This manual and the instruction manual (common to the 78K/0S Series).
78K/0S Series
µPD789489 Subseries
User’s Manual
User’s Manual
Instructions
• Pin functions
• CPU function
• Internal block functions
• Interrupts
• Instruction set
• Instruction description
• Other on-chip peripheral functions
• Electrical specifications
How to Use This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To understand the overall functions of the µPD789489 Subseries
→ Read this manual in the order of the CONTENTS.
• How to read register formats
→ The name of a bit whose number is enclosed with <> is reserved in the
assembler and is defined as an sfr variable by the #pragma sfr directive for the
C compiler.
• To learn the detailed functions of a register whose register name is known
→ See APPENDIX C REGISTER INDEX.
• To learn the details of the instruction functions of the 78K/0S series
→ Refer to 78K/0S Series Instructions User’s Manual (U11047E) separately
available.
• To learn about the electrical specifications of the µPD789489 Subseries
→ Refer to CHAPTER 22
ELECTRICAL SPECIFICATIONS (µPD789488,
78F9488, 789489, 78F9489)
8
User’s Manual U15331EJ4V1UD
Conventions
Data significance:
Active low representation:
Note:
Caution:
Remark:
Higher digits on the left and lower digits on the right
xxx (overscore over pin or signal name)
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Numerical representation:
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
This manual
U11047E
µPD789489 Subseries User’s Manual
78K/0S Series Instructions User’s Manual
Documents Related to Development Software Tools (User’s Manuals)
Document Name
Document No.
U17391E
U17390E
U17389E
U16654E
U16655E
U17246E
U17247E
U16768E
U15802E
U16584E
U16934E
RA78K0S Assembler Package
Operation
Language
Structured Assembly Language
CC78K0S C Compiler
Operation
Language
SM+ System Simulator
Operation
User Open Interface
SM78K Series Ver. 2.52 System Simulator
Operation
External Part User Open Interface Specification
Operation
ID78K0S-NS Ver. 2.52 Integrated Debugger
PM plus Ver.5.20
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
IE-78K0S-NS In-Circuit Emulator
Document No.
U13549E
IE-78K0S-NS-A In-Circuit Emulator
U15207E
IE-789488-NS-EM1 Emulation Board
U16492E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
User’s Manual U15331EJ4V1UD
9
Documents Related to Flash Memory Writing
Document Name
Document No.
U13502E
PG-FP3 Flash Memory Programmer User’s Manual
PG-FP4 Flash Memory Programmer User’s Manual
U15260E
Other Related Documents
Document Name
Document No.
X13769X
Note
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Quality Grades on NEC Semiconductor Devices
C11531E
C10983E
C11892E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html)
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
10
User’s Manual U15331EJ4V1UD
CONTENTS
CHAPTER 1 GENERAL ..........................................................................................................................26
1.1 Features ......................................................................................................................................26
1.2 Applications ...............................................................................................................................26
1.3 Ordering Information.................................................................................................................27
1.4 Pin Configuration (Top View) ...................................................................................................28
1.5 78K/0S Series Lineup ................................................................................................................31
1.6 Block Diagram............................................................................................................................34
1.7 Overview of Functions ..............................................................................................................35
CHAPTER 2 PIN FUNCTIONS...............................................................................................................37
2.1 List of Pin Functions .................................................................................................................37
2.2 Description of Pin Functions....................................................................................................40
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
P00 to P07 (Port 0) ....................................................................................................................... 40
P10, P11 (Port 1) .......................................................................................................................... 40
P20 to P25 (Port 2) ....................................................................................................................... 40
P30 to P34 (Port 3) ....................................................................................................................... 41
P50 to P53 (Port 5) ....................................................................................................................... 41
P60 to P67 (Port 6) ....................................................................................................................... 42
P70 to P73 (Port 7) ....................................................................................................................... 42
P80 to P87 (Port 8) ....................................................................................................................... 42
S0 to S27 ...................................................................................................................................... 42
2.2.10 COM0 to COM3 ............................................................................................................................ 42
2.2.11 VLC0 to VLC2 ................................................................................................................................... 42
2.2.12 CAPH, CAPL................................................................................................................................. 42
2.2.13 RESET.......................................................................................................................................... 43
2.2.14 X1, X2 ........................................................................................................................................... 43
2.2.15 XT1, XT2....................................................................................................................................... 43
2.2.16 AVDD.............................................................................................................................................. 43
2.2.17 AVSS.............................................................................................................................................. 43
2.2.18 VDD ................................................................................................................................................ 43
2.2.19 VSS ................................................................................................................................................ 43
2.2.20 VPP (flash memory version only).................................................................................................... 43
2.2.21 IC0 (mask ROM version only)....................................................................................................... 44
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................45
CHAPTER 3 CPU ARCHITECTURE......................................................................................................48
3.1 Memory Space............................................................................................................................48
3.1.1
3.1.2
3.1.3
Internal program memory space ................................................................................................... 52
Internal data memory space.......................................................................................................... 53
Special function register (SFR) area ............................................................................................. 53
User’s Manual U15331EJ4V1UD
11
3.1.4
Data memory addressing ..............................................................................................................54
3.2 Processor Registers ..................................................................................................................58
3.2.1
3.2.2
3.2.3
Control registers............................................................................................................................58
General-purpose registers.............................................................................................................61
Special function registers (SFRs)..................................................................................................62
3.3 Instruction Address Addressing ..............................................................................................66
3.3.1
3.3.2
3.3.3
3.3.4
Relative addressing.......................................................................................................................66
Immediate addressing...................................................................................................................67
Table indirect addressing ..............................................................................................................68
Register addressing ......................................................................................................................68
3.4 Operand Address Addressing..................................................................................................69
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
Direct addressing ..........................................................................................................................69
Short direct addressing .................................................................................................................70
Special function register (SFR) addressing...................................................................................71
Register addressing ......................................................................................................................72
Register indirect addressing..........................................................................................................73
Based addressing .........................................................................................................................74
Stack addressing...........................................................................................................................74
CHAPTER 4 PORT FUNCTIONS...........................................................................................................75
4.1 Port Functions............................................................................................................................75
4.2 Port Configuration .....................................................................................................................76
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
Port 0 ............................................................................................................................................77
Port 1 ............................................................................................................................................78
Port 2 ............................................................................................................................................79
Port 3 ............................................................................................................................................84
Port 5 ............................................................................................................................................86
Port 6 ............................................................................................................................................87
Port 7 ............................................................................................................................................89
Port 8 ............................................................................................................................................90
4.3 Registers Controlling Port Function........................................................................................91
4.4 Port Function Operation............................................................................................................94
4.4.1
4.4.2
4.4.3
Writing to I/O port..........................................................................................................................94
Reading from I/O port....................................................................................................................94
Arithmetic operation of I/O port .....................................................................................................94
CHAPTER 5 CLOCK GENERATOR ......................................................................................................95
5.1 Clock Generator Functions.......................................................................................................95
5.2 Clock Generator Configuration ................................................................................................95
5.3 Registers Controlling Clock Generator ...................................................................................98
5.4 System Clock Oscillators........................................................................................................101
5.4.1
5.4.2
5.4.3
5.4.4
Main system clock oscillator........................................................................................................101
Subsystem clock oscillator ..........................................................................................................102
Example of incorrect resonator connection .................................................................................103
Divider circuit...............................................................................................................................104
12
User’s Manual U15331EJ4V1UD
5.4.5
5.4.6
When subsystem clock is not used ............................................................................................. 104
Subsystem clock ×4 multiplication circuit .................................................................................... 104
5.5 Clock Generator Operation.....................................................................................................105
5.6 Changing Setting of System Clock and CPU Clock.............................................................106
5.6.1
5.6.2
Time required for switching between system clock and CPU clock............................................. 106
Switching between system clock and CPU clock ........................................................................ 107
CHAPTER 6 16-BIT TIMER 20............................................................................................................108
6.1 16-Bit Timer 20 Functions.......................................................................................................108
6.2 16-Bit Timer 20 Configuration ................................................................................................108
6.3 Registers Controlling 16-Bit Timer 20 ...................................................................................110
6.4 16-Bit Timer 20 Operation.......................................................................................................113
6.4.1
6.4.2
6.4.3
6.4.4
Operation as timer interrupt ........................................................................................................ 113
Operation as timer output............................................................................................................ 115
Capture operation ....................................................................................................................... 116
16-bit timer counter 20 readout................................................................................................... 117
6.5 Cautions on Using 16-Bit Timer 20 ........................................................................................118
6.5.1
Restrictions when rewriting 16-bit compare register 20............................................................... 118
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 ...................................................................................120
7.1 Functions of 8-Bit Timers 50, 60, and 61...............................................................................120
7.2 Configuration of 8-Bit Timers 50, 60, and 61 ........................................................................122
7.3 Control Registers for 8-Bit Timers 50, 60, and 61 ................................................................128
7.4 Operation of 8-Bit Timers 50, 60, and 61 ...............................................................................134
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Operation as 8-bit timer counter.................................................................................................. 134
Operation as 16-bit timer counter................................................................................................ 143
Operation as carrier generator.................................................................................................... 150
PWM output mode operation (timer 50) ...................................................................................... 154
PPG output mode operation (timer 60 and timer 61)................................................................... 158
7.5 Cautions on Using 8-Bit Timers 50, 60, and 61.....................................................................160
CHAPTER 8 WATCH TIMER ...............................................................................................................161
8.1 Watch Timer Functions ...........................................................................................................161
8.2 Configuration of Watch Timer ................................................................................................162
8.3 Control Registers for Watch Timer ........................................................................................163
8.4 Watch Timer Operation ...........................................................................................................165
8.4.1
Operation as watch timer ............................................................................................................ 165
8.4.2
Operation as interval timer.......................................................................................................... 165
CHAPTER 9 WATCHDOG TIMER.......................................................................................................167
9.1 Watchdog Timer Functions ....................................................................................................167
9.2 Watchdog Timer Configuration..............................................................................................168
9.3 Watchdog Timer Control Registers .......................................................................................169
9.4 Watchdog Timer Operation.....................................................................................................171
User’s Manual U15331EJ4V1UD
13
9.4.1
9.4.2
Operation as watchdog timer ......................................................................................................171
Operation as interval timer ..........................................................................................................172
CHAPTER 10 10-BIT A/D CONVERTER............................................................................................173
10.1 10-Bit A/D Converter Functions..............................................................................................173
10.2 10-Bit A/D Converter Configuration .......................................................................................173
10.3 10-Bit A/D Converter Control Registers ................................................................................176
10.4 10-Bit A/D Converter Operation..............................................................................................178
10.4.1 Basic operation of 10-bit A/D converter.......................................................................................178
10.4.2 Input voltage and conversion result.............................................................................................179
10.4.3 Operation mode of 10-bit A/D converter......................................................................................181
10.5 Cautions Related to 10-Bit A/D Converter.............................................................................182
CHAPTER 11 SERIAL INTERFACE 20 ..............................................................................................186
11.1 Serial Interface 20 Functions..................................................................................................186
11.2 Serial Interface 20 Configuration............................................................................................186
11.3 Serial Interface 20 Control Registers.....................................................................................190
11.4 Serial Interface 20 Operation ..................................................................................................197
11.4.1 Operation stop mode...................................................................................................................197
11.4.2 Asynchronous serial interface (UART) mode ..............................................................................199
11.4.3 3-wire serial I/O mode .................................................................................................................211
CHAPTER 12 SERIAL INTERFACE 1A0 ...........................................................................................216
12.1 Function of Serial Interface 1A0.............................................................................................216
12.2 Configuration of Serial Interface 1A0.....................................................................................217
12.3 Control Registers for Serial Interface 1A0 ............................................................................219
12.4 Serial Interface 1A0 Operation................................................................................................224
12.4.1 Operation stop mode...................................................................................................................224
12.4.2 3-wire serial I/O mode .................................................................................................................225
12.4.3 3-wire serial I/O mode with automatic transmit/receive function..................................................230
CHAPTER 13 LCD CONTROLLER/DRIVER.......................................................................................250
13.1 LCD Controller/Driver Functions............................................................................................250
13.2 LCD Controller/Driver Configuration .....................................................................................250
13.3 Registers Controlling LCD Controller/Driver ........................................................................253
13.4 Setting LCD Controller/Driver.................................................................................................257
13.5 LCD Display Data Memory ......................................................................................................257
13.6 Common and Segment Signals..............................................................................................258
13.7 Display Modes..........................................................................................................................260
13.7.1 Three-time-slice display example................................................................................................260
13.7.2 Four-time-slice display example..................................................................................................263
13.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 .............................................................266
CHAPTER 14 MULTIPLIER ..................................................................................................................267
14
User’s Manual U15331EJ4V1UD
14.1 Multiplier Function...................................................................................................................267
14.2 Multiplier Configuration ..........................................................................................................267
14.3 Multiplier Control Register......................................................................................................269
14.4 Multiplier Operation.................................................................................................................270
CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY)......................271
15.1 Remote Controller Receiver Functions .................................................................................271
15.2 Remote Controller Receiver Configuration...........................................................................271
15.3 Registers to Control Remote Controller Receiver................................................................277
15.4 Operation of Remote Controller Receiver.............................................................................279
15.4.1 Format of type A reception mode................................................................................................ 279
15.4.2 Operation flow of type A reception mode .................................................................................... 279
15.4.3 Timing......................................................................................................................................... 281
15.4.4 Compare register setting............................................................................................................. 283
15.4.5 Error interrupt generation timing ................................................................................................. 285
15.4.6 Noise elimination......................................................................................................................... 287
CHAPTER 16 INTERRUPT FUNCTIONS............................................................................................290
16.1 Interrupt Function Types.........................................................................................................290
16.2 Interrupt Sources and Configuration.....................................................................................290
16.3 Registers Controlling Interrupt Function..............................................................................294
16.4 Interrupt Servicing Operation.................................................................................................301
16.4.1 Non-maskable interrupt request acknowledgment operation ...................................................... 301
16.4.2 Maskable interrupt request acknowledgment operation .............................................................. 303
16.4.3 Multiple interrupt servicing .......................................................................................................... 304
16.4.4 Putting interrupt requests on hold ............................................................................................... 306
CHAPTER 17 STANDBY FUNCTION..................................................................................................307
17.1 Standby Function and Configuration ....................................................................................307
17.1.1 Standby function ......................................................................................................................... 307
17.1.2 Register controlling standby function .......................................................................................... 308
17.2 Standby Function Operation...................................................................................................309
17.2.1 HALT mode................................................................................................................................. 309
17.2.2 STOP mode ................................................................................................................................ 312
CHAPTER 18 RESET FUNCTION .......................................................................................................315
CHAPTER 19 FLASH MEMORY VERSION .......................................................................................319
19.1 Flash Memory Characteristics................................................................................................320
19.1.1 Programming environment.......................................................................................................... 320
19.1.2 Communication mode ................................................................................................................. 321
19.1.3 On-board pin processing............................................................................................................. 324
19.1.4 Connection of adapter for flash writing........................................................................................ 327
19.2 Cautions on µPD78F9488 and 78F9489.................................................................................330
User’s Manual U15331EJ4V1UD
15
CHAPTER 20 MASK OPTIONS ...........................................................................................................331
CHAPTER 21 INSTRUCTION SET ......................................................................................................332
21.1 Operation ..................................................................................................................................332
21.1.1 Operand identifiers and description methods..............................................................................332
21.1.2 Description of “Operation” column...............................................................................................333
21.1.3 Description of “Flag” column .......................................................................................................333
21.2 Operation List...........................................................................................................................334
21.3 Instructions Listed by Addressing Type ...............................................................................339
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) ..........342
CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER..............................362
CHAPTER 24 PACKAGE DRAWINGS.................................................................................................364
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS...........................................................366
APPENDIX A DEVELOPMENT TOOLS...............................................................................................369
A.1 Software Package ....................................................................................................................371
A.2 Language Processing Software .............................................................................................371
A.3 Control Software......................................................................................................................372
A.4 Flash Memory Writing Tools...................................................................................................372
A.5 Debugging Tools (Hardware)..................................................................................................373
A.6 Debugging Tools (Software)...................................................................................................374
APPENDIX B NOTES ON TARGET SYSTEM DESIGN...................................................................375
APPENDIX C REGISTER INDEX.........................................................................................................379
C.1 Register Index (Register Names in Alphabetic Order).........................................................379
C.2 Register Index (Register Symbols Alphabetic Order)..........................................................382
APPENDIX D REVISION HISTORY ......................................................................................................385
16
User’s Manual U15331EJ4V1UD
LIST OF FIGURES (1/6)
Figure No.
2-1
Title
Page
I/O Circuit Types ..........................................................................................................................................46
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Memory Map (µPD789488)..........................................................................................................................48
Memory Map (µPD78F9488)........................................................................................................................49
Memory Map (µPD789489)..........................................................................................................................50
Memory Map (µPD78F9489)........................................................................................................................51
Data Memory Addressing (µPD789488) ......................................................................................................54
Data Memory Addressing (µPD78F9488) ....................................................................................................55
Data Memory Addressing (µPD789489) ......................................................................................................56
Data Memory Addressing (µPD78F9489) ....................................................................................................57
Program Counter Configuration ...................................................................................................................58
Program Status Word Configuration ............................................................................................................58
Stack Pointer Configuration .........................................................................................................................60
Data to Be Saved to Stack Memory .............................................................................................................60
Data to Be Restored from Stack Memory.....................................................................................................60
General-Purpose Register Configuration .....................................................................................................61
3-9
3-10
3-11
3-12
3-13
3-14
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
Port Types....................................................................................................................................................75
Block Diagram of P00 to P07.......................................................................................................................77
Block Diagram of P10 and P11 ....................................................................................................................78
Block Diagram of P20 ..................................................................................................................................79
Block Diagram of P21 ..................................................................................................................................80
Block Diagram of P22 and P25 ....................................................................................................................81
Block Diagram of P23 ..................................................................................................................................82
Block Diagram of P24 ..................................................................................................................................83
Block Diagram of P30 to P33.......................................................................................................................84
Block Diagram of P34 ..................................................................................................................................85
Block Diagram of P50 to P53.......................................................................................................................86
Block Diagram of P60 to P67.......................................................................................................................87
Block Diagram of P70 to P73.......................................................................................................................89
Block Diagram of P80 to P87.......................................................................................................................90
Port Mode Register Format..........................................................................................................................91
Format of Pull-Up Resistor Option Registers ...............................................................................................93
Port Function Register Format.....................................................................................................................93
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
5-1
5-2
5-3
5-4
Clock Generator Block Diagram (µPD789488, 789489)...............................................................................96
Clock Generator Block Diagram (µPD78F9488, 78F9489) ..........................................................................97
Format of Processor Clock Control Register................................................................................................98
Format of Subclock Oscillation Mode Register.............................................................................................99
User’s Manual U15331EJ4V1UD
17
LIST OF FIGURES (2/6)
Figure No.
Title
Page
5-5
5-6
5-7
5-8
5-9
5-10
Format of Subclock Control Register............................................................................................................99
Subclock Selection Register Format ..........................................................................................................100
External Circuit of Main System Clock Oscillator........................................................................................101
External Circuit of Subsystem Clock Oscillator...........................................................................................102
Examples of Incorrect Resonator Connection............................................................................................103
Switching Between System Clock and CPU Clock.....................................................................................107
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
Block Diagram of 16-Bit Timer 20 ..............................................................................................................109
Format of 16-Bit Timer Mode Control Register 20......................................................................................111
Format of Port Mode Register 3.................................................................................................................112
Settings of 16-Bit Timer Mode Control Register 20 for Timer Interrupt Operation......................................113
Timing of Timer Interrupt Operation ...........................................................................................................114
Settings of 16-Bit Timer Mode Control Register 20 for Timer Output Operation ........................................115
Timer Output Timing ..................................................................................................................................115
Settings of 16-Bit Timer Mode Control Register 20 for Capture Operation.................................................116
Capture Operation Timing (with Both Edges of CPT20 Pin Specified).......................................................116
16-Bit Timer Counter 20 Readout Timing...................................................................................................117
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Block Diagram of 24-Bit Event Counter......................................................................................................121
Block Diagram of Timer 50.........................................................................................................................123
Block Diagram of Timer 60.........................................................................................................................124
Block Diagram of Timer 61.........................................................................................................................125
Block Diagram of Output Controller (Timer 60) ..........................................................................................126
Format of 8-Bit Timer Mode Control Register 50 .......................................................................................128
Format of 8-Bit Timer Mode Control Register 60........................................................................................130
Format of Carrier Generator Output Control Register 60 ...........................................................................131
Format of 8-Bit Timer Mode Control Register 61........................................................................................132
Format of Port Mode Register 3.................................................................................................................133
Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)...............................................136
Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Is Set to 00H)..............................136
Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Is Set to FFH)..............................137
Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Changes from N to M (N < M))....137
Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Changes from N to M (N > M))....138
Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 60 Match Signal Is Selected
for Timer 50 Count Clock) ..........................................................................................................................139
Timing of Operation of External Event Counter with 8-Bit Resolution ........................................................140
Timing of Square-Wave Output with 8-Bit Resolution ................................................................................142
Timing of Interval Timer Operation with 16-Bit Resolution .........................................................................145
Timing of External Event Counter Operation with 16-Bit Resolution ..........................................................147
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
18
User’s Manual U15331EJ4V1UD
LIST OF FIGURES (3/6)
Figure No.
Title
Page
7-21
7-22
7-23
7-24
7-25
7-26
7-27
7-28
Timing of Square-Wave Output with 16-Bit Resolution ..............................................................................149
Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N))........................................151
Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N))........................................152
Timing of Carrier Generator Operation (When CR60 = CRH60 = N) .........................................................153
Operation Timing in PWM Output Mode (When Rising Edge Is Selected).................................................154
Operation Timing When Overwriting CR50 (When Rising Edge Is Selected).............................................155
Operation Timing in PWM Output Mode (When Both Edges Are Selected)...............................................156
Operation Timing in PWM Output Mode (When Both Edges Are Selected)
(When CR50 Is Overwritten) ......................................................................................................................157
PPG Output Mode Timing (Basic Operation) .............................................................................................159
PPG Output Mode Timing (When CR6m and CRH6m Are Overwritten)....................................................159
Case in Which Error of 1.5 Clocks (Max.) Occurs......................................................................................160
Timing of Operation as External Event Counter (8-Bit Resolution) ............................................................160
7-29
7-30
7-31
7-32
8-1
8-2
8-3
8-4
Block Diagram of Watch Timer ..................................................................................................................161
Format of Watch Timer Mode Control Register..........................................................................................163
Format of Watch Timer Interrupt Time Selection Register .........................................................................164
Watch Timer/Interval Timer Operation Timing ...........................................................................................166
9-1
9-2
9-3
Block Diagram of Watchdog Timer.............................................................................................................168
Format of Watchdog Timer Clock Selection Register.................................................................................169
Format of Watchdog Timer Mode Register ................................................................................................170
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
Block Diagram of 10-Bit A/D Converter......................................................................................................174
Format of A/D Converter Mode Register 0.................................................................................................176
Format of Analog Input Channel Specification Register 0..........................................................................177
Basic Operation of 10-Bit A/D Converter....................................................................................................179
Relationship Between Analog Input Voltage and A/D Conversion Result ..................................................180
Software-Started A/D Conversion ..............................................................................................................181
How to Reduce Current Consumption in Standby Mode............................................................................182
Conversion Result Read Timing (if Conversion Result Is Undefined) ........................................................183
Conversion Result Read Timing (if Conversion Result Is Normal).............................................................183
Analog Input Pin Handling..........................................................................................................................184
A/D Conversion End Interrupt Request Generation Timing........................................................................185
AVDD Pin Handling......................................................................................................................................185
11-1
11-2
11-3
Block Diagram of Serial Interface 20..........................................................................................................187
Bock Diagram of Baud Rate Generator 20.................................................................................................188
Format of Serial Operation Mode Register 20............................................................................................190
User’s Manual U15331EJ4V1UD
19
LIST OF FIGURES (4/6)
Figure No.
Title
Page
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
Format of Asynchronous Serial Interface Mode Register 20......................................................................191
Format of Asynchronous Serial Interface Status Register 20.....................................................................193
Format of Baud Rate Generator Control Register 20 .................................................................................194
Format of Asynchronous Serial Interface Transmit/Receive Data..............................................................204
Asynchronous Serial Interface Transmission Completion Interrupt Timing ................................................206
Asynchronous Serial Interface Reception Completion Interrupt Timing .....................................................207
Receive Error Timing..................................................................................................................................208
3-Wire Serial I/O Mode Timing...................................................................................................................214
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
Block Diagram of Serial Interface 1A0........................................................................................................217
Format of Serial Operation Mode Register 1A0 .........................................................................................220
Format of Automatic Data Transmit/Receive Control Register 0................................................................221
Format of Automatic Data Transmit/Receive Interval Specification Register 0 ..........................................222
3-Wire Serial I/O Mode Timing...................................................................................................................227
Circuit of Switching in Transfer Bit Order ...................................................................................................229
Basic Transmit/Receive Mode Operation Timing .......................................................................................236
Basic Transmit/Receive Mode Flowchart ...................................................................................................237
Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) ..................238
Basic Transmit Mode Operation Timing .....................................................................................................240
Basic Transmit Mode Flowchart .................................................................................................................241
Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode)..................................................242
Repeat Transmit Mode Operation Timing ..................................................................................................244
Repeat Transmit Mode Flowchart ..............................................................................................................245
Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) ...............................................246
Automatic Transmission/Reception Suspension and Restart.....................................................................248
Interval Time of Automatic Transmission/Reception ..................................................................................249
12-9
12-10
12-11
12-12
12-13
12-14
12-15
12-16
12-17
13-1
13-2
13-3
13-4
13-5
13-6
Correspondence with LCD Display RAM....................................................................................................251
LCD Controller/Driver Block Diagram.........................................................................................................252
Format of LCD Display Mode Register 0....................................................................................................254
Format of LCD Clock Control Register 0....................................................................................................255
Format of LCD Voltage Boost Control Register 0.......................................................................................256
Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
(When Using S16 to S27)...........................................................................................................................257
Common Signal Waveforms.......................................................................................................................259
Voltages and Phases of Common and Segment Signals...........................................................................259
Three-Time-Slice LCD Display Pattern and Electrode Connections...........................................................260
Example of Connecting Three-Time-Slice LCD Panel................................................................................261
Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) .......................................................262
13-7
13-8
13-9
13-10
13-11
20
User’s Manual U15331EJ4V1UD
LIST OF FIGURES (5/6)
Figure No.
Title
Page
13-12
13-13
13-14
13-15
Four-Time-Slice LCD Display Pattern and Electrode Connections ............................................................263
Example of Connecting Four-Time-Slice LCD Panel .................................................................................264
Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method).........................................................265
Example of Connecting Pins for LCD Driver ..............................................................................................266
14-1
14-2
14-3
Block Diagram of Multiplier ........................................................................................................................268
Format of Multiplier Control Register 0.......................................................................................................269
Multiplier Operation Timing (Example of AAH × D3H)................................................................................270
15-1
15-2
Block Diagram of Remote Controller Receiver...........................................................................................272
Operation Examples of RMSR, RMSCR, and RMDR Registers When Receiving
1010101011111111B (16 Bits)...................................................................................................................273
Format of Remote Controller Receive Control Register.............................................................................277
Example of Type A Data Format................................................................................................................279
Operation Flow of Type A Reception Mode................................................................................................280
Setting Example (Where n1 = 1, n2 = 2) ....................................................................................................284
Generation Timing of INTRERR Signal......................................................................................................286
Noise Elimination Operation Example........................................................................................................288
15-3
15-4
15-5
15-6
15-7
15-8
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
Basic Configuration of Interrupt Function...................................................................................................293
Format of Interrupt Request Flag Registers...............................................................................................295
Format of Interrupt Mask Flag Registers....................................................................................................296
Format of External Interrupt Mode Registers .............................................................................................297
Program Status Word Configuration ..........................................................................................................298
Format of Key Return Mode Register 00....................................................................................................299
Block Diagram of Falling Edge Detector ....................................................................................................299
Format of Key Return Mode Register 01....................................................................................................300
Block Diagram of Falling Edge Detector ....................................................................................................300
Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment ........................................302
Timing of Non-Maskable Interrupt Request Acknowledgment....................................................................302
Non-Maskable Interrupt Request Acknowledgment ...................................................................................302
Interrupt Request Acknowledgment Program Algorithm.............................................................................303
Interrupt Request Acknowledgment Timing (Example: MOV A, r)..............................................................304
Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated in Final
16-9
16-10
16-11
16-12
16-13
16-14
16-15
Clock Under Execution) .............................................................................................................................304
Example of Multiple Interrupt Servicing......................................................................................................305
16-16
17-1
17-2
Format of Oscillation Stabilization Time Selection Register .......................................................................308
Releasing HALT Mode by Interrupt............................................................................................................310
User’s Manual U15331EJ4V1UD
21
LIST OF FIGURES (6/6)
Figure No.
Title
Page
17-3
17-4
17-5
Releasing HALT Mode by RESET Input.....................................................................................................311
Releasing STOP Mode by Interrupt............................................................................................................313
Releasing STOP Mode by RESET Input....................................................................................................314
18-1
18-2
18-3
18-4
Block Diagram of Reset Function...............................................................................................................315
Reset Timing by RESET Input ...................................................................................................................316
Reset Timing by Overflow in Watchdog Timer ...........................................................................................316
Reset Timing by RESET Input in STOP Mode...........................................................................................316
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
Environment for Writing Program to Flash Memory....................................................................................320
Communication Mode Selection Format ....................................................................................................321
Example of Connection with Dedicated Flash Programmer .......................................................................322
VPP Pin Connection Example .....................................................................................................................324
Signal Conflict (Input Pin of Serial Interface)..............................................................................................325
Abnormal Operation of Other Device .........................................................................................................325
Signal Conflict (RESET Pin).......................................................................................................................326
Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O...............................................................327
Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O with Handshake.....................................328
Wiring Example for Flash Writing Adapter with UART................................................................................329
A-1
Development Tools ....................................................................................................................................370
B-1
B-2
B-3
B-4
B-5
B-6
Distance Between In-Circuit Emulator and Conversion Socket (80GC) .....................................................375
Connection Conditions of Target System (When NP-80GC-TQ Is Used)...................................................376
Connection Conditions of Target System (When NP-H80GC-TQ Is Used)................................................376
Distance Between In-Circuit Emulator and Conversion Adapter (80GK)....................................................377
Connection Conditions of Target System (When NP-80GK Is Used).........................................................378
Connection Conditions of Target System (When NP-H80GK-TQ Is Used) ................................................378
22
User’s Manual U15331EJ4V1UD
LIST OF TABLES (1/3)
Table No.
2-1
Title
Page
Types of Pin I/O Circuits ..............................................................................................................................45
3-1
3-2
3-3
3-4
Internal ROM Capacity.................................................................................................................................52
Vector Table.................................................................................................................................................52
Internal High-Speed RAM, Internal Low-Speed RAM Capacity....................................................................53
Special Function Registers .........................................................................................................................63
4-1
4-2
4-3
Port Functions..............................................................................................................................................76
Configuration of Port ....................................................................................................................................76
Port Mode Registers and Output Latch Settings When Using Alternate Functions......................................92
5-1
5-2
Configuration of Clock Generator.................................................................................................................95
Maximum Time Required for Switching CPU Clock ...................................................................................106
6-1
6-2
6-3
16-Bit Timer 20 Configuration ....................................................................................................................108
Interval Time of 16-Bit Timer 20.................................................................................................................113
Settings of Capture Edge...........................................................................................................................116
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
Operation Modes........................................................................................................................................120
Configuration of 8-Bit Timers 50, 60, and 61..............................................................................................122
Interval Time of Timer 50 ...........................................................................................................................135
Interval Time of Timer 60 ...........................................................................................................................135
Interval Time of Timer 61 ...........................................................................................................................135
Square-Wave Output Range of Timer 50...................................................................................................141
Square-Wave Output Range of Timer 60...................................................................................................142
Square-Wave Output Range of Timer 61...................................................................................................142
Interval Time with 16-Bit Resolution...........................................................................................................144
Square-Wave Output Range with 16-Bit Resolution...................................................................................148
8-1
8-2
8-3
Interval Time of Interval Timer ...................................................................................................................162
Configuration of Watch Timer ....................................................................................................................162
Interval Time of Interval Timer ...................................................................................................................165
9-1
9-2
9-3
9-4
9-5
Watchdog Timer Program Loop Detection Time........................................................................................167
Interval Time ..............................................................................................................................................167
Configuration of Watchdog Timer...............................................................................................................168
Watchdog Timer Program Loop Detection Time........................................................................................171
Interval Time of Interval Timer ...................................................................................................................172
User’s Manual U15331EJ4V1UD
23
LIST OF TABLES (2/3)
Table No.
10-1
Title
Page
Configuration of 10-Bit A/D Converter........................................................................................................173
11-1
11-2
11-3
11-4
11-5
11-6
11-7
Configuration of Serial Interface 20............................................................................................................186
Serial Interface 20 Operation Mode Settings..............................................................................................192
Example of Relationship Between System Clock and Baud Rate ..............................................................195
Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H).......196
Example of Relationship Between System Clock and Baud Rate ..............................................................203
Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H).......203
Receive Error Causes ................................................................................................................................208
12-1
12-2
Configuration of Serial Interface 1A0..........................................................................................................217
Timing of Interrupt Request Signal Generation ..........................................................................................249
13-1
13-2
13-3
13-4
13-5
13-6
13-7
Maximum Number of Display Pixels...........................................................................................................250
Configuration of LCD Controller/Driver.......................................................................................................250
Frame Frequencies (Hz) ............................................................................................................................255
COM Signals..............................................................................................................................................258
Select and Deselect Voltages (COM0 to COM2) .......................................................................................260
Select and Deselect Voltages (COM0 to COM3) .......................................................................................263
Output Voltages of VLC0 to VLC2 Pins..........................................................................................................265
15-1
15-2
Remote Controller Receiver Configuration.................................................................................................271
Noise Elimination Width .............................................................................................................................287
16-1
16-2
16-3
16-4
Interrupt Sources (µPD789488, 78F9488) .................................................................................................291
Interrupt Sources (µPD789489, 78F9489) .................................................................................................292
Flags Corresponding to Interrupt Request Signal Names ..........................................................................294
Time from Generation of Maskable Interrupt Request to Servicing............................................................303
17-1
17-2
17-3
17-4
Operation Statuses in HALT Mode.............................................................................................................309
Operation After Releasing HALT Mode......................................................................................................311
Operation Statuses in STOP Mode............................................................................................................312
Operation After Releasing STOP Mode .....................................................................................................314
18-1
Status of Hardware After Reset..................................................................................................................317
19-1
19-2
19-3
Differences Between µPD78F9488, 78F9489, and Mask ROM Version ....................................................319
Communication Mode List..........................................................................................................................321
Pin Connection List ....................................................................................................................................323
24
User’s Manual U15331EJ4V1UD
LIST OF TABLES (3/3)
Table No.
21-1
Title
Page
Operand Identifiers and Description Methods ............................................................................................332
Surface Mounting Type Soldering Conditions ............................................................................................366
Distance Between IE System and Conversion Adapter..............................................................................375
25-1
B-1
User’s Manual U15331EJ4V1UD
25
CHAPTER 1 GENERAL
1.1 Features
•
ROM and RAM capacities
Item
Program Memory
(ROM)
Data Memory
LCD Display RAM
Internal RAM
Part Number
µPD789488
µPD78F9488
µPD789489
µPD78F9489
Mask ROM
32 KB
48 KB
1024 bytes
28 × 4 bits
Flash memory
Mask ROM
1536 bytes
Flash memory
•
•
Minimum instruction execution time can be selected from high speed (0.4 µs: @5.0 MHz operation with main
system clock), low speed (1.6 µs: @5.0 MHz operation with main system clock), and ultra low speed (122 µs:
@32.768 kHz operation with subsystem clock)
A circuit to multiply the subsystem clock by 4 is selectable (15.26 µs: @131 kHz operation: 32.768 kHz subsystem
clock × 4)
•
•
•
•
•
I/O ports: 45 (N-ch open-drain: 4)
Timer: 6 channels
Serial interface: 2 channels
10-bit resolution A/D converter: 8 channels
LCD controller/driver (on-chip voltage booster)
Segment signals: 28, common signals: 4
•
•
•
On-chip multiplier: 8 bits × 8 bits = 16 bits
On-chip infrared remote controller receiver (µPD789489, 78F9489 only)
On-chip key return signal detector
•
Supply voltage: VDD = 1.8 to 5.5 V
1.2 Applications
CD radio-cassette players, portable audio, compact cameras, healthcare equipment, etc.
26
User’s Manual U15331EJ4V1UD
CHAPTER 1 GENERAL
1.3 Ordering Information
Part Number
Package
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
80-pin plastic QFP (14 × 14)
Internal ROM
Mask ROM
Mask ROM
Flash memory
Flash memory
Mask ROM
µPD789488GC-×××-8BT
µPD789488GK-×××-9EU
µPD78F9488GC-8BT
µPD78F9488GK-9EU
µPD789489GC-×××-8BT
µPD789489GK-×××-9EU
µPD78F9489GC-8BT
Mask ROM
Flash memory
Flash memory
Mask ROM
µPD78F9489GK-9EU
µPD789488GC-×××-8BT-A
µPD789488GK-×××-9EU-A
µPD78F9488GC-8BT-A
µPD78F9488GK-9EU-A
µPD789489GC-×××-8BT-A
µPD789489GK-×××-9EU-A
µPD78F9489GC-8BT-A
µPD78F9489GK-9EU-A
Mask ROM
Flash memory
Flash memory
Mask ROM
Mask ROM
Flash memory
Flash memory
80-pin plastic TQFP (fine pitch) (12 × 12)
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by "-A" are lead-free products.
User’s Manual U15331EJ4V1UD
27
CHAPTER 1 GENERAL
1.4 Pin Configuration (Top View)
(1) µPD789488, 78F9488
80-pin plastic QFP (14 × 14)
µPD789488GC-×××-8BT
µPD78F9488GC-8BT
µPD789488GC-×××-8BT-A
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789488GK-×××-9EU
µPD78F9488GC-8BT-A
µPD78F9488GK-9EU
µPD789488GK-×××-9EU-A
µPD78F9488GK-9EU-A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
CAPH
CAPL
1
2
3
4
5
6
7
8
9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P10
P11
V
V
V
LC2
LC1
LC0
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/SCK10
COM0
COM1
COM2
COM3
S0
P24/SO10
P25/SI10
P30/INTP0/TO50/TMI60
P31/INTP1/TO60
P32/INTP2/TMI61/TO61
P33/INTP3/CPT20/TO20
P34/RIN
10
11
12
13
14
15
16
17
18
19
20
S1
S2
S3
S4
AVSS
S5
P60/ANI0/KR10
P61/ANI1/KR11
P62/ANI2/KR12
P63/ANI3/KR13
P64/ANI4/KR14
P65/ANI5/KR15
S6
S7
S8
S9
S10
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Notes 1. Whether to use these pins as input port pins (P70 to P73) or segment outputs (S16 to S19) can be
selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) Port function
registers and CHAPTER 20 MASK OPTIONS).
2. Whether to use these pins as I/O port pins (P80 to P87) or segment outputs (S20 to S27) can be
selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) Port function
registers and CHAPTER 20 MASK OPTIONS).
28
User’s Manual U15331EJ4V1UD
CHAPTER 1 GENERAL
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
Remark The parenthesized values apply to the µPD78F9488
(2) µPD789489, 78F9489
80-pin plastic QFP (14 × 14)
µPD789489GC-×××-8BT
µPD789489GC-×××-8BT-A
µPD78F9489GC-8BT
µPD78F9489GC-8BT-A
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD789489GK-×××-9EU
µPD78F9489GK-9EU
µPD789489GK-×××-9EU-A
µPD78F9489GK-9EU-A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
CAPH
CAPL
1
2
3
4
5
6
7
8
9
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P10
P11
V
V
V
LC2
LC1
LC0
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/SCK10
COM0
COM1
COM2
COM3
S0
P24/SO10
P25/SI10
P30/INTP0/TO50/TMI60
P31/INTP1/TO60
P32/INTP2/TMI61/TO61
P33/INTP3/CPT20/TO20
P34/RIN
10
11
12
13
14
15
16
17
18
19
20
S1
S2
S3
S4
AVSS
S5
P60/ANI0/KR10
P61/ANI1/KR11
P62/ANI2/KR12
P63/ANI3/KR13
P64/ANI4/KR14
P65/ANI5/KR15
S6
S7
S8
S9
S10
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
User’s Manual U15331EJ4V1UD
29
CHAPTER 1 GENERAL
Notes 1. Whether to use these pins as input port pins (P70 to P73) or segment outputs (S16 to S19) can be
selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) Port function
registers and CHAPTER 20 MASK OPTIONS).
2. Whether to use these pins as I/O port pins (P80 to P87) or segment outputs (S20 to S27) can be
selected in 1-bit units by means of a mask option or port function register (refer to 4.3 (3) Port function
registers and CHAPTER 20 MASK OPTIONS).
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
Remark The parenthesized values apply to the µPD78F9489.
Pin Name
ANI0 to ANI7:
ASCK20:
AVDD:
Analog input
RESET:
RIN:
Reset
Asynchronous serial input
Analog power supply
Analog ground
Remote control input
Receive data
RxD0:
AVSS:
S0 to S27:
SCK10:
SI10:
Segment output
Serial clock input/output
Serial data input
Serial data output
Serial block input/output
Serial data input
Serial data output
Timer input
CAPH, CAPL:
LCD power supply capacitance
control
COM0 to COM3: Common output
SO10:
CPT20:
IC0:
Capture trigger input
Internally connected
SCK20:
SI20:
INTP0 to INTP3: External interrupt input
SO20:
KR0 to KR7:
KR00 to KR07:
KR10 to KR17:
P00 to P07:
P10, P11:
Key return
Key return
Key return
Port 0
TMI60, 61:
TO20,50,60,61: Timer output
TxD0:
Transmit data
VDD:
Power supply
Port 1
VLC0 to VLC2:
VPP:
Power supply for LCD
Programming power supply
Ground
P20 to P25:
P30 to P34:
P60 to P67:
P70 to P73:
P80 to P87:
Port 2
Port 3
VSS:
Port 6
X1, X2:
XT1, XT2:
Crystal (Main system clock)
Crystal (Subsystem clock)
Port 7
Port 8
30
User’s Manual U15331EJ4V1UD
CHAPTER 1 GENERAL
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y Subseries products support SMB.
Small-scale package, general-purpose applications
µ
PD789074 with added subsystem clock
44-pin
PD789046
PD789026
PD789088
µ
µ
µ
µ
µ
On-chip UART and capable of low voltage (1.8 V) operation
42-/44-pin
30-pin
µ
µ
PD789074 with enhanced timer and increased ROM, RAM capacity
PD789026 with enhanced timer
30-pin
20-pin
20-pin
PD789074
PD789062
RC oscillation version of the
µ
PD789052
µ
PD789052
µ
PD789860 without EEPROM, POC, and LVI
Small-scale package, general-purpose applications and A/D converter
µ
µ
PD789177Y
PD789167Y
µ
µ
µ
PD789167 with enhanced A/D converter (10 bits)
PD789104A with enhanced timer
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
µ
µ
µ
µ
µ
PD789177
PD789167
PD789134A
PD789124A
PD789114A
PD789104A
PD789124A with enhanced A/D converter (10 bits)
RC oscillation version of the
µ
PD789104A
PD789104A with enhanced A/D converter (10 bits)
PD789026 with added 8-bit A/D converter and multiplier
µ
µ
µ
LCD drive
144-pin
88-pin
80-pin
µ
µ
µ
µ
PD789835B
PD789830
PD789489
PD789479
UART, 8-bit A/D, and dot LCD (Total display output pins: 96)
UART and dot LCD (40 × 16)
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4)
SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
80-pin
80-pin
PD789407A with enhanced A/D converter (10 bits)
SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
PD789446 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 × 4)
PD789426 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 × 4)
RC oscillation version of the PD789306
µ
PD789417A
PD789407A
µ
µ
78K/0S
Series
80-pin
64-pin
64-pin
64-pin
64-pin
µ
µ
µ
µ
µ
µ
µ
PD789456
PD789446
PD789436
PD789426
PD789316
PD789306
PD789467
µ
µ
µ
64-pin
64-pin
52-pin
52-pin
SIO and on-chip voltage booster type LCD (24 × 4)
8-bit A/D and on-chip voltage booster type LCD (23 × 4)
SIO and resistance division type LCD (24 × 4)
µ
PD789327
USB
44-pin
44-pin
µ
PD789800
For PC keyboard and on-chip USB function
On-chip inverter controller and UART
Inverter control
µ
PD789842
On-chip bus controller
µ
PD789850A with enhanced functions such as timer and A/D converter
µ
µ
PD789852
44-pin
30-pin
PD789850A
On-chip CAN controller
Keyless entry
30-pin
20-pin
20-pin
PD789862
PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity
µ
µ
µ
µ
RC oscillation version of the
µ
PD789860
PD789861
PD789860
On-chip POC and key return circuit
Sensor
PD789864
PD789863
On-chip analog macro for sensor
µ
20-pin
20-pin
RC oscillation version of the PD789864
µ
µ
VFD drive
µ
52-pin
PD789871
Meter control
PD789881
On-chip VFD controller (Total display output pins: 25)
µ
UART and resistance division type LCD (26 × 4)
64-pin
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
User’s Manual U15331EJ4V1UD
31
CHAPTER 1 GENERAL
The major functional differences between the subseries are listed below.
Series for General-purpose applications and LCD drive
Function
ROM
Capacity
Timer
8-Bit 10-Bit
A/D A/D
Serial
Interface
I/O
VDD
Remarks
8-Bit 16-Bit Watc WDT
h
MIN.
Value
Subseries Name
Small-scale µPD789046 16 KB
1 ch 1 ch 1 ch 1 ch
−
−
1 ch
(UART: 1 ch)
34
24
1.8 V
−
package,
general-
purpose
µPD789026 4 KB to 16 KB
−
µPD789088 16 KB to
3 ch
32 KB
applications
µPD789074 2 KB to 8 KB 1 ch
µPD789062 4 KB
2 ch
−
−
14
RC oscillation
version
µPD789052
−
−
Small-scale µPD789177 16 KB to
3 ch 1 ch 1 ch 1 ch
−
8 ch
−
8 ch 1 ch
31
20
1.8 V
package,
general-
purpose
applications
and A/D
converter
24 KB
(UART: 1 ch)
µPD789167
−
4 ch
−
µPD789134A 2 KB to 8 KB 1 ch
µPD789124A
−
RC oscillation
version
4 ch
−
µPD789114A
4 ch
−
−
µPD789104A
4 ch
LCD drive
µPD789835B 24 KB to
6 ch
−
1 ch 1 ch 3 ch
−
1 ch
(UART: 1 ch)
37 1.8 VNote Dot LCD
supported
60 KB
µPD789830 24 KB
1 ch 1 ch
3 ch
−
30
45
2.7 V
1.8 V
µPD789489 32 KB to
8 ch 2 ch
(UART: 1 ch)
−
48 KB
µPD789479 24 KB to
8 ch
−
48 KB
µPD789417A 12 KB to
−
7 ch
−
7 ch 1 ch
43
30
40
23
24 KB
(UART: 1 ch)
µPD789407A
−
6 ch
−
µPD789456 12 KB to
2 ch
16 KB
µPD789446
6 ch
−
µPD789436
6 ch
−
µPD789426
6 ch
−
µPD789316 8 KB to 16 KB
2 ch
RC oscillation
version
(UART: 1 ch)
µPD789306
−
µPD789467 4 KB to 24 KB
µPD789327
−
1 ch
−
18
21
−
1 ch
Note Flash memory version: 3.0 V
32
User’s Manual U15331EJ4V1UD
CHAPTER 1 GENERAL
Series for ASSP
Subseries Name
Function
ROM
Capacity
Timer
8-Bit 10-Bit
A/D A/D
Serial
Interface
I/O
VDD
Remarks
8-Bit 16-Bit Watc WDT
h
MIN.
Value
USB
µPD789800
8 KB
2 ch
−
−
1 ch
−
−
−
2 ch
(USB: 1 ch)
31
30
31
18
14
4.0 V
4.0 V
4.0 V
−
−
−
Inverter
control
µPD789842
8 KB to 16 KB 3 ch
1 ch 1 ch 8 ch
1 ch
(UART: 1 ch)
Note 1
On-chip bus µPD789852
controller
24 KB to
32 KB
3 ch 1 ch
1 ch
−
1 ch
−
4 ch
−
8 ch 3 ch
(UART: 2 ch)
µPD789850A 16 KB
−
2 ch
(UART: 1 ch)
Keyless
entry
µPD789861
4 KB
2 ch
−
−
1 ch
−
−
1.8 V RC oscillation
version, on-
chip EEPROM
µPD789860
µPD789862
On-chip
EEPROM
16 KB
4 KB
1 ch 2 ch
1 ch
(UART: 1 ch)
22
5
Sensor
µPD789864
µPD789863
1 ch
−
1 ch
−
4 ch
−
1.9 V On-chip
EEPROM
Note 2
RC oscillation
version, on-
chip EEPROM
VFD drive
µPD789871
µPD789881
4 KB to 8 KB 3 ch
16 KB
−
1 ch 1 ch
1 ch
−
−
−
−
1 ch
33
2.7 V
−
−
Meter
control
2 ch 1 ch
−
1 ch
(UART: 1 ch)
28 2.7 VNote
3
Notes 1. 10-bit timer: 1 channel
2. 12-bit timer: 1 channel
3. Flash memory version: 3.0 V
User’s Manual U15331EJ4V1UD
33
CHAPTER 1 GENERAL
1.6 Block Diagram
P00 to P07
P10 to P11
P20 to P25
P30 to P34
CPT20/TO20/P33
TO50/P30
Port 0
Port 1
Port 2
Port 3
16-bit timer 20
8-bit timer 50
TMI60/P30
TO60/P31
8-bit timer/
event counter 60
8-bit timer/
event counter 61
TMI61/TO61/P32
Port 5
Port 6
Port 7
Port 8
P50 to P53
Watch timer
ROM
78K/0S
(flash
P60 to P67
Watchdog timer
CPU core
memory)
SCK20/ASCK20/P20
SO20/TxD20/P21
SI20/RxD20/P22
P70 to P73Note 1
P80 to P87Note 2
Serial
interface 20
SCK10/P23
SO10/P24
SI10/P25
Serial
interface 1A0
RAM space
for LCD
data
RAM
Interrupt
control
INTP0/P30 to
INTP3/P33
Remote control
Note 4RIN/P34
signal receiverNote 4
Standby
control
Note 3KR0/P00 to
KR7/P07
Note 4KR00/P00 to
KR07/P07
Note 4KR10/ANI0/P60 to
KR17/ANI7/P67
Key return
RESET
X1
System
control
X2
XT1
XT2
ANI0/P60 to
ANI7/P67
A/D converter
AVDD
AVSS
Multiplier
S0 to S15
Note 1S16 to S19
Note 2S20 to S27
LCD
controller/driver
COM0 to COM3
V
LC0 to VLC2
CAPH
V
DD
V
SS IC0
(VPP
)
CAPL
Notes 1. Whether to use these pin as input ports (P70 to P73) or segment outputs (S16 to S19) can be selected
in 1-bit units by means of a mask option in the µPD789488, 789489 or a port mode register in the
µPD78F9488, 78F9489 (refer to 4.3 (3) Port function registers and CHAPTER 20 MASK OPTIONS).
2. Whether to use these pins as I/O port pins (P80 to P87) or segment outputs (S20 to S27) can be
selected in 1-bit units by means of a mask option in the µPD789488 or a port mode register in the
µPD78F9488, 78F9489 (refer to 4.3 (3) Port function registers and CHAPTER 20 MASK OPTIONS).
3. When µPD789488, 78F9488 is used.
4. When µPD789489, 78F9489 is used.
Remark The parenthesized values apply to the flash memory version.
34
User’s Manual U15331EJ4V1UD
CHAPTER 1 GENERAL
1.7 Overview of Functions
(1/2)
Item
µPD789488
µPD78F9488
µPD789489
48 KB
µPD78F9489
48 KB (flash
memory)
Internal memory
ROM
32 KB
32 KB (flash
memory)
High-speed RAM
Low-speed RAM
LCD display RAM
1024 bytes
−
512 bytes
28 bytes
Main system clock
Ceramic/crystal oscillation (1.0 to 5.0 MHz)
(oscillation frequency)
Subsystem clock
Crystal oscillation (32.768 kHz)
(oscillation frequency)
Minimum instruction execution time
0.4 µs/1.6 µs (@5.0 MHz operation with main system clock)
122 µs (@32.768 kHz operation with subsystem clock)
15.26 µs (@131 kHz operation with ×4 subsystem clock)
Subsystem clock multiplication function
General-purpose registers
Instruction set
×4 multiplication circuit (operating supply voltage: VDD = 2.7 to 5.5 V)Note 1
8 bits × 8 registers
•
•
16-bit operations
Bit manipulation (set, reset, test) etc.
Multiplier
I/O ports
8 bits × 8 bits = 16 bits
Total:
CMOS I/O:
45Note 2
29
CMOS input:
N-ch open-drain I/O:
12
4
Timers
•
•
•
•
16-bit timer:
8-bit timer:
Watch timer:
1 channel
3 channels
1 channel
Watchdog timer: 1 channel
Timer outputs
Serial interface
4
UART/3-wire serial I/O mode: 1 channel
3-wire serial I/O mode (with automatic transfer function): 1 channel
A/D converter
10-bit resolution × 8 channels
LCD controller/driver
•
•
Segment signal outputs: 28Note 3
Common signal outputs:
4
Power supply method for LCD drive
Internal voltage amplification method
Infrared remote control reception function Not provided
Provided
Key return detection function
8 pins
16 pins
Vectored interrupt
sources
Maskable
Non-maskable
Internal: 11, External: 5
Internal: 1
Internal: 16, External: 6
Reset
•
•
Reset by RESET signal input
Internal reset by watchdog timer
Notes 1. Whether a circuit to multiply the clock by 4 is used or not is selected by a mask option or the subclock
selection register.
2. 12 pins are used either as a port function or LCD segment output selected by a mask option or port
function register.
User’s Manual U15331EJ4V1UD
35
CHAPTER 1 GENERAL
(2/2)
Item
µPD789488
µPD78F9488
µPD789489
µPD78F9489
Supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
Package
TA = −40 to +85°C
•
•
80-pin plastic QFP (14 × 14)
80-pin plastic TQFP (fine pitch) (12 × 12)
An outline of the timer is shown below.
16-Bit
Timer 20
8-Bit
Timer 50
8-Bit
Timer 60
8-Bit
Timer 61
Watch
Timer
Watchdog
Timer
Operation
mode
Interval timer
−
1 channel
1 channel
1 channel
1 channelNote 1 channelNote
1
2
External event
counter
−
−
1 channel
1 channel
−
−
Function
Timer outputs
1 output
1 output
1 output
1 output
1 output
1 output
1 output
−
−
−
−
Square-wave
outputs
−
Capture
1 input
1
−
−
−
−
−
Interrupt sources
1
1
1
2
2
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer
by selecting either the watchdog timer function or interval timer function.
36
User’s Manual U15331EJ4V1UD
CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
(1) Port pins (1/2)
Pin Name
I/O
I/O
Function
After Reset
Input
Alternate Function
P00 to P07
Port 0.
8-bit I/O port.
KR0 to KR7Note 1
KR00 to KR07Note 2
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register B0
(PUB0) or the key return mode register (KRM00).
P10, P11
I/O
I/O
Port 1.
2-bit I/O port.
Input
Input
−
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register B1
(PUB1).
P20
Port 2.
6-bit I/O port.
SCK20/ASCK20
SO20/TxD20
SI20/RxD20
SCK10
P21
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register B2
(PUB2).
P22
P23
P24
SO10
P25
SI10
P30
I/O
Port 3.
5-bit I/O port.
Input
INTP0/TO50/TMI60
INTP1/TO60
INTP2/TMI61/TO61
INTP3/CPT20/TO20
RINNote 2
P31
Input/output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistors can be
specified in 1-bit units by pull-up resistor option register B3
(PUB3).
P32
P33
P34
P50 to P53
I/O
Port 5.
Input
Input
−
4-bit N-ch open-drain I/O port.
Input/output can be specified in 1-bit units.
For mask ROM version, an on-chip pull-up resistor can be
specified by mask option.
P60 to P67
Input
Port 6.
8-bit input port.
ANI0 to ANI7Note 1
ANI0/KR10 to
ANI7/KR17Note 2
Notes 1. µPD789488 and 78F9488 only
2. µPD789489 and 78F9489 only
User’s Manual U15331EJ4V1UD
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CHAPTER 2 PIN FUNCTIONS
(1) Port pins (2/2)
Pin Name
P70 to P73Note 1
I/O
Input
Function
After Reset
Input
Alternate Function
Port 7.
−
4-bit input port.
(Only when input port is selected by mask option or port
function register)
P80 to P87Note 2
I/O
Port 8.
8-bit I/O port.
Input
−
(Only when I/O port is selected by mask option or port function
register)
Notes 1. Whether to use these pins as input port pins (P70 to P73) or segment outputs (S16 to S19) can be
selected in 1-bit units by means of a mask option in the µPD789488, 789489 or a port mode register in
the µPD78F9488, 78F9489 (refer to 4.3 (3) Port function registers and CHAPTER 20 MASK
OPTIONS).
2. Whether to use these pins as I/O port pins (P80 to P87) or segment outputs (S20 to S27) can be
selected in 1-bit units by means of a mask option in the µPD789488, 789489 or a port mode register in
the µPD78F9488, 78F9489 (refer to 4.3 (3) Port function registers and CHAPTER 20 MASK
OPTIONS).
(2) Non-port pins (1/2)
Pin Name
INTP0
I/O
Function
After Reset
Alternate Function
P30/TO50/TMI60
P31/TO60
Input
External interrupt input for which the valid edge (rising edge, falling Input
edge, or both rising and falling edges) can be specified.
INTP1
INTP2
INTP3
P32/TMI61/TO61
P33/CPT20/TO20
P00 to P07
KR0 to KR7Note 1 Input
Key return signal detection
Key return signal detection
Input
Input
KR00 to
Input
P00 to P07
KR07Note 2
KR10 to
P60/ANI0 to
P67/ANI7
KR17Note 2
TO20
Output 16-bit timer 20 output
Output Capture edge input of 16-bit timer 20
Output 8-bit timer 50 output
Input
Input
Input
Input
Input
Input
Input
Input
P33/INTP3/CPT20
P33/INTP3/TO20
P30/INTP0/TMI60
P31/INTP1
P32/INTP2/TMI61
P30/INTP0/TO50
P32/INTP2/TO61
P20/ASCK20
P23
CPT20
TO50
TO60
Output 8-bit timer 60 output
TO61
Output 8-bit timer 61 output
TMI60
TMI61
SCK20
SCK10
SO20
Input
Input
I/O
External count clock input to 8-bit timer 60
External count clock input to 8-bit timer 61
Serial clock input/output of serial interface
Output Serial data output of serial interface
Input
Input
P21/TxD20
P24
SO10
SI20
Input
Input
Serial data input of serial interface
P22/RxD20
P25
SI10
ASCK20
TxD20
RxD20
RINNote 2
Serial clock input of asynchronous serial interface
Input
Input
Input
Input
P20/SCK20
P21/SO20
Output Serial data output of asynchronous serial interface
Input
Input
Serial data input of asynchronous serial interface
Remote control reception data input
P22/SI20
P34
Notes 1. µPD789488 and 78F9488 only
2. µPD789489 and 78F9489 only
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins (2/2)
Pin Name
S0 to S15
I/O
Function
After Reset
Alternate Function
–
Output LCD controller/driver segment signal outputs
Low-level
output
S16 to S19Note 1
S20 to S27Note 2
Only when segment output is selected by
–
–
–
mask option
Only when segment output is selected by
mask option
COM0 to COM3 Output LCD controller/driver common signal outputs
Low-level
output
VLC0 to VLC2
–
−
–
LCD drive voltage
–
–
–
–
–
CAPH, CAPL
ANI0 to ANI7
LCD drive voltage booster capacitor connection pin
A/D converter analog input
P60 to P67Note 3
P60/KR10 to
P67/KR17Note 4
AVSS
AVDD
X1
–
A/D converter ground potential
–
–
–
–
–
–
–
–
–
–
–
–
–
A/D converter analog power supply
–
Input
Connecting crystal resonator for main system clock oscillation
–
X2
–
–
XT1
XT2
RESET
VDD
Input
Connecting crystal resonator for subsystem clock oscillation
–
–
–
Input
System reset input
Input
–
–
–
–
Positive power supply
–
–
–
–
VSS
Ground potential
IC0
Internally connected. Connect directly to VSS.
VPP
Sets flash memory programming mode. Used to apply high
voltage when a program is written or verified.
Notes 1. Whether to use these pins as input ports pins (P70 to P73) or segment outputs (S16 to S19) can be
selected in 1-bit units by means of a mask option in the µPD789488, 789489 or a port mode register in
the µPD78F9488, 78F9489 (refer to 4.3(3) Port function registers and CHAPTER 20 MASK
OPTIONS).
2. Whether to use these pins as I/O port pins (P80 to P87) or segment outputs (S20 to S27) can be
selected in 1-bit units by means of a mask option in the µPD789488, 789489 or a port mode register in
the µPD78F9488, 78F9489 (refer to 4.3(3) Port function registers and CHAPTER 20 MASK
OPTIONS).
3. µPD789488 and 78F9488 only
4. µPD789489 and 78F9489 only
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CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 to P07 (Port 0)
These pins constitute an 8-bit I/O port. In addition, these pins enable key return signal detection.
Port 0 can be specified in the following operation modes in 1-bit units.
(1) Port mode
These pins constitute an 8-bit I/O port and can be set in the input or output port mode in 1-bit units by port
mode register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register B0 (PUB0) in 1-bit units.
(2) Control mode
In this mode, P00 to P07 function as key return signal detection pins (KR0 to KR7 (µPD789488, 78F9488),
KR00 to KR07 (µPD789489, 78F9489)).
2.2.2 P10, P11 (Port 1)
These pins constitute a 2-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode
register 1 (PM1). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor
option register B1 (PUB1) in 1-bit units.
2.2.3 P20 to P25 (Port 2)
These pins constitute a 6-bit I/O port. In addition, these pins enable serial interface data I/O and serial clock I/O.
Port 2 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, P20 to P25 function as a 6-bit I/O port. Port 2 can be set in the input or output port mode in 1-
bit units by port mode register 2 (PM2). When used as an input port, use of an on-chip pull-up resistor can
be specified by pull-up resistor option register B2 (PUB2) in 1-bit units.
(2) Control mode
In this mode, P20 to P25 function as the serial interface data I/O and serial clock I/O.
(a) SI20, SO20, SI10, SO10
These are the serial data I/O pins of the serial interface.
(b) SCK20, SCK10
These are the serial clock I/O pins of the serial interface.
(c) RxD20, TxD20
These are the serial data I/O pins of the asynchronous serial interface.
(d) ASCK20
This is the serial clock input pin of the asynchronous serial interface.
Caution When using P20 to P25 as serial interface pins, the I/O mode and output latch must be set
according to the functions to be used. For the details of the setting, refer to Table 11-2 Serial
Interface 20 Operation Mode Setting and 12.3 (1) Serial operation mode register 1A0 (CSIM1A0).
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CHAPTER 2 PIN FUNCTIONS
2.2.4 P30 to P34 (Port 3)
These pins constitute a 5-bit I/O port. In addition, they also function as timer I/O, external interrupt input, and
remote control receive data inputNote
.
Port 3 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, P30 to P34 function as a 5-bit I/O port. Port 3 can be set in the input or output port mode in 1-
bit units by port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can
be specified by pull-up resistor option register B3 (PUB3) in 1-bit units.
(2) Control mode
In this mode, P30 to P34 function as timer I/O, external interrupt input, and remote control receive data
inputNote
.
(a) TMI60, TMI61
These are the external clock input pins of timers 60 and 61.
(b) TO20, TO50, TO60, TO61
These are the timer output pins of timers 20, 50, 60, and 61.
(c) CPT20
This is the capture edge input pin of 16-bit timer 20.
(d) INTP0 to INTP3
These are external interrupt input pins for which valid edges (rising edge, falling edge, or both rising and
falling edges) can be specified.
(e) RINNote
This is the data input pin of the remote controller receiver.
Note µPD789489 and 78F9489 only
2.2.5 P50 to P53 (Port 5)
These pins constitute as a 4-bit N-ch open-drain I/O port. Port 5 can be set in the input or output port mode in 1-
bit units by port mode register 5 (PM5). In the mask ROM version, use of an on-chip pull-up resistor can be specified
by a mask option in 1-bit units.
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CHAPTER 2 PIN FUNCTIONS
2.2.6 P60 to P67 (Port 6)
This is an 8-bit input-only port. In addition to a general-purpose input port function, it has A/D converter input and
key return signal detectionNote functions.
(1) Port mode
In this mode, P60 to P67 function as an 8-bit input-only port.
(2) Control mode
In this mode, P60 to P67 function as the analog inputs of the A/D converter and key return signal detection
pinsNote
.
(a) ANI0 to ANI7
These are the analog input pins of the A/D converter.
(b) KR10 to KR17Note
These are the key return signal detection pins.
Note µPD789489 and 78F9489 only
2.2.7 P70 to P73 (Port 7)
These pins constitute a 4-bit input-only port. This port can be used only when the port function is selected by a
mask option in the µPD789488, 789489 or by a port function register in the µPD78F9488, 78F9489.
2.2.8 P80 to P87 (Port 8)
These pins constitute an 8-bit I/O port. Port 8 can be set in the input or output mode in 1-bit units by port mode
register 8 (PM8). This port can be used only when the port function is selected by a mask option in the µPD789488,
789489 or by a port function register in the µPD78F9488, 78F9489.
2.2.9 S0 to S27Note
These pins are the segment signal output pins for the LCD controller/driver.
Note Pins S16 through S27 can be used only when segment output is selected by a mask option in the
µPD789488, 789489 or by a port function register in the µPD78F9488, 78F9489.
2.2.10 COM0 to COM3
These pins are the common signal output pins for the LCD controller/driver.
2.2.11 VLC0 to VLC2
These pins are the power supply voltage pins for driving the LCD.
2.2.12 CAPH, CAPL
These pins are the capacitor connection pins for driving the LCD.
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CHAPTER 2 PIN FUNCTIONS
2.2.13 RESET
This pin inputs an active-low system reset signal.
2.2.14 X1, X2
These pins are used to connect a crystal resonator for main system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
2.2.15 XT1, XT2
These pins are used to connect a crystal resonator for subsystem clock oscillation.
To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.
2.2.16 AVDD
This is the analog power supply pin of the A/D converter. Always use the same potential as that of the VDD pin even
when the A/D converter is not used.
2.2.17 AVSS
This is the ground potential pin of the A/D converter. Always use the same potential as that of the VSS pin even
when the A/D converter is not used.
2.2.18 VDD
This is the positive power supply pin.
2.2.19 VSS
This is the ground pin.
2.2.20 VPP (flash memory version only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Handle the pins in either of the following ways.
• Independently connect a 10 kΩ pull-down resistor.
• Switch this pin to be directly connected to the dedicated flash programmer in programming mode or to VSS in
normal operation mode using a jumper on the board.
If the wiring between the VPP pin and VSS pin is very long or external noise is superimposed on the VPP pin, the
user program may not run correctly.
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2.2.21 IC0 (mask ROM version only)
The IC0 (Internally Connected) pin is used to set the µPD789489 Subseries in the test mode before shipment. In
the normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as possible.
If there is a potential difference between the IC0 pin and VSS pin due to a long wiring length or external noise
superimposed on the IC0 pin, the user program may not run correctly.
• Directly connect the IC0 pin to the VSS pin.
V
SS IC0
Keep short
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the I/O circuit configuration of each type, see Figure 2-1.
Table 2-1. Types of Pin I/O Circuits (1/2)
Pin Name
P00/KR0 to P07/KR7Note 1
P00/KR00 to P07/KR07Note 2
P10, P11
I/O Circuit Type
8-A
I/O
I/O
Recommended Connection of Unused Pins
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
5-A
8-A
5-A
8-A
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/SCK10
P24/SO10
5-A
8-A
P25/SI10
P30/INTP0/TO50/
TMI60
Input:
Output: Leave open.
Independently connect to VSS via a resistor.
P31/INTP1/TO60
P32/INTP2/TO61/
TMI61
P33/INTP3/CPT20/
TO20
P34Note 1
P34/RINNote 2
P50 to P53
(mask ROM version)
13-W
13-V
9-C
Input:
Output: Leave open.
Independently connect to VDD via a resistor.
P50 to P53
(flash memory version)
P60/ANI0 to P67/ANI7Note 1
Input
Connect to VDD or VSS.
P60/ANI0/KR10 to
P67/ANI7/KR17Note 2
P70 to P73Note 3
P80 to P87Note 3
2-H
5-K
I/O
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
COM0 to COM3
S0 to S15
18
17
Output
Leave open.
S16 to S19Note 4
S20 to S27Note 4
CAPH, CAPL
VLC0 to VLC2
AVDD
–
–
Connect directly to VDD
Connect directly to VSS
AVSS
Notes 1. When µPD789488, 78F9488 is used.
2. When µPD789489, 78F9489 is used.
3. Only when port pin is selected by mask option or port function register.
4. Only when segment output pin is selected by mask option or port function register.
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CHAPTER 2 PIN FUNCTIONS
Table 2-1. Types of Pin I/O Circuits (2/2)
Pin Name
I/O Circuit Type
I/O
Input
–
Recommended Connection of Unused Pins
XT1
XT2
–
Connect to VSS.
Leave open.
RESET
IC0
2
–
Input
–
–
Connect directly to VSS.
VPP
Independently connect a 10 kΩ pull-down resistor, or connect
directly to VSS.
Figure 2-1. I/O Circuit Types (1/2)
Type 2
Type 2-H
IN
IN
Input
enable
Schmitt-triggered input with hysteresis characteristics.
Type 5-A
Type 5-K
V
DD
V
DD
Pull-up
enable
P-ch
Data
P-ch
V
DD
IN/OUT
Data
P-ch
Output
disable
N-ch
IN/OUT
Output
disable
N-ch
V
SS
Input
enable
Input
enable
Type 8-A
Type 9-C
VDD
Comparator
P-ch
N-ch
Pull-up
enable
P-ch
IN
+
VDD
AVSS
V
REF
Data
P-ch
(Threshold voltage)
IN/OUT
Output
disable
N-ch
V
SS
Input
enable
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. I/O Circuit Types (2/2)
Type 13-W
Type 13-V
VDD
Mask
option
Data
IN/OUT
Output
disable
N-ch
Data
IN/OUT
Output
disable
VSS
N-ch
Input
enable
VSS
Middle-voltage input buffer
Input
enable
Middle-voltage input buffer
Type 17
Type 18
V
LC0
V
LC0
P-ch
P-ch
P-ch
N-ch
P-ch
N-ch
V
LC1
VLC1
P-ch
P-ch
N-ch
N-ch
SEG
data
OUT
OUT
COM
data
P-ch
N-ch
P-ch
N-ch
P-ch
V
LC2
V
LC2
N-ch
N-ch
N-ch
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The µPD789489 Subseries can access 64 KB of memory space. Figures 3-1 to 3-4 show the memory maps.
Figure 3-1. Memory Map (µPD789488)
F F F F H
Special function registers
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
1024 × 8 bits
F B 0 0 H
F A F F H
Reserved
F A 1 C H
F A 1 B H
LCD display RAM
28 × 4 bits
Data memory
F A 0 0 H
space
7 F F F H
F 9 F F H
Reserved
8 0 0 0 H
7 F F F H
Program area
0 0 8 0 H
0 0 7 F H
Internal ROM
32768 × 8 bits
Program memory
space
CALLT table area
Program area
0 0 4 0 H
0 0 3 F H
0 0 2 E H
0 0 2 D H
Vector table area
0 0 0 0 H
0 0 0 0 H
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Figure 3-2. Memory Map (µPD78F9488)
F F F F H
Special function registers
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
1024 × 8 bits
F B 0 0 H
F A F F H
Reserved
F A 1 C H
F A 1 B H
LCD display RAM
28 × 4 bits
Data memory
space
F A 0 0 H
F 9 F F H
7 F F F H
Reserved
8 0 0 0 H
7 F F F H
Program area
0 0 8 0 H
0 0 7 F H
Flash memory
32768 × 8 bits
Program memory
space
CALLT table area
Program area
0 0 4 0 H
0 0 3 F H
0 0 2 E H
0 0 2 D H
Vector table area
0 0 0 0 H
0 0 0 0 H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (µPD789489)
F F F F H
Special function registers
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
1024 × 8 bits
F B 0 0 H
F A F F H
Reserved
F A 1 C H
F A 1 B H
LCD display RAM
28 × 4 bits
Data memory
space
F A 0 0 H
F 9 F F H
B F F F H
Reserved
F 7 0 0 H
F 6 F F H
Internal low-speed
512 × 8 bits
F 5 0 0 H
F 4 F F H
Program area
Reserved
C 0 0 0 H
B F F F H
0 0 8 0 H
0 0 7 F H
CALLT table area
Program area
0 0 4 0 H
0 0 3 F H
Internal ROM
49152 × 8 bits
Program memory
space
0 0 3 0 H
0 0 2 F H
Vector table area
0 0 0 0 H
0 0 0 0 H
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Figure 3-4. Memory Map (µPD78F9489)
F F F F H
Special function registers
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
1024 × 8 bits
F B 0 0 H
F A F F H
Reserved
F A 1 C H
F A 1 B H
LCD display RAM
28 × 4 bits
Data memory
space
F A 0 0 H
F 9 F F H
B F F F H
Reserved
F 7 0 0 H
F 6 F F H
Internal low-speed RAM
512 × 8 bits
Program area
F 5 0 0 H
F 4 F F H
Reserved
C 0 0 0 H
B F F F H
0 0 8 0 H
0 0 7 F H
CALLT table area
Program area
Flash memory
0 0 4 0 H
0 0 3 F H
49152 × 8 bits
Program memory
space
0 0 3 0 H
0 0 2 F H
Vector table area
0 0 0 0 H
0 0 0 0 H
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CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The µPD789489 Subseries provide internal ROM (or flash memory) with the following capacity for each product.
Table 3-1. Internal ROM Capacity
Part Number
Internal ROM
Structure
Mask ROM
Capacity
µPD789488
32768 × 8 bits
µPD78F9488
µPD789489
µPD78F9489
Flash memory
Mask ROM
49152 × 8 bits
Flash memory
The following areas are allocated to the internal program memory space.
(1) Vector table area
The 46-byte area of addresses 0000H to 002DH is reserved in the µPD789488 and 78F9488, and the 48-
byte area of address 0000H to 002FH is reserved in the µPD789489 and 78F9489 as a vector table area.
This area stores program start addresses to be used when branching by RESET input or interrupt request
generation. Of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8
bits are stored in an odd address.
Table 3-2. Vector Table
Vector Table Address
0000H
Interrupt Request
RESET input
Vector Table Address
0018H
Interrupt Request
INTTM20
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
INTWDT
INTP0
001AH
001CH
001EH
0020H
0022H
0024H
0026H
0028H
002AH
002CH
002EH
INTTM50
INTTM60
INTP1
INTTM61
INTP2
INTAD0
INTP3
INTWT
INTRINNote
INTSR20/INTCSI20
INTCSI10
INTST20
INTWTI
INTKR00
INTRERRNote
INTGPNote
INTRENDNote
INTDFULLNote
INTKR01Note
Note µPD789489 and 78F9489 only. There are no interrupt requests corresponding to vector table
addresses 000EH, and 0026H through 002EH for µPD789488 and 78F9488.
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
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3.1.2 Internal data memory space
(1) Internal high-speed RAM and internal low-speed RAM
The µPD789489 Subseries products incorporate the internal high-speed RAM and internal low-speed RAM of
the following capacity for each product.
The internal high-speed RAM can also be used as a stack.
The internal low-speed RAM cannot be used as a stack.
Table 3-3. Internal High-Speed RAM, Internal Low-Speed RAM Capacity
Part Number
µPD789488
Internal High-Speed RAM
Internal Low-Speed RAM
1024 × 8 bits
−
µPD78F9488
µPD789489
µPD78F9489
512 × 8 bits
(2) LCD display RAM
LCD display RAM is incorporated in the area between FA00H and FA1BH.
The LCD display RAM can also be used as ordinary RAM.
3.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated in the area between FF00H and
FFFFH (see Table 3-4).
User’s Manual U15331EJ4V1UD
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CHAPTER 3 CPU ARCHITECTURE
3.1.4 Data memory addressing
The µPD789489 Subseries is provided with a variety of addressing modes to make memory manipulation as
efficient as possible. At the addresses corresponding to data memory area (FB00H to FFFFH) especially, specific
addressing modes that correspond to the particular function of an area, such as the special function registers, are
available. Figures 3-5 to 3-8 show the data memory addressing modes.
Figure 3-5. Data Memory Addressing (µPD789488)
F F F F H
Special function registers
SFR addressing
256 × 8 bits
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
1024 × 8 bits
F E 2 0 H
F E 1 F H
F B 0 0 H
F A F F H
Direct addressing
Reserved
Register indirect addressing
F A 1 C H
F A 1 B H
Based addressing
LCD display RAM
28 × 4 bits
F A 0 0 H
F 9 F F H
Reserved
8 0 0 0 H
7 F F F H
Internal ROM
32768 × 8 bits
0 0 0 0 H
54
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-6. Data Memory Addressing (µPD78F9488)
F F F F H
Special function registers
SFR addressing
256 × 8 bits
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
1024 × 8 bits
F E 2 0 H
F E 1 F H
F B 0 0 H
F A F F H
Direct addressing
Reserved
Register indirect addressing
Based addressing
F A 1 C H
F A 1 B H
LCD display RAM
28 × 4 bits
F A 0 0 H
F 9 F F H
Reserved
8 0 0 0 H
7 F F F H
Flash memory
32768 × 8 bits
0 0 0 0 H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-7. Data Memory Addressing (µPD789489)
F F F F H
Special function registers (SFR)
SFR addressing
256 × 8 bits
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
1024 × 8 bits
F E 2 0 H
F E 1 F H
F B 0 0 H
F A F F H
Reserved
F A 1 C H
F A 1 B H
LCD display RAM
Direct addressing
28 × 4 bits
F A 0 0 H
F 9 F F H
Register indirect addressing
Based addressing
Reserved
F 7 0 0 H
F 6 F F H
Internal low-speed RAM
512 × 8 bits
F 5 0 0 H
F 4 F F H
Reserved
C 0 0 0 H
B F F F H
Internal ROM
49152 × 8 bits
0 0 0 0 H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-8. Data Memory Addressing (µPD78F9489)
F F F F H
Special function registers
256 × 8 bits
SFR addressing
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
1024 × 8 bits
F E 2 0 H
F E 1 F H
F B 0 0 H
F A F F H
Reserved
F A 1 C H
F A 1 B H
LCD display RAM
Direct addressing
28 × 4 bits
F A 0 0 H
F 9 F F H
Register indirect addressing
Based addressing
Reserved
F 7 0 0 H
F 6 F F H
Internal low-speed
512 × 8 bits
F 5 0 0 H
F 4 F F H
Reserved
C 0 0 0 H
B F F F H
Flash memory
49152 × 8 bits
0 0 0 0 H
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CHAPTER 3 CPU ARCHITECTURE
3.2 Processor Registers
The µPD789489 Subseries is provided with the following on-chip processor registers.
3.2.1 Control registers
The control registers contain special functions to control the program sequence status and stack memory. The
program counter, program status word, and stack pointer are control registers.
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-9. Program Counter Configuration
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction
execution.
The program status word contents are automatically stacked upon interrupt request generation or PUSH
PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW
instructions.
RESET input sets PSW to 02H.
Figure 3-10. Program Status Word Configuration
7
0
IE
Z
0
AC
0
0
1
CY
PSW
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(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledgement operations of the CPU.
When 0, IE is set to the interrupt disabled status (DI), and interrupt requests other than non-maskable
interrupts are all disabled.
When 1, IE is set to the interrupt enabled status (EI). Interrupt request acknowledgement enable is
controlled by the interrupt mask flag for the corresponding interrupt source.
IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(d) Carry flag (CY)
This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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CHAPTER 3 CPU ARCHITECTURE
(3) Stack pointer (SP)
This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 3-11. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-12 and 3-13.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-12. Data to Be Saved to Stack Memory
Interrupt
PUSH rp
instruction
CALL, CALLT
instructions
_
_
_
_
SP SP
SP
3
3
2
1
_
_
_
_
_
_
SP SP
SP
2
2
1
SP SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Lower
register pairs
SP
PC7 to PC0
Higher
register pairs
SP
SP
PC15 to PC8
SP
SP
SP
SP
Figure 3-13. Data to Be Restored from Stack Memory
POP rp
RET instruction
RETI instruction
instruction
Lower
register pairs
SP
SP
SP + 1
PC7 to PC0
SP
PC7 to PC0
PC15 to PC8
PSW
Higher
register pairs
PC15 to PC8
SP + 1
SP + 1
SP + 2
SP SP + 2
SP SP + 2
SP SP + 3
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3.2.2 General-purpose registers
The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX,
BC, DE, and HL).
General-purpose registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, or HL)
or absolute names (R0 to R7 and RP0 to RP3).
Figure 3-14. General-Purpose Register Configuration
(a) Absolute names
16-bit processing
RP3
8-bit processing
R7
R6
R5
R4
RP2
RP1
RP0
R3
R2
R1
R0
15
0
7
0
(b) Function names
16-bit processing
HL
8-bit processing
H
L
D
E
DE
BC
AX
B
C
A
X
15
0
7
0
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3.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
The special function registers are allocated in the 256-byte area of FF00H to FFFFH.
Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit
manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special function register
type.
The manipulatable bits can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand. When
addressing an address, describe an even address.
Table 3-4 lists the special function registers. The meanings of the symbols in this table are as follows.
• Symbol
Indicates the addresses of the implemented special-function registers. The symbols shown in this column are
reserved words in the assembler, and have already been defined as sfr variables by the #pragma sfr directive in
the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated
debugger is used.
• R/W
Indicates whether the special function register in question can be read or written.
R/W:
R:
W:
Read/write
Read only
Write only
• Bit unit for manipulation
Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated.
• After reset
Indicates the status of the special function register when the RESET signal is input.
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Table 3-4. Special Function Registers (1/3)
Address
Special Function Register (SFR) Name
Symbol
R/W Bit Unit for Manipulation
1 Bit 8 Bits 16 Bits
After
Reset
FF00H
FF01H
FF02H
FF03H
FF05H
FF06H
FF07H
FF08H
FF0AH
FF0BH
FF0CH
FF0DH
FF0EH
FF0FH
FF11H
FF12H
FF13H
FF14H
FF15H
FF16H
FF17H
FF18H
FF19H
FF1AH
FF1BH
FF20H
FF21H
FF22H
FF23H
FF25H
Port 0
P0
P1
P2
P3
P5
P6
P7
P8
R/W
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
√
00H
Port 1
Port 2
Port 3
Port 5
Port 6
Port 7Note
Port 8Note
R
R/W
W
8-bit compare register 61
8-bit timer counter 61
8-bit compare register 60
8-bit compare register 50
8-bit timer counter 60
8-bit timer counter 50
Serial I/O shift register 1A0
16-bit multiplication result store register L
16-bit multiplication result store register H
A/D conversion result register 0
CR61
Undefined
00H
TM61
R
CR60
CR6
TM6
W
Undefined
CR50
TM60
R
√
00H
TM50
SIO1A0
MUL0L
MUL0H
ADCRL0
R/W
R
−
√
MUL0
Undefined
0000H
√
√
√
√
16-bit compare register 20
16-bit timer counter 20
16-bit capture register 20
CR20
TM20
TCP20
W
R
−
−
−
−
−
−
FFFFH
0000H
Undefined
FFH
Port mode register 0
Port mode register 1
Port mode register 2
Port mode register 3
Port mode register 5
PM0
PM1
PM2
PM3
PM5
R/W
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
FF28H
FF30H
FF31H
FF32H
FF33H
Port mode register 8Note
PM8
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
Pull-up resistor option register B0
Pull-up resistor option register B1
Pull-up resistor option register B2
Pull-up resistor option register B3
PUB0
PUB1
PUB2
PUB3
00H
Note When used as port function by mask option or port function register.
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Table 3-4. Special Function Registers (2/3)
Address
Special Function Register (SFR) Name
Symbol
R/W Bit Unit for Manipulation
1 Bit 8 Bits 16 Bits
After
Reset
FF40H 8-bit H width compare register 61
FF41H 8-bit timer mode control register 61
FF42H Watchdog timer clock selection register
FF46H Subclock selection registerNote 1
CRH61
W
−
√
−
√
√
√
√
−
√
√
√
−
−
√
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Undefined
00H
TMC61
WDCS
SSCK
TMC20
WTM
R/W
FF48H 16-bit timer mode control register 20
FF4AH Watch timer mode control register
FF4BH Watch timer interrupt time selection register
FF4CH 8-bit H width compare register 60
FF4DH 8-bit timer mode control register 50
FF4EH 8-bit timer mode control register 60
FF4FH Carrier generator output control register 60
FF57H Port function register 7Note 1
WTIM
CRH60
TMC50
TMC60
TCA60
PF7
W
Undefined
00H
R/W
W
FF58H Port function register 8Note 1
FF60H Remote controller receive control register Note 2
FF61H Remote controller receive data register Note 2
PF8
RMCN
RMDR
RMSCR
R/W
R
FF62H Remote controller shift register receive counter
register Note 2
FF63H Remote controller receive shift registerNote 2
FF66H Remote controller receive GPHS compare register Note 2
FF67H Remote controller receive GPHL compare register Note 2
FF68H Remote controller receive DLS compare register Note 2
FF69H Remote controller receive DLL compare register Note 2
FF6AH Remote controller receive DH0S compare register Note 2
FF6BH Remote controller receive DH0L compare register Note 2
FF6CH Remote controller receive DH1S compare register Note 2
FF6DH Remote controller receive DH1L compare register Note 2
FF6EH Remote controller receive end width select register Note 2
FF70H Asynchronous serial interface mode register 20
FF71H Asynchronous serial interface status register 20
FF72H Serial operation mode register 20
RMSR
−
−
−
−
−
−
−
−
−
−
√
√
√
−
−
−
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
RMGPHS
RMGPHL
RMDLS
RMDLL
R/W
RMDH0S
RMDH0L
RMDH1S
RMDH1L
RMER
ASIM20
ASIS20
R
CSIM20
BRGC20
TXS20 SIO20
RXB20
R/W
FF73H Baud rate generator control register 20
FF74H Transmit shift register 20
W
R
FFH
Receive buffer register 20
Undefined
00H
FF78H Serial operation mode register 1A0
CSIM1A0
ADTC0
R/W
FF79H Automatic data transmit/receive control register 0
FF7AH Automatic data transmit/receive address pointer 0
ADTP0
Undefined
00H
FF7BH Automatic data transmit/receive interval specification
register 0
ADTI0
Notes 1. These registers function only in the µPD78F9488 and 78F9489; however, writing to these registers in
the µPD789488 and 789489 will not affect the operation.
2. µPD789489 and 78F9489 only
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Table 3-4. Special Function Registers (3/3)
Address
Special Function Register (SFR) Name
Symbol
R/W Bit Unit for Manipulation
1 Bit 8 Bits 16 Bits
After
Reset
FF80H A/D converter mode register 0
FF84H Analog input channel specification register 0
FFA0H Serial interface buffer memory 0
FFA1H Serial interface buffer memory 1
FFA2H Serial interface buffer memory 2
FFA3H Serial interface buffer memory 3
FFA4H Serial interface buffer memory 4
FFA5H Serial interface buffer memory 5
FFA6H Serial interface buffer memory 6
FFA7H Serial interface buffer memory 7
FFA8H Serial interface buffer memory 8
FFA9H Serial interface buffer memory 9
FFAAH Serial interface buffer memory A
FFABH Serial interface buffer memory B
FFACH Serial interface buffer memory C
FFADH Serial interface buffer memory D
FFAEH Serial interface buffer memory E
FFAFH Serial interface buffer memory F
FFB0H LCD mode register 0
ADML0
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
√
−
−
√
√
√
√
√
√
√
−
−
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
00H
ADS0
SBMEM0
SBMEM1
SBMEM2
SBMEM3
SBMEM4
SBMEM5
SBMEM6
SBMEM7
SBMEM8
SBMEM9
SBMEMA
SBMEMB
SBMEMC
SBMEMD
SBMEME
SBMEMF
LCDM0
LCDC0
LCDVA0
MRA0
Undefined
00H
FFB2H LCD clock control register 0
FFB3H LCD voltage boost control register 0
FFD0H Multiplication data register A0
FFD1H Multiplication data register B0
FFD2H Multiplier control register 0
W
Undefined
00H
MRB0
MULC0
IF0
R/W
FFE0H Interrupt request flag register 0
FFE1H Interrupt request flag register 1
FFE2H Interrupt request flag register 2
FFE4H Interrupt mask flag register 0
FFE5H Interrupt mask flag register 1
FFE6H Interrupt mask flag register 2
FFECH External interrupt mode register 0
FFEDH External interrupt mode register 1
FFF0H Subclock oscillation mode register
FFF2H Subclock control register
FFF4H Key return mode register 01Note
FFF5H Key return mode register 00
FFF9H Watchdog timer mode register
FFFAH Oscillation stabilization time selection register
FFFBH Processor clock control register
IF1
IF2
MK0
FFH
00H
MK1
MK2
INTM0
INTM1
SCKM
CSS
KRM01
KRM00
WDTM
OSTS
04H
02H
PCC
Note µPD789489 and 78F9489 only
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination information is set
to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series
Instructions User’s Manual (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.
This means that information is relatively branched to a location between –128 and +127, from the start address
of the next instruction when relative addressing is used.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
0
0
...
PC is the start address of
the next instruction of
a BR instruction.
PC
+
8
7
6
α
S
jdisp8
15
0
PC
When S = 0, α indicates all bits 0.
When S = 1, α indicates all bits 1.
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
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3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch
to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.
[Illustration]
7
6
1
5
1
0
0
Instruction code
Effective address
0
ta4–0
15
8
0
7
0
6
1
5
1
0
0
0
0
0
0
0
0
0
7
Memory (Table)
Low Addr.
0
High Addr.
Effective address + 1
15
8
7
0
PC
3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
8
7
7
0
0
rp
A
X
15
PC
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3.4 Operand Address Addressing
The following various methods are available to specify the register and memory (addressing) which undergo
manipulation during instruction execution.
3.4.1 Direct addressing
[Function]
The memory indicated with immediate data in an instruction word is directly addressed.
[Operand format]
Identifier
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
OP code
00H
FEH
[Illustration]
7
0
OP code
addr16 (Lower)
addr16 (Higher)
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed
RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area.
Ports that are frequently accessed in a program and the compare register of the timer/event counter are
mapped in this area, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier
saddr
Description
Label or FE20H to FF1FH immediate data
saddrp
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
OP code
90H (saddr-offset)
50H (Immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
15
1
8
0
Effective
address
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0.
When 8-bit immediate data is 00H to 1FH, α = 1.
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3.4.3 Special function register (SFR) addressing
[Function]
The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an
instruction word.
This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to
FF1FH can also be accessed with short direct addressing.
[Operand format]
Identifier
sfr
Description
Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code
1
0
1
0
1
1
0
0
0
0
1
0
1
0
1
0
[Illustration]
7
0
OP code
sfr-offset
SFR
15
1
8 7
0
Effective
Address
1
1
1
1
1
1
1
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3.4.4 Register addressing
[Function]
In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose
register to be accessed is specified by a register specification code or functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier
Description
X, A, C, B, E, D, L, H
AX, BC, DE, HL
r
rp
r and rp can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
Register specification code
INCW DE; When selecting the DE register pair for rp
Instruction code
1
0
0
0
1
0
0
0
Register specification code
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3.4.5 Register indirect addressing
[Function]
In the register indirect addressing mode, memory is manipulated according to the contents of a register pair
specified as an operand. The register pair to be accessed is specified by the register pair specification code in
an instruction code.
This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
[DE], [HL]
−
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code
0
0
1
0
1
0
1
1
[Illustration]
15
8
7
7
0
0
DE
D
E
Memory address
specified with
register pair DE.
Addressed memory
contents are
transferred.
7
0
A
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3.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16
bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
[HL+byte]
−
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
3.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return
instructions are executed or the register is saved/restored upon generation of an interrupt request.
Only the internal high-speed RAM area can be addressed using stack addressing.
[Description example]
In the case of PUSH DE
Instruction code
1
0
1
0
1
0
1
0
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4.1 Port Functions
The µPD789489 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. The
functions of each port are shown in Table 4-1.
Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more
information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P50
P00
Port 5
P53
P60
Port 0
P07
Port 6
P10
P11
Port 1
Port 2
P67
P70
P20
Port 7
P73
P80
P25
P30
Port 3
Port 8
P34
P87
Remark Ports 7 and 8 are used when the port function is selected by a mask option or port function register.
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Table 4-1. Port Functions
Port Name
Port 0
Pin Name
P00 to P07
Function
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by
pull-up resistor option register B0 (PUB0) or the key return mode register (KRM00).
Port 1
Port 2
Port 3
Port 5
P10, P11
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by
pull-up resistor option register B1 (PUB1).
P20 to P25
P30 to P34
P50 to P53
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by
pull-up resistor option register B2 (PUB2).
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by
pull-up resistor option register B3 (PUB3).
N-ch open-drain I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by mask option.
Port 6
P60 to P67
P70 to P73
P80 to P87
Input port
Port 7Note 1
Port 8Note 2
Input port (only when input port is selected by mask option or port function register)
I/O port (only when I/O port is selected by mask option or port function register)
Notes 1. Whether to use these pins as input port pins (P70 to P73) or segment outputs (S16 to S19) can be
selected in 1-bit units by means of a mask option in the µPD789488, 789489 or a port mode register in
the µPD78F9488, 78F9489 (refer to 4.3 (3) Port function registers and CHAPTER 20 MASK
OPTIONS).
2. Whether to use these pins as I/O port pins (P80 to P87) or segment outputs (S20 to S27) can be
selected in 1-bit units by means of a mask option for the µPD789488, 789489 or a port mode register in
the µPD78F9488, 78F9489 (refer to 4.3 (3) Port function registers and CHAPTER 20 MASK
OPTIONS).
4.2 Port Configuration
Ports have the following hardware configuration.
Table 4-2. Configuration of Port
Item
Configuration
Control registers
Port mode registers (PMm: m = 0 to 3, 5, 8)
Pull-up resistor option registers (PUB0 to PUB3)
Port function registers (PF7, PF8) (µPD78F9488, 78F9489 only)
Ports
Total: 45 (CMOS I/O: 29, CMOS input: 12, N-ch open-drain I/O: 4)
Pull-up resistors
• Mask ROM version
Total: 25 (software control: 21, mask option specification: 4)
• Flash memory version
Total: 21 (software control only)
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4.2.1 Port 0
This is an 8-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by
using port mode register 0 (PM0). When the P00 to P07 pins are used as input port pins, on-chip pull-up resistors can
be connected in 1-bit units by using pull-up resistor option register B0 (PUB0).
This port is also used for key return signal input.
RESET input sets this port to input mode.
Figure 4-2 shows a block diagram of port 0.
Figure 4-2. Block Diagram of P00 to P07
V
DD
WRPUO
PUB00 to PUB07
P-ch
RD
WRKRM00
KRM000,
KRM004 to KRM007
WRPORT
Output latch
(P00 to P07)
P00/KR0 to
P07/KR7Note 1
or
W
RPM
P00/KR00 to
P07/KR07Note 2
PM00 to PM07
Alternate function
KRM00: Key return mode register 00
PUB0: Pull-up resistor option register B0
PM:
RD:
WR:
Port mode register
Port 0 read signal
Port 0 write signal
Notes 1. When µPD789488, 78F9488 is used
2. When µPD789489, 78F9489 is used
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4.2.2 Port 1
This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by
using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can
be connected in 1-bit units by using pull-up resistor option register B1 (PUB1).
RESET input sets this port to input mode.
Figure 4-3 shows a block diagram of port 1.
Figure 4-3. Block Diagram of P10 and P11
V
DD
WRPU0
PUB10, PUB11
P-ch
RD
WRPORT
Output latch
(P10, P11)
P10, P11
WRPM
PM10, PM11
PUB1: Pull-up resistor option register B1
PM:
RD:
WR:
Port mode register
Port 1 read signal
Port 1 write signal
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4.2.3 Port 2
This is a 6-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by
using port mode register 2 (PM2). When using the P20 to P25 pins as input port pins, on-chip pull-up resistors can be
connected in 1-bit units by using pull-up resistor option register B2 (PUB2).
This port is also used for serial interface I/O.
RESET input sets this port to input mode.
Figures 4-4 to 4-8 show block diagrams of port 2.
Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set
according to the function to be used. For how to set the latches, see Table 11-2 Serial Interface
20 Operation Mode Settings and 12.3 (1) Serial operation mode register 1A0 (CSIM1A0).
Figure 4-4. Block Diagram of P20
V
DD
WRPUB2
PUB20
P-ch
Alternate
function
RD
WRPORT
Output latch
(P20)
P20/ASCK20/
SCK20
WRPM
PM20
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-5. Block Diagram of P21
V
DD
WRPUB2
PUB21
P-ch
RD
WRPORT
Output latch
(P21)
P21/SO20/TxD20
WRPM
PM21
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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Figure 4-6. Block Diagram of P22 and P25
V
DD
WRPUB2
PUB22, PUB25
P-ch
Alternate
function
RD
WRPORT
Output latch
(P22, P25)
P22/SI20/
RxD20,
WRPM
P25/SI10
PM22, PM25
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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Figure 4-7. Block Diagram of P23
V
DD
WRPUB2
PUB23
P-ch
Alternate
function
RD
WRPORT
Output latch
(P23)
P23/SCK10
WRPM
PM23
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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Figure 4-8. Block Diagram of P24
V
DD
WRPUB2
PUB24
P-ch
RD
WRPORT
Output latch
(P24)
P24/SO10
WRPM
PM24
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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4.2.4 Port 3
This is a 5-bit I/O port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by
using port mode register 3 (PM3). When using the P30 to P34 pins as input port pins, on-chip pull-up resistors can be
connected in 1-bit units by using pull-up resistor option register B3 (PUB3).
This port is also used for external interrupt input, capture input, timer I/O, and remote control receive data inputNote
RESET input sets this port to input mode.
.
Figures 4-9 and 4-10 show block diagrams of port 3.
Note µ PD789489 and 78F9489 only
Figure 4-9. Block Diagram of P30 to P33
V
DD
WRPUB3
PUB30 to PUB33
P-ch
Alternate
function
RD
WRPORT
Output latch
(P30 to P33)
P30/INTP0/TO50/
TMI60,
WRPM
P31/INTP1/TO60,
P32/INTP2/TO61/
TMI61
PM30 to PM33
P33/INTP3/TO20/
CPT20
Alternate
function
PUB3: Pull-up resistor option register B3
PM:
RD:
WR:
Port mode register
Port 3 read signal
Port 3 write signal
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Figure 4-10. Block Diagram of P34
(a) When µPD789488, 78F9488 is used
V
DD
WRPUB3
PUB34
P-ch
RD
WRPORT
Output latch
(P34)
P34
WRPM
PM34
(b) When µPD789489, 78F9489 is used
VDD
WRPUB3
PUB34
P-ch
Alternate
function
RD
WRPORT
Output latch
(P34)
P34/RIN
WRPM
PM34
PUB3: Pull-up resistor option register B3
PM:
RD:
WR:
Port mode register
Port 3 read signal
Port 3 write signal
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4.2.5 Port 5
This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in
1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be
specified by a mask option.
RESET input sets this port to input mode.
Figure 4-11 shows a block diagram of port 5.
Figure 4-11. Block Diagram of P50 to P53
V
DD
RD
Mask option resistor
Mask ROM version only.
For a flash memory version,
a pull-up resistor is not
incorporated.
P50 to P53
WRPORT
Output latch
(P50 to P53)
N-ch
WRPM
PM50 to PM53
PM: Port mode register
RD: Port 5 read signal
WR: Port 5 write signal
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4.2.6 Port 6
This is an 8-bit input-only port.
This port is also used for the analog input of an A/D converter and key return signal inputNote
Figure 4-12 shows a block diagram of port 6.
.
Note µPD789489 and 78F9489 only.
Figure 4-12. Block Diagram of P60 to P67 (1/2)
(a) When µPD789488,78F9488 is used
RD
+
P60/ANI0 to P67/ANI7
A/D converter
−
V
REF
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CHAPTER 4 PORT FUNCTIONS
Figure 4-12. Block Diagram of P60 to P67 (2/2)
(b) When µPD789489, 78F9489 is used
RD
Alternate
function
WRKRM01
KRM010,
KRM014 to KRM017
+
−
P60/ANI0/KR10 to
P67/ANI7/KR17
A/D converter
V
REF
KRM01: Key return mode register 01
RD:
Port 6 read signal
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4.2.7 Port 7
This is a 4-bit input-only port. Only the bits for which the port function is selected can be used, by using a mask
option in the µPD789488 and 789489 or port function register 7 (PF7) in the µPD78F9488 and 78F9489.
Figure 4-13 shows a block diagram of port 7.
Figure 4-13. Block Diagram of P70 to P73
RD
P70 to P73
RD: Port 7 read signal
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4.2.8 Port 8
This is an 8-bit I/O port with an output latch. Only the bits for which the port function is selected can be used, by
using a mask option in the µPD789488 and 789489 or port function register 8 (PF8) in the µPD78F9488 and 78F9489.
Port 8 can be specified in the input or output mode in 1-bit units by using port mode register 8 (PM8).
RESET input sets this port to input mode.
Figure 4-14 shows a block diagram of port 8.
Figure 4-14. Block Diagram of P80 to P87
RD
WRPORT
Output latch
(P80 to P87)
P80 to P87
WRPM
PM80 to PM87
PM: Port mode register
RD: Port 8 read signal
WR: Port 8 write signal
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4.3 Registers Controlling Port Function
The ports are controlled by the following three types of registers.
• Port mode registers (PM0 to PM3, PM5, PM8)
• Pull-up resistor option registers (PUB0 to PUB3)
• Port function registers (PF7, PF8) (µPD78F9488, 78F9489 only)
(1) Port mode registers (PM0 to PM3, PM5, PM8)
Input and output can be specified in 1-bit units.
These registers can be set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When using the port pins as their alternate functions, set the port mode register and the output latch as
shown in Table 4-3.
Caution Because P30 to P33 function alternately as external interrupt inputs, when the output level
changes after the output mode of the port function is specified, the interrupt request flag
will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0 to
PMK3) before using the port in output mode.
Figure 4-15. Port Mode Register Format
Symbol
PM0
7
6
5
4
3
2
1
0
Address
FF20H
After reset R/W
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FFH
FFH
FFH
FFH
FFH
FFH
R/W
R/W
R/W
R/W
R/W
R/W
PM1
PM2
PM3
PM5
PM8
1
1
1
PM25
1
1
1
1
PM11
PM21
PM31
PM51
PM81
PM10
PM20
PM30
PM50
PM80
FF21H
FF22H
FF23H
FF25H
FF28H
1
1
1
1
PM24
PM34
1
PM23
PM33
PM53
PM83
PM22
PM32
PM52
PM82
1
1
1
PM87
PMmn
PM86
PM85
PM84
Pmn pin input/output mode selection
(m = 0 to 3, 5, 8, n = 0 to 7)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
Remark PM8 can only be used when one of pins P80 to P87 is selected as a port function pin by a mask
option or port function register 8 (PF8).
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Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions
Pin Name
Alternate Function
Name
PM××
P××
I/O
Input
P00 to P07
P30
KR0 to KR7 or KR00 to KR07
1
1
0
1
1
0
1
1
0
1
1
0
1
×
×
0
×
×
0
×
×
0
×
×
0
×
INTP0
Input
TO50
Output
Input
TMI60
P31
P32
INTP1
Input
TO60
Output
Input
INTP2
TMI61
Input
TO61
Output
Input
P33
INTP3
CPT20
Input
TO20
Output
Input
P34
RIN (µPD789489, 78F9489 only)
Remark ×:
don’t care
PM××: Port mode register
P××: Port output latch
Caution When port 2 is used for the interface, I/O and output latch settings must be made in accordance
with the function used. For the setting method, refer to Table 11-2 Serial Interface 20 Operation
Mode Settings and 12.3 (1) Serial operation mode register 1A0 (CSIM1A0).
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(2) Pull-up resistor option registers (PUB0 to PUB3)
These registers set whether to use on-chip pull-up resistors for pins P00 to P07, P10, P11, P20 to P25, and
P30 to P34. An on-chip pull-up resistor can be used only for those bits set to the input mode in a port for
which the use of the on-chip pull-up resistor has been specified using PUB0 to PUB3.
For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of
PUB0 to PUB3. This also applies to alternate-function pins used as output pins.
PUB0 to PUB3 are set via a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Figure 4-16. Format of Pull-Up Resistor Option Registers
Symbol
PUB0
<7>
<6>
<5>
<4>
PUB04
4
<3>
PUB03
3
<2>
PUB02
2
<1>
PUB01
<1>
<0>
PUB00
<0>
Address
FF30H
After reset R/W
PUB07
PUB06
PUB05
00H
00H
00H
00H
R/W
R/W
R/W
R/W
7
0
7
0
7
0
6
0
6
0
6
0
5
PUB1
PUB2
PUB3
0
<5>
PUB25
5
0
0
0
PUB11
<1>
PUB10
<0>
FF31H
FF32H
FF33H
<4>
<3>
<2>
PUB24
<4>
PUB23
<3>
PUB22
<2>
PUB21
<1>
PUB20
<0>
0
PUB34
PUB33
PUB32
PUB31
PUB30
PUBmn
Pmn on-chip pull-up resistor selection
(m = 0 to 3, n = 0 to 7)
0
1
An on-chip pull-up resistor is not connected.
An on-chip pull-up resistor is connected.
(3) Port function registers (PF7 and PF8) (µPD78F9488, 78F9489 only)
These registers specify in 1-bit units whether to use P70 to P73 and P80 to P87 as port pins or segment
outputs.
PF7 and PF8 are set via a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Caution This register is valid only in the µPD78F9488 and 78F9489; however, writing to it in the
µPD789488 and 789489 will simply make it invalid, causing no operational effect.
Figure 4-17. Port Function Register Format
Symbol
PF7
7
0
6
0
5
0
4
0
<3>
PF73
<3>
<2>
PF72
<2>
<1>
PF71
<1>
<0>
PF70
<0>
Address
FF57H
After reset R/W
00H
W
<7>
PF87
<6>
PF86
<5>
PF85
<4>
PF84
PF8
PF83
PF82
PF81
PF80
FF58H
00H
W
PFmn
Pmn port/segment output specification (m = 7 or 8, n = 0 to 7)
0
1
Pmn is used as a port pin.
Pmn is used as a segment output.
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4.4 Port Function Operation
The operation of a port differs depending on whether the port is set in the input or output mode, as described
below.
4.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin
is not changed because the output buffer is OFF.
Once data is written to the output latch, it is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an input/output port, therefore, the contents of the output latch of the
pin that is set in the input mode and not subject to manipulation become undefined.
4.4.2 Reading from I/O port
(1) In output mode
The status of an output latch can be read by using a transfer instruction. The contents of the output latch are
not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
4.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed on the contents of the output latch. The result of the operation is
written to the output latch. The contents of the output latch are output from the port pins.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because
the output buffer is OFF.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an input/output port, therefore, the contents of the output latch of the
pin that is set in the input mode and not subject to manipulation become undefined.
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5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following two types of system clock oscillators are used.
• Main system clock oscillator
This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting
the processor clock control register (PCC).
• Subsystem clock oscillator
This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).
Also, a circuit to multiply the subsystem clock by 4 can be used by setting a mask option or the subclock
selection register (SSCK).
5.2 Clock Generator Configuration
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Configuration
Control registers
Processor clock control register (PCC)
Subclock oscillation mode register (SCKM)
Subclock control register (CSS)
Subclock selection register (SSCK) (µPD78F9488, 78F9489 only)
Oscillators
Main system clock oscillator
Subsystem clock oscillator
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Figure 5-1. Clock Generator Block Diagram (µPD789488, 789489)
Internal bus
Subclock oscillation
mode register
(SCKM)
FRC
SCC
×4
multiplication
circuit
×2
multiplication
circuit
8fXT
f
XTT
Mask
option
Subsystem
clock
oscillator
XT1
XT2
Timer 50
Watch timer
LCD controller/driver
f
XT
1/2
X1
X2
Subsystem
clock
oscillator
Clock to peripheral
hardware
f
X
Prescaler
f
X
22
f
XTT
2
Standby
controller
Wait
controller
CPU clock
(fCPU
)
STOP
CLS CSS0
MCC PCC1
Subclock control
register (CSS)
Processor clock control
register (PCC)
Internal bus
Remark fXTT: fXT or 8fXT
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Figure 5-2. Clock Generator Block Diagram (µPD78F9488, 78F9489)
Internal bus
× 4 multiplication
× 2 multiplication
circuit
circuit
Subclock oscillation
mode register (SCKM)
Subclock selection
register (SSCK)
SCT
FRC
SCC
8fXT
f
XTT
Selector
XT1
XT2
Timer 50
Watch timer
LCD controller/driver
f
XT
Subsystem
clock oscillator
1/2
X1
X2
Main system
clock oscillator
Clock to peripheral
hardware
f
X
Prescaler
f
X
22
f
XTT
2
Standby
controller
Wait
controller
CPU clock
(fCPU
)
STOP
CLS CSS0
MCC PCC1
Processor clock
control register (PCC)
Subclock control
register (CSS)
Internal bus
Remark fXTT: fXT or 8fXT
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5.3 Registers Controlling Clock Generator
The clock generator is controlled by the following four registers.
• Processor clock control register (PCC)
• Subclock oscillation mode register (SCKM)
• Subclock control register (CSS)
• Subclock selection register (SSCK) (µPD78F9488, 78F9489 only)
(1) Processor clock control register (PCC)
This register is used to select the CPU clock and set the frequency division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 02H.
Figure 5-3. Format of Processor Clock Control Register
Symbol
PCC
<7>
6
0
5
0
4
0
3
0
2
0
<1>
0
0
Address
FFFBH
After reset R/W
02H R/W
MCC
PCC1
MCC
Main system clock oscillator operation control
0
1
Operation enabled
Operation stopped
Note
CPU clock (fCPU) selection
CSS0 PCC1
Minimum instruction execution time: 2/fCPU
fX = 5.0 MHz or fXT = 32.768 kHz
0
0
1
0
1
×
fX
0.4 µs
2
fX/2
1.6 µs
fXT/2
122 µs
4fXT (when ×4 multiplication circuit is used)
15.26 µs (when ×4 multiplication circuit is used)
Note The CPU clock is selected by a combination of flag settings in the PCC and CSS registers. (Refer to
5.3 (3) Subclock control register (CSS).)
Cautions 1. Always set bits 0 and 2 to 6 to 0.
2. MCC can be set only when the subsystem clock is selected as the CPU clock.
Setting MCC to 1 while the main system clock is operating is invalid.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
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(2) Subclock oscillation mode register (SCKM)
SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock.
SCKM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets SCKM to 00H.
Figure 5-4. Format of Subclock Oscillation Mode Register
Symbol
SCKM
7
0
6
0
5
0
4
0
3
0
2
0
1
<0>
Address
FFF0H
After reset
00H
R/W
R/W
FRC SCC
FRC
Feedback resistor selectionNote
0
1
On-chip feedback resistor used
On-chip feedback resistor not used
SCC
Control of subsystem clock oscillator operation
0
1
Operation enabled
Operation disabled
Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid
point of the supply voltage. When the subclock is not used, the power consumption in STOP mode can be
further reduced by setting FRC = 1.
Caution Bits 2 to 7 must be set to 0.
(3) Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the
CPU clock operation status.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSS to 00H.
Figure 5-5. Format of Subclock Control Register
Symbol
CSS
7
0
6
0
5
4
3
0
2
0
1
0
0
0
Address
FFF2H
After reset
00H
R/W
CLS CSS0
R/WNote
CLS
0
CPU clock operation status
Operation based on the output of the (divided) main system clock
Operation based on the subsystem clock
1
CSS0
Selection of the main system or subsystem clock oscillator
(Divided) output from the main system clock oscillator
Output from the subsystem clock oscillator
0
1
Note Bit 5 is read only.
Caution Bits 0 to 3, 6, and 7 must be set to 0.
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(4) Subclock selection register (SSCK) (µPD78F9488, 78F9489 only)
This register is used to control the operation of the ×4 subsystem clock multiplication circuit.
SSCK is set via a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Caution This register is valid only in the µPD78F9488 and 78F9489; however, writing to it in the
µPD789488 and 789489 will simply make it invalid, causing no operational effect.
Figure 5-6. Subclock Selection Register Format
Symbol
SSCK
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Address
FF46H
After reset R/W
Not
Retained
SCT
R/W
e
SCT
Control of ×4 subsystem clock multiplication circuit
Operation stopped (subsystem clock source (32.768 kHz) supplied to the CPU)
Operation enabled (clock that is the subsystem clock multiplied by 8 (262 kHz) supplied to the CPU)
0
1
Note The register is set to 00H only by RESET input.
Cautions 1. Always set bits 1 to 7 to 0.
2. Write to the SCT flag prior to setting the CSS0 flag to 1 following the release of reset. Write
operations following the first operation are invalid (input the RESET signal to rewrite).
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5.4 System Clock Oscillators
5.4.1 Main system clock oscillator
The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected
across the X1 and X2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the
inverted signal to the X2 pin.
Figure 5-7 shows the external circuit of the main system clock oscillator.
Figure 5-7. External Circuit of Main System Clock Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
External
clock
V
SS
X1
X1
X2
X2
Crystal
or
ceramic resonator
Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in Figure 5-7 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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5.4.2 Subsystem clock oscillator
The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1
and XT2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the
inverted signal to the XT2 pin.
Figure 5-8 shows the external circuit of the subsystem clock oscillator.
Figure 5-8. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation
(b) External clock
External
clock
IC (VPP
XT1
)
XT1
32.768
kHz
XT2
XT2
Crystal resonator
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 5-7 and 5-8 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
When using the subsystem clock, particular care is required because the subsystem clock
oscillator is designed as a low-amplitude circuit for reducing current consumption.
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5.4.3 Example of incorrect resonator connection
Figure 5-9 shows examples of incorrect resonator connection.
Figure 5-9. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORTn
(n = 0 to 3, 5)
V
SS
X1
X2
V
SS
X1
X2
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
DD
P
mn
X1
X2
V
SS
V
SS
X1
X2
High current
A
B
C
High current
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to XT2 in series.
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Figure 5-9. Examples of Incorrect Resonator Connection (2/2)
(e) Signal is fetched
X1
X2
V
SS
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to XT2 in series.
5.4.4 Divider circuit
The divider circuit divides the output of the main system clock oscillator (fX) to generate various clocks.
5.4.5 When subsystem clock is not used
If the subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,
handle the XT1 and XT2 pins as follows.
XT1: Connect to VSS
XT2: Leave open
In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator
when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the subclock oscillation mode register
(SCKM) so that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as
stated above.
5.4.6 Subsystem clock ×4 multiplication circuit
This circuit multiplies the subsystem clock by 4 and supplies it to the CPU.
The circuit stops operating in the HALT mode (to reduce power consumption).
When the circuit starts operating after HALT mode is released, a one-clock wait of the original subsystem clock is
inserted to eliminate noise.
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5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
standby mode.
• Main system clock
• Subsystem clock
fX
fXT
• CPU clock
fCPU
• Clock to peripheral hardware
The operation and function of the clock generator is determined by the processor clock control register (PCC),
subclock oscillation mode register (SCKM), and subclock control register (CSS), as follows.
(a) The low-speed mode (1.6 µs: at 5.0 MHz operation) of the main system clock is selected when the
RESET signal is generated (PCC = 02H). While a low level is being to the RESET pin, oscillation of the
main system clock is stopped.
(b) Three types of minimum instruction execution time (0.4 µs and 1.6 µs: main system clock (at 5.0 MHz
operation), 122 µs: subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM,
and CSS settings. Also, the subsystem clock can be changed to a clock that uses a circuit to multiply
the subclock by 4 via a mask option in the µPD789488 and 789489 or the subclock selection register
(SSCK) in the µPD78F9488 and 78F9489 (15.26 µs: a circuit to multiply the subsystem clock by 4 is
used).
(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where the subsystem clock is not used, setting bit 1 (FRC) of SCKM so that the on-chip feedback
resistor cannot be used reduces current consumption in STOP mode. In a system where the
subsystem clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.
(d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation
is used (122 µs: at 32.768 kHz operation).
(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating
using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.
(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock, but the subsystem clock pulse is only supplied to 8-bit timer 50, the watch timer, and the LCD
controller/driver. 8-bit timer 50, the watch timer, and the LCD controller/driver can therefore keep
running even during standby. The other hardware stops when the main system clock stops because it
runs based on the main system clock (except for external input clock operations).
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5.6 Changing Setting of System Clock and CPU Clock
5.6.1 Time required for switching between system clock and CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4
(CSS0) of the subclock control register (CSS).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed; the old clock
is used for the duration of several instructions after that (see Table 5-2).
Table 5-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching
Set Value After Switching
CSS0
PCC1
CSS0
0
PCC1
0
CSS0
0
PCC1
1
CSS0
1
PCC1
x
0
0
1
x
4 clocks
2 clocks
2fX/fXT clocks
(306 clocks)
2 clocks
2 clocks
fX/2fXT clocks
(76 clocks)
1
Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching.
2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
3. x: don’t care
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5.6.2 Switching between system clock and CPU clock
The following figure illustrates how the CPU clock and system clock switch.
Figure 5-10. Switching Between System Clock and CPU Clock
V
DD
RESET
Interrupt request signal
f
X
f
X
f
XT
f
X
System clock
CPU clock
Low-speed
operation
High-speed
operation
High-speed operation
Subsystem clock
operation
Wait (6.55 ms: at 5.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the
oscillation stabilization time (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the main system clock (1.6 µs: at
5.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock
control register (CSS) are rewritten so that high-speed operation can be selected.
<3> A drop of the VDD voltage is detected with an interrupt request signal. The clock is switched to the
subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization status).
<4> A recover of the VDD voltage is detected with an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and
then the main system clock starts oscillating. After the time required for the oscillation to stabilize has
elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.
Caution
When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
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CHAPTER 6 16-BIT TIMER 20
6.1 16-Bit Timer 20 Functions
16-bit timer 20 has the following functions.
• Timer interrupt
• Timer output
• Count value capture
(1) Timer interrupt
An interrupt is generated when a count value and compare value match.
(2) Timer output
Timer output can be controlled when a count value and compare value match.
(3) Count value capture
The count value of 16-bit timer counter 20 (TM20) is latched into a capture register in synchronization with
the capture trigger and retained.
6.2 16-Bit Timer 20 Configuration
16-bit timer 20 includes the following hardware.
Table 6-1. 16-Bit Timer 20 Configuration
Item
Timer counters
Registers
Configuration
16 bits × 1 (TM20)
Compare register:
Capture register:
16 bits × 1 (CR20)
16 bits × 1 (TCP20)
Timer outputs
1 (TO20)
Control registers
16-bit timer mode control register 20 (TMC20)
Port mode register 3 (PM3)
Port 3 (P3)
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Figure 6-1. Block Diagram of 16-Bit Timer 20
Internal bus
16-bit timer mode
control register 20
(TMC20)
P33
output latch
PM33
TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TO20/CPT20
/INTP3/P33
F/F
TOD20
16-bit compare register 20 (CR20)
16-bit timer mode
control register 20
Match
16-bit timer counter 20 (TM20)
16-bit capture
INTTM20
f
X
f
X
/22
/25
OVF
f
X
Timer 61 interrupt
request signal
CPT20/TO20
/INTP3/P33
16-bit counter
read buffer
Edge detector
register 20 (TCP20)
Internal bus
(1) 16-bit compare register 20 (CR20)
This 16-bit register is used to continually compare the value set to CR20 with the count value in 16-bit timer
counter 20 (TM20) and to issue an interrupt request (INTTM20) when a match occurs.
CR20 is set via a 16-bit memory manipulation instruction. Values from 0000H to FFFFH can be set.
RESET input sets this register to FFFFH.
Caution To rewrite CR20 during a count operation, first set interrupt mask flag register 0 (MK0) to
disable interrupts. Also, set inversion inhibited for the timer output data in 16-bit timer
mode control register 20 (TMC20). If CR20 is rewritten while interrupts are enabled, an
interrupt request may be issued at the point of rewrite.
(2) 16-bit timer counter 20 (TM20)
This is a 16-bit register that is used to count the count pulses.
TM20 can be read with a 16-bit memory manipulation instruction.
The counter is in free-running mode when the count clock is being input.
RESET input sets this counter to 0000H and restarts free-running mode.
Caution The count value after releasing STOP mode is undefined because the count operation
occurred during the oscillation stabilization time.
(3) 16-bit capture register 20 (TCP20)
This is a 16-bit register used to capture the contents of 16-bit timer counter 20 (TM20).
TCP20 is set with a 16-bit memory manipulation instruction.
RESET input makes this register undefined.
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CHAPTER 6 16-BIT TIMER 20
(4) 16-bit counter read buffer 20
This buffer is used to latch and hold the count value for TM20.
6.3 Registers Controlling 16-Bit Timer 20
16-bit timer 20 is controlled by the following three registers.
• 16-bit timer mode control register 20 (TMC20)
• Port mode register 3 (PM3)
• Port 3 (P3)
(1) 16-bit timer mode control register 20 (TMC20)
16-bit timer mode control register 20 (TMC20) controls the setting of the count clock, capture edge, etc.
TMC20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC20 to 00H.
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Figure 6-2. Format of 16-Bit Timer Mode Control Register 20
Symbol
<7>
<6>
5
4
3
2
1
<0>
Address
FF48H
After reset R/W
00H
R/WNote 1
TMC20 TOD20
TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TOD20
Timer output data
Timer output is “0”
0
1
Timer output is “1”
TOF20
Set overflow flag
Reset and clear by software
0
1
Set by overflow of 16-bit timer
CPT201 CPT200
Selection of capture edge
0
0
1
1
0
1
0
1
Capture operation disabled
Rising edge of CPT20 pin
Falling edge of CPT20 pin
Both edges of CPT20 pin
TOC20
Timer output data inversion control
0
1
Inversion disabled
Inversion enabled
TCL201 TCL200
Selection of count clock for 16-bit timer counter 20
Timer 61 interrupt signal
0
0
1
1
0
1
0
1
fX (5.0 MHz)Notes 2, 3
2
fX/2 (1.25 MHz)Note 4
5
fX/2 (156.25 kHz)Note 4
TOE20
Output control for 16-bit timer counter 20
0
1
Output disabled (port mode)
Output enabled
Notes 1. Bit 7 is read-only.
2. If fX is selected for the count clock, the signal cannot be used as a capture signal.
3. In a read operation, set the CPU clock as the high-speed main clock (PCC1 = 0, CSS = 0).
4. In a read operation, set the CPU clock as the main clock (CSS = 0).
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operational fX = 5.0 MHz.
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CHAPTER 6 16-BIT TIMER 20
(2) Port mode register 3 (PM3)
This register is used to set the I/O mode of port 3 in 1-bit units.
When using the P33/INTP3/CPT20/TO20 pin as a capture input (CPT20), set PM33 to 1. When using the
above pin as a timer output (TO20), set the PM33 and P33 output latches to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 6-3. Format of Port Mode Register 3
Symbol
PM3
7
1
6
1
5
1
4
3
2
1
0
Address
FF23H
After reset R/W
FFH R/W
PM34
PM33
PM32
PM31
PM30
PM33
Selection of P33 pin I/O mode
0
1
Output mode (output buffer is on)
Input mode (output buffer is off)
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6.4 16-Bit Timer 20 Operation
6.4.1 Operation as timer interrupt
16-bit timer 20 can generate interrupts repeatedly each time the free-running counter value reaches the value set
to CR20. Since this counter is not cleared and holds the count even after an interrupt is generated, the interval time is
equal to one cycle of the count clock set in TCL201 and TCL200.
To operate 16-bit timer 20 as a timer interrupt, the following settings are required.
• Set count values in CR20
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 6-4.
Figure 6-4. Settings of 16-Bit Timer Mode Control Register 20 for Timer Interrupt Operation
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TMC20
−
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Setting of count clock (see Table 6-2)
Caution If both the CPT201 and CPT200 flags are set to 0, the capture edge operation is prohibited.
When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, counting of TM20
continues and an interrupt request signal (INTTM20) is generated.
Table 6-2 shows interval time, and Figure 6-5 shows timing of timer interrupt operation.
Caution When rewriting the value in CR20 during a count operation, be sure to execute the following
processing.
<1> Disable interrupts (set TMMK20 (bit 2 of interrupt mask flag register 1 (MK1)) to 1).
<2> Disable inversion control of timer output data (set TOC20 to 0)
If the value in CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at
the moment of rewrite.
Table 6-2. Interval Time of 16-Bit Timer 20
TCL201
TCL200
Count Clock
Timer 61 interrupt signal
Interval Time
Cycle of timer 61 interrupt signal × 216
216/fX (13.1 ms)
218/fX (52.4 ms)
221/fXT (419 ms)
0
0
1
1
0
1
0
1
1/fX (0.2 µs)
22/fX (0.8 µs)
25/fX (6.4 µs)
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 6 16-BIT TIMER 20
Figure 6-5. Timing of Timer Interrupt Operation
t
Count clock
TM20 count value
0000H
0001H
N
0000H 0001H
N
N
FFFFH
CR20
N
N
N
N
INTTM20
Interrupt
acknowledgement
Interrupt
acknowledgement
TO20
TOF20
Overflow flag set
Remark N = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 20
6.4.2 Operation as timer output
16-bit timer 20 can invert the timer output repeatedly each time the free-running counter value reaches the value
set to CR20. Since this counter is not cleared and holds the count even after the timer output is inverted, the interval
time is equal to one cycle of the count clock set in TCL201 and TCL200.
To operate 16-bit timer 20 as a timer output, the following settings are required.
• Set P33 to output mode (PM33 = 0).
• Reset the output latch of P33 to 0.
• Set the count value in CR20.
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 6-6.
Figure 6-6. Settings of 16-Bit Timer Mode Control Register 20 for Timer Output Operation
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TMC20
−
0/1
0/1
0/1
1
0/1
0/1
1
TO20 output enable
Setting of count clock (see Table 6-2)
Inverse enable of timer output data
Caution If both the CPT201 flag and CPT200 flag are set to 0, the capture edge operation is prohibited.
When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of the
TO20 pin is inverted. This enables timer output. At that time, TM20 continues counting and an interrupt request
signal (INTTM20) is generated.
Figure 6-7 shows the timing of timer output (see Table 6-2 for the interval time of 16-bit timer 20).
Figure 6-7. Timer Output Timing
t
Count clock
TM20 count value
CR20
0000H
0001H
N
0000H 0001H
N
N
FFFFH
N
N
N
N
INTTM20
Interrupt
acknowledgement
Interrupt
acknowledgement
TO20Note
TOF20
Overflow flag set
Note The initial value of TO20 becomes low level when output is enabled (TOE20 = 1).
Remark N = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 20
6.4.3 Capture operation
The capture operation consists of latching the count value of 16-bit timer counter 20 (TM20) into a capture register
in synchronization with a capture trigger, and retaining the count value.
Set TMC20 as shown in Figure 6-8 to allow the 16-bit timer to start the capture operation.
Figure 6-8. Settings of 16-Bit Timer Mode Control Register 20 for Capture Operation
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TMC20
−
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Count clock selection
Capture edge selection (see Table 6-3)
16-bit capture register 20 (TCP20) starts a capture operation after a CPT20 capture trigger edge is detected, and
latches and retains the count value of 16-bit timer 20. TCP20 fetches the count value within 2 clocks and retains the
count value until the next capture edge detection.
Table 6-3 and Figure 6-9 show the settings of the capture edge and the capture operation timing, respectively.
Table 6-3. Settings of Capture Edge
CPT201
CPT200
Capture Edge Selection
0
0
1
1
0
1
0
1
Capture operation prohibited
CPT20 pin rising edge
CPT20 pin falling edge
CPT20 pin both edges
Caution Because TCP20 is rewritten when a capture trigger edge is detected during TCP20 read, disable
capture trigger edge detection during TCP20 read.
Figure 6-9. Capture Operation Timing (with Both Edges of CPT20 Pin Specified)
Count clock
TM20
Count read buffer
TCP20
0000H 0001H
0000H 0001H
N
N
M
1
M
M
Undefined
N
M
Capture start
Capture start
CPT20
Capture edge detection
Capture edge detection
Remark N, M = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 20
6.4.4 16-bit timer counter 20 readout
The count value of 16-bit timer counter 20 (TM20) is read out using a 16-bit manipulation instruction.
TM20 readout is performed via the counter read buffer. The counter read buffer latches the TM20 count value, the
buffer operation is held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises, and
the count value is retained. The retained counter read buffer value can be read out as the count value.
Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM20
higher byte falls.
RESET input sets TM20 to 0000H and TM20 starts free running.
Figure 6-10 shows the timing of 16-bit timer counter 20 readout.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during the oscillation stabilization time.
2. Though TM20 is designed for a 16-bit transfer instruction, an 8-bit transfer instruction can
also be used.
When using an 8-bit transfer instruction, execute it by direct addressing.
3. When using an 8-bit transfer instruction, execute in the order from lower byte to higher byte
in pairs. If only the lower byte is read, the pending state of the counter read buffer is not
canceled, and if only the higher byte is read, an undefined count value is read.
Figure 6-10. 16-Bit Timer Counter 20 Readout Timing
CPU clock
Count clock
TM20
Count read buffer
TM20 read signal
0000H
0000H
0001H
0001H
N
N + 1
N
Read signal latch
prohibited period
Remark N = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 20
6.5 Cautions on Using 16-Bit Timer 20
6.5.1 Restrictions when rewriting 16-bit compare register 20
(1) Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0) before rewriting the
compare register (CR20).
If the value in CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment
of rewrite.
(2) Depending on the timing of rewriting the compare register (CR20), the interval time may become twice as
long as the intended time. Similarly, a shorter waveform or twice-longer waveform than the intended timer
output waveform may be output.
To avoid this problem, rewrite the compare register using either of the following procedures.
<Countermeasure A> When rewriting using 8-bit access
<1> Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0).
<2> First rewrite the higher byte of CR20 (16 bits).
<3> Then rewrite the lower byte of CR20 (16 bits).
<4> Clear the interrupt request flag (TMIF20).
<5> Enable timer interrupts/timer output inversion after half a cycle or more of the count clock has elapsed from
the start of the interrupt.
<Program example A> (count clock = 32/fX, CPU clock = fX)
TM20_VCT: SET1 TMMK20
CLR1 TMC20.3
MOV A, #xxH
; Disable timer interrupts (6 clocks)
; Disable timer output inversion (6 clocks)
; Set the rewrite value of the higher byte (6 clocks)
; Rewrite the CR20 higher byte (8 clocks)
; Set the rewrite value of the lower byte (6 clocks)
; Rewrite the CR20 lower byte (8 clocks)
; Clear the interrupt request flag (6 clocks)
; Enable timer interrupts (6 clocks)
MOV !0FF17H, A
MOV A, #yyH
Total: 16 clocks
or moreNote
MOV !0FF16H,A
CLR1 TMIF20
CLR1 TMMK20
SET1 TMC20.3
; Enable timer output inversion
Note Because the INTTM20 signal becomes high level for half a cycle of the count clock after an interrupt is
generated, the output is inverted if TOC20 is set to 1 during this period.
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CHAPTER 6 16-BIT TIMER 20
<Countermeasure B> When rewriting using 16-bit access
<1> Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0).
<2> Rewrite CR20 (16 bits).
<3> Wait for one cycle or more of the count clock.
<4> Clear the interrupt request flag (TMIF20).
<5> Enable timer interrupts/timer output inversion
<Program example B> (count clock = 32/fX, CPU clock = fX)
TM20_VCT: SET1 TMMK20
; Disable timer interrupts
; Disable timer output inversion
; Set the rewrite value of CR20
; Rewrite CR20
CLR1 TMC20.3
MOVW A, #xxyyH
MOVW CR20, AX
NOP
NOP
:
; 16 NOP instructions (wait for 32/fX)Note
NOP
NOP
CLR1 TMIF20
CLR1 TMMK20
SET1 TMC20.3
; Clear the interrupt request flag
; Enable timer interrupts
; Enable timer output inversion
Note Clear the interrupt request flag (TMIF20) after waiting for one cycle or more of the count clock from the
instruction that rewrites CR20 (MOVW CR20, AX).
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
7.1 Functions of 8-Bit Timers 50, 60, and 61
One 8-bit timer channel (timer 50) and two 8-bit timer/event counter channels (timer 60 and 61) are incorporated in
the µPD789489 Subseries. The operation modes listed in the following table can be set via mode register settings.
Table 7-1. Operation Modes
Channel
Timer 50
Available
Timer 60
Available
Timer 61
Mode
8-bit timer counter mode
(stand-alone mode)
Available
16-bit timer counter mode
(cascade connection mode)
Available
Available
Not available
Carrier generator mode
PWM output mode
PPG output mode
Not available
Not available
Available
Available
Not available
Available
Not available
Not available
24-bit event counter mode
Not available
Available
(connect with 16-bit timer 20)
(1) Mode to use 8-bit timer/event counter as discrete unit (stand-alone mode)
The following functions can be used in this mode.
<Timer 50>
• Interval timer with 8-bit resolution
• Square wave output with 8-bit resolution
<Timer 60 and 61>
• Interval timer with 8-bit resolution
• External event counter with 8-bit resolution
• Square wave output with 8-bit resolution
(2) Mode to use timer 50 and timer 60 connected in cascade (16-bit resolution: cascade connection)
Operation as a 16-bit timer/event counter is enabled in cascade connection mode.
The following functions can be used in this mode.
• Interval timer with 16-bit resolution
• External event counter with 16-bit resolution
• Square wave output with 16-bit resolution
(3) Carrier generator mode
The carrier clock generated by timer 60 is output in the cycle set by timer 50.
(4) PWM output mode (PWM: Pulse Width Modulator)
Pulses are output using any duty ratio (pulse width). The cycle (overflow cycle of the timer) becomes
constant (free running).
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
(5) PPG output mode (PPG: Programmable Pulse Generator)
Pulses are output using any cycle or duty ratio (pulse width) set (both the cycle and pulse width are
programmable).
(6) 24-bit event counter mode
Operation as an external event counter with 24-bit resolution is enabled using 16-bit timer 20 and timer 61.
However, this mode operates only as a counter read function.
There is no compare, match, or clear function.
<Setting method>
<1> Select the timer 61 interrupt signal for the count clock of 16-bit timer 20 (TCL201 = 0, TCL200 = 0)
<2> Set timer 61 in stand-alone mode (TMD611 = 0)
Select the external clock input from pin TMI61 for the count clock of timer 61
((TCL612 = 0, TCL611 = 1) or (TCL612 = 1, TCL611 = 0))
<3> Set CR61 to FFH
<4> Read the current count value of 16-bit timer 20
(16-bit timer 20 does not have a count clear function and is counting constantly)
<5> Enable timer 61 count operation (TCE61 = 1)
Figure 7-1. Block Diagram of 24-Bit Event Counter
Internal bus
Timer read
Timer read
Timer 61
(lower 8 bits)
Timer 20
(higher 16 bits)
TMI61/TO61
/INTP2/P32
Select timer 61 interrupt
signal for count clock
Select external clock
for count clock
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
7.2 Configuration of 8-Bit Timers 50, 60, and 61
8-bit timers 50, 60, and 61 include the following hardware.
Table 7-2. Configuration of 8-Bit Timers 50, 60, and 61
Item
Configuration
Timer counter
Registers
8 bits × 3 (TM50, TM60, TM61)
Compare registers: 8 bits × 5 (CR50, CR60, CRH60, CR61, CRH61)
Timer outputs
3 (TO50, TO60, TO61)
Control registers
8-bit timer mode control register 50 (TMC50)
8-bit timer mode control register 60 (TMC60)
Carrier generator output control register 60 (TCA60)
8-bit timer mode control register 61 (TMC61)
Port mode register 3 (PM3)
Port 3 (P3)
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Figure 7-2. Block Diagram of Timer 50
Internal bus
8-bit timer mode control register 50
(TMC50)
P30
output latch
TEG50
TCE50
TCL502 TCL501 TCL500 TMD501 TMD500
TOE50
PM30
8-bit compare register 50
(CR50)
Decoder
Timer 50 match signal
to Figure 7-3(F)
(F)
Match
(in cascade connection mode)
(A)
Bit 7 of TM60
(from Figure 7-3(A))
INTTM50
f
X
f
X
/23
/27
OVF
8-bit timer counter 50
(TM50)
f
X
S
R
TO50/TMI60/
INTP0/P30
f
XT
IN
Q
Q
(B)
(C)
Timer 60 interrupt request signal
(from Figure 7-3(B))
Carrier clock
Clear
Selector
CK
(from Figure 7-3(C))
Timer 50 match signal
to Figure 7-3(G)
(G)
(in carrier generator mode)
Cascade
connection
mode
PWM mode
Timer 60 match signal
from Figure 7-3(E)
(in cascade connection mode)
(D)
(E)
Count operation start signal
from Figure 7-3(D)
(cascade connection)
Figure 7-3. Block Diagram of Timer 60
Internal bus
8-bit timer mode control
register 60 (TMC60)
Carrier generator output
control register 60 (TCA60)
8-bit H width compare
8-bit compare
register 60
register 60 (CR60)
(CRH60)
TCE60 TCL602 TCL601 TCL600 TMD601 TMD600 TOE600
RMC60 NRZB60 NRZ60
Decoder
(G)
Timer counter match signal
from timer 50 in Figure 7-2(G)
(in carrier generator mode)
Selector
Output
F/F
Match
TO60/INTP1/P31
controllerNote
(C)
(A)
To Figure 7-2(C) carrier clock
f
X
8-bit timer counter 60
f
/22
X
(TM60)
OVF
f
TMI
TMI60/TO50/
INTP0/P30
Clear
f
TMI/2
PPG mode
f
TMI/22
TMI/23
To Figure 7-2(A)
Bit 7 of TM60
(in cascade connection mode)
Cascade connection mode
f
Reset
(D)
INTTM60
To Figure 7-2(B)
Timer 60 interrupt request signal
To Figure 7-2(D)
Count operation start
signal to timer 50
(B)
(E)
To Figure 7-2(E)
Timer counter match
signal for TM60
count clock signal
input to TM50
(in cascade connection mode)
(in cascade connection mode)
(F)
From Figure 7-2(F)
TM50 match signal
(in cascade connection mode)
Figure 7-4. Block Diagram of Timer 61
Internal bus
8-bit timer mode control
register 61 (TMC61)
8-bit H width compare
register 61 (CRH61)
8-bit compare
register 61 (CR61)
P32
output latch
TCE61 TCL612 TCL611 TCL610 TMD611 TMD610 TOE610
PM32
Decoder
Selector
TO61/TMI61
/INTP2/P32
Match
F/F
f
X
8-bit timer counter 61
(TM61)
f
/24
X
f
TMI
Clear
TMI61/TO61
/INTP2/P32
f
TMI/2
PPG mode
f
TMI/22
TMI/23
INTTM61
f
Reset
To timer 20 count clock
input signal in Figure 6-1
Timer 61 interrupt request signal
(in 24-bit event counter mode)
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-5. Block Diagram of Output Controller (Timer 60)
RMC60
TOE60
NRZ60
P31
output latch
PM31
TO60/INTP1/P31
Carrier clock
F/F
Carrier generator mode
(1) 8-bit compare register 50 (CR50)
This 8-bit register is used to continually compare the value set to CR50 with the count value in 8-bit timer
counter 50 (TM50) and to issue an interrupt request (INTTM50) when a match occurs. In PWM mode, this
register is used for high-level width setting.
CR50 is set with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
Cautions 1. In PWM output mode (TMD501 = 1, TMD500 = 0), if CR50 is rewritten while the timer is
operating, a high level may be output for one clock cycle immediately after this rewrite
operation. If this waveform may cause problems in the application, either <1> stop the
timer when rewriting CR50, or <2> rewrite CR50 after TOE50 has been cleared.
2. If both edges have been selected as the valid edge of the count clock in PWM output
mode (TEG50 = 1), do not set CR50 to 00H, 01H, or FFH. Also, if the rising edge has
been selected as the valid edge (TEG50 = 0), do not set CR50 to 00H.
(2) 8-bit compare register 60 (CR60)
When connected to TM50 via a cascade connection and using as a 16-bit timer/event counter, the interrupt
request (INTTM60) occurs only when matches occur simultaneously between CR50 and TM50 and between
CR60 and TM60 (INTTM50 is not generated).
In carrier generator mode and PPG output mode, the low-level width of timer output is set by writing a value
to CR60.
CR60 is set with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
(3) 8-bit compare register 61 (CR61)
This 8-bit register is used to continually compare the value set to CR61 with the count value in 8-bit timer
counter 61 (TM61) and issue an interrupt request (INTTM61) when a match occurs. In PPG output mode,
this registered used for low-level width setting.
CR61 is set with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
(4) 8-bit H width compare registers 60 and 61 (CRH60, CRH61)
In carrier generator mode and PPG output mode, the high-level width of timer output is set by writing a value
to CRH6n. This 8-bit register is used to continually compare the value set to CRH6n with the count value in
8-bit timer counter 6n (TM6n) and to issue an interrupt request (INTTM6n) when a match occurs.
CRH6n is set with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
Remark n = 0, 1
(5) 8-bit timer counters 50, 60, and 61(TM50, TM60, TM61)
These are 8-bit registers that are used to count the count pulse.
TM50, TM60, and TM61 are read via an 8-bit memory manipulation instruction.
RESET input sets these register values to 00H.
TM50, TM60, and TM61 are cleared to 00H under the following conditions.
(a) Stand-alone mode
• After reset
• When TCEmn (bit 7 of 8-bit timer mode control register mn (TMCmn)) is cleared to 0
• When a match occurs between TMmn and CRmn
• When the TMmn count value overflows
Remark mn = 50, 60, 61
(b) Cascade connection mode (TM50 and TM60 are simultaneously cleared to 00H)
• After reset
• When the TCE60 flag is cleared to 0
• When matches occur simultaneously between TM50 and CR50 and between TM60 and CR60
• When the TM50 and TM60 count values overflow simultaneously
(c) Carrier generator (TM60) and PPG output mode (TM60 and TM61)
• After reset
• When the TCE6n flag is cleared to 0
• When a match occurs between TM6n and CR6n
• When a match occurs between TM6n and CRH6n
• When the TM6n count value overflows
Remark n = 0, 1
(d) PWM output mode (TM50)
• After reset
• When the TCE50 flag is cleared to 0
• When the TM50 count value overflows
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
7.3 Control Registers for 8-Bit Timers 50, 60, and 61
8-bit timers 50, 60, and 61 are controlled by the following six registers.
• 8-bit timer mode control register 50 (TMC50)
• 8-bit timer mode control register 60 (TMC60)
• Carrier generator output control register 60 (TCA60)
• 8-bit timer mode control register 61 (TMC61)
• Port mode register 3 (PM3)
• Port 3
(1) 8-bit timer mode control register 50 (TMC50)
8-bit timer mode control register 50 (TMC50) is used to control the timer 50 count clock setting and the
operation mode setting.
TMC50 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 7-6. Format of 8-Bit Timer Mode Control Register 50 (1/2)
Symbol
<7>
<6>
5
4
3
2
1
<0>
Address After reset
FF4DH 00H
R/W
R/W
TMC50 TCE50
TEG50
TCL502 TCL501 TCL500 TMD501 TMD500 TOE50
TCE50
Control of TM50 count operationNote 1
0
1
Clear TM50 count value and stop operation
Start count operation
TEG50
Selection of valid edge of TM50 count clock
0
1
Count at the rising edge of the count clock
Count at both edges of the count clockNote 2
TCL502 TCL501 TCL500
Selection of timer 50 count clock
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fX (5.0 MHz)
fX/23 (625 kHz)
fX/27 (39.1 kHz)
fXT (32.768 kHz)
Timer 60 match signal (INTTM60)
Carrier clock (in carrier generator mode) or timer 60 output signal (in other than carrier
generator mode)
Other than above
Setting prohibited
TMD501 TMD500 TMD601 TMD600
Selection of operation mode for timer 50Note 3
Stand-alone mode (8-bit counter mode)
0
0
0
1
0
1
0
0
×
0
1
×
0
1
1
0
16-bit counter mode (cascade connection mode)
Carrier generator mode
PWM output mode
Other than above
Setting prohibited
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-6. Format of 8-Bit Timer Mode Control Register 50 (2/2)
Symbol
<7>
<6>
5
4
3
2
1
<0>
Address After reset
FF4DH 00H
R/W
R/W
TMC50 TCE50
TEG50
TCL502 TCL501 TCL500 TMD501 TMD500 TOE50
TOE50
Control of timer outputNote 4
0
1
Output disabled
Output enabled
Notes 1. Since the count operation is controlled by TCE60 (bit 7 of TMC60) in cascade connection mode,
any setting for TCE50 is ignored.
2. Selection of both edges is valid only in PWM mode. In 8-bit counter mode or cascade connection
mode, even if TEG50 is set to 1, counting occurs at the rising edge.
3. The operation mode selection is set by a combination of the TMC50 and TMC60 registers.
4. Since timer 50 output is disabled in cascade connection mode, set TOE50 to 0.
Cautions 1. In cascade connection mode, the timer 60 output signal is forcibly selected for the count
clock.
2. To manipulate TMC50, follow the setting procedure below.
<1> Set the TM50 count operation to stop.
<2> Set the operation mode and count clock.
<3> The count operation starts.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
4. ×: don’t care
(2) 8-bit timer mode control register 60 (TMC60)
8-bit timer mode control register 60 (TMC60) is used to control the timer 60 count clock setting and the
operation mode setting.
TMC60 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-7. Format of 8-Bit Timer Mode Control Register 60
Symbol
<7>
6
0
5
4
3
2
1
<0>
Address After reset
FF4EH 00H
R/W
R/W
TMC60 TCE60
TCL602 TCL601 TCL600 TMD601 TMD600 TOE600
TCE60
0
Control of TM60 count operationNote 1
Clear TM60 count value and stop operation (the count value is also cleared for TM50 in cascade connection
mode)
1
Start count operation (the count operation is also started for TM50 in cascade connection mode)
TCL602 TCL601 TCL600
Selection of timer 60 count clock
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fX (5.0 MHz)
2
fX/2 (1.25 MHz)
fTMI
fTMI/2
2
fTMI/2
3
fTMI/2
Other than above
Setting prohibited
TMD501 TMD500 TMD601 TMD600
Selection of operation mode for timer 60Note 2
×
0
0
×
0
1
0
0
0
0
1
1
0
1
1
0
Stand-alone mode (8-bit counter mode)
16-bit counter mode (cascade connection mode)
Carrier generator mode
PPG output mode
Other than above
Setting prohibited
TOE600
Control of timer output
0
1
Output disabled
Output enabled
Notes 1. Since the count operation is controlled by TCE60 (bit 7 of TMC60) in cascade connection mode,
any setting for TCE50 is ignored.
2. The operation mode selection is set by a combination of the TMC50 and TMC60 registers.
Caution To manipulate TMC60, follow the setting procedure below.
<1> Set the TM60 count operation to stop.
<2> Set the operation mode and count clock.
<3> The count operation starts.
Remarks 1. fX:
Main system clock oscillation frequency
2. fTMI: External input clock frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz.
4. ×:
don’t care
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
(3) Carrier generator output control register 60 (TCA60)
This register is used to set the timer output data in carrier generator mode.
TCA60 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 7-8. Format of Carrier Generator Output Control Register 60
Symbol
TCA60
7
0
6
0
5
0
4
0
3
0
<2>
<1>
<0>
Address
FF4FH
After reset
00H
R/W
R/WNote
RMC60 NRZB60 NRZ60
RMC60
0
Control of remote control output
When NRZ60 = 1, a carrier pulse is output to TO60/INTP1/P31 pin
(when NRZ60 = 0, a low level is output to TO60/INTP1/P31 pin)
1
When NRZ60 = 1, high-level signal is output to TO60/INTP1/P31 pin
(when NRZ60 = 0, a low level is output to TO60/INTP1/P31 pin)
NRZB60 This is the bit that stores the next data to be output to NRZ60. When a match signal occurs (for a match with
timer 50), the data is output to NRZ60.
NRZ60
No return zero data
Output low-level signal (carrier clock is stopped)
Output carrier pulse or high-level signal
0
1
Note Bit 0 is write-only
Cautions 1. At the count start, input the values of the data reloaded from NRZB60 to NRZ60. For
NRZB60, input the data required by the program in advance.
2. When timer 60 output is disabled (TOE600 = 0), use of a 1-bit memory manipulation
instruction for TCA60 is disabled (only an 8-bit memory manipulation instruction can be
used).
3. When timer 60 output is enabled (TOE600 = 1), a write operation to NRZ is invalid.
However, while the timer 50 interrupt signal (INTTM50) is high level, the NRZB60 value is
immediately transferred to NRZ60 if TCA60 is rewritten. Rewrite TCA60 after waiting for
half a clock of the TM50 count clock during INTTM50 interrupt servicing.
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
(4) 8-bit timer mode control register 61 (TMC61)
8-bit timer mode control register 61 (TMC61) is used to control the timer 61 count clock setting and the
operation mode setting.
TMC61 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 7-9. Format of 8-Bit Timer Mode Control Register 61
Symbol
TMC61
<7>
6
0
5
4
3
2
1
<0>
Address
FF41H
After reset
00H
R/W
R/W
TCE61
TCL612 TCL611 TCL610 TMD611 TMD610 TOE610
TCE61
Control of TM61 count operation
0
1
Clear TM61 count value and stop operation
Start count operation
Note
Selection of timer 61 count clock
TCL612 TCL611
TCL610
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fX (5.0 MHz)
4
fX/2 (313 kHz)
fTMI
fTMI/2
fTMI/22
fTMI/23
Other than above
Setting prohibited
Note
Selection of operation mode for timer 61
TMD611 TMD610
0
1
0
0
Stand-alone mode (8-bit counter mode)
PPG output mode
Other than above
Setting prohibited
TOE610
Control of timer output
0
1
Output disabled
Output enabled
Note To set the register in 24-bit event counter mode, the external input clock and stand-alone mode need to
be selected.
Caution To manipulate TMC61, follow the setting procedure below.
<1> Set the TM61 count operation to stop.
<2> Set the operation mode and count clock.
<3> The count operation starts.
Remarks 1. fX: Main system clock oscillation frequency
2. fTMI: External input clock frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
(5) Port mode register 3 (PM3)
This register is used to set the I/O mode of port 3 in 1-bit units.
When using the P30/INTP0/TO50/TMI60 pin as a timer output (TO50), set PM30 and the P30 output latch to 0.
When used as a timer input (TMI60), set PM30 to 1.
When using the P31/INTP1/TO60 pin as a timer output (TO60), set PM31 and the P31 output latch to 0.
When using the P32/INTP2/TO61/TMI61 pin as a timer input (TMI61), set PM32 to 1. When used as a timer
output (TO61), set PM32 and the P32 output latch to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 7-10. Format of Port Mode Register 3
Symbol
PM3
7
1
6
1
5
1
4
3
2
1
0
Address
FF23H
After reset
FFH
R/W
R/W
PM34
PM33
PM32
PM31
PM30
PM3n
I/O mode of P3n pin
(n = 0 to 2)
0
1
Output mode (output buffer is on)
Input mode (output buffer is off)
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
7.4 Operation of 8-Bit Timers 50, 60, and 61
7.4.1 Operation as 8-bit timer counter
Timer 50, timer 60, and timer 61 can be independently used as 8-bit timer counters.
The following modes can be used for the 8-bit timer counter.
•
•
•
Interval timer with 8-bit resolution
External event counter with 8-bit resolution (timer 60 and timer 61 only)
Square wave output with 8-bit resolution
(1) Operation as interval timer with 8-bit resolution
The interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register nm (CRnm).
To operate 8-bit timer nm as an interval timer, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter nm (TMnm) (TCEnm = 0).
<2> For timer 50, disable timer output of TO50 (TOE50 = 0).
For timer 60, disable timer output of TO60 (TOE600 = 0).
For timer 61, disable timer output of TO61 (TOE610 = 0).
<3> Set a count value in CRnm.
<4> Set the operation mode of timer nm to 8-bit timer counter mode
(see Figures 7-6, 7-7, and 7-9).
<5> Set the count clock for timer nm (see Figures 7-6, 7-7, and 7-9).
<6> Enable the operation of TMnm (TCEnm = 1).
When the count value of 8-bit timer counter nm (TMnm) matches the value set in CRnm, TMnm is cleared to
00H and continues counting. At the same time, an interrupt request signal (INTTMnm) is generated.
Tables 7-3 to 7-5 show the interval time, and Figures 7-11 to 7-16 show the timing of the interval timer
operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Remark nm = 50, 60, 61
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Table 7-3. Interval Time of Timer 50
TCL502 TCL501 TCL500
Minimum Interval Time
Maximum Interval Time
28/fX (51.2 µs)
211/fX (409.6 µs)
215/fX (6.55 ms)
Resolution
1/fX (0.2 µs)
23/fX (1.6 µs)
27/fX (25.6 µs)
1/fXT (30.5 µs)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1/fX (0.2 µs)
23/fX (1.6 µs)
27/fX (25.6 µs)
1/fXT (30.5 µs)
28/fXT (7.81 ms)
Input cycle of timer 60 match
signal
Input cycle of timer 60 match
Input cycle of timer 60 match
signal
signal × 28
1
0
1
Input cycle of timer 60 output
Input cycle of timer 60 output
Input cycle of timer 60
output
× 28
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
Table 7-4. Interval Time of Timer 60
TCL602 TCL601 TCL600
Minimum Interval Time
1/fX (0.2 µs)
22/fX (0.8 µs)
Maximum Interval Time
28/fX (51.2 µs)
210/fX (204 µs)
fTMI input cycle × 28
fTMI/2 input cycle × 28
fTMI/22 input cycle × 28
fTMI/23 input cycle × 28
Resolution
1/fX (0.2 µs)
22/fX (0.8 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fTMI input cycle
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remarks 1. fX: Main system clock oscillation frequency
2. fTMI: External input clock frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz.
Table 7-5. Interval Time of Timer 61
TCL612 TCL611 TCL610
Minimum Interval Time
1/fX (0.2 µs)
24/fX (3.2 µs)
Maximum Interval Time
28/fX (51.2 µs)
212/fX (819 µs)
fTMI input cycle × 28
fTMI/2 input cycle × 28
fTMI/22 input cycle × 28
fTMI/23 input cycle × 28
Resolution
1/fX (0.2 µs)
24/fX (3.2 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fTMI input cycle
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remarks 1. fX: Main system clock oscillation frequency
2. fTMI: External input clock frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-11. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
t
Count clock
TMnm
N
00H 01H
Clear
00H
01H
00H 01H
Clear
00H 01H
Clear
00H
N
N
N
CRnm
TCEnm
Count start
Count stop
INTTMnm
TOnm
Interrupt acknowledgement
Interval time
Interrupt acknowledgement
Interval time
Interrupt acknowledgement
Remarks 1. Interval time = (N + 1) × t: N = 00H to FFH
2. nm = 50, 60, 61
Figure 7-12. Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Is Set to 00H)
Count clock
00H
00H
TMnm
CRnm
TCEnm
Count start
INTTMnm
TOnm
Remark nm = 50, 60, 61
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Is Set to FFH)
Count clock
FFH
00H
01H
00H 01H
Clear
00H 01H
Clear
00H
00H
FFH
FFH
TMnm
FFH
Clear
FFH
CRnm
TCEnm
Count start
INTTMnm
TOnm
Remark nm = 50, 60, 61
Figure 7-14. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRnm Changes from N to M (N < M))
Count clock
TMnm
00H
N
N
M
00H
M
00H
Clear
01H
01H
00H
N
Clear
Clear
N
CRnm
M
TCEnm
Count start
INTTMnm
TOnm
Interrupt acknowledgement
CRnm overwritten
Interrupt acknowledgement
Remark 00H ≤ N < M ≤ FFH
nm = 50, 60, 61
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-15. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRnm Changes from N to M (N > M))
Count clock
TMnm
N − 1
M
N
FFH
00H
M
M
00H
N
00H
00H
Clear
Clear
Clear
N
CRnm
M
H
TCEnm
TMnm overflows
because M < N
INTTMnm
TOnm
CRnm overwritten
Remark 00H ≤ M < N ≤ FFH
nm = 50, 60, 61
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-16. Timing of Interval Timer Operation with 8-Bit Resolution
(When Timer 60 Match Signal Is Selected for Timer 50 Count Clock)
Timer 60
count clock
M
M
M
00H
00H
01H
N
00H
00H
00H
M
TM60
Clear
Clear
Clear
Clear
N
CR60
TCE60
Count start
INTTM60
Input clock to timer 50
(timer 60 match signal)
Y
00H
00H
00H
01H
Y − 1
Y
TM50
CR50
Y
TCE50
INTTM50
TO60
Count start
TO50
Remark 00H ≤ N < M ≤ FFH
Y = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
(2) Operation as external event counter with 8-bit resolution (timer 60 and timer 61 only)
The external event counter counts the number of external clock pulses input to the TMI6m pin by using 8-bit
timer counter 6m (TM6m).
To operate timer 6m as an external event counter, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 6m (TM6m) (TCE6m = 0).
<2> Disable timer output of TO6m (TOE6m0 = 0).
<3> When using timer 60, set P30 to input mode (PM30 = 1).
When using timer 61, set P32 to input mode (PM32 = 1).
<4> Select the external input clock for timer 6m (see Figures 7-7 and 7-9).
<5> Set the operation mode of timer 6m to 8-bit timer counter mode (see Figures 7-7 and 7-9).
<6> Set a count value in CR6m.
<7> Enable the operation of TM6m (TCE6m = 1).
Each time the valid edge is input, the value of TM6m is incremented.
When the count value of TM6m matches the value set in CR6m, TM6m is cleared to 00H and continues
counting. At the same time, an interrupt request signal (INTTM6m) is generated.
Figure 7-17 shows the timing of the external event counter operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Remark m = 0, 1
Figure 7-17. Timing of Operation of External Event Counter with 8-Bit Resolution
TMI6m pin input
TM6m count value
CR6m
00H 01H 02H 03H 04H 05H
N − 1
N
00H 01H 02H 03H
N
TCE6m
INTTM6m
Remark N = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
(3) Operation as square-wave output with 8-bit resolution
Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare
register nm (CRnm).
To operate timer nm for square-wave output, settings must be made in the following sequence.
<1> When using timer 50, set P30 to output mode (PM30 = 0) and the P30 output latch to 0, respectively.
When using timer 60, set P31 to output mode (PM31 = 0) and the P31 output latch to 0, respectively.
When using timer 61, set P32 to output mode (PM32 = 0) and the P32 output latch to 0, respectively.
<2> Disable operation of timer counter nm (TMnm) (TCEnm = 0).
<3> Set a count clock for timer nm (see Figures 7-6, 7-7 and 7-9)
<4> For timer 50, enable timer output of TO50 (TOE50 = 1).
For timer 60, enable timer output of TO60 (TOE600 = 1).
For timer 61, enable timer output of TO61 (TOE610 = 1).
<5> Set a count value in CRnm.
<6> Enable the operation of TMnm (TCEnm0 = 1).
When the count value of TMnm matches the value set in CRnm, the TOnm pin output will be inverted.
Through application of this mechanism, square waves of any frequency can be output. As soon as a match
occurs, TMnm is cleared to 00H and continues counting. At the same time, an interrupt request signal
(INTTMnm) is generated.
The square-wave output is cleared to 0 by setting TCEnm to 0.
Tables 7-6 to 7-8 show the square-wave output range, and Figure 7-18 shows the timing of square-wave
output.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Remark nm = 50, 60, 61
Table 7-6. Square-Wave Output Range of Timer 50
TCL502 TCL501 TCL500
Minimum Pulse Width
1/fX (0.2 µs)
23/fX (1.6 µs)
27/fX (25.6 µs)
1/fXT (30.5 µs)
Maximum Pulse Width
28/fX (51.2 µs)
211/fX (409.6 µs)
215/fX (6.55 ms)
28/fXT (7.81 ms)
Resolution
1/fX (0.2 µs)
23/fX (1.6 µs)
27/fX (25.6 µs)
1/fXT (30.5 µs)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Input cycle of timer 60 match
signal
Input cycle of timer 60 match
Input cycle of timer 60 match
signal
signal × 28
1
0
1
Input cycle of timer 60 output
Input cycle of timer 60 output
Input cycle of timer 60 output
× 28
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Table 7-7. Square-Wave Output Range of Timer 60
TCL602 TCL601 TCL600
Minimum Pulse Width
1/fX (0.2 µs)
22/fX (0.8 µs)
Maximum Pulse Width
Resolution
8
2 /fX (51.2 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1/fX (0.2 µs)
10
2
2
/fX (204 µs)
2 /fX (0.8 µs)
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI input cycle × 28
fTMI/2 input cycle × 28
fTMI/22 input cycle × 28
fTMI/23 input cycle × 28
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remarks 1. fX: Main system clock oscillation frequency
2. fTMI: External input clock frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz.
Table 7-8. Square-Wave Output Range of Timer 61
TCL612 TCL611 TCL610
Minimum Pulse Width
1/fX (0.2 µs)
24/fX (3.2 µs)
Maximum Pulse Width
Resolution
8
2 /fX (51.2 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1/fX (0.2 µs)
12
4
2
/fX (819 µs)
2 /fX (3.2 µs)
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI input cycle × 28
fTMI/2 input cycle × 28
fTMI/22 input cycle × 28
fTMI/23 input cycle × 28
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remarks 1. fX: Main system clock oscillation frequency
2. fTMI: External input clock frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz.
Figure 7-18. Timing of Square-Wave Output with 8-Bit Resolution
Count clock
TMnm
N
00H 01H
Clear
01H
N
00H 01H
Clear
00H 01H
Clear
00H
N
N
CRnm
TCEnm
Count start
INTTMnm
TOnmNote
Interrupt acknowledgement
Interrupt acknowledgement
Interrupt acknowledgement
Note The initial value of TOnm is low level when output is enabled.
Remark N = 00H to FFH
nm = 50, 60, 61
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
7.4.2 Operation as 16-bit timer counter
Timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer
counter 50 (TM50) is the higher 8 bits and 8-bit timer counter 60 (TM60) is the lower 8 bits. 8-bit timer 60 controls
reset and clear.
The following modes can be used for the 16-bit timer counter.
•
•
•
Interval timer with 16-bit resolution
External event counter with 16-bit resolution
Square-wave output with 16-bit resolution
(1) Operation as interval timer with 16-bit resolution
The interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register 50 (CR50) and 8-bit compare register 60 (CR60).
To operate as an interval timer with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 50 (TM50) and 8-bit timer counter 60 (TM60) (TCE50 = 0,
TCE60 = 0).
<2> Disable timer output of TO60 (TOE600 = 0).
<3> Set the count clock for timer 60 (see Figure 7-7).
<4> Set the operation mode of timer 50 and timer 60 to 16-bit timer counter mode (see Figures 7-6 and 7-7).
<5> Set a count value in CR50 and CR60.
<6> Enable the operation of TM50 and TM60 (TCE60 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE60 (the value of
TCE50 is invalid).
When the count values of TM50 and TM60 match the values set in CR50 and CR60 respectively, both TM50 and
TM60 are simultaneously cleared to 00H and continue counting. At the same time, an interrupt request signal
(INTTM60) is generated (INTTM50 is not generated).
Table 7-9 shows interval time, and Figure 7-19 shows the timing of the interval timer operation.
Cautions 1. Be sure to stop the timer operation before overwriting the count clock with different data.
2. In the 16-bit timer counter mode, TO50 cannot be used. Be sure to set TOE50 = 0 to disable
TO50 output.
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Table 7-9. Interval Time with 16-Bit Resolution
TCL602 TCL601 TCL600
Minimum Interval Time
1/fX (0.2 µs)
22/fX (0.8 µs)
Maximum Interval Time
216/fX (13.1 ms)
218/fX (52.4 ms)
fTMI input cycle × 216
fTMI/2 input cycle × 216
fTMI/22 input cycle × 216
fTMI/23 input cycle × 216
Resolution
1/fX (0.2 µs)
22/fX (0.8 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fTMI input cycle
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remarks 1. fX: Main system clock oscillation frequency
2. fTMI: External input clock frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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Figure 7-19. Timing of Interval Timer Operation with 16-Bit Resolution
t
Count clock
TM60 count value
00H
N
N
80H
N
7FH
FFH 00H
80H
00H
FFH
7FH
80H
FFH
00H
N
N
00H
7FH
00H
Not cleared because TM50 does not match
Cleared because TM50 and TM60 match simultaneously
CR60
N
N
N
N
N
N
N
N
TCE60
Count start
TM50 count pulse
X
X − 1
00H
X
TM50
CR50
00H
X
01H
00H
X − 1
X
X
INTTM60
TO60
Interrupt acknowledgement
Interrupt acknowledgement
Interrupt not generated because
TM50 does not match
Interval time
Remark Interval time = (256X + N + 1) × t: X = 00H to FFH, N = 00H to FFH
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
(2) Operation as external event counter with 16-bit resolution
The external event counter counts the number of external clock pulses input to the TMI60 pin by TM50 and
TM60.
To operate as an external event counter with 16-bit resolution, settings must be made in the following
sequence.
<1> Disable operation of TM50 and TM60 (TCE50 = 0, TCE60 = 0).
<2> Disable timer output of TO60 (TOE600 = 0).
<3> Set P31 to input mode (PM31 = 1).
<4> Select the external input clock for timer 60 (see Figure 7-7).
<5> Set the operation mode of timer 50 and timer 60 to 16-bit timer counter mode (see Figures 7-6 and 7-7).
<6> Set a count value in CR50 and CR60.
<7> Enable the operation of TM50 and TM60 (TCE60 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE60 (the value of
TCE50 is invalid).
Each time the valid edge is input, the values of TM50 and TM60 are incremented.
When the count values of TM50 and TM60 simultaneously match the values set in CR50 and CR60
respectively, both TM50 and TM60 are cleared to 00H and continue counting. At the same time, an interrupt
request signal (INTTM60) is generated (INTTM50 is not generated).
Figure 7-20 shows the timing of the external event counter operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
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Figure 7-20. Timing of External Event Counter Operation with 16-Bit Resolution
TMI60 pin input
TM60 count value
00H
N
N
7FH 80H
FFH 00H
N
7FH 80H
FFH 00H
00H
7FH 80H
FFH 00H
N
N
00H
Not cleared because TM50 does not match
Cleared because TM50 and TM60 match simultaneously
CR60
N
N
N
N
N
N
N
N
TCE60
Count start
TM50 count pulse
TM50
X
X − 1
00H
X
00H
01H
00H
X − 1
X
CR50
INTTM60
Interrupt not generated because
TM50 does not match
Interrupt acknowledgement
Interrupt
acknowledgement
Remark X = 00H to FFH, N = 00H to FFH
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
(3) Operation as square-wave output with 16-bit resolution
Square waves of any frequency can be output at an interval specified by the count value preset in CR50 and
CR60.
To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of TM50 and TM60 (TCE50 = 0, TCE60 = 0).
<2> Disable output of TO50 and TO60 (TOE50 = 0, TOE600 = 0).
<3> Set a count clock for timer 60. (see Figure 7-7)
<4> Set P31 to the output mode (PM31 = 0), set the P31 output latch to 0, and set TO60 to output enable
(TOE600 = 1). (Use of TO50 is prohibited.)
<5> Set the operation mode of timer 50 and timer 60 to 16-bit timer counter mode (see Figures 7-6 and 7-7).
<6> Set count values in CR50 and CR60.
<7> Enable the operation of TM60 (TCE60 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE60 (the value of
TCE50 is invalid).
When the count values of TM50 and TM60 simultaneously match the values set in CR50 and CR60
respectively, the TO60 pin output will be inverted. Through application of this mechanism, square waves of
any frequency can be output. As soon as a match occurs, TM50 and TM60 are cleared to 00H and continue
counting. At the same time, an interrupt request signal (INTTM60) is generated (INTTM50 is not generated).
The square-wave output is cleared to 0 by setting TCE60 to 0.
Table 7-10 shows the square-wave output range, and Figure 7-21 shows timing of square-wave output.
Cautions 1. Be sure to stop the timer operation before overwriting the count clock with different
data.
2. In the 16-bit timer counter mode, TO50 cannot be used. Be sure to set TOE50 = 0 to
disable TO50 output.
Table 7-10. Square-Wave Output Range with 16-Bit Resolution
TCL602 TCL601 TCL600
Minimum Pulse Width
1/fX (0.2 µs)
22/fX (0.8 µs)
Maximum Pulse Width
/fX (13.1 ms)
Resolution
1/fX (0.2 µs)
22/fX (0.8 µs)
16
18
2
2
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
/fX (52.4 ms)
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
fTMI input cycle × 216
fTMI/2 input cycle × 216
fTMI/22 input cycle × 216
fTMI/23 input cycle × 216
fTMI input cycle
fTMI/2 input cycle
fTMI/22 input cycle
fTMI/23 input cycle
Remarks 1. fX: Main system clock oscillation frequency
2. fTMI: External input clock frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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Figure 7-21. Timing of Square-Wave Output with 16-Bit Resolution
Count clock
TM60 count value
00H
N
N
7FH 80H
FFH 00H
N
7FH 80H
FFH 00H
00H
7FH 80H
FFH 00H
N
N
00H
Not cleared because TM50 does not match
Cleared because TM50 and TM60 match simultaneously
CR60
N
N
N
N
N
N
N
N
TCE60
Count start
TM50 count pulse
X
X − 1
00H
X
TM50
CR50
00H
X
01H
00H
X − 1
X
X
INTTM60
TO60Note
Interrupt acknowledgement
Interrupt not generated because
TM50 does not match
Interrupt acknowledgement
Note The initial value of TO60 is low level when output is enabled.
Remark X = 00H to FFH, N = 00H to FFH
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
7.4.3 Operation as carrier generator
An arbitrary carrier clock generated by TM60 can be output in the cycle set in TM50.
To operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence.
<1> Disable operation of TM50 and TM60 (TCE50 = 0, TCE60 = 0).
<2> Disable timer output of TO50 and TO60 (TOE50 = 0, TOE600 = 0).
<3> Set count values in CR50, CR60, and CRH60.
<4> Set the operation mode of timer 50 and timer 60 to carrier generator mode (see Figures 7-6 and 7-7).
<5> Set the count clock for timer 50 and timer 60.
<6> Set remote control output to carrier pulse (RMC60 (bit 2 of carrier generator output control register 60
(TCA60)) = 0).
Input the required value to NRZB60 (bit 1 of TCA60) by program.
Input a value to NRZ60 (bit 0 of TCA60) before it is reloaded from NRZB60.
<7> Set P31 to the output mode (PM31 = 0), set the P31 output latch to 0, and set TO60 to output enable
(TOE600 = 1).
<8> Enable the operation of TM50 and TM60 (TCE50 = 1, TCE60 = 1).
<9> When the value of NRZB60 is transferred to NRZ60, input the value to be transferred to NRZ60 next time to
NRZB60 after INTTM50 falling.
<10> Generate the desired carrier signal by repeating <9>.
The operation of the carrier generator is as follows.
<1> When the count value of TM60 matches the value set in CR60, an interrupt request signal (INTTM60) is
generated and output of timer 60 is inverted, which makes the compare register switch from CR60 to CRH60.
<2> After that, when the count value of TM60 matches the value set in CRH60, an interrupt request signal
(INTTM60) is generated and output of timer 60 is inverted again, which makes the compare register switch
from CRH60 to CR60.
<3> The carrier clock is generated by repeating <1> and <2> above.
<4> When the count value of TM50 matches the value set in CR50, an interrupt request signal (INTTM50) is
generated. The rising edge of INTTM50 is the data reload signal of NRZB60 and is transferred to NRZ60.
<5> When NRZ60 is 1, a carrier clock is output from the TO60 pin.
Cautions 1. While timer 60 output is disabled (TOE600 = 0), TCA60 cannot be set with a 1-bit memory
manipulation instruction. Be sure to use an 8-bit memory manipulation instruction.
2. When setting the carrier generator operation again after stopping it once, reset NRZB60
because the previous value is not retained. In this case also a 1-bit memory manipulation
instruction cannot be used while timer 60 output is disabled (TOE600 = 0). Be sure to use
an 8-bit memory manipulation instruction.
3. When timer 60 output is enabled (TOE600 = 1), a write operation to NRZ60 is invalid.
However, while the timer 50 interrupt signal (INTTM50) is high level, the NRZB60 value is
immediately transferred to NRZ60 if TCA60 is rewritten. Rewrite TCA60 after waiting for
half a clock of the TM50 count clock during INTTM50 interrupt servicing.
Figures 7-22 to 7-24 show the operation timing of the carrier generator.
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-22. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N))
TM60
count clock
TM60
count value
00H
01H
N
00H
N
M
N
00H
00H
00H
N
M
Clear
Clear
Clear
Clear
CR60
N
CRH60
TCE60
M
Count start
INTTM60
Carrier clock
TM50
count clock
TM50
count value
L
00H
L
00H
00H
00H
L
01H
01H
01H
00H
01H
L
CR50
L
TCE50
INTTM50
0
0
1
0
NRZB60
NRZ60
1
1
0
0
1
0
Carrier clock
TO60
Remark 00H ≤ N < M ≤ FFH, L = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-23. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N))
TM60
count clock
TM60
count value
00H
M
N
00H
M
00H
M
N
00H
M
00H
Clear
Clear
Clear
Clear
CR60
N
CRH60
TCE60
M
Count start
INTTM60
Carrier clock
TM50
count clock
TM50
count value
00H
L
L
00H
01H
01H
L
01H
00H
00H
L
00H 01H
CR50
L
TCE50
INTTM50
0
0
1
0
NRZB60
NRZ60
1
1
0
0
1
0
Carrier clock
TO60
Remark 00H ≤ M < N ≤ FFH, L = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-24. Timing of Carrier Generator Operation (When CR60 = CRH60 = N)
TM60
count clock
TM60
count value
00H
N
00H
N
N
N
00H
00H
00H
00H
N
N
Clear
Clear
Clear
Clear
Clear
CR60
N
N
CRH60
TCE60
Count start
INTTM60
Carrier clock
TM50
count clock
TM50
count value
00H
01H
00H
L
00H
00H
01H
L
01H
L
00H
01H
L
CR50
L
TCE50
INTTM50
0
0
1
0
NRZB60
NRZ60
1
1
0
0
1
0
Carrier clock
TO60
Remark N = 00H to FFH, L = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
7.4.4 PWM output mode operation (timer 50)
In the PWM output mode, TO50 becomes high level when TM50 overflows, and TO50 becomes low level when
CR50 and TM50 match. It is thus possible to output a pulse with any duty ratio (free-running).
To operate timer 50 in the PWM output mode, settings must be made in the following sequence.
<1> Disable operation of TM50 (TCE50 = 0).
<2> Disable timer output of TO50 (TOE50 = 0).
<3> Set a count value to CR50.
<4> Set the operation mode of timer 50 to the PWM output mode (see Figure 7-6).
<5> Set the count clock for timer 50.
<6> Set P30 to the output mode (PM30 = 0) and the P30 output latch to 0 and enable timer output of TO50
(TOE50 = 1).
<7> Enable the operation of TM50 (TCE50 = 1).
The operation in the PWM output mode is as follows.
<1> When the count value of TM50 matches the value set in CR50, an interrupt request signal (INTTM50) is
generated and a low level is output by the TO50. The TM50 continues counting without being cleared.
<2> TO50 outputs a high level when the TM50 overflows.
A pulse of any duty is output by repeating the above procedure. Figures 7-25 to 7-28 show the operation timing in
the PWM output mode.
Figure 7-25. Operation Timing in PWM Output Mode (When Rising Edge Is Selected)
Count clock
N
N
00H
01H
FFH 00H
Overflow
N
FFH 00H
Overflow
TM50
Overflow
N
CR50
TCE50
Count start
INTTM50
TO50
Caution When the rising edge is selected, do not set CR50 to 00H. If CR50 is set to 00H, PWM output
may not be performed normally.
Remark N = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-26. Operation Timing When Overwriting CR50 (When Rising Edge Is Selected)
(1) When setting CR50 > TM50 after overflow
Count clock
N
00H
01H
FFH 00H
Overflow
M
FFH 00H
Overflow
TM50
01H
Overflow
M
CR50
N
TCE50
Count start
INTTM50
TO50
CR50 overwrite
(2) When setting CR50 < TM50 after overflow
Count clock
N
00H 01H
00H
01H
FFH 00H 01H 02H
Overflow
FFH
TM50
Overflow
Overflow
01H
CR50
N
TCE50
Count start
INTTM50
TO50
Overflow occurs but
CR50 overwrite
no change takes place
because TO50 is
high level.
Remark N, M = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-27. Operation Timing in PWM Output Mode (When Both Edges Are Selected)
(1) CR50 = Even number
Count clock
TM50
00H
Overflow
02H
2N
2N
FEH FFH
01H
FFH
00H
01H 02H
FEH
Overflow
2N
CR50
TCE50
Count start
INTTM50
TO50
(2) When CR50 = Odd number
Count clock
00H
Overflow
2N + 1
FFH
01H
Overflow
FFH
2N + 1
00H
01H
00H
01H
2N + 1
TM50
Overflow
CR50
TCE50
Count start
INTTM50
TO50
Caution When both edges are selected, do not set CR50 to 00H, 01H, and FFH. If CR50 is set to these
values, PWM output may not be performed normally.
Remark N = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-28. Operation Timing in PWM Output Mode
(When Both Edges Are Selected) (When CR50 Is Overwritten)
Count clock
TM50
2N + 1
02H
FFH
00H
01H
2N
00H
Overflow
00H
Overflow
FEH
01H
FFH
01H
Overflow
2N + 1
CR50
2N
TCE50
Count start
INTTM50
TO50
CR50 overwrite
Remark N = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
7.4.5 PPG output mode operation (timer 60 and timer 61)
In the PPG output mode, a pulse of any duty ratio can be output by setting a low-level width using CR6m and a
high-level width using CRH6m.
To operate timer 6m in PPG output mode, settings must be made in the following sequence.
<1> Disable operation of TM6m (TCE6m = 0).
<2> Disable timer output of TO6m (TOE6m0 = 0).
<3> Set count values in CR6m and CRH6m.
<4> Set the operation mode of timer 6m to the PPG output mode (see Figures 7-7 and 7-9).
<5> Set the count clock for timer 6m.
<6> When using timer 60, set P31 to output mode (PM31 = 0) and the P31 output latch to 0, respectively.
When using timer 61, set P32 to output mode (PM32 = 0) and the P32 output latch to 0, respectively.
<7> Enable timer output of TO6m (TOE6m0 = 1).
<8> Enable the operation of TM6m (TCE6m = 1).
The operation in the PPG output mode is as follows.
<1> When the count value of TM6m matches the value set in CR6m, an interrupt request signal (INTTM6m) is
generated and output of timer 6m is inverted, which makes the compare register switch from CR6m to
CRH6m.
<2> A match between TM6m and CR6m clears the TM6m value to 00H and then counting starts again.
<3> After that, when the count value of TM6m matches the value set in CRH6m, an interrupt request signal
(INTTM6m) is generated and output of timer 6m is inverted again, which makes the compare register switch
from CRH6m to CR6m.
<4> A match between TM6m and CRH6m clears the TM6m value to 00H and then counting starts again.
A pulse of any duty ratio is output by repeating <1> to <4> above. Figures 7-29 and 7-30 show the operation timing
in the PPG output mode.
Remark m = 0, 1
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
Figure 7-29. PPG Output Mode Timing (Basic Operation)
Count clock
TM6m
count value
01H
M
00H
M
00H
N
01H
00H
N
01H
00H
00H
01H
Clear
Clear
Clear
Clear
CR6m
N
CRH6m
TCE6m
M
Count start
INTTM6m
TO6mNote
Note The initial value of TO6m is low level when output is enabled (TOE6m0 = 1).
Remark N, M = 00H to FFH
m = 0, 1
Figure 7-30. PPG Output Mode Timing (When CR6m and CRH6m Are Overwritten)
Count clock
TM6m
count value
N
00H
N
00H
01H
Y
00H
X
M
00H
00H
X
Clear
Clear
Clear
Clear
CR6m
N
X
CRH6m
TCE6m
M
Y
M
Count start
INTTM6m
TO6mNote
Note The initial value of TO6m is low level when output is enabled (TOE6m0 = 1).
Remark N, M, X, Y = 00H to FFH
m = 0, 1
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CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
7.5 Cautions on Using 8-Bit Timers 50, 60, and 61
(1) Error on starting timer
An error of up to 1.5 clocks is included in the time between the timer being started and a match signal being
generated. This is because the rising edge is detected and the counter is incremented if the timer is started
while the count clock is high (see Figure 7-31).
Figure 7-31. Case in Which Error of 1.5 Clocks (Max.) Occurs
Delay A
Count
pulse
8-bit timer counter n0
(TMn0)
Selected clock
TCEn0
Clear signal
Delay B
Selected clock
TCEn0
Clear signal
Count pulse
TMn0 counter value
00H
01H
02H
03H
Delay A
Delay B
An error of up to 1.5 clocks occurs if the timer is started
when the selected clock is high and delay A > delay B.
Remark nm = 50, 60, 61
(2) Setting of 8-bit compare register nm
8-bit compare register nm (CRnm) can be set to 00H.
Therefore, one pulse can be counted when the 8-bit timer operates as an event counter.
Remark nm= 50, 60, 61
Figure 7-32. Timing of Operation as External Event Counter (8-Bit Resolution)
TMI60 input
CR60
00H
00H
00H
00H
00H
TM60
count value
Interrupt request flag
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CHAPTER 8 WATCH TIMER
8.1 Watch Timer Functions
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch and interval timers can be used at the same time.
Figure 8-1 shows a block diagram of the watch timer.
Figure 8-1. Block Diagram of Watch Timer
Clear
f
/27
X
5-bit counter
Clear
INTWT
INTWTI
9-bit prescaler
f
W
f
W
f
W
f
W
f
W
f
W
f
W
29
24 25 26 27 28
f
XT
1/2
XT/2
f
WTS
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer interrupt Watch timer mode
time selection
register (WTIM)
control register (WTM)
Internal bus
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CHAPTER 8 WATCH TIMER
(1) Watch timer
An interrupt request (INTWT) occurs at an interval of 0.5 second when using either the 4.19 MHz main
system clock or the 32.768 kHz subsystem clock.
Also, an interrupt request (INTWT) occurs at an interval of 1.0 seconds when using the 32.768 kHz
subsystem clock via a setting in the watch timer interrupt time selection register (WTIM).
Caution An interval of 0.5 second cannot be created when using the 5.0 MHz main system clock.
Instead, switch to the 32.768 kHz subsystem clock, and then create the 0.5-second interval.
(2) Interval timer
An interrupt request (INTWTI) occurs at preset intervals.
Table 8-1. Interval Time of Interval Timer
Interval Time
At fX = 5.0 MHz
409.6 µs
At fX = 4.19 MHz
488 µs
At fXT = 32.768 kHz
488 µs
At fXT/2 = 16.384 kHz
976 µs
4
2 ×1/fW
5
2 ×1/fW
819.2 µs
1.64 ms
3.28 ms
6.55 ms
13.1 ms
977 µs
977 µs
1.95 ms
3.90 ms
7.82 ms
15.6 ms
31.2 ms
6
2 ×1/fW
1.95 ms
3.91 ms
7.81 ms
15.6 ms
1.95 ms
3.91 ms
7.81 ms
15.6 ms
7
2 ×1/fW
8
2 ×1/fW
9
2 ×1/fW
Remarks 1. fW: Watch timer clock frequency (fX/27, fXT, or fXT/2)
2. fX: Main system clock oscillation frequency
3. fXT: Subsystem clock oscillation frequency
8.2 Configuration of Watch Timer
The watch timer includes the following hardware.
Table 8-2. Configuration of Watch Timer
Item
Configuration
Counter
5 bits × 1
9 bits × 1
Prescaler
Control registers
Watch timer mode control register (WTM)
Watch timer interrupt time selection register (WTIM)
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CHAPTER 8 WATCH TIMER
8.3 Control Registers for Watch Timer
The watch timer is controlled by the following registers.
• Watch timer mode control register (WTM)
• Watch timer interrupt time selection register (WTIM)
(1) Watch timer mode control register (WTM)
This register is used to control the watch timer count clock, operation enable/disable status, prescaler interval
time, and the 5-bit counter operation.
WTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 8-2. Format of Watch Timer Mode Control Register
Symbol
WTM
7
6
5
4
3
0
2
0
<1>
<0>
Address After reset
FF4AH 00H
R/W
R/W
WTM7
WTM6
WTM5
WTM4
WTM1
WTM0
WTM7
Selection of watch timer count clock (fW)
7
fX/2 (39.1 kHz)
0
1
fXT (32.768 kHz) or fXT/2 (16.384 kHz)Note
WTM6
WTM5
WTM4
Selection of prescaler interval time
4
2 /fW
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
5
2 /fW
6
2 /fW
7
2 /fW
8
2 /fW
9
2 /fW
Other than above
Setting prohibited
WTM1
Control of 5-bit counter operation
0
1
Cleared after stopping operation
Start
WTM0
Watch timer operation enable/disable
0
1
Operation stopped (prescaler and timer are both cleared)
Operation enabled
Note This is the frequency (fXT or fXT/2) set via the watch timer interrupt time selection register (WTIM).
Remarks 1. fW: Watch timer clock frequency (fX/27, fXT, or fXT/2)
2. fX: Main system clock oscillation frequency
3. fXT: Subsystem clock oscillation frequency
4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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CHAPTER 8 WATCH TIMER
(2) Watch timer interrupt time selection register (WTIM)
This register is used to set the interrupt time by selecting either the source clock or the clock divided by 2 for
the subsystem clock to be input to watch timer.
WTIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 8-3. Format of Watch Timer Interrupt Time Selection Register
Symbol
WTIM
7
0
6
0
5
0
4
0
3
0
2
0
1
0
<0>
Address
FF4BH
After reset
00H
R/W
R/W
WTS
WTS
Selection of watch timer interrupt timeNote
0
1
0.5 s (fXT)
1.0 s (fXT/2)
Note The selection is only available when bit 7 (WTM7) of the watch timer mode control register (WTM) is 1.
Remark fXT: Subsystem clock oscillation frequency
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CHAPTER 8 WATCH TIMER
8.4 Watch Timer Operation
8.4.1 Operation as watch timer
The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate
at 0.5-second intervals.
Also, an interrupt request (INTWT) occurs at an interval of 1.0 seconds when using the 32.768 kHz subsystem
clock via a setting in the watch timer interrupt time selection register (WTIM).
The watch timer is used to generate an interrupt request at specified intervals.
By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer
starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.
It is possible to start the watch timer from zero seconds by clearing WTM1 to 0 when the interval timer and watch
timer operate at the same time. In this case, however, an error of up to 29 × 1/fW seconds may occur in the overflow
(INTWT) after the zero-second start of the watch timer because the 9-bit prescaler is not cleared to 0.
8.4.2 Operation as interval timer
The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count
value.
The interval can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).
Table 8-3. Interval Time of Interval Timer
WTM6
WTM5
WTM4
Interval Time
At fX = 5.0 MHz
At fX = 4.19 MHz
At fXT = 32.768
kHz
At fXT = 16.384
kHz
24 × 1/fW
25 × 1/fW
26 × 1/fW
27 × 1/fW
28 × 1/fW
29 × 1/fW
409.6 µs
819.2 µs
1.64 ms
3.28 ms
6.55 ms
13.1 ms
488 µs
488 µs
976 µs
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
977 µs
977 µs
1.95 ms
3.90 ms
7.82 ms
15.6 ms
31.2 ms
1.95 ms
3.91 ms
7.81 ms
15.6 ms
1.95 ms
3.91 ms
7.81 ms
15.6 ms
Other than above
Setting prohibited
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. fW: Watch timer clock frequency
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CHAPTER 8 WATCH TIMER
Figure 8-4. Watch Timer/Interval Timer Operation Timing
5-bit counter
0H
Overflow
Start
Overflow
Count clock
/29
fW
Watch timer
interrupt
INTWT
Watch timer interrupt time (0.5 s)
Watch timer interrupt time (0.5 s)
Interval timer
interrupt
INTWTI
Interval
time (T)
T
Caution When operation of the watch timer and 5-bit counter operation is enabled by setting bit 0
(WTM0) of the watch timer mode control register (WTM) to 1, the interval until the first interrupt
request (INTWT) is generated after the register is set does not exactly match the watch timer
interrupt time (0.5 s). This is because there is a delay of one 9-bit pre-scaler output cycle until
the 5-bit counter starts counting. Subsequently, however, the INTWT signal is generated at the
specified intervals.
Remarks 1. fW: Watch timer clock frequency
2. The parenthesized values apply to operation at fW = 32.768 kHz.
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9.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect a program loop. When a program loop is detected, a non-maskable
interrupt or the RESET signal can be generated.
Table 9-1. Watchdog Timer Program Loop Detection Time
Program Loop Detection Time
At fX = 5.0 MHz
211 × 1/fX
410 µs
213 × 1/fX
215 × 1/fX
217 × 1/fX
1.64 ms
6.55 ms
26.2 ms
fX: Main system clock oscillation frequency
(2) Interval timer
The interval timer generates an interrupt at an arbitrary preset interval.
Table 9-2. Interval Time
Interval
At fX = 5.0 MHz
211 × 1/fX
213 × 1/fX
215 × 1/fX
217 × 1/fX
410 µs
1.64 ms
6.55 ms
26.2 ms
fX: Main system clock oscillation frequency
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CHAPTER 9 WATCHDOG TIMER
9.2 Watchdog Timer Configuration
The watchdog timer includes the following hardware.
Table 9-3. Configuration of Watchdog Timer
Item
Configuration
Watchdog timer clock selection register (WDCS)
Control registers
Watchdog timer mode register (WDTM)
Figure 9-1. Block Diagram of Watchdog Timer
Internal bus
f
X
WDTMK
Prescaler
24
f
X
f
X
f
X
26
28
210
INTWDT
Maskable
WDTIF
interrupt request
7-bit counter
Clear
Controller
RESET
INTWDT
Non-maskable
interrupt request
3
WDCS2 WDCS1 WDCS0
RUN WDTM4 WDTM3
Watchdog timer clock selection register
(WDCS)
Watchdog timer mode register (WDTM)
Internal bus
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9.3 Watchdog Timer Control Registers
The watchdog timer is controlled by the following two registers.
•
•
Watchdog timer clock selection register (WDCS)
Watchdog timer mode register (WDTM)
(1) Watchdog timer clock selection register (WDCS)
This register sets the watchdog timer count clock.
WDCS is set with an 8-bit memory manipulation instruction.
RESET input sets WDCS to 00H.
Figure 9-2. Format of Watchdog Timer Clock Selection Register
Symbol
WDCS
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF42H
After reset
00H
R/W
R/W
WDCS2 WDCS1 WDCS0
WDCS2 WDCS1 WDCS0
Interval
Watchdog timer count clock selection
/24 (312.5 kHz)
211/f
213/f
215/f
217/f
X
X
X
X
(410 µs)
f
f
f
f
X
X
X
X
0
0
1
1
0
0
0
0
0
1
/26 (78.1 kHz)
(1.64 ms)
(6.55 ms)
(26.2 ms)
0
/28 (19.5 kHz)
1
/210 (4.88 kHz)
Other than above
Setting prohibited
Remarks 1. fX : Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 9 WATCHDOG TIMER
(2) Watchdog timer mode register (WDTM)
This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WDTM to 00H.
Figure 9-3. Format of Watchdog Timer Mode Register
Symbol
WDTM
<7>
6
0
5
0
4
3
2
0
1
0
0
0
Address
FFF9H
After reset
00H
R/W
R/W
RUN
WDTM4 WDTM3
Watchdog timer operation selectionNote 1
RUN
0
1
Stop counting.
Clear counter and start counting.
Watchdog timer operation mode selectionNote 2
WDTM4 WDTM3
0
0
1
1
0
1
0
1
Operation stop
Interval timer mode (a maskable interrupt is generated upon overflow occurrence)Note 3
Watchdog timer mode 1 (a non-maskable interrupt is generated upon overflow occurrence)
Watchdog timer mode 2 (a reset operation is started upon overflow occurrence)
Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.
3. The watchdog timer starts operation as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up
to 0.8% shorter than the time set by the watchdog timer clock selection register (WDCS).
2. To set watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming WDTIF (bit 0 of
interrupt request flag register 0 (IF0)) is set to 0. When watchdog timer mode 1 or 2 is
selected with WDTIF set to 1, a non-maskable interrupt is generated upon the
completion of rewriting WDTM4.
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9.4 Watchdog Timer Operation
9.4.1 Operation as watchdog timer
The watchdog timer detects a program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is
set to 1.
The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2
(WDCS0 to WDCS2) of watchdog timer clock selection register (WDCS). By setting bit 7 (RUN) of WDTM to 1, the
watchdog timer is started. Set RUN to 1 within the set program loop detection time interval after the watchdog timer
has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1,
and the program loop detection time is exceeded, a system reset signal or a non-maskable interrupt is generated,
depending on the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to
clear the watchdog timer before executing the STOP instruction.
Cautions 1. The actual program loop detection time may be up to 0.8% shorter than the set time.
2. When the subsystem clock is selected as the CPU clock, the watchdog timer count
operation is stopped. Even when the main system clock continues oscillating in this case,
watchdog timer count operation is stopped.
Table 9-4. Watchdog Timer Program Loop Detection Time
WDCS2 WDCS1 WDCS0
Program Loop Detection Time
At fX = 5.0 MHz
410 µs
0
0
1
1
0
1
0
1
0
0
0
0
211 × 1/fX
213 × 1/fX
215 × 1/fX
217 × 1/fX
1.64 ms
6.55 ms
26.2 ms
fX: Main system clock oscillation frequency
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9.4.2 Operation as interval timer
When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals
specified by a preset count value.
Select a count clock (or interval) by setting bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock selection
register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to
1.
In interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to
clear the interval timer before executing the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval
timer mode is not set unless the RESET signal is input.
2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been set.
Table 9-5. Interval Time of Interval Timer
WDCS2 WDCS1 WDCS0
Interval
At fX = 5.0 MHz
410 µs
0
0
1
1
0
1
0
1
0
0
0
0
211 × 1/fX
213 × 1/fX
215 × 1/fX
217 × 1/fX
1.64 ms
6.55 ms
26.2 ms
fX: Main system clock oscillation frequency
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CHAPTER 10 10-BIT A/D CONVERTER
10.1 10-Bit A/D Converter Functions
The 10-bit A/D converter is a 10-bit resolution converter used to convert analog inputs into digital signals. This
converter can control eight channels (ANI0 to ANI7) of analog inputs.
A/D conversion can only be started by software.
One of analog inputs ANI0 to ANI7 is selected for A/D conversion. A/D conversion is performed repeatedly, with
an interrupt request (INTAD0) being issued each time A/D conversion is complete.
10.2 10-Bit A/D Converter Configuration
The 10-bit A/D converter includes the following hardware.
Table 10-1. Configuration of 10-Bit A/D Converter
Item
Analog inputs
Registers
Configuration
8 channels (ANI0 to ANI7)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCRL0)
Control registers
A/D converter mode register 0 (ADML0)
Analog input channel specification register 0 (ADS0)
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Figure 10-1. Block Diagram of 10-Bit A/D Converter
AVDD
P-ch
ANI0/P60
ANI1/P61
ANI2/P62
ANI3/P63
ANI4/P64
ANI5/P65
ANI6/P66
ANI7/P67
Sample & hold circuit
Voltage comparator
AVSS
V
SS
Successive
approximation
register (SAR)
Band -gap circuit
INTAD0
Controller
A/D conversion result
register 0 (ADCRL0)
ADS02
ADS01 ADS00
ADCS0 FR02 FR01 FR00
ADCE0
Analog input channel
specification register 0
(ADS0)
A/D converter mode
register 0 (ADML0)
Internal bus
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCRL0).
(2) A/D conversion result register 0 (ADCRL0)
ADCRL0 is a 16-bit register that holds the result of A/D conversion. The lower 6 bits are fixed to 0. Each
time A/D conversion ends, the conversion result in the successive approximation register is loaded into
ADCRL0. The results are stored in ADCRL0 from the highest bit.
The higher 8 bits of the conversion result are stored in FF15H and the lower 2 bits of the conversion result
are stored in FF14H.
ADCRL0 can be read with a 16-bit memory manipulation instruction.
RESET input sets ADCRL0 to 0000H.
Address
After reset R/W
ADCRL0L (FF14H)
Symbol
ADCRL0H (FF15H)
FF14H,
FF15H
ADCRL0
0
0
0
0
0
0
0000H
R
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(3) Sample & hold circuit
The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the series resistor string.
(5) Series resistor string
The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 to ANI7
The ANI0 to ANI7 pins are the 8-channel analog input pins for the A/D converter. They are used to receive
the analog signals for A/D conversion.
Caution Do not supply the ANI0 to ANI7 pins with voltages that fall outside the rated range. If a
voltage greater than or equal to AVDD or less than or equal to AVSS (even if within the
absolute maximum rating) is applied to any of these pins, the conversion value for the
corresponding channel will be undefined. Furthermore, the conversion values for the other
channels may also be affected.
(7) AVSS pin
The AVSS pin is the ground potential pin for the A/D converter. This pin must be held at the same potential as
the VSS pin, even while the A/D converter is not being used.
(8) AVDD pin
The AVDD pin is the analog power supply pin for the A/D converter. This pin must be held at the same
potential as the VDD pin, even while the A/D converter is not being used.
(9) Band-gap circuit
The band-gap circuit activates the reference voltage inside the comparator prior to A/D conversion. Start
conversion after 14 µs have elapsed following the activation of the band-gap circuit.
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10.3 10-Bit A/D Converter Control Registers
The 10-bit A/D converter is controlled by the following two registers.
•
•
A/D converter mode register 0 (ADML0)
Analog input channel specification register 0 (ADS0)
(1) A/D converter mode register 0 (ADML0)
ADML0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADML0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADML0 to 00H.
Figure 10-2. Format of A/D Converter Mode Register 0
Symbol
ADML0
<7>
6
0
5
4
3
2
0
1
0
0
Address
FF80H
After reset
00H
R/W
R/W
ADCS0
FR02
FR01
FR00
ADCE0
ADCS0
A/D conversion control
0
1
Conversion disabled
Conversion enabled
A/D conversion time selectionNote 1
FR02
FR01
FR00
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
144/f
120/f
X
X
(28.8
µ
s)
µ
s)
(24
µ
96/f
72/f
60/f
48/f
X
X
X
X
(19.2
(14.4
s)
s)
µ
(Setting prohibitedNote 2
(Setting prohibitedNote 2
)
)
Other than above
Setting prohibited
ADCE0
Control of band-gap circuit
0
1
Band-gap circuit stopped
Band-gap circuit operating
Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least
14 µs.
2. When fX is 5.0 MHz, these bit combinations must not be used, as the A/D conversion time will fall
below 14 µs.
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Cautions 1. Start conversion (ADCS0 = 1) after 14 µs have elapsed following the setting of ADCE0.
If ADCE0 is not used, the conversion result immediately after the setting of bit 7 (ADCS0)
is undefined.
2. The conversion result may be undefined after ADCS0 has been cleared to 0. To read the
conversion result, perform the read operation during A/D conversion. If the conversion
result needs to be read after A/D conversion has been stopped, stop the A/D conversion
operation before the end of the next A/D conversion.
3. Always set bits 1, 2, and 6 to 0.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
(2) Analog input channel specification register 0 (ADS0)
ADS0 specifies the port used to input the analog voltage to be converted to a digital signal.
ADS0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADS0 to 00H.
Figure 10-3. Format of Analog Input Channel Specification Register 0
Symbol
ADS0
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF84H
After reset
00H
R/W
R/W
ADS02
ADS01
ADS00
Analog input channel specification
ADS02
ADS01
ADS00
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Caution Bits 3 to 7 must be set to 0.
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10.4 10-Bit A/D Converter Operation
10.4.1 Basic operation of 10-bit A/D converter
<1> Bit 0 of A/D converter mode register 0 (ADML0) is set (ADCE0 = 1).
<2> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0).
<3> When 14 µs or more have elapsed after ADCE0 was set, set bit 7 of ADML0 (ADCS0 = 1). The voltage
supplied to the selected analog input channel is sampled using the sample & hold circuit.
<4> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the
input analog voltage until A/D conversion is completed.
<5> Bit 9 of the successive approximation register (SAR) is set. The series resistor string tap voltage at the
tap selector is set to half of AVDD.
<6> The series resistor string tap voltage is compared with the analog input voltage using the voltage
comparator. If the analog input voltage is higher than half of AVDD, the MSB of SAR is left set. If it is
lower than half of AVDD, the MSB is reset.
<7> Bit 8 of SAR is set automatically, and comparison shifts to the next stage. The next tap voltage of the
series resistor string is selected according to bit 9, which reflects the previous comparison result, as
follows:
• Bit 9 = 1: Three quarters of AVDD
• Bit 9 = 0: One quarter of AVDD
The tap voltage is compared with the analog input voltage. Bit 8 is set or reset according to the result of
comparison.
• Analog input voltage ≥ tap voltage: Bit 8 = 1
• Analog input voltage < tap voltage: Bit 8 = 0
<8> Comparison is repeated until bit 0 of SAR is reached.
<9> When comparison is completed for all of the 10 bits, a significant digital result is left in SAR. This value is
sent to and latched in A/D conversion result register 0 (ADCRL0). At the same time, it is possible to
generate an A/D conversion end interrupt request (INTAD0).
Cautions 1. Start conversion (ADCS0 = 1) after 14 µs have elapsed following the setting of ADCE0.
If ADCE0 is not used, the conversion result immediately after the setting of bit 7 (ADCS0)
is undefined.
2. In standby mode, A/D converter operation is stopped.
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Figure 10-4. Basic Operation of 10-Bit A/D Converter
Conversion
time
Sampling
time
A/D converter
operation
A/D conversion
Sampling
Conversion
result
SAR
ADCRL0
INTAD0
Undefined
Conversion
result
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADML0) is reset (0) by software.
If an attempt is made to write to ADML0 or analog input channel specification register 0 (ADS0) during A/D
conversion, the A/D conversion in progress is canceled. In this case, A/D conversion is restarted from the beginning,
if ADCS0 is set (1).
RESET input clears A/D conversion result register 0 (ADCRL0) to 0000H.
10.4.2 Input voltage and conversion result
The relationship between the analog input voltage at the analog input pins (ANI0 to ANI7) and the A/D conversion
result (A/D conversion result register 0 (ADCRL0)) is represented by:
VIN
AVDD
ADCRL0 = INT (
or
× 1,024 + 0.5)
AVDD
1,024
AVDD
1,024
(ADCRL0 − 0.5) ×
≤ VIN < (ADCRL0 + 0.5) ×
INT( ):
VIN:
Function that returns the integer part of a parenthesized value
Analog input voltage
AVDD:
Supply voltage for the A/D converter
ADCRL0: Value in A/D conversion result register 0 (ADCRL0)
Figure 10-5 shows the relationship between the analog input voltage and the A/D conversion result.
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Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Result
1,023
1,022
1,021
A/D conversion
result (ADCRL0)
3
2
1
0
1
1
3
2
5
3
2,043 1,022 2,045 1,023 2,047
2,048 1,024 2,048 1,024 2,048
1
2,048 1,024 2,048 1,024 2,048 1,024
Input voltage/AVDD
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10.4.3 Operation mode of 10-bit A/D converter
The A/D converter is initially in select mode. In this mode, analog input channel specification register 0 (ADS0) is
used to select an analog input channel from ANI0 to ANI7 for A/D conversion.
A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADML0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCRL0). At the same time, an interrupt
request signal (INTAD0) is generated.
• Software-started A/D conversion
Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADML0) to 1 triggers A/D conversion for the voltage
applied to the analog input pin specified in analog input channel specification register 0 (ADS0).
Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCRL0).
At the same time, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated and
completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to
ADML0.
If data where ADCS0 is 1 is written to ADML0 again during A/D conversion, the A/D conversion in progress is
discontinued, and a new session of A/D conversion begins for the new data.
If data where ADCS0 is 0 is written to ADML0 again during A/D conversion, A/D conversion is stopped
immediately.
Figure 10-6. Software-Started A/D Conversion
Rewriting ADML0
ADCS0 = 1
Rewriting ADML0
ADCS0 = 1
ADCS0 = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion is
discontinued;
no conversion
Stop
result is preserved.
ADCRL0
INTAD0
ANIn
ANIn
ANIm
Remarks 1. n = 0 to 7
2. m = 0 to 7
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10.5 Cautions Related to 10-Bit A/D Converter
(1) Current consumption in standby mode
In standby mode, the A/D converter stops operation. Clearing bit 7 (ADCS0) and bit 0 (ADCE0) of A/D
converter mode register 0 (ADML0) to 0 can reduce the current consumption.
Figure 10-7 shows how to reduce the current consumption in standby mode.
Figure 10-7. How to Reduce Current Consumption in Standby Mode
AVREF
P-ch
ADCS0
Series resistor string
V
SS
0: Stopped
1: Operating
ADCE0
Band-gap circuit
(2) Input range for pins ANI0 to ANI7
Be sure to keep the input voltage at ANI0 to ANI7 within the rating. If a voltage greater than or equal to AVDD
or less than or equal to AVSS (even within the absolute maximum ratings) is input into a conversion channel,
the conversion output of the channel becomes undefined, which may affect the conversion output of the other
channels.
(3) Conflict
<1> Conflict between writing to A/D conversion result register 0 (ADCRL0) at the end of conversion and
reading from ADCRL0 using instruction
Reading from ADCRL0 takes precedence. After reading, the new conversion result is written to ADCRL0.
<2> Conflict between writing to ADCRL0 at the end of conversion and writing to A/D converter mode register 0
(ADML0) or analog input channel specification register 0 (ADS0)
Writing to ADML0 or ADS0 takes precedence. ADCRL0 is not written to. No A/D conversion end
interrupt request signal (INTAD0) is generated.
(4) Conversion result immediately after start of A/D conversion
If the band-gap circuit is not used (ADCE0 = 0) or conversion is started before 14 µs has elapsed following
the setting of ADCE, only the first A/D conversion value immediately after A/D conversion has been started is
undefined. Poll the A/D conversion end interrupt request (INTAD0), drop the first conversion result and use
the second and subsequent conversion results. When 14 µs have elapsed following the activation of the
band-gap circuit (ADCE0 = 1), the first conversion value is normal.
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CHAPTER 10 10-BIT A/D CONVERTER
(5) Timing of undefined A/D conversion result
The A/D conversion value may become undefined if the timing of the completion of A/D conversion and the
timing to stop the A/D conversion operation conflict. Therefore, read the A/D conversion result while the A/D
conversion operation is in progress. To read the A/D conversion result after the A/D conversion operation
has been stopped, stop the A/D conversion operation before the next conversion operation is completed.
Figures 10-8 and 10-9 show the timing at which the conversion result is read.
Figure 10-8. Conversion Result Read Timing (if Conversion Result Is Undefined)
End of A/D conversion
End of A/D conversion
ADCRL0
Normal conversion result
Undefined value
INTAD0
ADCS0
Normal conversion result is read.
A/D conversion
stops.
Undefined value
is read.
Figure 10-9. Conversion Result Read Timing (if Conversion Result Is Normal)
End of A/D conversion
ADCRL0
Normal conversion result
INTAD0
ADCS0
A/D conversion stops.
Normal conversion
result is read.
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(6) Noise prevention
To maintain a resolution of 10 bits, watch for noise at the AVDD and ANI0 to ANI7 pins. The higher the output
impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external
capacitor to the relevant pins as shown in Figure 10-10.
Figure 10-10. Analog Input Pin Handling
If noise greater than or equal to AVDD or less than or
equal to AVSS is likely to come to the ANI0 to ANI7 pins,
clamp the voltage at the pin by attaching a diode with
a small VF (0.3 V or lower).
VDD
AVDD
ANI0 to ANI7
AVSS
C = 100 to 1,000 pF
VSS
(7) ANI0 to ANI7
The analog input pins (ANI0 to ANI7) are alternate-function pins. They are also used as port pins (P60 to
P67).
If any of ANI0 to ANI7 has been selected for A/D conversion, do not execute input instructions for the ports;
otherwise the conversion resolution may be reduced.
If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise
may occur that prevents an A/D conversion result from being obtained as expected. Avoid applying a digital
pulse to pins adjacent to the analog input pins during A/D conversion.
(8) Input impedance of ANI0 to ANI7 pins
This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and
performs sampling.
Therefore at times other than sampling, only the leak current flows. During sampling, the current for charging
the capacitor also flows, so the input impedance fluctuates and has no meaning.
However, to ensure adequate sampling, it is recommend that the output impedance of the analog input
source be set to 10 kΩ or lower, or a capacitor of about 100 pF to the ANI0 to ANI7 pins (see to Figure 10-
10).
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(9) Interrupt request flag (ADIF0)
Changing the contents of A/D converter mode register 0 (ADML0) does not clear the interrupt request flag
(ADIF0).
If the analog input pins are changed during A/D conversion, therefore, the A/D conversion result and the
conversion end interrupt request flag may reflect the previous analog input immediately before rewriting
ADML0. In this case, ADIF0 may already be set if it is read-accessed immediately after ADML0 is rewritten,
even when A/D conversion has not been completed for the new analog input.
In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand.
Figure 10-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting ADML0
(to begin conversion
for ANIm)
Rewriting ADML0
(to begin conversion
for ANIn)
ADIF0 has been set, but conversion
for ANIm has not been completed.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCRL0
INTAD0
ANIm
ANIn
ANIm
ANIn
Remarks 1. n = 0 to 7
2. m = 0 to 7
(10) AVDD pin
The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to
ANI7 input circuit.
If your application is designed to be changed to backup power, the AVDD pin must be supplied with the same
voltage level as the VDD pin, as shown in Figure 10-12.
Figure 10-12. AVDD Pin Handling
VDD
AVDD
Backup
Main power
supply
capacitor
V
SS
AVSS
(11) AVDD pin input impedance
A series resistor string of several ten of kΩ is connected between the AVDD and AVSS pins. Consequently, if
the output impedance of the reference voltage supply is high, the reference voltage supply will form a series
connection with the series resistor string, creating a large reference voltage differential.
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CHAPTER 11 SERIAL INTERFACE 20
11.1 Serial Interface 20 Functions
Serial interface 20 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.
(2) Asynchronous serial interface (UART) mode
This mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplex
communication.
Serial interface 20 contains a UART-dedicated baud rate generator, enabling communication over a wide
range of baud rates. It is also possible to define baud rates by dividing the frequency of the clock input to the
ASCK20 pin.
(3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission)
This mode is used to transmit 8-bit data, using three lines: a serial clock line (SCK20) and two serial data
lines (SI20 and SO20).
As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing time
for data transmission than asynchronous serial interface mode.
Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the
MSB or LSB, serial interface 20 can be connected to any device regardless of whether that device is
designed for MSB-first or LSB-first transmission.
3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having
conventional synchronous serial interfaces, such as those of the 75XL, 78K, and 17K Series devices.
11.2 Serial Interface 20 Configuration
Serial interface 20 includes the following hardware.
Table 11-1. Configuration of Serial Interface 20
Item
Configuration
Registers
Transmit shift register 20 (TXS20)
Receive shift register 20 (RXS20)
Receive buffer register 20 (RXB20)
Control registers
Serial operation mode register 20 (CSIM20)
Asynchronous serial interface mode register 20 (ASIM20)
Asynchronous serial interface status register 20 (ASIS20)
Baud rate generator control register 20 (BRGC20)
Port mode register 2 (PM2)
Port 2 (P2)
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Figure 11-1. Block Diagram of Serial Interface 20
Internal bus
Serial operation mode
register 20 (CSIM20)
Asynchronous serial interface
status register 20 (ASIS20)
Asynchronous serial interface
mode register 20 (ASIM20)
Receive buffer
register 20 (RXB20)
TXE20 RXE20 PS201 PS200 CL20 SL20
CSIE20 DIR20 CSCK20
PE20 FE20 OVE20
Switch of the first bit
Transmit shift register
20 (TXS20)
Transmit shift
clock
SI20/P22
/RxD20
Receive shift register
20 (RXS20)
Selector
CSIE20
Output latch
(P21)
Receive shift
clock
Data phase
control
SO20/P21
/TxD20
Parity operation
Addition of stop bit
Port mode
register (PM21)
INTST20
4
Transmit data counter
Parity detection
SL20, CL20, PS200, PS201
INTSR20/INTCSI20
Detection of stop bit
Receive data counter
Transmit/receive
clock control
Reception enable
Receive clock
CSIE20
CSCK20
/2 to f
/28
Baud rate
generatorNote
Detection
of start bit
Detection clock
Output latch
(P20)
f
X
X
Receive
detection
4
SCK20/P20
/ASCK20
CSIE20
TPS203
TPS202 TPS201 TPS200
Internal clock
output
CSCK20
Baud rate generator control
register 20 (BRGC20)
Port mode
register (PM20)
Clock phase
control
External clock input
Internal bus
Note See Figure11-2 for the configuration of the baud rate generator.
Figure 11-2. Block Diagram of Baud Rate Generator 20
Clock for receive detection
Transmit shift clock
Transmit clock
counter (3 bits)
1/2
f
X
/2
f
f
f
f
f
f
f
X
X
X
X
X
X
X
/22
/23
/24
/25
/26
/27
/28
1/2
Receive shift clock
Receive clock
counter (3 bits)
TXE20
ASCK20/SCK20/P20
RXE20
CSIE20
Receive detection
4
TPS203 TPS202 TPS201 TPS200
Baud rate generator control
register 20 (BRGC20)
Internal bus
CHAPTER 11 SERIAL INTERFACE 20
(1) Transmit shift register 20 (TXS20)
TXS20 is a register in which transmit data is prepared. The transmit data is output from TXS20 bit-serially.
When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmit data. Writing data to
TXS20 triggers transmission.
TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read.
RESET input sets TXS20 to FFH.
Caution Do not write to TXS20 during transmission.
TXS20 and receive buffer register 20 (RXB20) are mapped at the same address, so any
attempt to read from TXS20 results in a value being read from RXB20.
(2) Receive shift register 20 (RXS20)
RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one
entire byte has been received, RXS20 feeds the receive data to receive buffer register 20 (RXB20).
RXS20 cannot be manipulated directly by a program.
(3) Receive buffer register 20 (RXB20)
RXB20 holds receive data. New receive data is transferred from receive shift register 20 (RXS20) at every 1-
byte data reception.
When the data length is seven bits, the receive data is sent to bits 0 to 6 of RXB20, in which the MSB is
always fixed to 0.
RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written.
RESET input makes RXB20 undefined.
Caution RXB20 and transmit shift register 20 (TXS20) are mapped at the same address, so any
attempt to write to RXB20 results in a value being written to TXS20.
(4) Transmit controller
The transmit controller controls transmission. For example, it adds start, parity, and stop bits to the data in
transmit shift register 20 (TXS20), according to the setting of asynchronous serial interface mode register 20
(ASIM20).
(5) Receive controller
The receive controller controls reception according to the setting of asynchronous serial interface mode
register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is detected,
asynchronous serial interface status register 20 (ASIS20) is set according to the status of the error.
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CHAPTER 11 SERIAL INTERFACE 20
11.3 Serial Interface 20 Control Registers
Serial interface 20 is controlled by the following six registers.
• Serial operation mode register 20 (CSIM20)
• Asynchronous serial interface mode register 20 (ASIM20)
• Asynchronous serial interface status register 20 (ASIS20)
• Baud rate generator control register 20 (BRGC20)
• Port mode register 2 (PM2)
• Port 2
(1) Serial operation mode register 20 (CSIM20)
CSIM20 is used to make the settings related to 3-wire serial I/O mode.
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM20 to 00H.
Figure 11-3. Format of Serial Operation Mode Register 20
Symbol <7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20
DIR20 CSCK20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
DIR20
First-bit specification
0
1
MSB
LSB
3-wire serial I/O mode clock selection
CSCK20
External clock input to the SCK20 pin
0
1
Output of the dedicated baud rate generator
Cautions 1. Bits 0 and 3 to 6 must be set to 0.
2. CSIM20 must be cleared to 00H if UART mode is selected.
3. When the external input clock is selected in 3-wire serial I/O mode, set input mode by
setting bit 0 of port mode register 2 (PM2) to 1.
4. Switch operating modes after halting the serial transmit/receive operation.
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CHAPTER 11 SERIAL INTERFACE 20
(2) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is used to make the settings related to asynchronous serial interface mode.
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM20 to 00H.
Figure 11-4. Format of Asynchronous Serial Interface Mode Register 20
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20
TXE20
Transmit operation control
Receive operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE20
0
1
Receive operation stopped
Receive operation enabled
PS201 PS200
Parity bit specification
0
0
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (no parity error is generated).
1
1
0
1
Odd parity
Even parity
CL20
Transmit data character length specification
0
1
7 bits
8 bits
SL20
Transmit data stop bit length
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must be set to 0.
2. If 3-wire serial I/O mode is selected, ASIM20 must be set to 00H.
3. Switch operation modes after halting the serial transmission/reception operation.
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CHAPTER 11 SERIAL INTERFACE 20
Table 11-2. Serial Interface 20 Operation Mode Settings
(1) Operation stop mode
ASIM20
CSIM20
PM22 P22 PM21 P21 PM20 P20
First
Bit
Shift
P22/SI20/
P21/SO20/ P20/SCK20/
TxD20 Pin ASCK20 Pin
Clock RxD20 Pin
Function
TXE20 RXE20 CSIE20 DIR20
CSCK20
Function
Function
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
0
0
0
×
×
×
×
×
×
×
×
−
−
P22
P21
P20
Other than above
Setting prohibited
(2) 3-wire serial I/O mode
ASIM20
CSIM20
PM22 P22 PM21 P21 PM20 P20
First
Bit
Shift
P22/SI20/
P21/SO20/ P20/SCK20/
TxD20 Pin ASCK20 Pin
Clock RxD20 Pin
Function
TXE20 RXE20 CSIE20 DIR20
CSCK20
0
Function
Function
Note 2
0
0
1
1
0
1
1Note 2
×
0
1
1
0
1
0
×
1
×
1
MSB
SI20Note 2
External
SO20
SCK20
input
(CMOS output)
clock
1
0
1
SCK20
output
Internal
clock
LSB
SCK20
input
External
clock
SCK20
output
Internal
clock
Other than above
Setting prohibited
(3) Asynchronous serial interface mode
ASIM20
CSIM20
PM22 P22 PM21 P21 PM20 P20
First
Bit
Shift
P22/SI20/
P21/SO20/ P20/SCK20/
TxD20 Pin ASCK20 Pin
Clock RxD20 Pin
Function
TXE20 RXE20 CSIE20 DIR20
CSCK20
0
Function
Function
Note 1
Note 1
1
0
1
0
1
1
0
0
0
0
0
0
×
×
0
1
1
×
LSB
P22
TxD20
ASCK20
input
External
clock
(CMOS output)
P21
Note 1
×
×
×
P20
Internal
clock
Note 1
Note 1
0
0
1
1
×
×
×
×
1
RxD20
ASCK20
input
External
clock
Note 1
P20
Internal
clock
0
1
1
TxD20
ASCK20
input
External
clock
(CMOS output)
Note 1
P20
Internal
clock
Other than above
Setting prohibited
Notes 1. These pins can be used for port functions.
2. When only transmission is used, this pin can be used as P22 (CMOS I/O).
Remark ×: don’t care
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CHAPTER 11 SERIAL INTERFACE 20
(3) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set.
ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction.
The contents of ASIS20 are undefined in 3-wire serial I/O mode.
RESET input sets ASIS20 to 00H.
Figure 11-5. Format of Asynchronous Serial Interface Status Register 20
Symbol
ASIS20
7
0
6
0
5
0
4
0
3
0
<2> <1> <0>
Address
FF71H
After reset
00H
R/W
R
PE20 FE20 OVE20
PE20
Parity error flag
0
1
No parity error occurred.
A parity error occurred (when the transmit parity and receive parity did not match).
FE20
Framing error flag
No framing error occurred.
0
1
A framing error occurred (when stop bit was not detected).Note 1
OVE20
Overrun error flag
No overrun error occurred.
0
1
An overrun error occurredNote 2
(when the next receive operation was completed before the data was read from receive buffer register 20).
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial
interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, an
overrun error will occur every time data is received.
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CHAPTER 11 SERIAL INTERFACE 20
(4) Baud rate generator control register 20 (BRGC20)
BRGC20 is used to specify the serial clock for serial interface 20.
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input sets BRGC20 to 00H.
Figure 11-6. Format of Baud Rate Generator Control Register 20
Symbol
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
BRGC20 TPS203 TPS202 TPS201 TPS200
TPS203 TPS202 TPS201 TPS200
Selection of baud rate generator source clock
n
1
2
3
4
5
6
7
8
−
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
External clock input to the ASCK20 pinNote
Setting prohibited
Other than above
Note An external clock can be used only in UART mode.
Cautions 1. When writing to BRGC20 during a communication operation, the output of the baud
rate generator is disrupted and communications cannot be performed normally. Be
sure not to write to BRGC20 during a communication operation.
2. Be sure not to select n = 1 in UART mode when fX > 2.5 MHz because the baud rate will
exceed the rated range.
3. When the external input clock is selected, set input mode by setting bit 0 of port mode
register 2 (PM2) to 1.
Remarks 1. fX: Main system clock oscillation frequency
2. n: Values determined by the settings of TPS200 to TPS203 (1 ≤ n ≤ 8)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 11 SERIAL INTERFACE 20
The baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal
obtained by dividing the clock input to the ASCK20 pin.
(a) Generation of UART baud rate transmit/receive clock form system clock
The transmit/receive clock is generated by dividing the system clock. The baud rate of a clock generated
from the system clock is estimated by using the following expression.
fX
[Baud rate] =
[bps]
2n + 1 × 8
fX: Main system clock oscillation frequency
n: Values in Figure 11-6, determined by the values of TPS200 to TPS203 (2 ≤ n ≤ 8)
Table 11-3. Example of Relationship Between System Clock and Baud Rate
Baud Rate (bps)
n
BRGC20 Set Value
Error (%)
fX = 5.0 MHz
1.73
fX = 4.9152 MHz
0
1,200
2,400
8
7
6
5
4
3
2
70H
60H
50H
40H
30H
20H
10H
4,800
9,600
19,200
38,400
76,800
Caution Do not select n = 1 during operation at fX > 2.5 MHz because the resulting baud rate exceeds the
rated range.
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CHAPTER 11 SERIAL INTERFACE 20
(b) Generation of UART baud rate transmit/receive clock from external clock input to ASCK20 pin
The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate
of a clock generated from the clock input to the ASCK20 pin is estimated by using the following
expression.
fASCK
16
[Baud rate] =
[bps]
fASCK: Frequency of clock input to the ASCK20 pin
Table 11-4. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps)
75
ASCK20 Pin Input Frequency (kHz)
1.2
2.4
150
300
4.8
600
9.6
1,200
2,400
4,800
9,600
19,200
31,250
38,400
19.2
38.4
76.8
153.6
307.2
500.0
614.4
(c) Generation of serial clock from system clock in 3-wire serial I/O
The serial clock is generated by dividing the system clock. The frequency of the serial clock can be
obtained by the following expression. If the serial clock is externally input to the SCK20 pin, it is
unnecessary to set BRGC20.
fX
Serial clock frequency =
[Hz]
2n+1
fX: Main system clock oscillation frequency
n: Values in Figure 11-6 determined by the settings of TPS200 to TPS203 (1 ≤ n ≤ 8)
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CHAPTER 11 SERIAL INTERFACE 20
11.4 Serial Interface 20 Operation
Serial interface 20 provides the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
11.4.1 Operation stop mode
In operation stop mode, serial transfer is not executed, thereby reducing the power consumption. The
P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports.
(1) Register setting
Operation stop mode is set by serial operation mode register 20 (CSIM20) and asynchronous serial interface
mode register 20 (ASIM20).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Symbol
<7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20
DIR20
CSCK20
CSIE20
Operation control in 3-wire serial I/O mode
0
1
Operation disabled
Operation enabled
Caution Bits 0 and 3 to 6 must be set to 0.
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CHAPTER 11 SERIAL INTERFACE 20
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM20 to 00H.
Symbol
ASIM20
<7>
<6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
TXE20
RXE20
PS201
PS200
CL20
SL20
TXE20
Transmit operation control
Receive operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE20
0
1
Receive operation stopped
Receive operation enabled
Caution Bits 0 and 1 must be set to 0.
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CHAPTER 11 SERIAL INTERFACE 20
11.4.2 Asynchronous serial interface (UART) mode
In this mode, the one-byte data following the start bit is transmitted/received, enabling full-duplex communication.
This device incorporates a UART-dedicated baud rate generator that enables communications at the desired baud
rate. In addition, the baud rate can also be defined by dividing the clock input to the ASCK20 pin.
The UART-dedicated baud rate generator also can output the 31.25 Kbps baud rate that complies with the MIDI
standard.
(1) Register setting
UART mode is set by serial operation mode register 20 (CSIM20), asynchronous serial interface mode
register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), baud rate generator control
register 20 (BRGC20), port mode register 2 (PM2), and port 2 (P2).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM20 to 00H.
Set CSIM20 to 00H when UART mode is selected.
Symbol <7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20
DIR20 CSCK20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
DIR20
First-bit specification
0
1
MSB
LSB
3-wire serial I/O mode clock selection
CSCK20
External clock input to the SCK20 pin
0
1
Output of the dedicated baud rate generator
Cautions 1. Bits 0 and 3 to 6 must be set to 0.
2. Switch operation modes after halting the serial transmission/reception operation.
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CHAPTER 11 SERIAL INTERFACE 20
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM20 to 00H.
Symbol
ASIM20
<7>
<6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
TXE20
RXE20
PS201
PS200
CL20
SL20
TXE20
Transmit operation control
Receive operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE20
0
1
Receive operation stopped
Receive operation enabled
PS201
PS200
Parity bit specification
0
0
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (no parity error is generated).
Odd parity
Even parity
1
1
0
1
CL20
Character length specification
0
1
7 bits
8 bits
SL20
Transmit data stop bit length specification
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must be set to 0.
2. Switch operation modes after halting the serial transmission/reception operation.
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(c) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIS20 to 00H.
Symbol
ASIS20
7
0
6
0
5
0
4
0
3
0
<2>
<1>
<0>
Address
FF71H
After reset
00H
R/W
R
PE20
FE20
OVE20
PE20
Parity error flag
0
1
No parity error occurred
A parity error occurred (when the transmit parity and receive parity did not match)
Framing error flag
FE20
0
1
No framing error occurred
A framing error occurred (when stop bit was not detected)Note 1
OVE20
Overrun error flag
No overrun error occurred
0
1
An overrun error occurredNote 2
(when the next receive operation was completed before data was read from reception buffer register 20)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial
interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, an
overrun error will occur every time data is received.
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CHAPTER 11 SERIAL INTERFACE 20
(d) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input sets BRGC20 to 00H.
Symbol
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
BRGC20 TPS203 TPS202 TPS201 TPS200
n
TPS203 TPS202 TPS201 TPS200
Selection of baud rate generator source clock
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
1
2
3
4
5
6
7
8
−
External clock input to ASCK20 pinNote
Setting prohibited
Other than above
Note Can only be used in the UART mode.
Cautions 1. When writing to BRGC20 during a communication operation, the output of the baud
rate generator is disrupted and communications cannot be performed normally. Be
sure not to write to BRGC20 during a communication operation.
2. Be sure not to select n = 1 during operation at fX > 2.5 MHz because the resulting
baud rate exceeds the rated range.
3. When the external input clock is selected, set input mode by setting bit 0 of port
mode register 2 (PM2) to 1.
Remarks 1. fX: Main system clock oscillation frequency
2. n: Values determined by the settings of TPS200 to TPS203 (1 ≤ n ≤ 8)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
The baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal
obtained by dividing the clock input to the ASCK20 pin.
(i) Generation of baud rate transmit/receive clock from system clock
The transmit/receive clock is generated by dividing the system clock. The baud rate of a clock
generated from the system clock is estimated by using the following expression.
fX
[Baud rate] =
[bps]
2n + 1 × 8
fX: Main system clock oscillation frequency
n: Values in the above table determined by the settings of TPS200 to TPS203 (2 ≤ n ≤ 8)
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Table 11-5. Example of Relationship Between System Clock and Baud Rate
Baud Rate (bps)
n
BRGC20 Set Value
Error (%)
fX = 5.0 MHz
1.73
fX = 4.9152 MHz
0
1,200
2,400
8
7
6
5
4
3
2
70H
60H
50H
40H
30H
20H
10H
4,800
9,600
19,200
38,400
76,800
Caution Do not select n = 1 during operation at fX > 2.5 MHz because the resulting baud rate exceeds the
rated range.
(ii) Generation of baud rate transmit/receive clock from external clock input to ASCK20 pin
The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud
rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following
expression.
fASCK
16
[Baud rate] =
[bps]
fASCK: Frequency of clock input to ASCK20 pin
Table 11-6. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps)
75
ASCK20 Pin Input Frequency (kHz)
1.2
2.4
150
300
4.8
600
9.6
1,200
2,400
4,800
9,600
19,200
31,250
38,400
19.2
38.4
76.8
153.6
307.2
500.0
614.4
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(2) Communication operation
(a) Data format
The transmit/receive data format is as shown in Figure 11-7. One data frame consists of a start bit,
character bits, parity bit, and stop bit(s).
The specification of character bit length in one data frame, parity selection, and specification of stop bit
length is carried out using asynchronous serial interface mode register 20 (ASIM20).
Figure 11-7. Format of Asynchronous Serial Interface Transmit/Receive Data
One data frame
Start
bit
Parity
bit
D0 D1 D2 D3 D4 D5 D6 D7
Stop bit
• Start bits ................... 1 bit
• Character bits............ 7 bits/8 bits
• Parity bits.................. Even parity/odd parity/0 parity/no parity
• Stop bits.................... 1 bit/2 bits
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is
always “0”.
The serial transfer rate is selected by baud rate generator control register 20 (BRGC20).
If a serial data receive error occurs, the receive error contents can be determined by reading the status
of asynchronous serial interface status register 20 (ASIS20).
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity
bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd
number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
• At transmission
The parity bit is determined so that the number of bits with a value of “1” in the transmit data
including the parity bit is even. The parity bit value should be as follows.
The number of bits with a value of “1” is an odd number in transmit data:
1
The number of bits with a value of “1” is an even number in transmit data: 0
• At reception
The number of bits with a value of “1” in the receive data including parity bit is counted, and if the
number is odd, a parity error occurs.
(ii) Odd parity
• At transmission
Opposite to even parity, the parity bit is determined so that the number of bits with a value of “1” in
the transmit data including parity bit is odd. The parity bit value should be as follows.
The number of bits with a value of “1” is an odd number in transmit data:
0
The number of bits with a value of “1” is an even number in transmit data: 1
• At reception
The number of bits with a value of “1” in the receive data including parity bit is counted, and if the
number is even, a parity error occurs.
(iii) 0 parity
When transmitting, the parity bit is set to “0” irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error does not occur,
irrespective of whether the parity bit is set to “0” or “1”.
(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is no
parity bit. Since there is no parity bit, a parity error does not occur.
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CHAPTER 11 SERIAL INTERFACE 20
(c) Transmission
A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start bit,
parity bit, and stop bit(s) are added automatically.
When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a
transmission completion interrupt (INTST20) is generated.
Figure 11-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
STOP
TxD20 (output)
INTST20
D0
D1
D2
D6
D7
Parity
START
(b) Stop bit length: 2
D0
D1
D2
D6
D7
Parity
TxD20 (output)
INTST20
STOP
START
Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during a
transmit operation. If the ASIM20 register is rewritten during transmission, subsequent
transmission may not be able to be performed (the normal state is restored by RESET
input).
It is possible to determine whether transmission is in progress by software by using a
transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set
by INTST20.
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CHAPTER 11 SERIAL INTERFACE 20
(d) Reception
When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive
operation is enabled and sampling of the RxD20 pin input is performed.
RxD20 pin input sampling is performed using the serial clock specified by BRGC20.
When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time
determined by the specified baud rate has passed, the data sampling start timing signal is output. If the
RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit,
the 3-bit counter is initialized and starts counting, and data sampling is performed. When character data,
a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to receive
buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated.
If an error occurs, the receive data in which the error occurred is still transferred to RXB20, and INTSR20
is generated.
If the RXE20 bit is reset (0) during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are
not changed, and INTSR20 is not generated.
Figure 11-9. Asynchronous Serial Interface Reception Completion Interrupt Timing
STOP
D0
D1
D2
D6
D7
Parity
RxD20 (input)
INTSR20
START
Caution Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will occur when the next data is received, and the
receive error state will continue indefinitely.
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(e) Receive errors
The following three errors may occur during a receive operation: a parity error, framing error, and
overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20
(ASIS20). Receive error causes are shown in Table 11-7.
It is possible to determine what kind of error occurred during reception by reading the contents of ASIS20
in the reception error interrupt servicing (see Table 11-7 and Figure 11-10).
The contents of ASIS20 are reset (0) by reading receive buffer register 20 (RXB20) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Table 11-7. Receive Error Causes
Receive Errors
Parity error
Receive Errors
Parity at transmission and reception do not match
Stop bit not detected
Value of ASIS20
04H
02H
01H
Framing error
Overrun error
Reception of next data is completed before data is read from receive buffer
register
Figure 11-10. Receive Error Timing
(a) Parity error occurrence
STOP
D0
D1
D2
D6
D7
Parity
RxD20 (input)
START
INTSR20
(b) Framing error or overrun error occurrence
STOP
D0
D1
D2
D6
D7
Parity
RxD20 (input)
INTSR20
START
Cautions 1. The contents of the ASIS20 register are reset (0) by reading receive buffer register
20 (RXB20) or receiving the next data. To ascertain the error contents, read ASIS20
before reading RXB20.
2. Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will occur when the next data is received, and
the receive error state will continue indefinitely.
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(f) Reading receive data
When the reception completion interrupt (INTSR20) occurs, receive data can be read by reading the
value of receive buffer register 20 (RXB20).
To read the receive data stored in receive buffer register 20 (RXB20), read while reception is enabled
(RXE20 = 1).
Remark However, if it is necessary to read receive data after reception has stopped (RXE20 = 0), read
using either of the following methods.
(a) Read after setting RXE20 = 0 after waiting for one cycle or more of the source clock
selected by BRGC20.
(b) Read after bit 2 (DIR20) of serial operation mode register 20 (CSIM20) is set (1).
Program example of (a) (BRGC20 = 00H (source clock = fx/2))
INTREX:
;<Reception completion interrupt routine>
NOP
;2 clocks
CLR1 RXE20
MOV A, RXB20
;Reception stopped
;Read receive data
Program example of (b)
INTRXE:
;<Reception completion interrupt routine>
;DIR20 flag is set to LSB first
;Reception stopped
SET1 CSIM20.2
CLR1 RXE20
MOV A, RXB20
;Read receive data
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(3) Cautions related to UART mode
(a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before
executing the next transmission.
(b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
reception, receive buffer register 20 (RXB20) and the receive completion interrupt (INTSR20) are as
follows.
RxD20 pin
Parity
RXB20
INTSR20
<1>
<3>
<2>
When RXE20 is set to 0 at the time indicated by <1>, RXB20 holds the previous data and INTSR20 is not
generated.
When RXE20 is set to 0 at the time indicated by <2>, RXB20 renews the data and INTSR20 is not generated.
When RXE20 is set to 0 at the time indicated by <3>, RXB20 renews the data and INTSR20 is generated.
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11.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which
incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series.
Communication is performed using three lines: a serial clock (SCK20), serial output (SO20), and serial input
(SI20).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operation mode register 20 (CSIM20),
asynchronous serial interface mode register 20 (ASIM20), baud rate generator control register 20 (BRGC20),
port mode register 2 (PM2), and port 2 (P2).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM20 to 00H.
Symbol <7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20
DIR20 CSCK20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
DIR20
First-bit specification
0
1
MSB
LSB
3-wire serial I/O mode clock selection
CSCK20
0
1
External clock input to the SCK20 pin
Output of the dedicated baud rate generator
Cautions 1. Bits 0 and 3 to 6 must be set to 0.
2. When the external input clock is selected, set input mode by setting bit 0 of port
mode register 2 (PM2) to 1.
3. Switch operation modes after halting the serial transmission/reception operation.
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CHAPTER 11 SERIAL INTERFACE 20
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM20 to 00H.
When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H.
Symbol
ASIM20
<7>
<6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
TXE20
RXE20
PS201
PS200
CL20
SL20
TXE20
Transmit operation control
Receive operation control
Parity bit specification
0
1
Transmit operation stopped
Transmit operation enabled
RXE20
0
1
Receive operation stopped
Receive operation enabled
PS201
PS200
0
0
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (no parity error occurs).
Odd parity
Even parity
1
1
0
1
CL20
Transmit data character length specification
Transmit data stop bit length specification
0
1
7 bits
8 bits
SL20
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must be set to 0.
2. Switch operation modes after halting the serial transmission/reception operation.
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(c) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input sets BRGC20 to 00H.
Symbol
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
BRGC20 TPS203 TPS202 TPS201 TPS200
n
1
2
3
4
5
6
7
8
TPS203 TPS202 TPS201 TPS200
Selection of baud rate generator source clock
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX
fX
fX
fX
fX
fX
fX
fX
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
Other than above
Setting prohibited
Caution When writing to BRGC20 during a communication operation, the baud rate generator
output is disrupted and communications cannot be performed normally. Be sure not to
write to BRGC20 during a communication operation.
Remarks 1. fX: Main system clock oscillation frequency
2. n: Values determined by the settings of TPS200 to TPS203 (1 ≤ n ≤ 8)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
If the internal clock is used as the serial clock for 3-wire serial I/O mode, set bits TPS200 to TPS203 to
set the frequency of the serial clock. To obtain the frequency to be set, use the following expression.
When an external clock is used, setting BRGC20 is not necessary.
fX
Serial clock frequency =
[Hz]
2n + 1
fX: Main system clock oscillation frequency
n: Values in the above table determined by the settings of TPS200 to TPS203 (1 ≤ n ≤ 8)
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CHAPTER 11 SERIAL INTERFACE 20
(2) Communication operation
In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/
received bit by bit in synchronization with the serial clock.
Transmit shift register 20 (TXS20/SIO20) and receive shift register 20 (RXS20) shift operations are
performed in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20
latch and output from the SO20 pin. Also, receive data input to the SI20 pin is latched in receive buffer
register 20 (RXB20/SIO20) on the rise of SCK20.
At the end of an 8-bit transfer, the operation of TXS20/SIO20 and RXS20 stops automatically, and the
interrupt request signal (INTCSI20) is generated.
Figure 11-11. 3-Wire Serial I/O Mode Timing (1/2)
(i) Master operation timing (CSCK20=0)
SIO20
write
SCK20
SO20
1
2
3
4
5
6
7
8
Note
DO7
DI7
DO6
DI6
DO5
DI5
DO4
DI4
DO3
DI3
DO2
DI2
DO1
DI1
DO0
DI0
SI20
INTCSI20
Note The value of the last bit previously output is output.
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CHAPTER 11 SERIAL INTERFACE 20
Figure 11-11. 3-Wire Serial I/O Mode Timing (2/2)
(ii) Slave operation timing (CSCK20=1)
SIO20
write
SCK20
SI20
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
Note
INTCSI20
Note The value of the last bit previously output is output.
(3) Transfer start
Serial transfer is started by setting transfer data to transmit shift register 20 (TXS20/SIO20) when the
following two conditions are satisfied.
• Bit 7 (CSIE20) of serial operation mode register 20 (CSIM20) = 1
• Internal serial clock is stopped or SCK20 is high after 8-bit serial transfer.
Caution If CSIE20 is set to “1” after data is written to TXS20/SIO20, transfer does not start.
Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal
(INTCSI20).
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CHAPTER 12 SERIAL INTERFACE 1A0
12.1 Function of Serial Interface 1A0
Serial interface 1A0 has the following three modes.
• Operation stop mode
• 3-wire serial I/O mode
• 3-wire serial I/O mode with automatic transmit/receive function
(1) Operation stop mode
This mode is used when serial transfer will not be performed. It enables a reduction in power consumption.
(2) 3-wire serial I/O mode (MSB/LSB-first switchable)
This mode is used to transfer 8-bit data using three lines: a serial clock line (SCK10) and two serial data lines
(SI10 and SO10).
Because this mode supports simultaneous transmission and reception, 3-wire serial I/O mode requires less
processing time for data transfer.
Also, when using 3-wire serial I/O mode, it is possible to select whether 8-bit data transfer will start with the
MSB or LSB, so any device can be connected regardless of whether that device is designed for MSB-first or
LSB-first transfers.
3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers with conventional
clocked serial interfaces, such as those found in the 75XL Series, 78K Series, and 17K Series.
(3) 3-wire serial mode with automatic transmit/receive function (MSB/LSB-first switchable)
This mode has an automatic transmit/receive function in addition to the functions in (2) above.
The automatic transmit/receive function is used to transmit/receive data with a maximum of 16 bytes. This
function enables the hardware to transmit/receive data to/from the OSD (On Screen Display) device and a
device with an on-chip display controller/driver independently of the CPU, thus alleviating the software load.
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12.2 Configuration of Serial Interface 1A0
Serial interface 1A0 includes the following hardware.
Table 12-1. Configuration of Serial Interface 1A0
Item
Configuration
Registers
Serial I/O shift register 1A0 (SIO1A0)
Automatic data transmit/receive address pointer 0 (ADTP0)
Control registers
Serial operation mode register 1A0 (CSIM1A0)
Automatic data transmit/receive control register 0 (ADTC0)
Automatic data transmit/receive interval specification register 0 (ADTI0)
Port mode register 2 (PM2)
Port 2 (P2)
Figure 12-1. Block Diagram of Serial Interface 1A0
Automatic data
transmit/receive
address pointer 0
(ADTP0)
Buffer RAM
Internal bus
Automatic data
transmit/receive
interval specification
register 0 (ADTI0)
Automatic data
transmit/receive
control register 0
(ADTC0)
Serial operation
mode register 1A0
(CSIM1A0)
ATE0
DIR
10
DIR
10
SCL SCL
LSCK
ADTI ADTI ADTI ADTI ADTI ADTI
07 04 03 02 01 00
CSIE DIR
ARLD
0
ATE0
TRF0
RE0
101 100
10
10
10
Serial I/O shift
register 1A0
(SIO1A0)
SI10/
P25
ADTI00 to ADTI04
Match
PM24
TRF0
SO10/
P24
P24 output
latch
Selector
5-bit counter
Hand
shake
ARLD0
Serial clock
counter
INTCSI10
SIO1A0 write
Clear
CSIE10
f
SCK
PM23
Selector
R
Q
S
/22 /23
fX fX
fX
/2
4
P23 output
latch
LSCK
10
SCK10/
P23
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(1) Serial I/O shift register 1A0 (SIO1A0)
This is an 8-bit register used to carry out parallel/serial conversion and to carry out serial
transmission/reception (shift operation) in synchronization with the serial clock.
SIO1A0 is set with an 8-bit memory manipulation instruction.
When the value in bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) is 1, writing data to
SIO1A0 starts a serial operation.
During transmission, data written to SIO1A0 is output to the serial output (SO10). During reception, data is
read from the serial input (SI10) to SIO1A0.
RESET input sets SIO1A0 to 00H.
Caution Do not write data to SIO1A0 while the automatic transmit/receive function is activated.
(2) Automatic data transmit/receive address pointer 0 (ADTP0)
This register stores value of (transmit data byte − 1) while the automatic transmit/receive function is activated.
As data is transferred/received, it is automatically decremented.
ADTP0 is set via an 8-bit memory manipulation instruction. The higher 4 bits must be set to 0.
RESET input makes ADTP0 undefined.
Caution Do not write data to ADTP0 while the automatic transmit/receive function is activated.
(3) Serial clock counter
This counter counts the serial clocks to be output and input during transmission/reception to check whether
8-bit data has been transmitted/received.
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12.3 Control Registers for Serial Interface 1A0
Serial interface 1A0 is controlled by the following five registers.
• Serial operation mode register 1A0 (CSIM1A0)
• Automatic data transmit/receive control register 0 (ADTC0)
• Automatic data transmit/receive interval specification register 0 (ADTI0)
• Port mode register 2 (PM2)
• Port 2 (PM)
(1) Serial operation mode register 1A0 (CSIM1A0)
This register sets serial interface 1A0 serial clock, operation mode, operation enable/disable, and automatic
transmission/reception operation enable/disable.
CSIM1A0 is set via a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Caution Set the port mode register 2 (PM2) in the 3-wire serial I/O mode or 3-wire serial I/O mode
with automatic transmit/receive function as follows.
• In the case of serial clock output (master transmission or master reception)
Set the SCK10/P23 pin to output mode (PM23 = 0) and clear the output latch of P23 to 0.
• In the case of serial clock input (slave transmission or slave reception)
Set the SCK10/P23 pin to input mode (PM23 = 1).
• In transmission or transmission/reception mode
Set the SO10/P24 pin to output mode (PM24 = 0) and clear the output latch of P24 to 0.
Set the SI10/P25 pin to input mode (PM25 = 1).
• In reception mode
Set the SI10/P25 pin to input mode (PM25 = 1).
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Figure 12-2. Format of Serial Operation Mode Register 1A0
Symbol
<7>
6
<5>
<4>
3
0
2
0
1
0
Address
FF78H
After reset
00H
R/W
R/W
CSIM1A0 CSIE10
DIR10
ATE0
LSCK10
SCL101 SCL100
CSIE10
Specification of operation enable/disable
Serial counter
Shift register operation
Operation stopped
PortNote
0
1
Cleared
Port function
Operation enabled
Count operation enabled
Serial function + port function
DIR10
Specification of first bit of serial transfer data
Selection of operation mode
0
1
MSB
LSB
ATE0
0
1
3-wire serial mode
3-wire serial mode with automatic transmit/receive function
LSCK10
0
Chip enable control of SCK10 pin
SCK10 is used as port (P23) when CSIE10 = 0.
SCK10 is used for clock output when CSIE10 = 1.
1
SCK10 is fixed to high-level output when CSIE10 = 0.
SCK10 is used for clock output when CSIE10 = 1.
SCL101 SCL100
Selection of serial clock (fSCK)
0
0
1
1
0
1
0
1
External clock input to SCK10 pin
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
Note When CSIE10 = 0 (SIO1A0 operation stop status), the SCK10/P23, SO10/P24, and SI10/P25 pins can
freely be used as port pins. Also, when CSIE10 is used for transmission only, the SI10/P25 pin can be
used as P25 (CMOS I/O) (set bit 7 (RE0) of ADTC0 to 0).
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2) Automatic data transmit/receive control register 0 (ADTC0)
This register sets automatic reception enable/disable, the operation mode, and displays the state of
automatic transmit/receive control.
ADTC0 is set via a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 12-3. Format of Automatic Data Transmit/Receive Control Register 0
Symbol
ADTC0
<7>
<6>
5
0
4
0
<3>
2
0
1
0
0
0
Address
FF79H
After reset
00H
R/W
R/WNote 1
RE0
ARLD0
TRF0
RE0
0
Control of reception of automatic transmit/receive function
Reception disabledNote 2
Reception enabled
1
ARLD0
Selection of operation mode for automatic transmit/receive function
0
1
One-shot mode
Repeat mode
TRF0
0
Status of automatic transmission/reception functionNote 3
Detection of termination of automatic transmission/reception (this bit is set to 0 upon suspension of automatic
transmission/reception or when ARLD0 = 0)
1
Automatic transmission/reception in progress (this bit is set to 1 when data is written to SIO1A0)
Notes 1. Bit 3 (TRF0) is read-only.
2. When RE0 is reset to 0, P25 (CMOS I/O) is used even when bit 7 (CSIE10) of serial operation
mode register 1A0 (CSIM1A0) is set to 1.
3. Use TRF0, instead of CSIIF10 (interrupt request flag), to identify the completion of automatic
transmission/reception.
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(3) Automatic data transmit/receive interval specification register 0 (ADTI0)
This register sets the automatic data transmit/receive function data transfer interval.
ADTI0 is set via a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 12-4. Format of Automatic Data Transmit/Receive Interval Specification Register 0 (1/2)
Symbol
<7>
6
0
5
0
<4>
<3>
<2>
<1>
<0>
Address
FF7BH
After reset
00H
R/W
R/W
ADTI0 ADTI07
ADTI04 ADTI03 ADTI02 ADTI01 ADTI00
ADTI07
Data transfer interval control
0
1
No control of interval by ADTI00 to ADTI04Note 1
Control of interval by ADTI00 to ADTI04
n
ADTI04
ADTI03 ADTI02 ADTI01
ADTI00
Data transfer interval specification
(fX = 5.0 MHz, fSCK = 1.25 MHz)Note 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.60 µs + 0.5/fSCK
0
1
2.40 µs + 0.5/fSCK
3.20 µs + 0.5/fSCK
4.00 µs + 0.5/fSCK
4.80 µs + 0.5/fSCK
5.60 µs + 0.5/fSCK
6.40 µs + 0.5/fSCK
7.20 µs + 0.5/fSCK
8.00 µs + 0.5/fSCK
8.80 µs + 0.5/fSCK
9.60 µs + 0.5/fSCK
10.4 µs + 0.5/fSCK
11.2 µs + 0.5/fSCK
12.0 µs + 0.5/fSCK
12.8 µs + 0.5/fSCK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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Figure 12-4. Format of Automatic Data Transmit/Receive Interval Specification Register 0 (2/2)
Symbol
<7>
6
0
5
0
<4>
<3>
<2>
<1>
<0>
Address
FF7BH
After reset
00H
R/W
R/W
ADTI0 ADTI07
ADTI04 ADTI03 ADTI02 ADTI01 ADTI00
n
ADTI04 ADTI03 ADTI02 ADTI01
ADTI00
Data transfer interval specification
(fX = 5.0 MHz, fSCK = 1.25 MHz)Note 2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
13.6 µs + 0.5/fSCK
14.4 µs + 0.5/fSCK
15.2 µs + 0.5/fSCK
16.0 µs + 0.5/fSCK
16.8 µs + 0.5/fSCK
17.6 µs + 0.5/fSCK
18.4 µs + 0.5/fSCK
19.2 µs + 0.5/fSCK
20.0 µs + 0.5/fSCK
20.8 µs + 0.5/fSCK
21.6 µs + 0.5/fSCK
22.4 µs + 0.5/fSCK
23.2 µs + 0.5/fSCK
24.0 µs + 0.5/fSCK
24.8 µs + 0.5/fSCK
25.6 µs + 0.5/fSCK
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Notes 1. The interval time depends only on the CPU processing.
2. The data transfer interval time is found from the following expressions (n: Value set to ADTI00 to
ADTI04).
<1> n = 0
2
0.5
Interval time =
+
+
fSCK
fSCK
<2> n = 1 to 31
Interval time =
n+1
fSCK
0.5
fSCK
Cautions 1. Do not write to ADTI0 during operation of the automatic transmit/receive function.
2. Be sure to set bits 5 and 6 to 0.
Remark fX:
Main system clock oscillation frequency
fSCK: Serial clock frequency
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12.4 Serial Interface 1A0 Operation
Serial interface 1A0 provides the following three modes.
• Operation stop mode
• 3-wire serial I/O mode
• 3-wire serial I/O mode with automatic transmit/receive function
12.4.1 Operation stop mode
In operation stop mode, serial transfer is not executed, thereby reducing the power consumption. The P23/SCK10,
P24/SO10, and P25/SI10 pins can be used as normal I/O ports.
(1) Register setting
Operation stop mode is set by serial operation mode register 1A0 (CSIM1A0).
(a) Serial operation mode register 1A0 (CSIM1A0)
CSIM1A0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM1A0 to 00H.
Symbol
<7>
6
<5>
<4>
3
0
2
0
1
0
Address
FF78H
After reset
00H
R/W
R/W
CSIM1A0 CSIE10
DIR10
ATE0
LSCK10
SCL101 SCL100
CSIE10
Specification of operation enable/disable
Serial counter
Shift register operation
Operation stopped
Operation enabled
PortNote
0
1
Cleared
Port function
Count operation enabled
Serial function + port function
Note When CSIE10 = 0 (SIO1A0 operation stop status), the SCK10/P23, SO10/P24, and SI10/P25 pins can
freely be used as port pins.
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12.4.2 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which
incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series.
Communication is performed using three lines: a serial clock (SCK10), serial output (SO10), and serial input
(SI10).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operation mode register 1A0 (CSIM1A0), port
mode register 2 (PM2), and port 2 (P2).
(a) Serial operation mode register 1A0 (CSIM1A0)
CSIM1A0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM1A0 to 00H.
Caution Set the port mode register 2 (PM2) in the 3-wire serial I/O mode as follows.
•
•
•
In the case of serial clock output (master transmission or master reception)
Set the SCK10/P23 pin to output mode (PM23 = 0) and clear the output latch of P23 to 0.
In the case of serial clock input (slave transmission or slave reception)
Set the SCK10/P23 pin to input mode (PM23 = 1).
In transmission or transmission/reception mode
Set the SO10/P24 pin to output mode (PM24 = 0) and clear the output latch of P24 to 0.
Set the SI10/P25 pin to input mode (PM25 = 1).
•
In reception mode
Set the SI10/P25 pin to input mode (PM25 = 1).
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Symbol
<7>
6
<5>
<4>
3
0
2
0
1
0
Address
FF78H
After reset
00H
R/W
R/W
CSIM1A0 CSIE10
DIR10
ATE0
LSCK10
SCL101 SCL100
CSIE10
Specification of operation enable/disable
Serial counter
Shift register operation
Operation stopped
PortNote
0
1
Cleared
Port function
Operation enabled
Count operation enabled
Serial function + port function
DIR10
Specification of first bit of serial transfer data
0
1
MSB
LSB
ATE0
Selection of operation mode
0
1
3-wire serial mode
3-wire serial mode with automatic transmit/receive function
LSCK10
0
Chip enable control of SCK10 pin
SCK10 is used as port (P23) when CSIE10 = 0.
SCK10 is used for clock output when CSIE10 = 1.
1
SCK10 is fixed to high-level output when CSIE10 = 0.
SCK10 is used for clock output when CSIE10 = 1.
SCL101 SCL100
Selection of serial clock
0
0
1
1
0
1
0
1
External clock input to SCK10 pin
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
Note When CSIE10 = 0 (SIO1A0 operation stop status), the SCK10/P23, SO10/P24, and SI10/P25 pins can
freely be used as port pins. Also, when CSIE10 is used for transmission only, the SI10/P25 pin can be
used as P25 (CMOS I/O) (set bit 7 (RE0) of ADTC0 to 0).
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2) Communication operation
In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.
Data is
transmitted/received bit by bit in synchronization with the serial clock.
Serial I/O shift register 1A0 (SIO1A0) shift operations are performed in synchronization with the fall of the
serial clock (SCK10). Then transmit data is held in the SO10 latch and output from the SO10 pin. Also,
receive data input to the SI10 pin is latched in the SIO1A0 on the rise of SCK10.
At the end of an 8-bit transfer, the operation of SIO1A0 stops automatically, and the interrupt request signal
(INTCSI10) is generated.
Figure 12-5. 3-Wire Serial I/O Mode Timing (1/2)
(i) Master operation timing
SIO1A0
write
SCK10
SO10
1
2
3
4
5
6
7
8
Note
DO7
DI7
DO6
DI6
DO5
DI5
DO4
DI4
DO3
DI3
DO2
DI2
DO1
DI1
DO0
DI0
SI10
INTCSI10
Note The value of the last bit previously output is output.
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Figure 12-5. 3-Wire Serial I/O Mode Timing (2/2)
(ii) Slave operation timing
SIO1A0
write
SCK10
SI10
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO10
Note
INTCSI10
Note The value of the last bit previously output is output.
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(3) MSB/LSB switching as the start bit
In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB.
Figure 12-6 shows the configuration of serial I/O shift register 1A0 (SIO1A0) and the internal bus. As shown
in the figure, MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 6 (DIR10) of serial operation mode register 1A0
(CSIM1A0).
Figure 12-6. Circuit of Switching in Transfer Bit Order
7
6
Internal bus
1
0
LSB-first
MSB-first
Read/write gate
Read/write gate
SO1 latch
SI10
Shift I/O shift register 1A0 (SIO1A0)
D
Q
SO10
SCK10
Start bit switching is realized by switching the bit order for data write to SIO1A0. The SIO1A0 shift order
remains unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(4) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 1A0 (SIO1A0) when the following
two conditions are satisfied.
• Bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) = 1
• Internal serial clock is stopped or SCK10 is high after 8-bit serial transfer.
Caution If CSIE10 is set to “1” after data is written to SIO1A0, transfer does not start.
Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal
(INTCSI10).
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12.4.3 3-wire serial I/O mode with automatic transmit/receive function
This 3-wire serial I/O mode is used for transmission/reception of a maximum of 16-byte data without the use of
software. Once transfer is started, the set number of bytes of data prestored in the RAM can be transmitted, and the
set number of bytes of data can be received and stored in the RAM.
(1) Register setting
The 3-wire serial I/O mode with automatic transmit/receive function is set with serial operation mode register
1A0 (CSIM1A0), automatic data transmit/receive control register 0 (ADTC0), automatic data transmit/receive
interval specification register 0 (ADTI0), port mode register 2 (PM2), and port 2 (P2).
(a) Serial operation mode register 1A0 (CSIM1A0)
CSIM1A0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM1A0 to 00H.
Caution Set port mode register 2 (PM2) in the 3-wire serial I/O mode with automatic transmit/
receive function as follows.
• In the case of serial clock output (master transmission or master reception)
Set the SCK10/P23 pin to output mode (PM23 = 0) and clear the output latch of P23 to 0.
• In the case of serial clock input (slave transmission or slave reception)
Set the SCK10/P23 pin to input mode (PM23 = 1).
• In transmission or transmission/reception mode
Set the SO10/P24 pin to output mode (PM24 = 0) and clear the output latch of P24 to 0.
Set the SI10/P25 pin to input mode (PM25 = 1).
• In reception mode
Set the SI10/P25 pin to input mode (PM25 = 1).
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Symbol
<7>
6
<5>
<4>
3
0
2
0
1
0
Address
FF78H
After reset
00H
R/W
R/W
CSIM1A0 CSIE10
DIR10
ATE0
LSCK10
SCL101 SCL100
CSIE10
Specification of operation enable/disable
Serial counter
Shift register operation
Operation stopped
PortNote
0
1
Cleared
Port function
Operation enabled
Count operation enabled
Serial function + port function
DIR10
Specification of first bit of serial transfer data
0
1
MSB
LSB
ATE0
Selection of operation mode
0
1
3-wire serial mode
3-wire serial mode with automatic transmit/receive function
LSCK10
0
Chip enable control of SCK10 pin
SCK10 is used as port (P23) when CSIE10 = 0.
SCK10 is used for clock output when CSIE10 = 1.
1
SCK10 is fixed to high-level output when CSIE10 = 0.
SCK10 is used for clock output when CSIE10 = 1.
SCL101 SCL100
Selection of serial clock
0
0
1
1
0
1
0
1
External clock input to SCK10 pin
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
Note When CSIE10 = 0 (SIO1A0 operation stop status), the SCK10/P23, SO10/P24, and SI10/P25 pins can
freely be used as port pins. Also, when CSIE10 is used for transmission only, the SI10/P25 pin can be
used as P25 (CMOS I/O) (set bit 7 (RE0) of ADTC0 to 0).
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(b) Automatic data transmit/receive control register 0 (ADTC0)
ADTC0 is set via a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Symbol
ADTC0
<7>
<6>
5
0
4
0
<3>
2
0
1
0
0
0
Address
FF79H
After reset
00H
R/W
R/WNote 1
RE0
ARLD0
TRF0
RE0
0
Control of reception of automatic transmit/receive function
Reception disabledNote 2
Reception enabled
1
ARLD0
Selection of operation mode for automatic transmit/receive function
0
1
One-shot mode
Repeat mode
TRF0
0
Status of automatic transmit/receive functionNote 3
Detection of termination of automatic transmission/reception (this bit is set to 0 upon suspension of automatic
transmission/reception or when ARLD0 = 0)
1
Automatic transmission/reception in progress (this bit is set to 1 when data is written to SIO1A0)
Notes 1. Bit 3 (TRF0) is read-only.
2. When RE0 is reset to 0, P25 (CMOS I/O) is used even when bit 7 (CSIE10) of serial operation
mode register 1A0 (CSIM1A0) is set to 1.
3. Use TRF0, instead of CSIIF10 (interrupt request flag), to identify the completion of automatic
transmission/reception.
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(c) Automatic data transmit/receive interval specification register 0 (ADTI0)
ADTI0 is set via a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Symbol
<7>
6
0
5
0
<4>
<3>
<2>
<1>
<0>
Address
FF7BH
After reset
00H
R/W
R/W
ADTI0 ADTI07
ADTI04 ADTI03 ADTI02 ADTI01 ADTI00
ADTI07
Data transfer interval control
0
1
No control of interval by ADTI00 to ADTI04Note 1
Control of interval by ADTI00 to ADTI04
n
ADTI04
ADTI03 ADTI02 ADTI01
ADTI00
Data transfer interval specification
(fX = 5.0 MHz, fSCK = 1.25 MHz)Note 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.60 µs + 0.5/fSCK
0
1
2.40 µs + 0.5/fSCK
3.20 µs + 0.5/fSCK
4.00 µs + 0.5/fSCK
4.80 µs + 0.5/fSCK
5.60 µs + 0.5/fSCK
6.40 µs + 0.5/fSCK
7.20 µs + 0.5/fSCK
8.00 µs + 0.5/fSCK
8.80 µs + 0.5/fSCK
9.60 µs + 0.5/fSCK
10.4 µs + 0.5/fSCK
11.2 µs + 0.5/fSCK
12.0 µs + 0.5/fSCK
12.8 µs + 0.5/fSCK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
(Continued)
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CHAPTER 12 SERIAL INTERFACE 1A0
Symbol
<7>
6
0
5
0
<4>
<3>
<2>
<1>
<0>
Address
FF7BH
After reset
00H
R/W
R/W
ADTI0 ADTI07
ADTI04 ADTI03 ADTI02 ADTI01 ADTI00
n
ADTI04 ADTI03 ADTI02 ADTI01
ADTI00
Data transfer interval specification
(fX = 5.0 MHz, fSCK = 1.25 MHz)Note 2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
13.6 µs + 0.5/fSCK
14.4 µs + 0.5/fSCK
15.2 µs + 0.5/fSCK
16.0 µs + 0.5/fSCK
16.8 µs + 0.5/fSCK
17.6 µs + 0.5/fSCK
18.4 µs + 0.5/fSCK
19.2 µs + 0.5/fSCK
20.0 µs + 0.5/fSCK
20.8 µs + 0.5/fSCK
21.6 µs + 0.5/fSCK
22.4 µs + 0.5/fSCK
23.2 µs + 0.5/fSCK
24.0 µs + 0.5/fSCK
24.8 µs + 0.5/fSCK
25.6 µs + 0.5/fSCK
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Notes 1. The interval time depends only on the CPU processing.
2. The data transfer interval time is found from the following expressions (n: Value set to ADTI00 to
ADTI04).
<1> n = 0
2
0.5
Interval time =
+
+
fSCK
fSCK
<2> n = 1 to 31
Interval time =
n+1
fSCK
0.5
fSCK
Cautions 1. Do not write to ADTI0 during operation of the automatic transmit/receive function.
2. Be sure to set bits 5 and 6 to 0.
Remark fX:
Main system clock oscillation frequency
fSCK: Serial clock frequency
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(2) Automatic transmit/receive data setting
(a) Transmit data setting
<1> Write transmit data from the least significant address FFA0H of buffer RAM (up to FFAFH). The
transmit data should be in the order from higher address to lower address.
<2> Set the value obtained by subtracting 1 from the number of transmit data bytes to automatic data
transmit/receive address pointer 0 (ADTP0).
(b) Automatic transmit/receive mode setting
<1> Set bit 7 (CSIE10) and bit 5 (ATE0) of serial operation mode register 1A0 (CSIM1A0) to 1.
<2> Set bit 7 (RE0) of automatic data transmit/receive control register 0 (ADTC0) to 1.
<3> Set the data transmit/receive interval in automatic data transmit/receive interval specification
register 0 (ADTI0).
<4> Write any value to serial I/O shift register 1A0 (SIO1A0) (transfer start trigger).
Caution Writing any value to SIO1A0 orders the start of automatic transmission/reception
operation; the written value has no meaning.
The following operations are automatically carried out when (a) and (b) are carried out.
•
After the buffer RAM data specified by ADTP0 is transferred to SIO1A0, transmission is carried out
(start of automatic transmission/reception).
•
•
The received data is written to the buffer RAM address specified by ADTP0.
ADTP0 is decremented and the next data transmission/reception is carried out.
Data
transmission/reception continues until the ADTP0 decremental output becomes 00H and address
FFA0H data is output (end of automatic transmission/reception).
•
When automatic transmission/reception is terminated, bit 3 (TRF0) of ADTC0 is cleared to 0.
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CHAPTER 12 SERIAL INTERFACE 1A0
(3) Communication operation
(a) Basic transmit/receive mode
This transmit/receive mode is the same as the 3-wire serial I/O mode in which the specified number of
data are transmitted/received in 8-bit units.
Serial transfer is started when any data is written to serial I/O shift register 1A0 (SIO1A0) while bit 7
(CSIE10) of serial operation mode register 1A0 (CSIM1A0) is set to 1.
Upon completion of transmission of the last byte, the interrupt request flag (CSIIF10) is set. The
termination of automatic transmission/reception should be checked by using bit 3 (TRF0) of automatic
data transmit/receive control register 0 (ADTC0), not by CSIIF10 because CSIIF10 of the interrupt
request flag is cleared if an interrupt is acknowledged.
Figure 12-7 shows the basic transmit/receive mode operation timing, and Figure 12-8 shows the
operation flowchart.
Figure 12-9 shows buffer RAM operation at 6-byte transmission.
Figure 12-7. Basic Transmit/Receive Mode Operation Timing
Interval
SCK10
SO10
SI10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSIIF10
TRF0
Cautions 1. Because, in the basic transmit/receive mode, the automatic transmit/receive
function writes/reads data to/from the buffer RAM after 1-byte
transmission/reception, an interval is inserted till the next transmission/reception.
As the buffer RAM write/read is performed at the same time as CPU processing, the
maximum interval is dependent upon CPU processing and the value of automatic
data transmit/receive interval specification register 0 (ADTI0) (refer to 12.4.3 (5)
Interval time of automatic transmission/reception).
2. When TRF0 is cleared, the SO10 pin becomes low level.
Remark CSIIF10: Interrupt request flag
TRF0: Bit 3 of automatic data transmit/receive control register 0 (ADTC0)
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Figure 12-8. Basic Transmit/Receive Mode Flowchart
Start
Write transmit data
in buffer RAM
Set ADTP0 to the value (pointer
value) obtained by subtracting 1
from the number of transmit
data bytes
Software execution
Set the transmission/reception
operation interval time in ADTI0
Write any data to SIO1A0
(Start trigger)
Write transmit data from
buffer RAM to SIO1A0
Transmission/reception
operation
Decrement pointer value
Hardware execution
Write receive data from
SIO1A0 to buffer RAM
No
No
Pointer value = 0
Yes
TRF0 = 0
Software execution
Yes
End
Remark ADTP0: Automatic data transmit/receive address pointer 0
ADTI0: Automatic data transmit/receive interval specification register 0
SIO1A0: Serial I/O shift register 1A0
TRF0:
Bit 3 of automatic data transmit/receive control register 0 (ADTC0)
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CHAPTER 12 SERIAL INTERFACE 1A0
In 6-byte transmission/reception (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/receive control
register 0 (ADTC0) = 0, and 1, respectively) in basic transmit/receive mode, buffer RAM operates as follows.
(i) Before transmission/reception (refer to Figure 12-9 (a))
After any data has been written to SIO1A0 (start trigger: this data is not transferred), transmit data 1
(T1) is transferred from the buffer RAM to SIO1A0. When transmission of the first byte is completed,
receive data 1 (R1) is transferred from SIO1A0 to the buffer RAM, and automatic data
transmit/receive address pointer 0 (ADTP0) is decremented. Then transmit data 2 (T2) is
transferred from the buffer RAM to SIO1A0.
(ii) 4th byte transmit/receive point (refer to Figure 12-9 (b))
Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from
the buffer RAM to SIO1A0. When transmission of the fourth byte is completed, receive data 4 (R4)
is transferred from SIO1A0 to the buffer RAM, and ADTP0 is decremented.
(iii) Completion of transmission/reception (refer to Figure 12-9 (c))
When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIO1A0 to
the buffer RAM, and the interrupt request flag (CSIIF10) is set (INTCSI10 generation).
Figure 12-9. Buffer RAM Operation in 6-Byte Transmission/Reception
(in Basic Transmit/Receive Mode) (1/2)
(a) Before transmission/reception
FFAFH
Transmit data 1 (T1)
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
Transmit data 5 (T5)
Transmit data 6 (T6)
Receive data 1 (R1)
FFA5H
SIO1A0
ADTP0
CSIIF10
5
0
_
1
FFA0H
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Figure 12-9. Buffer RAM Operation in 6-Byte Transmission/Reception
(in Basic Transmit/Receive Mode) (2/2)
(b) 4th byte transmission/reception
FFAFH
Receive data 1 (R1)
Receive data 2 (R2)
Receive data 3 (R3)
Transmit data 4 (T4)
Transmit data 5 (T5)
Transmit data 6 (T6)
FFA5H
Receive data 4 (R4) SIO1A0
2
0
ADTP0
_
1
FFA0H
CSIIF10
(c) Completion of transmission/reception
FFAFH
FFA5H
Receive data 1 (R1)
SIO1A0
ADTP0
CSIIF10
Receive data 2 (R2)
Receive data 3 (R3)
Receive data 4 (R4)
Receive data 5 (R5)
Receive data 6 (R6)
0
1
FFA0H
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CHAPTER 12 SERIAL INTERFACE 1A0
(b) Basic transmit mode
In this mode, the specified number of 8-bit unit data are transmitted.
Serial transfer is started when any data is written to serial I/O shift register 1A0 (SIO1A0) while bit 7
(CSIE10) of serial operation mode register 1A0 (CSIM1A0) is set to 1, and bit 7 (RE0) of automatic data
transmit/receive control register 0 (ADTC0) is set to 0.
Upon completion of transmission of the last byte, the interrupt request flag (CSIIF10) is set. The
termination of automatic transmission/reception should be checked by using bit 3 (TRF0) of automatic
data transmit/receive control register 0 (ADTC0), not by CSIIF10.
If a receive operation is not executed, the P25/SI10 pin can be use as normal I/O port.
Figure 12-10 shows the basic transmit mode operation timing, and Figure 12-11 shows the operation
flowchart.
Figure 12-12 shows buffer RAM operation when repeatedly transmitting 6 bytes.
Figure 12-10. Basic Transmit Mode Operation Timing
Interval
SCK10
SO10
CSIIF10
TRF0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Cautions 1. Because, in the basic transmit mode, the automatic transmit/receive function reads
data from the buffer RAM after 1-byte transmission, an interval is inserted until the
next transmission. As the buffer RAM read is performed at the same time as CPU
processing, the maximum interval is dependent upon CPU processing and the
value of automatic data transmit/receive interval specification register 0 (ADTI0)
(refer to 12.4.3 (5) Interval time of automatic transmission/reception).
2. When TRF0 is cleared, the SO10 pin becomes low level.
Remark CSIIF10: Interrupt request flag
TRF0:
Bit 3 of automatic data transmit/receive control register 0 (ADTC0)
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Figure 12-11. Basic Transmit Mode Flowchart
Start
Write transmit data
in buffer RAM
Set ADTP0 to the value (pointer
value) obtained by subtracting 1
from the number of transmit
data bytes
Software execution
Set the transmission/reception
operation interval time in ADTI0
Write any data to SIO1A0
(Start trigger)
Write transmit data from
buffer RAM to SIO1A0
Decrement pointer value
Transmission operation
Hardware execution
No
No
Pointer value = 0
Yes
TRF0 = 0
Software execution
Yes
End
Remark ADTP0:
Automatic data transmit/receive address pointer 0
ADTI0:
Automatic data transmit/receive interval specification register 0
SIO1A0: Serial I/O shift register 1A0
TRF0:
Bit 3 of automatic data transmit/receive control register 0 (ADTC0)
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CHAPTER 12 SERIAL INTERFACE 1A0
In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/receive control register 0
(ADTC0) are 0) in basic transmit mode, buffer RAM operates as follows.
(i) Before transmission (refer to Figure 12-12 (a))
After any data has been written to SIO1A0 (start trigger: this data is not transferred), transmit data 1
(T1) is transferred from the buffer RAM to SIO1A0. When transmission of the first byte is completed,
ADTP0 is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1A0.
(ii) 4th byte transmission point (refer to Figure 12-12 (b))
Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the buffer
RAM to SIO1A0. When transmission of the fourth byte is completed, ADTP0 is decremented.
(iii) Completion of transmission/reception (refer to Figure 12-12 (c))
When transmission of the sixth byte is completed, the interrupt request flag (CSIIF10) is set
(INTCSI10 generation).
Figure 12-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (1/2)
(a) Before transmission
FFAFH
FFA5H
Transmit data 1 (T1)
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
Transmit data 5 (T5)
Transmit data 6 (T6)
SIO1A0
ADTP0
CSIIF10
5
0
_
1
FFA0H
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Figure 12-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2)
(b) 4th byte transmission point
FFAFH
FFA5H
Transmit data 1 (T1)
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
Transmit data 5 (T5)
Transmit data 6 (T6)
SIO1A0
ADTP0
CSIIF10
5
0
_
1
FFA0H
(c) Completion of transmission/reception
FFAFH
FFA5H
Transmit data 1 (T1)
SIO1A0
ADTP0
CSIIF10
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
Transmit data 5 (T5)
Transmit data 6 (T6)
0
1
FFA0H
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CHAPTER 12 SERIAL INTERFACE 1A0
(c) Repeat transmit mode
In this mode, data stored in the buffer RAM is transmitted repeatedly.
Serial transfer is started by writing any data to serial shift I/O register 1A0 (SIO1A0) when bit 7 (CSIE10)
of serial operation mode register 1A0 (CSIM1A0) is set to 1, and bit 7 (RE0) of automatic data
transmit/receive control register 0 (ADTC0) is set to 0.
Unlike the basic transmission mode, after the last byte (data in address FFA0H) has been transmitted,
the interrupt request flag (CSIIF10) is not set, the value at the time when the transmission was started is
set in automatic data transmit/receive address pointer 0 (ADTP0) again, and the buffer RAM contents
are transmitted again.
When a reception operation is not performed, the P25/SI10 pin can be used as a normal I/O port.
The repeat transmit mode operation timing is shown in Figure 12-13, and the operation flowchart in
Figure 12-14.
Figure 12-13. Repeat Transmit Mode Operation Timing
Interval
Interval
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
Caution Because, in the repeat transmit mode, a read is performed on the buffer RAM after the
transmission of one byte, the interval is included in the period up to the next
transmission. As the buffer RAM read is performed at the same time as CPU
processing, the maximum interval is dependent upon the CPU operation and the value
of automatic data transmit/receive interval specification register 0 (ADTI0) (refer to
12.4.3 (5) Interval time of automatic transmission/reception).
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Figure 12-14. Repeat Transmit Mode Flowchart
Start
Write transmit data
in buffer RAM
Set ADTP0 to the value (pointer
value) obtained by subtracting 1
from the number of transmit
data bytes
Software execution
Set the transmission/reception
operation interval time in ADTI0
Write any data to SIO1A0
(Start trigger)
Write transmit data from
buffer RAM to SIO1A0
Decrement pointer value
Transmission operation
Hardware execution
No
Pointer value = 0
Yes
Reset ADTP0
Remark ADTP0:
Automatic data transmit/receive address pointer 0
Automatic data transmit/receive interval specification register 0
ADTI0:
SIO1A0: Serial I/O shift register 1A0
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CHAPTER 12 SERIAL INTERFACE 1A0
In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transmit/receive control register 0
(ADTC0) are 1 and 0, respectively) in repeat transmit mode, buffer RAM operates as follows.
(i) Before transmission (refer to Figure 12-15 (a))
After any data has been written to SIO1A0 (start trigger: this data is not transferred), transmit data 1
(T1) is transferred from the buffer RAM to SIO1A0. When transmission of the first byte is completed,
ADTP0 is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1A0.
(ii) Upon completion of transmission of 6 bytes (refer to Figure 12-15 (b))
When transmission of the sixth byte is completed, the interrupt request flag (CSIIF10) is not set. The
previous pointer value is assigned to the ADTP0.
(iii) 7th byte transmission point (refer to Figure 12-15 (c))
Transmit data 1 (T1) is transferred from the buffer RAM to SIO1A0 again. When transmission of the
first byte is completed, ADTP0 is decremented. Then transmit data 2 (T2) is transferred from the
buffer RAM to SIO1A0.
Figure 12-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (1/2)
(a) Before transmission
FFAFH
Transmit data 1 (T1)
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
Transmit data 5 (T5)
Transmit data 6 (T6)
FFA5H
SIO1A0
ADTP0
CSIIF10
5
0
_
1
FFA0H
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Figure 12-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2)
(c) Upon completion of transmission of 6 bytes
FFAFH
FFA5H
Transmit data 1 (T1)
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
Transmit data 5 (T5)
Transmit data 6 (T6)
SIO1A0
ADTP0
CSIIF10
0
0
FFA0H
(d) 7th byte transmission point
FFAFH
FFA5H
Transmit data 1 (T1)
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
Transmit data 5 (T5)
Transmit data 6 (T6)
SIO1A0
5
0
ADTP0
_
1
FFA0H
CSIIF10
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CHAPTER 12 SERIAL INTERFACE 1A0
(d) Automatic transmission/reception suspension and restart
Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE10) of serial
operation mode register 1A0 (CSIM1A0) to 0.
During 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE10) is set to 0. It is
suspended upon completion of 8-bit data transfer.
When suspended, bit 3 (TRF0) of automatic data transmit/receive control register 0 (ADTC0) is set to 0
after transfer of the 8th bit, and all the port pins used alternately as serial interface pins (P23/SCK10,
P24/SO10, P25/SI10) are set to the port mode.
During restart of transmission/reception, the remaining data can be transferred by setting CSIE10 to 1
and writing any data to serial I/O shift register 1A0 (SIO1A0).
Cautions 1. If the HALT instruction is executed during automatic transmission/reception,
transfer is suspended and the HALT mode is set even if 8-bit data is being
transferred.
2. When suspending automatic transmission/reception, do not change the operation
mode to 3-wire serial mode while TRF0 = 1.
Figure 12-16. Automatic Transmission/Reception Suspension and Restart
Suspend
CSIE10 = 0 (Suspended command)
Restart command
CSIE10 = 1, Write to SIO1A0
SCK10
SO10
SI10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSIE10: Bit 7 of serial operation mode register 1A0 (CSIM1A0)
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(4) Timing of interrupt request signal generation
The interrupt request signal is generated in synchronization with the timing shown in Table 12-2.
Table 12-2. Timing of Interrupt Request Signal Generation
Operation Mode
Master mode
Slave mode
Timing of Interrupt Request Signal
10th serial clock at end of transfer
Single mode
8th serial clock at end of transfer
Not generated
Repeat transmit mode
(5) Interval time of automatic transmission/reception
Because read/write to/from the buffer RAM using the automatic transmit/receive function is performed
asynchronously to the CPU processing, the interval time is dependent on the CPU processing of the timing of
the eighth rising of the serial clock and the set value of automatic data transmit/receive interval specification
register 0 (ADTI0). Whether the interval time is dependent on ADTI0 is selected by setting bit 7 (ADTI07) of
ADTI0. If ADTI07 is reset to 0, the interval time is 2/fSCK. If ADTI07 is set to 1, whichever is greater of the
interval time determined by the set contents of ADTI0 or the interval time (2/fSCK) determined by the CPU
processing is selected.
Figure 12-17 shows the interval time of automatic transmission/reception.
Remark fSCK: Serial clock frequency
Figure 12-17. Interval Time of Automatic Transmission/Reception
Interval
SCK10
SO10
SI10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSIIF10
The following expression must be satisfied to access the buffer RAM.
1 transfer cycle + Interval time ≥ Read access + Write access + CPU buffer RAM access (time)
In the case of a “high-speed CPU & low-speed SCK”, the interval time is not necessary. In the case of a
“low-speed CPU & high-speed SCK”, the interval time is necessary.
In this case, make sure that a sufficient interval time elapses, by using automatic data transmit/receive
interval specification register 0 (ADTI0), so that the above expression is satisfied.
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CHAPTER 13 LCD CONTROLLER/DRIVER
13.1 LCD Controller/Driver Functions
The functions of the LCD controller/driver of the µPD789489 Subseries are as follows.
(1) Automatic output of segment and common signals based on automatic display data memory read
(2) Two different display modes:
• 1/3 duty (1/3 bias)
• 1/4 duty (1/3 bias)
(3) Four different frame frequencies, selectable in each display mode
(4) 16 to 28 segment signal outputs (S0 to S15, S16 to S27Note
4 common signal outputs (COM0 to COM3)
Note Usable mask option or port function register
(5) Operation with subsystem clock is possible
(6) On-chip voltage booster
)
The maximum number of displayable pixels is shown in Table 13-1 below.
Table 13-1. Maximum Number of Display Pixels
Bias Method
1/3
Time Division
Common Signals
Used
Maximum Number
of Segments
Maximum Number of Display Pixels
3
4
COM0 to COM2
COM0 to COM3
28
84 (28 segments × 3 commons)Note 1
112 (28 segments × 4 commons)Note 2
Notes 1. The LCD panel of the figure
2. The LCD panel of the figure
consists of 9 rows with 3 segments per row.
consists of 14 rows with 2 segments per row.
13.2 LCD Controller/Driver Configuration
The LCD controller/driver includes the following hardware.
Table 13-2. Configuration of LCD Controller/Driver
Item
Configuration
Display outputs
Segment signals: 16 to 28
Common signals: 4 (COM0 to COM3)
Control registers
LCD display mode register 0 (LCDM0)
LCD clock control register 0 (LCDC0)
LCD voltage boost control register 0 (LCDVA0)
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The correspondence with the LCD display RAM is shown in Figure 13-1 below.
Figure 13-1. Correspondence with LCD Display RAM
Address
Bit
Segment
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
FA1BH
FA1AH
FA19H
FA18H
FA17H
FA16H
FA15H
FA14H
FA13H
FA12H
FA11H
FA10H
FA0FH
FA0EH
FA0DH
FA0CH
FA0BH
FA0AH
FA09H
FA08H
FA07H
FA06H
FA05H
FA04H
FA03H
FA02H
FA01H
FA00H
→ S27Note
→ S26Note
→ S25Note
→ S24Note
→ S23Note
→ S22Note
→ S21Note
→ S20Note
→ S19Note
→ S18Note
→ S17Note
→ S16Note
→ S15
→ S14
→ S13
→ S12
→ S11
→ S10
→ S9
→ S8
→ S7
→ S6
→ S5
→ S4
→ S3
→ S2
→ S1
→ S0
↑
↑
↑
↑
Common
COM3
COM2
COM1
COM0
Note Segments S16 to S27 are selected in 1-bit units via a mask option or port function register (segment
output pin/port pin).
Remark Bits 4 to 7 are fixed to 0.
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Figure 13-2. LCD Controller/Driver Block Diagram
Internal bus
LCD clock control
register 0 (LCDC0)
LCD display mode
register 0 (LCDM0)
LCD voltage boost
control register 0 (LCDVA0)
Display data memory
FA00H
7 6 5 4 3 2 1 0
FA0FH
7 6 5 4 3 2 1 0
FA10H
7 6 5 4 3 2 1 0
FA1BH
7 6 5 4 3 2 1 0
.........
.......
LCDC03 LCDC02 LCDC01 LCDC00
LCDON0
LIPS0 LCDM00
VAON0
GAIN
2
2
f
f
f
X
X
X
/25
/26
/27
f
LCD
Prescaler
f
XT
f
LCD
26
f
LCD
f
LCD
f
LCD
29
27
28
LCD
clock
selector
Timing
controller
LCDCL
........
........
........
........
3 2 1 0
Selector
3 2 1 0
Selector
3 2 1 0
Selector
3 2 1 0
Selector
VAON0
LCDON0
LCDON0
........
LCDON0
LCDON0
........
Clock
generator for
boosting
........
........
Segment voltage
........
........
........
........
controller
Booster circuit
Common voltage
controller
Segment
driver
Segment
driver
Segment
driver
Segment
driver
........
........
Common driver
. . . . . . . . .
. . . . . . . . .
CAPL
CAPH
VLC0
VLC2
VLC1
COM0 COM1 COM2 COM3
S15
S16
S27
S0
Selected by mask option
or port function register
CHAPTER 13 LCD CONTROLLER/DRIVER
13.3 Registers Controlling LCD Controller/Driver
The LCD controller/driver is controlled by the following three registers.
• LCD display mode register 0 (LCDM0)
• LCD clock control register 0 (LCDC0)
• LCD voltage boost control register 0 (LCDVA0)
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CHAPTER 13 LCD CONTROLLER/DRIVER
(1) LCD display mode register 0 (LCDM0)
LCDM0 specifies whether to enable display. It also specifies whether to enable booster circuit operation,
segment pin/common pin output, and the display mode.
LCDM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDM0 to 00H.
Figure 13-3. Format of LCD Display Mode Register 0
Symbol
<7> <6>
5
0
<4>
3
0
2
0
1
0
0
Address
FFB0H
After reset
00H
R/W
R/W
LCDM0 LCDON0 VAON0
LIPS0
LCDM00
LCDON0
LCD display enable/disable
0
1
Display off (all segment outputs are deselect signal outputs)
Display on
VAON0
Booster circuit operation enable/disable
0
1
No internal voltage boosting
Internal voltage boosting enabled
LIPS0
Segment pin/common pin output controlNote
0
1
Output ground level to segment/common pin
Output select level to segment pin and LCD waveform to common pin
LCD controller/driver display mode selection
Number of time slices
LCDM00
Bias mode
4
3
1/3
1/3
0
1
Note When the LCD display panel is not used, set VAON0 and LIPS0 to 0 to reduce power consumption.
Cautions 1. Bits 1 to 3 and 5 must be set to 0.
2. When operating VAON0, follow the procedure described below.
A. To stop voltage boosting after switching display status from on to off:
1) Set to display off status by setting LCDON0 = 0.
2) Disable outputs of all the segment buffers and common buffers by setting LIPS0 = 0.
3) Stop voltage boosting by setting VAON0= 0.
B. To stop voltage boosting during display on status:
Setting prohibited. Be sure to stop voltage boosting after setting display off.
C. To set display on from voltage boosting stop status:
1) Start voltage boosting by setting VAON0 = 1, then wait for the voltage boost wait time
(tVAWAIT) (refer to CHAPTER 22 ELECTRICAL SPECIFICATION).
2) Set all the segment buffers and common buffers to non-display output status by
setting LIPS0 = 1.
3) Set display on by setting LCDON0 = 1.
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(2) LCD clock control register 0 (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the
LCD clock and number of time slices.
LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDC0 to 00H.
Figure 13-4. Format of LCD Clock Control Register 0
Symbol
LCDC0
7
0
6
0
5
0
4
3
2
1
0
Address
FFB2H
After reset
00H
R/W
R/W
0
LCDC03 LCDC02 LCDC01 LCDC00
LCDC03 LCDC02
LCD source clock (fLCD) selectionNote
0
0
1
1
0
1
0
1
f
f
f
f
XT
(32.768 kHz)
X
X
X
/25 (156.3 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
LCDC01 LCDC00
LCD clock (LCDCL) selection
0
0
1
1
0
1
0
1
f
f
f
f
LCD/26
LCD/27
LCD/28
LCD/29
Note Specify an LCD source clock (fLCD) frequency of at least 32 kHz.
Cautions 1. Bits 4 to 7 must be set to 0.
2. Before changing the LCDC0 setting, be sure to stop voltage boosting (VAON0 = 0).
3. Set the frame frequency to 128 Hz or lower.
Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
As an example, Table 13-3 lists the frame frequencies used when fXT (32.768 kHz) is supplied as the LCD
source clock (fLCD).
Table 13-3. Frame Frequencies (Hz)
LCD Clock (LCDCL)
fXT/29
fXT/28
fXT/27
fXT/26
(64 Hz)
(128 Hz)
(256 Hz)
(512 Hz)
Time Slots
3
4
21
16
43
32
85
64
171Note
128
Note This setting is prohibited because it causes the frame frequency to exceed 128 Hz.
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CHAPTER 13 LCD CONTROLLER/DRIVER
(3) LCD voltage boost control register 0 (LCDVA0)
LCDVA0 controls the voltage boost level during the voltage boost operation.
LCDVA0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDVA0 to 00H.
Figure 13-5. Format of LCD Voltage Boost Control Register 0
Symbol
7
0
6
0
5
0
4
0
3
0
2
0
1
0
<0>
Address
FFB3H
After reset
00H
R/W
R/W
LCDVA0
GAIN
GAIN
Reference voltage (VLC2) level selectionNote
0
1
1.5 V (specification of the LCD panel used is 4.5 V.)
1.0 V (specification of the LCD panel used is 3 V.)
Note Select the settings according to the specifications of the LCD panel that is used.
Caution Before changing the LCDVA0 setting, be sure to stop voltage boosting (VAON0 = 0).
Remark The TYP. value is indicated as the reference voltage (VLC2) value.
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13.4 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
<1> Set the LCD clock using LCD clock control register 0 (LCDC0).
<2> Set the voltage boost level using LCD voltage boost control register 0 (LCDVA0).
GAIN = 0: VLC0 = 4.5 V, VLC1 = 3 V, VLC2 = 1. 5 V
GAIN = 1: VLC0 = 3 V, VLC1 = 2 V, VLC2 = 1 V
<3> Set the time slice using LCDM00 (bit 0 of LCD display mode register 0 (LCDM0)).
<4> Enable voltage boost by setting VAON0 (bit 6 of LCDM0) (VAON0 = 1).
<5> Wait for the voltage boost wait time (tVAWAIT) after setting VAON0 (refer to CHAPTER 22 ELECTRICAL
SPECIFICATION).
<6> Set LIPS0 (bit 4 of LCDM0) (LIPS0 = 1) and output the deselect potential.
<7> Start output corresponding to each data memory by setting LCDON0 (bit 7 of LCDM0) (LCDON0 = 1).
13.5 LCD Display Data Memory
The LCD display data memory is mapped at addresses FA00H to FA1BH. Data in the LCD display data memory
can be displayed on the LCD panel using the LCD controller/driver.
Figure 13-6 shows the relationship between the contents of the LCD display data memory and the
segment/common outputs.
That part of the display data memory which is not used for display can be used as ordinary RAM.
Figure 13-6. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
(When Using S16 to S27)
b7
b6
b5
b4
b3
b2
b1
b0
Address
FA1BH
S27
S26
S25
S24
FA1AH
FA19H
FA18H
FA02H
FA01H
FA00H
S2
S1
S0
COM3 COM2 COM1 COM0
Caution No memory has been installed as the higher 4 bits of the LCD display data memory. Be sure to
set them to 0.
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CHAPTER 13 LCD CONTROLLER/DRIVER
13.6 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and
segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). It turns off when the potential
difference becomes lower than VLCD.
Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it. To avoid this
problem, this LCD panel is driven with AC voltage.
(1) Common signals
Each common signal is selected sequentially according to the specified number of time slots at the timing
listed in Table 13-4. In the static display mode, the same signal is output commonly to COM0 to COM3.
In the three-time-slice mode, leave the COM3 pin open.
Table 13-4. COM Signals
COM Signal
COM0
COM1
COM2
COM3
Number of Time Slices
Three-time-slice mode
Four-time-slice mode
Open
(2) Segment signals
The segment signals correspond to LCD display data memory. Bits 0, 1, 2, and 3 of each byte are read in
synchronization with COM0, COM1, COM2, and COM3, respectively. If the contents of each bit are 1, that
bit is converted to the select voltage, and if 0, it is converted to the deselect voltage. The conversion results
are output to the segment pins.
Check, with the information given above, what combination of the front-surface electrodes (corresponding to
the segment signals) and the rear-surface electrodes (corresponding to the common signals) forms display
patterns in the LCD display data memory, and write the bit data that corresponds to the desired display
pattern on a one-to-one basis.
Bit 3 of the LCD display data memory is not used for LCD display in the three-time-slice mode. So this bit
can be used for purposes other than display.
LCD display data memory bits 4 to 7 are fixed to 0.
(3) Output waveforms of common and segment signals
When both common and segment signals are at the select voltage, a display-on voltage of VLCD is obtained.
The other combinations of the signals correspond to the display-off voltage.
Figure 13-7 shows the common signal waveforms, and Figure 13-8 shows the voltages and phases of the common
and segment signals.
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CHAPTER 13 LCD CONTROLLER/DRIVER
Figure 13-7. Common Signal Waveforms
V
V
V
V
LC0
LC1
LC2
SS
COMn
V
LCD
(Three-time-slice mode)
T
F
= 3 × T
V
V
V
V
LC0
COMn
LC1
LC2
SS
V
LCD
(Four-time-slice mode)
TF = 4 × T
T: One LCD clock period
TF: Frame frequency
Figure 13-8. Voltages and Phases of Common and Segment Signals
Select
Deselect
V
LC0
V
LC1
LC2
V
V
LCD
Common signal
Segment signal
V
V
SS
V
V
V
LC0
LC1
LC2
LCD
V
SS
T
T
T: One LCD clock period
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CHAPTER 13 LCD CONTROLLER/DRIVER
13.7 Display Modes
13.7.1 Three-time-slice display example
Figure 13-10 shows how a nine-digit LCD panel having the display pattern shown in Figure 13-9 is connected to
the segment signals (S0 to S26) and the common signals (COM0 to COM2) of the µPD789489 Subseries chip. This
example displays the data "123456.789" in the LCD panel. The contents of the display data memory (addresses
FA00H to FA1AH) correspond to this display.
The following description focuses on numeral "6." ( ) displayed as the fourth digit from the right. To display "6." in
the LCD panel, it is necessary to apply the select or deselect voltage to the S9 to S11 pins according to Table 13-5 at
the timing of the common signals COM0 to COM2; see Figure 13-9 for the relationship between the segment signals
and LCD segments.
Table 13-5. Select and Deselect Voltages (COM0 to COM2)
Segment
S9
S10
S11
Common
COM0
Deselect
Select
Select
Select
Select
Select
Select
−
COM1
COM2
Select
According to Table 13-5, it is determined that the display data memory location (FA09H) that corresponds to S9
must contain x110.
Figure 13-11 shows an example of LCD drive waveforms between the S9 signal and each common signal. When
the select voltage is applied to S9 at the timing of COM1 or COM2, an alternate rectangle waveform, +VLCD/-VLCD, is
generated to turn on the corresponding LCD segment.
Figure 13-9. Three-Time-Slice LCD Display Pattern and Electrode Connections
COM0
S3n+1
S
3n+2
S
3n
COM1
COM2
Remark n = 0 to 8
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CHAPTER 13 LCD CONTROLLER/DRIVER
Figure 13-10. Example of Connecting Three-Time-Slice LCD Panel
COM 3
Open
COM 2
COM 1
COM 0
S 0
FA00H
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
S 16
FA10H
S 17
S 18
S 19
S 20
S 21
S 22
S 23
S 24
S 25
S 26
1
2
3
4
5
6
7
8
9
A
x’: Can be used to store any data because there is no corresponding segment in the LCD panel.
×: Can always be used to store any data because the three-time-slice mode is being used.
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CHAPTER 13 LCD CONTROLLER/DRIVER
Figure 13-11. Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
T
F
V
V
V
V
LC0
LC1
LC2
SS
COM0
COM1
COM2
S9
VLC0
VLC1
VLC2
VSS
VLC0
VLC1
VLC2
VSS
VLC0
VLC1
VLC2
VSS
+VLCD
+1/3VLCD
0
COM0-S9
COM1-S9
COM2-S9
-1/3VLCD
-VLCD
+VLCD
+1/3VLCD
0
-1/3VLCD
-VLCD
+VLCD
+1/3VLCD
0
-1/3VLCD
-VLCD
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CHAPTER 13 LCD CONTROLLER/DRIVER
13.7.2 Four-time-slice display example
Figure 13-13 shows how a 14-digit LCD panel having the display pattern shown in Figure 13-12 is connected to the
segment signals (S0 to S27) and the common signals (COM0 to COM3) of the µPD789489 Subseries chip. This
example displays the data "123456.78901234" in the LCD panel. The contents of the display data memory
(addresses FA00H to FA1BH) correspond to this display.
The following description focuses on numeral "6." ( ) displayed as the ninth digit from the right. To display "6." in
the LCD panel, it is necessary to apply the select or deselect voltage to the S16 and S17 pins according to Table 13-6
at the timing of the common signals COM0 to COM3; see Figure 13-12 for the relationship between the segment
signals and LCD segments.
Table 13-6. Select and Deselect Voltages (COM0 to COM3)
Segment
S16
S17
Common
COM0
COM1
COM2
COM3
Select
Deselect
Select
Select
Select
Select
Select
Select
According to Table 13-7, it is determined that the display data memory location (FA10H) that corresponds to S16
must contain 1101.
Figure 13-14 shows examples of LCD drive waveforms between the S16 signal and the common signals. When
the select voltage is applied to S16 at the timing of COM0, an alternate rectangle waveform, +VLCD/-VLCD, is generated
to turn on the corresponding LCD segment.
Figure 13-12. Four-Time-Slice LCD Display Pattern and Electrode Connections
S2n
COM0
COM2
COM1
COM3
S2n+1
Remark n = 0 to 13
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CHAPTER 13 LCD CONTROLLER/DRIVER
Figure 13-13. Example of Connecting Four-Time-Slice LCD Panel
COM 3
COM 2
COM 1
COM 0
S 0
FA00H
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
S 16
FA10H
S 17
S 18
S 19
S 20
S 21
S 22
S 23
S 24
S 25
S 26
S 27
1
2
3
4
5
6
7
8
9
A
B
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CHAPTER 13 LCD CONTROLLER/DRIVER
Figure 13-14. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
T
F
V
V
V
V
LC0
LC1
LC2
SS
COM0
COM1
COM2
COM3
S16
VLC0
VLC1
VLC2
VSS
VLC0
VLC1
VLC2
VSS
VLC0
VLC1
VLC2
VSS
VLC0
VLC1
VLC2
VSS
+VLCD
+1/3VLCD
0
COM0-S16
-1/3VLCD
-VLCD
+VLCD
+1/3VLCD
0
COM1-S16
-1/3VLCD
-VLCD
Remark The waveforms of COM2-S16 and COM3-S16 are omitted.
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CHAPTER 13 LCD CONTROLLER/DRIVER
13.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
The µPD789489 Subseries contains a booster circuit (×3 only) to generate a supply voltage to drive the LCD. The
internal LCD reference voltage is output from the VLC2 pin. A voltage two times higher than that on VLC2 is output from
the VLC1 pin and a voltage three times higher than that on VLC2 is output from the VLC0 pin.
The LCD reference voltage (VLC2) can be specified by setting LCD boost control register 0 (LCDVA0).
The µPD789489 Subseries requires an external capacitor (recommended value: 0.47 µF) because it employs a
capacitance division method to generate a supply voltage to drive the LCD.
Table 13-7. Output Voltages of VLC0 to VLC2 Pins
LCDVA0
GAIN = 0
GAIN = 1
LCD drive power supply pin
VLC0
4.5 V
3.0 V
VLC1
3.0 V
1.5 V
2.0 V
1.0 V
VLC2 (LCD reference voltage)
Cautions 1. When using the LCD function, do not leave the VLC0, VLC1, and VLC2 pins open. Refer to
Figure 13-15 for connection.
2. Since the LCD drive voltage is separate from the main power supply, a constant voltage
can be supplied regardless of VDD fluctuation.
Figure 13-15. Example of Connecting Pins for LCD Driver
V
V
V
LC0
LC1
LC2
C2
C3
C4
CAPH
CAPL
C1
C1 = C2 = C3 = C4 = 0.47
External pin
µF
Remark Use a capacitor with as little leakage as possible.
In addition, make C1 a nonpolar capacitor.
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CHAPTER 14 MULTIPLIER
14.1 Multiplier Function
The multiplier has the following function.
• Calculation of 8 bits × 8 bits = 16 bits
14.2 Multiplier Configuration
(1) 16-bit multiplication result storage register 0 (MUL0)
This register stores the 16-bit result of multiplication.
This register holds the result of multiplication after 16 CPU clocks have elapsed.
MUL0 is set with a 16-bit memory manipulation instruction.
RESET input makes this register undefined.
Caution Although this register is manipulated with a 16-bit memory manipulation instruction, it can
also be manipulated with an 8-bit memory manipulation instruction. When using an 8-bit
memory manipulation instruction, however, access the register by means of direct
addressing.
(2) Multiplication data registers A and B (MRA0 and MRB0)
These are 8-bit multiplication data storage registers. The multiplier multiplies the values of MRA0 and MRB0.
MRA0 and MRB0 are set with an 8-bit memory manipulation instructions.
RESET input makes these registers undefined.
Figure 14-1 shows the block diagram of the multiplier.
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CHAPTER 14 MULTIPLIER
Figure 14-1. Block Diagram of Multiplier
Internal bus
Multiplication data
register A (MRA0)
Multiplication data
register B (MRB0)
Counter value
CPU clock
Selector
3-bit counter
Start Clear
3
16-bit
adder
16-bit multiplication result
storage register 0 (Master) (MUL0)
16-bit multiplication result
storage register 0 (Slave)
Reset
MULST0
Multiplier control
register 0 (MULC0)
Internal bus
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CHAPTER 14 MULTIPLIER
14.3 Multiplier Control Register
The multiplier is controlled by the following register.
• Multiplier control register 0 (MULC0)
(1) Multiplier control register 0 (MULC0)
MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier.
MULC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 14-2. Format of Multiplier Control Register 0
Symbol
MULC0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
<0>
Address
FFD2H
After reset
00H
R/W
R/W
MULST0
MULST0
Multiplier operation start control bit
Operating status of multiplier
Operation stopped
Operation in progress
0
1
Stop operation after resetting counter to 0.
Enable operation
Caution Be sure to set bits 1 to 7 to 0.
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CHAPTER 14 MULTIPLIER
14.4 Multiplier Operation
The multiplier of the µPD789489 Subseries can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 14-3
shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H.
<1> Counting is started by setting MULST0.
<2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter value
is incremented by one.
<3> If MULST0 is cleared when the counter value is 111B, the operation is stopped. At this time, MUL0 holds the
data.
<4> While MULST0 is low, the counter and slave are cleared.
Figure 14-3. Multiplier Operation Timing (Example of AAH × D3H)
CPU clock
MRA0
MRB0
AA
D3
MULST0
Counter
000B
001B 010B 011B 100B 101B 110B 111B
0154 0000 0000 0AA0 0000 2A80 5500
00AA 01FE 01FE 01FE 0C9E 0C9E 371E
00AA 01FE 01FE 01FE 0C9E 0C9E 371E
000B
00AA
00AA
Selector output
MUL0
(Master)
8C1E
0000
0000
(Slave)
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CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY)
15.1 Remote Controller Receiver Functions
The remote controller receiver uses the following remote controller modes.
• Type A reception mode … Guide pulse (half clock) provided
15.2 Remote Controller Receiver Configuration
The remote controller receiver includes the following hardware.
Table 15-1. Remote Controller Receiver Configuration
Item
Configuration
Remote controller receive shift register (RMSR)
Registers
Remote controller receive data register (RMDR)
Remote controller shift register receive counter register (RMSCR)
Remote controller receive GPHS compare register (RMGPHS)
Remote controller receive GPHL compare register (RMGPHL)
Remote controller receive DLS compare register (RMDLS)
Remote controller receive DLL compare register (RMDLL)
Remote controller receive DH0S compare register (RMDH0S)
Remote controller receive DH0L compare register (RMDH0L)
Remote controller receive DH1S compare register (RMDH1S)
Remote controller receive DH1L compare register (RMDH1L)
Remote controller receive end width select register (RMER)
Control register
Remote controller receive control register (RMCN)
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Figure 15-1. Block Diagram of Remote Controller Receiver
Noise
canceler
Edge
detection
INTRIN
RIN/P34
Remote controller receive
data register (RMDR)
NCW
RMEN
RMIN
Clock
counter
Remote controller receive
shift register (RMSR)
Remote
controller shift
register receive
counter register
(RMSCR)
Compare register
RMGPHL
RMGPHS
INTDFULL
f
X
/26
/27
RMDLL
RMDLS
f
X
RMDH0L
RMDH0S
f
/28
X
INTGP
RMDH1S RMDH1L
f
XT
INTRERR
INTREND
End-width select register (RMER)
Selection control
signal
NCW
RMEN
RMIN
RMCK0
RMCK1
PRSEN
Remote controller receive control register (RMCN)
Internal bus
(1) Remote controller receive shift register (RMSR)
This is an 8-bit register for reception of remote controller data.
Data is stored in bit 7 first. Each time new data is stored, the stored data is shifted to the lower bits. Therefore,
the latest data is stored in bit 7, and the first data is stored in bit 0.
RMSR is read with an 8-bit memory manipulation instruction.
RESET input sets RMSR to 00H.
Also, RMSR is cleared to 00H under any of the following conditions.
• Remote controller stops operation (RMEN = 0).
• Error is detected (INTRERR is generated).
• INTDFULL is generated.
• RMSR is read after INTREND has been generated.
Caution Reading RMSR is disabled during remote controller reception. Complete reception, then
read RMSR. When the reading operation is complete, RMSR is cleared. Therefore, values
once read are not guaranteed.
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(2) Remote controller receive data register (RMDR)
This register holds the remote controller reception data. When the remote controller receive shift register
(RMSR) overflows, the data in RMSR is transferred to RMDR. Bit 7 stores the last data, and bit 0 stores the
first data. INTDFULL is generated at the same time as data is transferred from RMSR to RMDR.
RMDR is read with an 8-bit memory manipulation instruction.
RESET input sets RMDR to 00H.
When the remote controller operation is disabled (RMEN = 0), RMDR is cleared to 00H.
Caution When INTDFULL has been generated, read RMDR before the next 8-bit data is received. If the
next INTDFULL is generated before the read operation is complete, RMDR is overwritten.
(3) Remote controller shift register receive counter register (RMSCR)
This is an 8-bit counter register used to indicate the number of valid bits remaining in the remote controller
receive shift register (RMSR) when remote controller reception is complete (INTREND is generated). Reading
the values of this register allows confirmation of the number of bits, even if the received data is in a format
other than an integral multiple of 8 bits.
RMSCR is read with an 8-bit memory manipulation instruction.
RESET input sets RMSCR to 00H.
It is cleared to 00H under any of the following conditions.
• Remote controller stops operation (RMEN = 0).
• Error is detected (INTRERR is generated).
• RMSR is read after INTREND has been generated.
Caution When INTREND has been generated, immediately read RMSCR before reading RMSR. If
reading occurs at another timing, the value is not guaranteed.
Figure 15-2. Operation Examples of RMSR, RMSCR, and RMDR Registers
When Receiving 1010101011111111B (16 Bits)
RMSR
RMSCR
RMDR
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
After reset
Receiving 1 bit
Receiving 2 bits
Receiving 3 bits
…
00H
01H
02H
03H
…
00000000B
00000000B
00000000B
00000000B
…
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
…
1
…
0
…
1
…
0
…
1
…
0
…
1
…
0
Receiving 7 bits
07H
00000000B
Receiving 8 bits
↓
RMDR transfer
0
↓
0
1
↓
0
0
↓
0
1
↓
0
0
↓
0
1
↓
0
0
↓
0
1
↓
0
00H
↓
00H
00000000B
↓
01010101B
Receiving 9 bits
Receiving 10 bits
…
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
01H
02H
…
01010101B
01010101B
…
…
…
…
…
…
…
…
…
Receiving 16 bits
↓
RMDR transfer
1
↓
0
1
↓
0
1
↓
0
1
↓
0
1
↓
0
1
↓
0
1
↓
0
1
↓
0
00H
↓
00H
01010101B
↓
11111111B
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(4) Remote controller receive GPHS compare register (RMGPHS)
This register is used to detect the high level of a remote controller guide pulse (short side).
RMGPHS is set with an 8-bit memory manipulation instruction.
RESET input sets RMGPHS to 00H.
(5) Remote controller receive GPHL compare register (RMGPHL)
This register is used to detect the high level of a remote controller guide pulse (long side).
RMGPHL is set with an 8-bit memory manipulation instruction.
RESET input sets RMGPHL to 00H.
RIN
Counter value
If RMGPHS ≤ counter value < RMGPHL
Guide pulse
is satisfied, it is assumed that the high
level of the guide pulse has been
successfully received.
RMGPHS register value
RMGPHL register value
Allowable
range
(6) Remote controller DLS compare register (RMDLS)
This register is used to detect the low level of a remote controller data (short side).
RMDLS is set with an 8-bit memory manipulation instruction.
RESET input sets RMDLS to 00H.
(7) Remote controller receive DLL compare register (RMDLL)
This register is used to detect the low level of a remote controller data (long side).
RMDLL is set with an 8-bit memory manipulation instruction.
RESET input sets RMDLL to 00H.
RIN
Counter value
Data 0/data 1
If RMDLS ≤ counter value < RMDLL
is satisfied, it is assumed that the low level
of data 0 or data 1 has been successfully
received.
RMDLS register value
RMDLL register value
Allowable
range
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(8) Remote controller receive DH0S compare register (RMDH0S)
This register is used to detect the high level of remote controller data 0 (short side).
RMDH0S is set with an 8-bit memory manipulation instruction.
RESET input sets RMDH0S to 00H.
(9) Remote controller receive DH0L compare register (RMDH0L)
This register is used to detect the high level of remote controller data 0 (long side).
RMDH0L is set with an 8-bit memory manipulation instruction.
RESET input sets RMDH0L to 00H.
RIN
Counter value
If RMDH0S ≤ counter value < RMDH0L
Data 0
is satisfied, it is assumed that the high level
of data 0 has been successfully received, and
therefore RMSR receives the data.
RMDH0S register value
RMDH0L register value
Allowable
range
(10)Remote controller receive DH1S compare register (RMDH1S)
This register is used to detect the high level of remote controller data 1 (short side).
RMDH1S is set with an 8-bit memory manipulation instruction.
RESET input sets RMDH1S to 00H.
(11) Remote controller receive DH1L compare register (RMDH1L)
This register is used to detect the high level of remote controller data 1 (long side).
RMDH1L is set with an 8-bit memory manipulation instruction.
RESET input sets RMDH1L to 00H.
RIN
Counter value
If RMDH1S ≤ counter value < RMDH1L is
Data 1
satisfied, it is assumed that the high level of
data 1 has been successfully received, and
therefore RMSR receives the data.
RMDH1S register value
RMDH1L register value
Allowable
range
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(12)Remote controller receive end-width select register (RMER)
This register determines the interval between the timing at which the INTREND signal is output.
RMER is set with an 8-bit memory manipulation instruction.
RESET input sets RMER to 00H.
RIN
Data
Counter value = RMER
RMDLL
Counter
INTREND
Caution For RMER and all the remote controller receive compare registers (RMGPHS, RMGPHL,
RMDLS, RMDLL, RMDH0S, RMDH0L, RMDH1S, and RMDH1L), disable remote controller
reception (bit 7 (RMEN) of the remote controller receive control register (RMCN) = 0) first,
and then change the value.
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15.3 Registers to Control Remote Controller Receiver
The remote controller receiver is controlled by the following register.
• Remote controller receive control register (RMCN)
(1) Remote controller receive control register (RMCN)
This register is used to enable/disable remote controller reception and to set the noise elimination width, clock
internal division, input invert signal, and source clock.
RMCN is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets RMCN to 00H.
Figure 15-3. Format of Remote Controller Receive Control Register (1/2)
Symbol
RMCN
7
6
5
4
3
0
2
0
1
0
Address After reset
FF60H 00H
R/W
R/W
RMEN
NCW
PRSEN
RMIN
RMCK1 RMCK0
RMEN
Control of remote controller receive operation
0
1
Disable remote controller reception
Enable remote controller reception
NCW
Noise elimination width control signal
Internal clock division control signal
0
1
Eliminate noise less than 1/fPRS
Eliminate noise less than 2/fPRS
PRSEN
0
1
Clock not divided internally (fPRS = fREM)
Clock internally divided into two (fPRS = fREM/2)
RMIN
Remote controller input invert signal
0
1
Input positive phase
Input negative phase
Cautions 1. Always set bits 2 and 3 to 0.
2. To change the values of NCW, PRSEN, RMIN, RMCK1, and RMCK0, disable remote
controller reception (RMEN = 0) first.
Remarks 1. fREM: Source clock of remote controller counter (selected by bits 0 and 1 (RMCK0 and RMCK1)
2. fPRS: Operation clock inside remote controller receiver
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Figure 15-3. Format of Remote Controller Receive Control Register (2/2)
Symbol
RMCN
7
6
5
4
3
0
2
0
1
0
Address After reset
FF60H 00H
R/W
R/W
RMEN
NCW
PRSEN
RMIN
RMCK1 RMCK0
RMCK1 RMCK0
Selection of source clock (fREM) of remote controller counter
0
0
1
1
0
1
0
1
fX/26 (625 kHz)
fX/27 (313 kHz)
fX/28 (156 kHz)
fXT (32.768 kHz)
Cautions 1. Always set bits 2 and 3 to 0.
2. To change the values of NCW, PRSEN, RMIN, RMCK1, and RMCK0, disable remote
controller reception (RMEN = 0) first.
Remarks 1. fX: Oscillation frequency of main system clock
2. fXT: Oscillation frequency of subsystem clock
3. The parenthesized values apply to operation at fX = 4.0 MHz and fXT = 32.768 kHz.
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15.4 Operation of Remote Controller Receiver
The following remote controller reception mode is used for this remote controller receiver.
• Type A reception mode with guide pulse (half clock)
15.4.1 Format of type A reception mode
Figure 15-4 shows the data format for type A.
Figure 15-4. Example of Type A Data Format
0.6 ms
1.2 ms
1.8 ms
2.4 ms
RIN
Data
“0”
Data
“1”
Data
“1”
Data
“0”
Data
“0”
Data
“0”
Data
“0”
Data
“0”
Data
“0”
Guide pulse
INTRIN
INTGP
INTDFULL
INTREND
RMDLL
RMER
15.4.2 Operation flow of type A reception mode
Figure 15-5 shows the operation flow.
Cautions 1. When INTRERR is generated, RMSR and RMSCR are automatically cleared immediately.
2. When data has been set to all the bits of RMSR, the following processing is automatically
performed.
• The value of RMSR is transferred to RMDR.
• INTDFULL is generated.
• RMSR is cleared.
RMDR must then be read before the next data is set to all the bits of RMSR.
3. When INTREND has been generated, read RMSCR first followed by RMSR.
When RMSR has been read, RMSCR and RMSR are automatically cleared.
If INTREND is generated, the next data cannot be received until RMSR is read.
4. RMSR, RMSCR, and RMDR are cleared simultaneously to operation termination (RMEN = 0).
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Figure 15-5. Operation Flow of Type A Reception Mode
Start
Set compare registers
Operation enabled (RMEN = 1)
No
Guide pulse high
level width OK?
Yes
Generate INTGP
No
No
Data low level
width OK?
Generate INTRERR
Read RMDRNote
Yes
Clear RMSR and RMSCR
Data high level
width OK?
No
Longer than END
interval?
Yes
Set data to RMSR
Yes
Generate INTREND
No
Set data to all bits
of RMSR OK?
Read RMSCR
Yes
RMSR → RMDR
Generate INTDFULL
Clear RMSR
Read RMSR
Clear RMSR and RMSCR
Process received data
No
Receive operation
completed
Yes
: Software processing
(User executes via program)
Terminate operation (RMEN = 0)
: Hardware processing
(Macro automatically performs)
Clear RMSR, RMSCR,
and RMDR
END
Note Read RMDR before data has been set to all the bits of RMSR.
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15.4.3 Timing
Operation varies depending on the positions of the RIN input waveform below.
(1) Guide pulse high level width determination
<1>
<2>
<3>
RIN
RIN
RIN
RMGPHS
RMGPHL
Allowable
range
Relationship Between
RMGPHS/RMGPHL/Counter
Position of Waveform
<1>: Short
Corresponding Operation
Counter < PMGPHS
Measuring guide pulse high-level width is started
from the next rising edge.
PMGPHS ≤ counter < PMGPHL
PMGPHL ≤ counter
<2>: Within the range
<3>: Long
INTGP is generated.
Data measurement is started.
Measuring guide pulse high-level width is started
from the next rising edge.
(2) Data low level width determination
<1>
<2>
<3>
RIN
RIN
RIN
RMDLS
RMDLL
Allowable
range
∆
Relationship Between RMDLS/RMDLL/Counter
Position of Waveform
<1>: Short
Corresponding Operation
Counter < RMDLS
Error interrupt INTRERR is generated.
Measuring guide pulse high-level width is started.
RMDLS ≤ counter < RMDLL
RMDLL ≤ counter
<2>: Within the range
<3>: Long
Measuring data high-level width is started.
Measuring the end width is started from the ∆ point.
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(3) Data high level width determination
<1>
<3>
<2>
<5>
<4>
RIN
RIN
RIN
RIN
RIN
RMDH0S
RMDH0L
RMDH1S
RMDH1L
Allowable
range
Allowable
range
∆
Relationship Between
RMDH0S/RMDH0L/RMDH1S/RMDH1L/Counter
Position of Waveform
<1>: Short
Corresponding Operation
Counter < RMDH0S
Error interrupt INTRERR is generated.
Measuring the guide pulse high-level width is started
at the next rising edge.
RMDH0S ≤ counter < RMDH0L
RMDH0L ≤ counter < RMDH1S
<2>: Within the range
Data 0 is received.
Measuring data low-level width is started.
<3>: Outside of the
range
Error interrupt INTRERR is generated.
Measuring the guide pulse high-level width is started
at the next rising edge.
RMDH1S ≤ counter < RMDH1L
RMDH1L ≤ counter
<4>: Within the range
<5>: Long
Data 1 is received.
Measuring the data low-level width is started.
Error interrupt INTRERR is generated at the ∆ point.
Measuring the guide pulse high-level width is started
at the next rising edge.
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(4) End width determination
<1>
<2>
RIN
RIN
RMDLS
RMDLL
RMER
∆
Relationship Between RMER/Counter
Position of Waveform
Corresponding Operation
Counter < RMER
<1>: Short
Error interrupt INTRERR is generated.
Measuring the guide pulse high-level width is started.
RMER ≤ counter
<2>: Long
INTREND is generated at the ∆ point.
Reception via circuit stops until RMSR is read.
15.4.4 Compare register setting
This remote controller receiver has the following 9 types of compare registers.
• Remote controller receive GPHS compare register (RMGPHS)
• Remote controller receive GPHL compare register (RMGPHL)
• Remote controller receive DLS compare register (RMDLS)
• Remote controller receive DLL compare register (RMDLL)
• Remote controller receive DH0S compare register (RMDH0S)
• Remote controller receive DH0L compare register (RMDH0L)
• Remote controller receive DH1S compare register (RMDH1S)
• Remote controller receive DH1L compare register (RMDH1L)
• Remote controller receive end width select register (RMER)
Use formulas (1) to (3) below to set the value of each compare register.
Making allowances for tolerance enables a normal reception operation, even if the RIN input waveform is RIN_1 or
RIN_2 shown in Figure 15-6 due to the effect of noise.
Cautions 1. Always set each compare register while remote controller reception is disabled (RMEN = 0).
2. Set the set values so that they satisfy all the following three conditions.
• RMGPHS < RMGPHL
• RMDLS < RMDLL
• RMDH0S < RMDH0L ≤ RMDH1S < RMDH1L
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Figure 15-6. Setting Example (Where n1 = 1, n2 = 2)
Clock
RIN
T
W
T
WE
RMGPHS/RMDH0S/RMDH1S
RMDLS
RMER
RMDLL
RMGPHL/RMDH0L/RMDH1L
n1
RIN_1
RIN_2
n2
(1) Formula for RMGPHS, RMDLS, RMDH0S, and RMDH1S
TW × (1 − a/100)
− 2 − n1
1/fPRS
INT
(2) Formula for RMGPHL, RMDLL, RMDH0L, and RMDH1L
TW × (1 + a/100)
+ 1 + n2
1/fPRS
INT
(3) Formula for RMER
TWE × (1 − a/100)
− 1
1/fPRS
INT
TW:
Width of RIN input waveform
1/fPRS: Width of internal operation clock cycle after division control by PRSEN
a:
[ ] INT:
Tolerance (%)
Round down the fractional portion of the value produced by the formula in the brackets.
n1, n2: Variables of waveform change caused by noiseNote1
TWE:
End width of RIN inputNote2
Notes 1. Set the values of n1 and n2 as required to meet the user′s system specification.
2. This end width is counted after RMDLL.
The low-level width actually required after the last data has been received is as follows:
(RMDLL + 1 + RMER + 1) × (width of internal operation clock cycle after division control by PRSEN)
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15.4.5 Error interrupt generation timing
After the guide pulse has been detected normally, the INTRERR signal is generated under any of the following
conditions.
• Counter < RMDLS at the rising edge of RIN
• RMDLL ≤ counter and counter after RMDLL < RMER at the rising edge of RIN
• Counter < RMDH0S at the falling edge of RIN
• RMDH0L ≤ counter < RMDH1S at the falling edge of RIN
• Register changes so that RMDH1L ≤ counter while RIN is at high level
The INTRERR signal is not generated until the guide pulse is detected.
Once the INTRERR signal has been generated, it will not be generated again until the next guide pulse is detected.
The generation timing of the INTRERR signal is shown in Figure 15-7.
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Figure 15-7. Generation Timing of INTRERR Signal
RMDLL
RMDH1L
RMDH1S
RMDH0L
RMGPHL
RMGPHS
RMER
RMDLS
RMDH0S
RIN
Basic waveform
INTRERR
RIN
Example 1
Counter < RMGPHS
→ INTRERR is not generated.
INTRERR
RIN
Example 2
RMGPHL ≤ counter
→ INTRERR is not generated.
INTRERR
RIN
Example 3
Counter < RMDLS
→ INTRERR is generated.
INTRERR
Example 4
RIN
RMDLL ≤ counter and counter < RMER
→ INTRERR is generated.
INTRERR
RIN
INTRERR
INTREND
Example 5
RMDLL ≤ counter and
RMER ≤ counter
→ INTRERR is not generated.
→ INTREND is generated.
Example 6
RIN
Counter < RMDH0S
→ INTRERR is generated.
INTRERR
RIN
Example 7
RMDH0L ≤ counter ≤ RMDH1S
→ INTRERR is generated.
INTRERR
RIN
Example 8
RMDH1L ≤ counter
→ INTRERR is generated.
INTRERR
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15.4.6 Noise elimination
This remote controller receiver provides a function that supplies the signals input from the outside to the RIN pin
after eliminating noise.
Noise width can be eliminated by setting bit 5 (PRSEN) and bit 6 (NCW) of the remote controller receive control
register (RMCN) as shown in Figure 15-2.
Table 15-2. Noise Elimination Width
PRSEN Division
Control Signal
NCW Noise Elimination Width Control
Signal
Internal Operation Clock Cycle After
Division Control by PRSEN (1/fPRS)
Eliminatable Noise
Width
0
0
1
1
0
1
0
1
1/fREM
1/fREM
2/fREM
2/fREM
Less than 1/fREM
Less than 2/fREM
Less than 2/fREM
Less than 4/fREM
Remark fREM: Source clock of remote controller counter
A noise elimination operation is performed by using the internal operation clock after division control by PRSEN.
Then, after the external input signal from RIN pin has been synchronized with the clock,
If NCW = 0, the signal after sampling is performed twice is processed as a RIN input in the circuit.
If NCW = 1, the signal after sampling is performed three times is processed as a RIN input in the circuit.
The following shows the flow of a noise elimination operation.
<1> Select whether or not the internal operation clock is divided by PRSEN.
PRSEN = 0: Not divided (fPRS = fREM)
PRSEN = 1: Divided (fPRS = fREM/2)
<2> Synchronize the external input signal from the RIN pin with the internal operation clock.
<3> Generate a signal (samp1) sampling the synchronized signal for the first time.
(The signal is later than the synchronized signal by one clock.)
<4> Generate a signal (samp2) sampling the synchronized signal and samp1 for the second time.
(When synchronized signal = samp1 = H, samp1 is latched.)
<5> Generate a signal (samp3) sampling the synchronized signal and samp2 for the third time.
(When synchronized signal = samp2 = H, samp2 is latched.)
<6> Select a signal to be the RIN input in the circuit using NCW.
NCW = 0: samp2 is processed as the RIN input in the circuit.
NCW = 1: samp3 is processed as the RIN input in the circuit.
Figure 15-8 shows an example of a noise elimination operation.
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Figure 15-8. Noise Elimination Operation Example (1/2)
(a) 1-clock noise elimination (PRSEN = 0, NCW = 0)
Clock
RIN (ideal)
RIN
L
Noise
Synchronization
L
H
samp1
samp2
Since synchronized signal = samp1 = H is not satisfied, samp1 is not latched.
L
L
Internal RIN
Delayed by 2 to 3 clocks
Remark Internal RIN is a signal after synchronization and sampling are performed twice, and is therefore later
than the actual signal input from the outside to the RIN pin by two to three clocks.
(b) 2-clock noise elimination (PRSEN = 0, NCW = 1)
Clock
Clock RIN (ideal)
L
Noise
RIN
H
Synchronization
L
H
samp1
Since synchronized signal = samp1 = H, samp1 is latched from this
H
samp2
samp3
point and later.
Since synchronized signal = samp2 = H is not satisfied, samp2 is
not latched.
L
L
Internal RIN
Delayed by 3 to 4 clocks
Remark Internal RIN is a signal after synchronization and sampling are performed three times, and is therefore
later than the actual signal input from the outside to the RIN pin by 3 to 4 clocks.
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Figure 15-8. Noise Elimination Operation Example (2/2)
(c) 2-clock noise elimination (PRSEN = 1, NCW = 0)
Clock
Clock divider
RIN (ideal)
RIN
L
Noise
Synchronization
L
H
samp1
samp2
Since synchronized signal = samp1 = H is not satisfied, samp1 is
not latched.
L
L
Internal RIN
Delayed by 4 to 6 clocks
Remark Internal RIN is a signal after synchronization and sampling are performed twice, and is therefore later
than the actual signal input from the outside to the RIN pin by 4 to 6 clocks.
(d) 4-clock noise elimination (PRSEN = 1, NCW = 1)
Clock
Clock divider
RIN (ideal)
L
Noise
RIN
H
Synchronization
L
H
samp1
H
Since synchronized signal =
samp1 = H, samp1 is
samp2
latched.
Since synchronized signal = samp2 = H
is not satisfied, samp2 is not latched.
samp3
L
L
Internal RIN
Delayed by 6 to 8 clocks
Remark Internal RIN is a signal after synchronization and sampling are performed three times, and is therefore
later than the actual signal input from the outside to the RIN pin by 6 to 8 clocks.
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16.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top
priority over all other interrupt requests.
A standby release signal is generated.
One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt.
(2) Maskable interrupt
This interrupt undergoes mask control. If two or more interrupts with the same priority are simultaneously
generated, each interrupt has a predetermined priority as shown in Tables 16-1 and 16-2.
A standby release signal is generated.
For the µPD789488 and 78F9488, 5 external and 11 internal interrupt sources are incorporated as maskable
interrupts.
For the µPD789489 and 78F9489, 6 external and 16 internal interrupt sources are incorporated as maskable
interrupts.
16.2 Interrupt Sources and Configuration
A total of 17 non-maskable and maskable interrupts are incorporated as interrupt sources for the µPD789488 and
78F9488, and a total of 23 for the µPD789489 and 78F9489 (Tables 16-1 and 16-2).
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Table 16-1. Interrupt Sources (µPD789488, 78F9488)
Interrupt Type PriorityNote 1
Interrupt Source
Trigger
Internal/
External
Vector Table
Address
Basic
Configuration
Name
TypeNote 2
Non-maskable
Maskable
−
INTWDT
Watchdog timer overflow (with
watchdog timer mode 1 selected)
Internal
0004H
(A)
(B)
(C)
0
INTWDT
Watchdog timer overflow (with
interval timer mode selected)
1
2
3
4
−
5
INTP0
INTP1
INTP2
INTP3
−
Pin (INTP0) input edge detection
Pin (INTP1) input edge detection
Pin (INTP2) input edge detection
Pin (INTP3) input edge detection
−
External
0006H
0008H
000AH
000CH
000EH
0010H
−
Note 3
INTSR20
INTCSI20
UART reception completion
Internal
(B)
End of 3-wire SIO transfer for serial
interface 20
6
7
8
INTCSI10
INTST20
INTWTI
End of 3-wire SIO transfer for serial
interface 1A0
0012H
0014H
0016H
End of UART transmission for serial
interface 20
Reference time interval signal of
watch timer (WT)
9
INTTM20
INTTM50
INTTM60
Match between TM20 and CR20
Match between TM50 and CR50
0018H
001AH
001CH
10
11
Match between TM60 and CR60
(in 8-bit counter mode), and
between TM50, TM60 and CR50,
CR60 (in 16-bit timer mode)
12
13
14
15
−
INTTM61
INTAD0
INTWT
INTKR00
−
Match between TM61 and CR61
End of A/D conversion
Watch timer (WT) overflow
Key return signal detection
−
001EH
0020H
0022H
External
0024H
(C)
−
0026H to 002CH
Note 3
Notes 1. Priority is the priority order when more than one maskable interrupt request is generated at the same
time. 0 is the highest priority and 15 is the lowest.
2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 16-1.
3. There is no interrupt source that applies to 000EH and 0026H to 002CH of vector table address.
Remark Only one of the two watchdog timer interrupt (INTWDT) sources, non-maskable or maskable (internal),
can be selected.
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Table 16-2. Interrupt Sources (µPD789489, 78F9489)
Interrupt Type PriorityNote 1
Interrupt Source
Trigger
Internal/
External
Vector Table
Address
Basic
Configuration
Name
TypeNote 2
Non-maskable
Maskable
−
INTWDT
Watchdog timer overflow (with
Internal
0004H
(A)
(B)
(C)
watchdog timer mode 1 selected)
0
INTWDT
Watchdog timer overflow (with
interval timer mode selected)
1
2
3
4
5
6
INTP0
Pin (INTP0) input edge detection
Pin (INTP1) input edge detection
Pin (INTP2) input edge detection
Pin (INTP3) input edge detection
Remote controller edge detection
UART reception completion
External
Internal
0006H
0008H
000AH
000CH
000EH
0010H
INTP1
INTP2
INTP3
INTRIN
INTSR20
INTCSI20
(B)
End of 3-wire SIO transfer for serial
interface 20
7
8
9
INTCSI10
INTST20
INTWTI
End of 3-wire SIO transfer for serial
interface 1A0
0012H
0014H
0016H
End of UART transmission for serial
interface 20
Reference time interval signal of
watch timer (WT)
10
11
12
INTTM20
INTTM50
INTTM60
Match between TM20 and CR20
Match between TM50 and CR50
0018H
001AH
001CH
Match between TM60 and CR60
(in 8-bit counter mode), and
between TM50, TM60 and CR50,
CR60 (in 16-bit timer mode)
13
14
15
16
17
INTTM61
INTAD0
INTWT
Match between TM61 and CR61
End of A/D conversion
001EH
0020H
0022H
0024H
0026H
Watch timer (WT) overflow
Key return signal detection
INTKR00
INTRERR
External
Internal
(C)
(B)
Remote controller reception error
occurrence
18
19
20
21
INTGP
Remote controller guide pulse
detection
0028H
002AH
002CH
002EH
INTREND
INTDFULL
INTKR01
Remote controller data reception
completion
Read request for remote controller
8-bit shift data
Key return signal detection
External
(C)
Notes 1. Priority is the priority order when more than one maskable interrupt request is generated at the same
time. 0 is the highest priority and 21 is the lowest.
2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 16-1.
Remark Only one of the two watchdog timer interrupt (INTWDT) sources, non-maskable or maskable (internal),
can be selected.
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Figure 16-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Vector table
address generator
Interrupt request
Standby release signal
(B) Internal maskable interrupt
Internal bus
IE
MK
Vector table
address generator
Interrupt request
IF
Standby release signal
(C) External maskable interrupt
Internal bus
INTM0, INTM1,
KRM00, KRM01
MK
IE
Vector table
address generator
Interrupt
request
Edge
detector
IF
Standby
release signal
INTM0: External interrupt mode register 0
INTM1: External interrupt mode register 1
KRM00: Key return mode register 00
KRM01: Key return mode register 01
IF:
IE:
MK:
Interrupt request flag
Interrupt enable flag
Interrupt mask flag
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16.3 Registers Controlling Interrupt Function
The following five types of registers are used to control the interrupt functions.
• Interrupt request flag registers (IF0 to IF2)
• Interrupt mask flag registers (MK0 to MK2)
• External interrupt mode registers (INTM0 and INTM1)
• Program status word (PSW)
• Key return mode registers (KRM00, KRM01)
Table 16-3 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt
requests.
Table 16-3. Flags Corresponding to Interrupt Request Signal Names
Interrupt Request Signal Name
Interrupt Request Flag
Interrupt Mask Flag
INTWDT
INTP0
WDTIF
PIF0
WDTMK
PMK0
INTP1
PIF1
PMK1
INTP2
PIF2
PMK2
INTP3
PIF3
PMK3
INTRINNote
INTSR20/INTCSI20
INTCSI10
INTST20
INTWTI
RINIFNote
SRIF20
CSIIF10
STIF20
WTIIF
RINMKNote
SRMK20
CSIMK10
STMK20
WTIMK
INTTM20
INTTM50
INTTM60
INTTM61
INTAD0
TMIF20
TMIF50
TMIF60
TMIF61
ADIF0
WTIF
TMMK20
TMMK50
TMMK60
TMMK61
ADMK0
INTWT
WTMK
INTKR00
INTRERRNote
INTGPNote
INTRENDNote
INTDFULLNote
INTKR01Note
KRIF00
KRMK00
RERRMKNote
GPMKNote
RENDMKNote
DFULLMKNote
KRMK01Note
RERRIFNote
GPIFNote
RENDIFNote
DFULLIFNote
KRIF01Note
Note µPD789489 and 78F9489 only
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(1) Interrupt request flag registers (IF0 to IF2)
An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an
instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal
is input, or when an instruction is executed.
IF0 to IF2 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Figure 16-2. Format of Interrupt Request Flag Registers
Symbol
IF0
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address After reset
FFE0H 00H
R/W
R/W
CSIIF10 SRIF20 RINIFNote
PIF3
PIF2
PIF1
PIF0
WDTIF
Symbol
IF1
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address After reset
FFE1H 00H
R/W
R/W
WTIF
ADIF0
TMIF61
TMIF60
TMIF50
TMIF20
WTIIF
STIF20
Symbol
IF2
7
0
6
0
<5>
<4>
<3>
<2>
GPIFNote
<1>
<0>
Address After reset
FFE2H 00H
R/W
R/W
KRIF01Not
KRIF00
DFULLIFNot RENDIFNote
RERRIFNote
e
e
××IF×
Interrupt request flag
0
1
No interrupt request signal generated
An interrupt request signal is generated and an interrupt request made
Note µPD789489 and 78F9489 only
Cautions 1. The WDTIF flag can be read/written only when the watchdog timer is being used as an
interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer
mode 1 or 2.
2. Because P30 to P33 function alternately as external interrupts, when the output level
changes after the output mode of the port function is specified, the interrupt request
flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0
to PMK3) before using the port in output mode.
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(2) Interrupt mask flag registers (MK0 to MK2)
Interrupt mask flags are used to enable and disable the corresponding maskable interrupts.
MK0 to MK2 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 16-3. Format of Interrupt Mask Flag Registers
Symbol
MK0
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address After reset
FFH
R/W
R/W
CSIMK10 SRMK20 RINMKNote PMK3
PMK2
PMK1
PMK0
WDTMK FFE4H
Symbol
MK1
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address After reset
R/W
R/W
WTMK
ADMK0 TMMK61 TMMK60 TMMK50 TMMK20 WTIMK STMK20 FFE5H FFH
Symbol
MK2
7
1
6
1
<5>
<4>
<3>
<2>
GPMKNote
<1>
<0>
Address After reset
FFH
R/W
R/W
KRMK01Note DFULLMKNot RENDMKNot
RERRMKNot
KRMK00 FFE6H
e
e
e
××MK×
Interrupt servicing control
0
1
Interrupt servicing enabled
Interrupt servicing disabled
Note µPD789489 and 78F9489 only
Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to
read the WDTMK flag results in an undefined value being detected.
2. Because P30 to P33 function alternately as external interrupts, when the output level
changes after the output mode of the port function is specified, the interrupt request
flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0
to PMK3) before using the port in output mode.
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(3) External interrupt mode registers (INTM0, INTM1)
These registers are used to specify the valid edge for INTP0 to INTP3.
INTM0 and INTM1 are set with an 8-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Figure 16-4. Format of External Interrupt Mode Registers
Symbol
INTM0
7
6
5
4
3
2
1
0
0
0
Address After reset
FFECH 00H
R/W
R/W
ES21
ES20
ES11
ES10
ES01
ES00
Symbol
INTM1
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address After reset
FFEDH 00H
R/W
R/W
ES31
ES30
ESn1
ESn0
INTPn valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Remark n = 0, 1, 2, and 3
Cautions 1. Always set bits 0 and 1 of INTM0, and 2 to 7 of INTM1 to 0.
2. Before setting INTM0 and INTM1, set (1) the interrupt mask flags (PMK0 to PMK3) to
disable interrupts.
To enable interrupts, clear (0) the interrupt request flags (PIF0 to PIF3), then clear (0) the
interrupt mask flags (PMK0 to PMK3).
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(4) Program status word (PSW)
The program status word is used to hold the instruction execution results and the current status of the
interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW.
The PSW can be read and written in 8-bit units, and can be manipulated by using bit manipulation
instructions and dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is
automatically saved to the stack, and the IE flag is reset (0).
RESET input sets the PSW to 02H.
Figure 16-5. Program Status Word Configuration
Symbol
PSW
7
6
Z
5
0
4
3
0
2
0
1
1
0
After reset
02H
IE
AC
CY
Used in the execution of ordinary instructions
IE
0
Interrupt acknowledgment enable/disable
Disabled
Enabled
1
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(5) Key return mode register 00 (KRM00)
This register is used to set the pin that is to detect the key return signal (rising edge of port 0).
KRM00 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 16-6. Format of Key Return Mode Register 00
Symbol
7
6
5
4
3
0
2
0
1
0
0
Address After reset
FFF5H 00H
R/W
R/W
KRM00 KRM007 KRM006 KRM005 KRM004
KRM000
KRM000
Control of key return signal detection
0
1
Key return signal not detected
Key return signal detected (P00 to P03 falling edge detection)
KRM00n
Control of key return signal detection
0
1
Key return signal not detected
Key return signal detected (P0n falling edge detection)
Remark n = 4 to 7
Cautions 1. Always set bits 1 to 3 to 0.
2. Before setting KRM00, set (1) bit 0 (KRMK00) of MK2 to disable interrupts. To enable
interrupts, clear (0) KRMK00 after clearing (0) bit 0 (KRIF00) of IF2.
3. On-chip pull-up resistors are not automatically connected in input mode even when key
return signal detection is specified. Therefore, when detecting the key return signal,
connect the pull-up resistor of the corresponding bit using pull-up resistor option
register B0 (PUB0). Although these resistors are disconnected when the mode changes
to output, key return signal detection continues unchanged.
Figure 16-7. Block Diagram of Falling Edge Detector
Key return mode register 00
(KRM00)
Note 1
P00/KR0
P01/KR1
P02/KR2
P03/KR3
INTKR00
Falling edge detector
KRMK00
P04/KR4
P05/KR5
P06/KR6
P07/KR7
Standby release
signal
Notes 1. The pin names one P00/KR00 to P07/KR07 in the µPD789489 and 78F9489.
2. For selecting the pin to be used as falling edge input.
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(6) Key return mode register 01 (KRM01) (µPD789489, 78F9489 only)
This register is used to set the pin that is to detect the key return signal (falling edge of port 6).
KRM01 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 16-8. Format of Key Return Mode Register 01
Symbol
7
6
5
4
3
0
2
0
1
0
0
Address After reset
FFF4H 00H
R/W
R/W
KRM01 KRM017 KRM016 KRM015 KRM014
KRM010
KRM010
Control of key return signal detection
0
1
Key return signal not detected
Key return signal detected (P60 to P63 falling edge detection)
KRM01n
Control of key return signal detection
0
1
Key return signal not detected
Key return signal detected (P6n falling edge detection)
Remark n = 4 to 7
Cautions 1. Always set bits 1 to 3 to 0.
2. Before setting KRM01, set bit 5 of MK2 (KRMK01 = 1) to disable interrupts. To enable
interrupts, clear KRMK01 after clearing bit 5 of IF2 (KRIF01 = 0)
3. If any of the pins specified for key return signal detection is low level, the key return
signal cannot be detected even if a falling edge is generated at other key return pins.
4. When even one of the P60/ANI0/KR10 to P67/ANI7/KR17 pins is used as an A/D input, set
KRM010 and KRM014 to KRM017 to 0.
Figure 16-9. Block Diagram of Falling Edge Detector
Key return mode register 01
(KRM01)
P60/ANI0/KR10
P61/ANI1/KR11
P62/ANI2/KR12
P63/ANI3/KR13
INTKR01
Falling edge detector
KRMK01
P64/ANI4/KR14
P65/ANI5/KR15
P66/ANI6/KR16
P67/ANI7/KR17
Standby release
signal
Note For selecting the pin to be used as falling edge input
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16.4 Interrupt Servicing Operation
16.4.1 Non-maskable interrupt request acknowledgment operation
The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not
subject to interrupt priority control and takes precedence over all other interrupts.
When the non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order,
the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 16-10 shows the flow from non-maskable interrupt request generation to acknowledgment, Figure 16-11
shows the timing of non-maskable interrupt acknowledgment, and Figure 16-12 shows the acknowledgment operation
when a number of non-maskable interrupts are generated.
Caution During non-maskable interrupt service program execution, do not input another non-maskable
interrupt request; if it is input, the service program will be interrupted and the new non-
maskable interrupt request will be acknowledged.
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Figure 16-10. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment
Start
WDTM4 = 1
No
(watchdog timer mode
is selected)
Interval timer
Yes
No
No
WDT
overflows
Yes
WDTM3 = 0
(non-maskable interrupt
is selected)
Reset processing
Yes
Interrupt request is generated
Interrupt servicing starts
WDTM: Watchdog timer mode register
WDT: Watchdog timer
Figure 16-11. Timing of Non-Maskable Interrupt Request Acknowledgment
Saving PSW and PC, and
jump to interrupt servicing
CPU processing
WDTIF
Instruction
Instruction
Interrupt servicing program
Figure 16-12. Non-Maskable Interrupt Request Acknowledgment
Main routine
First interrupt servicing
NMI request
(second)
NMI request
(first)
Second interrupt servicing
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16.4.2 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status
(when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in
Table 16-4.
Refer to Figures 16-14 and 16-15 for the timing of interrupt request acknowledgement.
Table 16-4. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time
Maximum TimeNote
19 clocks
9 clocks
Note The wait time is maximum when an interrupt request is generated immediately before
the BT or BF instruction.
1
fCPU
Remark 1 clock:
(fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the one assigned the highest priority by the priority specification flag.
A pending interrupt is acknowledged when the status in which it can be acknowledged is set.
Figure 16-13 shows the algorithm of interrupt request acknowledgment.
When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE
flag is reset to 0, the data in the vector table determined for each interrupt request is loaded to the PC, and execution
branches.
To return from interrupt servicing, use the RETI instruction.
Figure 16-13. Interrupt Request Acknowledgment Program Algorithm
Start
No
xxIFx = 1 ?
Yes (Interrupt request generated)
No
xxMKx = 0 ?
Yes
Interrupt request pending
Interrupt request pending
No
IE = 1 ?
Yes
Vectored interrupt
servicing
xxIFx: Interrupt request flag
xxMKx: Interrupt mask flag
IE:
Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)
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Figure 16-14. Interrupt Request Acknowledgment Timing (Example: MOV A, r)
8 clocks
Clock
Saving PSW and PC, and
jump to interrupt servicing
MOV A, r
Interrupt servicing program
CPU
Interrupt
If the interrupt request has generated an interrupt request flag (xxIFx) by the time the instruction clocks under
execution, n clocks (n = 4 to 10), are n − 1, interrupt request acknowledgment processing will start following the
completion of the instruction under execution. Figure 16-14 shows an example using the 8-bit data transfer instruction
MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of
execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of
MOV A, r.
Figure 16-15. Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated in Final Clock Under Execution)
8 clocks
Clock
Interrupt servicing
program
Saving PSW and PC, and
jump to interrupt servicing
NOP
MOV A, r
CPU
Interrupt
If the interrupt request flag (xxIFx) is generated in the final clock of the instruction, interrupt request
acknowledgment processing will begin after execution of the next instruction is complete.
Figure 16-15 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock
instruction). In this case, the interrupt request will be processed after execution of MOV A, r, which follows NOP, is
complete.
Caution When interrupt request flag registers (IF0 to IF2), or interrupt mask flag registers (MK0 to MK2)
are being accessed, interrupt requests will be held pending.
16.4.3 Multiple interrupt servicing
Multiple interrupt servicing, in which an interrupt request is acknowledged while another interrupt request being
serviced, can be executed using the priority order. If multiple interrupts are generated at the same time, they are
serviced in the order according to the priority assigned to each interrupt request in advance (refer to Tables 16-1 and
16-2).
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Figure 16-16. Example of Multiple Interrupt Servicing
Example 1. Acknowledging multiple interrupts
INTxx servicing
INTyy servicing
Main servicing
IE = 0
IE = 0
EI
EI
INTxx
INTyy
RETI
RETI
The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are
performed. Before each interrupt request is acknowledged, the EI instruction is issued and the interrupt request is
enabled.
Example 2. Multiple interrupt servicing is not performed because interrupts are disabled
INTxx servicing
INTyy servicing
Main servicing
EI
IE = 0
INTyy is held pending
INTyy
RETI
INTxx
IE = 0
RETI
Because interrupt requests are disabled (the EI instruction has not been issued) in the INTxx interrupt servicing,
the interrupt request INTyy is not acknowledged and multiple interrupt servicing is not performed. INTyy is held
pending and is acknowledged after INTxx servicing is completed.
IE = 0: Interrupt requests disabled
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CHAPTER 16 INTERRUPT FUNCTIONS
16.4.4 Putting interrupt requests on hold
If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type
of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such
instructions (interrupt request pending instructions) are as follows.
• Instructions that manipulate interrupt request flag registers (IF0 to IF2)
• Instructions that manipulate interrupt mask flag registers (MK0 to MK2)
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CHAPTER 17 STANDBY FUNCTION
17.1 Standby Function and Configuration
17.1.1 Standby function
The standby function is used to reduce the power consumption of the system and can be effected in the following
two modes.
(1) HALT mode
This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the
CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption
as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in
this mode.
The data memory can be retained at a low voltage (VDD = 1.8 V). Therefore, this mode is useful for retaining
the contents of the data memory at an extremely low current.
The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent
operation. However, some time is required until the system clock oscillator stabilizes after the STOP mode
has been released. If processing must be resumed immediately by using an interrupt request, therefore, use
the HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are
all retained. In addition, the statuses of the output latches of the I/O ports and output buffers are also retained.
Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then
execute the STOP instruction.
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CHAPTER 17 STANDBY FUNCTION
17.1.2 Register controlling standby function
The wait time after the STOP mode is released upon interrupt request generation until oscillation stabilizes is
controlled by the oscillation stabilization time selection register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, it takes 215/fX, not 217/fX, to stabilize oscillation after RESET input.
Figure 17-1. Format of Oscillation Stabilization Time Selection Register
7
0
6
0
5
0
4
0
3
0
2
1
0
Symbol
OSTS
Address
FFFAH
After reset
04H
R/W
R/W
OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
12/f
X
X
X
µ
(819 s)
0
0
1
0
1
0
0
0
0
2
215/f
217/f
(6.55 ms)
(26.2 ms)
Other than above
Setting prohibited
Caution The wait time after the STOP mode is released does not include the time from STOP mode
release to clock oscillation start (“a” in the figure below), regardless of whether STOP mode is
released by RESET input or by interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 17 STANDBY FUNCTION
17.2 Standby Function Operation
17.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operation statuses in the HALT mode are shown in the following table.
Table 17-1. Operation Statuses in HALT Mode
Item
HALT Mode Operation Status During Main
System Clock Operation
HALT Mode Operation Status During Subsystem
Clock Operation
Subsystem Clock
Operating
Subsystem Clock
Stopped
Main System Clock
Operating
Main System Clock
Stopped
Clock generator
Oscillation enabled for both main system clock and subsystem clock, but clock supply to CPU is
stopped
Subsystem clock ×4
Operation stopped
multiplication circuit
CPU
Operation stopped
Ports (output latches)
16-bit timer 20
8-bit timer 50
Status before HALT mode setting retained
Operable
OperableNote 1
OperableNote 2
OperableNote 3
OperableNote 3
OperableNote 5
Operable
8-bit timer 60
Operable
8-bit timer 61
Operable
Watch timer
Operable
OperableNote 4
Operable
Watchdog timer
Key return circuit
Serial interface 20
Serial interface 1A0
LCD controller/driver
A/D converter
Multiplier
Operable
Operation stopped
Operable
Operable
OperableNote 6
OperableNote 6
OperableNotes 5, 7
Operable
OperableNote 7
Operation stopped
Operation stopped
Operable
OperableNotes 4, 7
OperableNote 4
OperableNote 7
Operable
Remote controller
receiverNote 8
OperableNote 5
External interrupts
OperableNote 9
Notes 1. Operation is enabled when the 24-bit counter mode is selected.
2. Operation is enabled when either the subsystem clock or the input signal from timer 60 (when timer 60
is operable) is selected as the count clock.
3. Operation is enabled only when the external input clock is selected as the count clock.
4. Operation is enabled when the main system clock is selected.
5. Operation is enabled when the subsystem clock is selected.
6. Operation is enabled only when an external clock is selected.
7. The HALT instruction can be set after display instruction execution.
8. µPD789489 and 78F9489 only.
9. Operation is enabled only for a maskable interrupt that is not masked.
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CHAPTER 17 STANDBY FUNCTION
(2) Releasing HALT mode
The HALT mode can be released by the following three sources.
(a) Release by unmasked interrupt request
The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to
be acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at
the next address is executed.
Figure 17-2. Releasing HALT Mode by Interrupt
HALT
instruction
Wait
Wait
Standby
release signal
Operation
mode
HALT mode
Operation mode
Oscillation
Clock
Remarks 1. The broken lines indicate the case where the interrupt request that released the standby mode is
acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is performed:
• When vectored interrupt servicing is not performed:
9 to 10 clocks
1 to 2 clocks
(b) Release by non-maskable interrupt request
The HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored
interrupt servicing is performed.
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CHAPTER 17 STANDBY FUNCTION
(c) Release by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address
in the same manner as the ordinary reset operation, and program execution is started.
Figure 17-3. Releasing HALT Mode by RESET Input
Wait
: 6.55 ms)
HALT
instruction
(215/f
X
RESET
signal
Oscillation
stabilization
wait status
Reset
period
Operation
mode
Operation
mode
HALT mode
Oscillation
Oscillation
stops
Oscillation
Clock
Remark fX: Main system clock oscillation frequency
Table 17-2. Operation After Releasing HALT Mode
Releasing Source
MKxx
IE
0
1
x
Operation
Maskable interrupt request
0
0
Executes next address instruction
Executes interrupt servicing
Retains HALT mode
1
Non-maskable interrupt request
RESET input
−
x
Executes interrupt servicing
Reset processing
-−-
−
x: don’t care
Caution Some constraints apply when the flash version (µPD78F9488 and 78F9489) is used in the HALT
mode with the subclock multiplied by 4 as the CPU clock. For details, refer to 19.2 Cautions on
µPD78F9488 and 78F9489.
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CHAPTER 17 STANDBY FUNCTION
17.2.2 STOP mode
(1) Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Because the standby mode can be released by an interrupt request signal, the standby
mode is released as soon as it is set if there is an interrupt source whose interrupt request
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait time
set by the oscillation stabilization time selection register (OSTS) elapses, and then the
operation mode is set.
The operation statuses in the STOP mode are shown in the following table.
Table 17-3. Operation Statuses in STOP Mode
Item
STOP Mode Operation Status During Main System Clock Operation
Subsystem Clock Operating Subsystem Clock Stopped
Oscillation stopped
Main system clock
Subsystem clock ×4
Operation stopped
multiplication circuit
CPU
Operation stopped
Status before STOP mode setting retained
Operation stopped
OperableNote 1
Ports (output latches)
16-bit timer 20
8-bit timer 50
OperableNote 2
8-bit timer 60
OperableNote 3
8-bit timer 61
OperableNote 3
Watch timer
OperableNote 4
Operation stopped
Watchdog timer
Key return circuit
Serial interface 20
Serial interface 1A0
LCD controller/driver
A/D converter
Multiplier
Operation stopped
Operable
OperableNote 5
OperableNote 5
OperableNote 4
Operation stopped
Operation stopped
Operation stopped
Operation stopped
OperableNote 4
Remote controller
receiverNote 6
External interrupts
OperableNote 7
Notes 1. Operation is enabled when either the subsystem clock or the input signal from the timer 60 (when timer
60 is operable) is selected as the count clock.
2. Operation is enabled when the input signal from timer 60 (when timer 60 is operable) is selected as the
count clock.
3. Operation is enabled when the external input clock is selected as the count clock.
4. Operation is enabled when the subsystem clock is selected.
5. Operation is enabled only for a maskable interrupt that is not masked.
6. µPD789489 and 78F9489 only
7. Operation is enabled only for a maskable interrupt that is not masked.
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CHAPTER 17 STANDBY FUNCTION
(2) Releasing STOP mode
The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request
The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are
enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization
time has elapsed. If interrupts are disabled, the instruction at the next address is executed.
Figure 17-4. Releasing STOP Mode by Interrupt
Wait
STOP
instruction
(set time by OSTS)
Standby
release signal
Oscillation stabilization
Operation
mode
Operation
mode
wait status
STOP mode
Oscillation
stops
Oscillation
Oscillation
Clock
Remark The broken lines indicate the case where the interrupt request that released the standby mode is
acknowledged.
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CHAPTER 17 STANDBY FUNCTION
(b) Release by RESET input
When the STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 17-5. Releasing STOP Mode by RESET Input
Wait
X
STOP
instruction
(215/f
: 6.55 ms)
RESET
signal
Oscillation
stabilization
wait status
Operation
mode
Reset
period
Operation
mode
STOP mode
Oscillation
Oscillation
stops
Oscillation
Clock
Remark fX: Main system clock oscillation frequency
Table 17-4. Operation After Releasing STOP Mode
Releasing Source
MKxx
IE
0
Operation
Maskable interrupt request
0
0
1
−
Executes next address instruction
Executes interrupt servicing
Retains STOP mode
1
x
RESET input
-−-
Reset processing
x: don’t care
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CHAPTER 18 RESET FUNCTION
The following two operations are available to generate reset signals.
(1) External reset input by RESET pin
(2) Internal reset by watchdog timer program loop time detection
External and internal reset have no functional differences. In both cases, program execution starts at the address
at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
is set to the status shown in Table 18-1. Each pin is high impedance during reset input or during oscillation
stabilization time just after reset release.
When a high level is input to the RESET pin, the reset is released and program execution is started after the
oscillation stabilization time (215/fX) has elapsed. The reset applied by the watchdog timer overflow is automatically
released after reset, and program execution is started after the oscillation stabilization time (215/fX) has elapsed (see
Figures 18-2 to 18-4.)
Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
2. When the STOP mode is released by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
Figure 18-1. Block Diagram of Reset Function
RESET
Reset signal
Reset controller
Over-
flow
Interrupt function
Count clock
Watchdog timer
Stop
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CHAPTER 18 RESET FUNCTION
Figure 18-2. Reset Timing by RESET Input
X1
Oscillation
During normal
operation
Reset period
stabilization
Normal operation
(reset processing)
(oscillation stops)
time wait
RESET
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
Figure 18-3. Reset Timing by Overflow in Watchdog Timer
X1
Oscillation
stabilization
time wait
Reset period
(oscillation
continues)
During normal
operation
Normal operation
(reset processing)
Overflow in
watchdog timer
Internal
reset signal
Hi-Z
Port pin
Figure 18-4. Reset Timing by RESET Input in STOP Mode
X1
STOP instruction execution
Oscillation
During normal
operation
Stop status
Reset period
Normal operation
(reset processing)
stabilization
time wait
(oscillation stops)
(oscillation stops)
RESET
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
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CHAPTER 18 RESET FUNCTION
Table 18-1. Status of Hardware After Reset (1/2)
Hardware
Status After Reset
Program counter (PC)Note 1
Contents of reset
vector table (0000H,
0001H) set
Stack pointer (SP)
Undefined
Program status word (PSW)
02H
RAM
Data memory
UndefinedNote 2
UndefinedNote 2
00H
General-purpose registers
Ports (P0 to P3, P5, P8Note 3) (output latches)
Port mode registers (PM0 to PM3, PM5, PM8Note 3
Port function registers (PF7, PF8)
)
FFH
00H
Pull-up resistor option registers (PUB0 to PUB3)
Processor clock control register (PCC)
Subclock oscillation mode register (SCKM)
Subclock selection register (SSCK)
00H
02H
00H
RetainedNote 4
Subclock control register (CSS)
00H
Oscillation stabilization time selection register (OSTS)
04H
16-bit timer 20
8-bit timer 50, 60, 61
Watch timer
Timer counter (TM20)
0000H
FFFFH
00H
Compare register (CR20)
Mode control register (TMC20)
Capture register (TCP20)
Undefined
00H
Timer counters (TM50, TM60, TM61)
Compare registers (CR50, CR60, CRH60, CR61, CRH61)
Mode control registers (TMC50, TMC60, TMC61)
Carrier generator output control register (TCA60)
Mode control register (WTM)
Undefined
00H
00H
00H
Interrupt time selection register (WTIM)
Clock selection register (WDCS)
00H
Watchdog timer
00H
Mode register (WDTM)
00H
00H
Serial interface 20
Serial operation mode register (CSIM20)
Asynchronous serial interface mode register (ASIM20)
Asynchronous serial interface status register (ASIS20)
Baud rate generator control register (BRGC20)
Transmit shift register (TXS20)
00H
00H
00H
FFH
Receive buffer register (RXB20)
Undefined
Notes 1. While a reset signal is being input, and during the oscillation stabilization period, only the contents of the
PC will be undefined; the remainder of the hardware will be the same state as after reset.
2. In standby mode, RAM enters the hold state after reset.
3. Port 8 is used only when the port function is specified by a mask option or port function register (refer
to CHAPTER 20 MASK OPTIONS and 4.3 (3) Port function registers).
4. The register is set to 00H only by RESET input.
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CHAPTER 18 RESET FUNCTION
Table 18-1. Status of Hardware After Reset (2/2)
Hardware
Status After Reset
00H
Serial interface 1A0
Operation mode register (CSIM1A0)
Shift register (SIO1A0)
00H
Buffer memory (SBMEM0 to SBMEMF)
Automatic data transmit/receive control register (ADTC0)
Automatic data transmit/receive address pointer (ADTP0)
Automatic data transmit/receive transfer interval specification register (ADTI0)
Mode register (ADML0)
Undefined
00H
Undefined
00H
A/D converter
LCD controller/driver
Multiplier
00H
Input channel specification register (ADS0)
Conversion result register (ADCRL0)
Display mode register (LCDM0)
00H
0000H
00H
Clock control register (LCDC0)
00H
Voltage boost control register (LCDVA0)
16-bit result storage register (MUL0)
Data register (MRA0, MRB0)
00H
Undefined
Undefined
00H
Control register (MULC0)
Remote controller
receiverNote
Control register (RMCN)
00H
Data register (RMDR)
00H
Shift register reception counter register (RMSCR)
Shift register (RMSR)
00H
00H
Compare registers (RMGPHS, RMGPHL, RMDLS, RMDLL, RMDH0S,
RMDH0L, RMDH1S, RMDH1L)
00H
End width selection register (RMER)
Request flag register (IF0 to IF2)
00H
00H
FFH
00H
00H
Interrupts
Mask flag register (MK0 to MK2)
External interrupt mode register (INTM0, INTM1)
Key return mode registers (KRM00, KRM01Note
)
Note µPD789489 and 78F9489 only
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CHAPTER 19 FLASH MEMORY VERSION
The µPD78F9488 is available as the flash memory version of the µPD789488 (mask ROM version).
The µPD78F9489 is available as the flash memory version of the µPD789489 (mask ROM version).
The differences between the µPD78F9488, 78F9489, and the mask ROM version are shown in Table 19-1.
Table 19-1. Differences Between µPD78F9488, 78F9489, and Mask ROM Version
Item
Flash Memory Version
µPD78F9488 µPD78F9489
Mask ROM Version
µPD789488 µPD789489
Internal memory
ROM
32 KB (flash
memory)
48 KB (flash
memory)
32 KB
48 KB
Internal RAM
1024 bytes
1536 bytes
1024 bytes
1536 bytes
LCD display RAM
28 × 4 bits
Pin function selection
Selectable by a port function register (PF7
and PF8) in bit units
Selectable by a mask option in bit
units
S16 to S27 (LCD segment output) or
P70 to P73 and P80 to P87 (general-
purpose ports)
Circuit to multiply subsystem clock by ×4
Use enabled/disabled by subclock select
register (SSCK)
Use enabled/disabled by a mask
option
Pull-up resistor of port 5
None
Selectable by a mask option in 1-bit
units
Remote controller receiver
Not provided
Provided
Not provided
Provided
Key return signal detection pins
P00/KR0 to
P07/KR7
P00/KR00 to
P07/KR07,
P00/KR0 to
P07/KR7
P00/KR00 to
P07/KR07,
P60/ANI0/KR10 to
P67/ANI7/KR17
P60/ANI0/KR10 to
P67/ANI7/KR17
Restrictions in HALT mode when using
Refer to 19.2 Cautions on µPD78F9488
None
subclock ×4 clock
and 78F9489
IC0 pin
Not provided
Provided
Provided
VPP pin
Not Provided
Electrical specifications
Refer to CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488,
789489, 78F9489)
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the
commercial samples (not engineering samples) of the mask ROM version.
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CHAPTER 19 FLASH MEMORY VERSION
19.1 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL-
PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the µPD78F9488 or 78F9489
mounted on the target system (on-board). A flash memory program adapter (FA adapter), which is a target board used
exclusively for programming, is also provided.
Remark FL-PR3, FL-PR4, and the program adapter are products of Naito Densei Machida Mfg. Co., Ltd. (TEL
+81-45-475-4191).
Programming using flash memory has the following advantages.
• Software can be modified after the microcontroller is solder-mounted on the target system.
• Distinguishing software facilities low-quantity, varied model production
• Easy data adjustment when starting mass production
19.1.1 Programming environment
The following shows the environment required for µPD78F9488 and 78F9489 flash memory programming.
When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated
flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the
host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1).
For details, refer the manuals of Flashpro III/Flashpro IV.
Remark USB is supported by Flashpro IV only.
Figure 19-1. Environment for Writing Program to Flash Memory
VPP
V
DD
SS
RS-232C
USB
V
RESET
3-wire serial I/O
or UART
µ
or
PD78F9488
µPD78F9489
Dedicated flash
programmer
Host machine
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CHAPTER 19 FLASH MEMORY VERSION
19.1.2 Communication mode
Use the communication mode shown in Table 19-2 to perform communication between the dedicated flash
programmer and µPD78F9488 or 78F9489.
Table 19-2. Communication Mode List
TYPE SettingNote 1
Communication
Mode
Pins Used
Number of VPP
Pulses
COMM
PORT
SIO Clock
CPU Clock
Multiple
Rate
In Flashpro
On Target Board
3-wire serial I/O SIO ch-0
100 Hz to
1.25
1, 2, 4, 5
MHzNote 3
1 to 5 MHzNote
1.0
SI20/RxD20/P22
SO20/TxD20/P21
SCK20/ASCK20/
P20
0
3
2
(3-wired,
sync.)
MHzNote 2
3-wire serial I/O SIO ch-3
SI20/RxD20/P22
SO20/TxD20/P21
SCK20/ASCK20/
P20
with handshake + handshake
P11 (HS)
UART
UART ch-0 4,800 to
(Async.) 76,800 bps
5 MHzNote 5
4.91 or
1.0
RxD20/SI20/P22
TxD20/SO20/P21
8
5 MHzNote 2
Notes 2, 4
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3,
PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)).
2. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 22
ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489).
3. Only 2 MHz or 4 MHz can be selected for Flashpro III.
4. Because signal wave slew also affects UART communication, in addition to the baud rate error,
thoroughly evaluate the slew.
5. Flashpro IV only. However, when using Flashpro III, be sure to select the clock of the resonator on the
board. UART cannot be used with the clock supplied by Flashpro III.
Figure 19-2. Communication Mode Selection Format
10 V
VPP
VDD
1
2
n
VSS
VPP pulses
VDD
VSS
RESET
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CHAPTER 19 FLASH MEMORY VERSION
Figure 19-3. Example of Connection with Dedicated Flash Programmer
(a) 3-wire serial I/O
Dedicated flash programmer
PD78F9488
PD78F9489
µ
µ
VPP1
VDD
V
V
PP
DD
RESET
SCK
RESET
SCK20
SI20
SO
SI
SO20
X1
CLKNote 1
GND
V
SS
(b) 3-wire serial I/O with handshake
Dedicated flash programmer
PD78F9488
PD78F9489
µ
µ
VPP1
VDD
V
V
PP
DD
RESET
SCK
RESET
SCK20
SI20
SO
SI
SO20
HS
CLKNote 1
P11 (HS)
X1
GND
V
SS
(c) UART
Dedicated flash programmer
PD78F9488
PD78F9489
µ
µ
VPP1
VDD
V
PP
DD
V
RESET
SO
RESET
D20
D20
X1
R
X
SI
T
X
CLKNotes 1, 2
GND
V
SS
Notes 1. When the system clock is supplied from the dedicated flash programmer, connect the CLK pin with X1
pin and disconnect the on-board resonator. When using the clock of the on-board resonator, do not
connect the CLK pin.
2. When using UART with Flashpro III, the clock of the resonator connected to the X1 pin must be used, do
not connect the CLK pin.
Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the
dedicated flash programmer. Before using the power supply connected to the VDD pin, supply
voltage before starting programming.
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CHAPTER 19 FLASH MEMORY VERSION
If Flashpro III/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the
µPD78F9488 and 78F9489. For details, refer to the manual of Flashpro III/Flashpro IV.
Table 19-3. Pin Connection List
Signal Name
I/O
Pin Function
Pin Name
3-Wire Serial I/O
3-Wire Serial I/O
with Handshake
UART
VPP1
VPP2
VDD
Output
−
Write voltage
VPP
VDD
×
Note
×
Note
×
Note
−
−
I/O
VDD voltage generation/
voltage monitoring
GND
CLK
RESET
SI
−
Ground
VSS
Output
Output
Input
Clock output
Reset signal
Receive signal
Transmit signal
Transfer clock
Handshake signal
X1
RESET
SO20/TxD20
SI20/RxD20
SCK20
SO
Output
Output
Input
×
×
SCK
HS
×
P11 (HS)
Note VDD voltage must be supplied before programming is started.
Remark : Pin must be connected.
: If the signal is supplied on the target board, pin does not need to be connected.
× : Pin does not need to be connected.
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CHAPTER 19 FLASH MEMORY VERSION
19.1.3 On-board pin processing
When performing programming on the target system, provide a connector on the target system to connect the
dedicated flash programmer.
An on-board function that allows switching between normal operation mode and flash memory programming mode
may be required in some cases.
<VPP pin>
In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0 V
(TYP.) is supplied to the VPP pin, so perform either of the following.
(1) Connect a pull-down resistor (RVPP = 10 kΩ) to the VPP pin.
(2) Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND.
A VPP pin connection example is shown below.
Figure 19-4. VPP Pin Connection Example
PD78F9488,
µ
PD78F9489
µ
Connection pin of dedicated flash programmer
VPP
Pull-down resistor (RVPP
)
<Serial interface pin>
The following shows the pins used by the serial interface.
Serial Interface
3-wire serial I/O
Pins Used
SI20, SO20, SCK20
3-wire serial I/O with handshake
UART
SI20, SO20, SCK20, P11 (HS)
RxD20, TxD20
When connecting the dedicated flash programmer to a serial interface pin that is connected to another device on-
board, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with such
connections.
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(1) Signal conflict
If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to
another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device
or set the other device to the output high impedance status.
Figure 19-5. Signal Conflict (Input Pin of Serial Interface)
PD78F9488,
µ
PD78F9489
µ
Connection pin of
dedicated flash
programmer
Signal conflict
Input pin
Other device
Output pin
In the flash memory programming mode, the signal output by another
device and the signal sent by the dedicated flash programmer conflict,
therefore, isolate the signal of the other device.
(2) Abnormal operation of other device
If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that
is connected to another device (input), a signal is output to the device, and this may cause an abnormal
operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the
input signals to the other device are ignored.
Figure 19-6. Abnormal Operation of Other Device
PD78F9488,
µ
PD78F9489
µ
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
If the signal output by the
µ
PD78F9488, 78F9489 affects another device in
the flash memory programming mode, isolate the signals of the other
device.
PD78F9488,
µ
PD78F9489
µ
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device in the flash memory programming mode, isolate the signals of the
other device.
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CHAPTER 19 FLASH MEMORY VERSION
<RESET pin>
If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal
generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator.
If the reset signal is input from the user system in the flash memory programming mode, a normal programming
operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash
programmer.
Figure 19-7. Signal Conflict (RESET Pin)
PD78F9488,
µ
PD78F9489
µ
Connection pin of
dedicated flash
programmer
Signal conflict
RESET
Reset signal generator
Output pin
The signal output by the reset signal generator and the signal output from
the dedicated flash programmer conflict in the flash memory programming
mode, so isolate the signal of the reset signal generator.
<Port pins>
When the µPD78F9488 or 78F9489 enters the flash memory programming mode, all the pins other than those that
communicate with flash programmer are in the same status as immediately after reset.
If the external device does not recognize initial statuses such as the output high impedance status, therefore,
connect the external device to VDD or VSS via a resistor.
<Resonator>
When using the on-board clock, connect X1, X2, XT1, and XT2 as required in the normal operation mode.
When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main resonator
on-board, and leave the X2 pin open. The subsystem clock conforms to the normal operation mode.
<Power supply>
To use the power output from the flash programmer, connect the VDD pin to VDD of the flash programmer, and VSS
pin to GND of the flash programmer, respectively.
To use the on-board power supply, make connection in accordance with the normal operation mode. However,
because the voltage is monitored by the flash programmer, be sure to connect VDD of the flash programmer.
Supply the same power as in the normal operation mode to the other power pins (AVDD and AVSS).
<Other pins>
Process the other pins (S0 to S27, COM0 to COM3, VLC0 to VLC2, CAPH, and CAPL) in the same manner as in the
normal operation mode.
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19.1.4 Connection of adapter for flash writing
The following figure shows an example of recommended connection when the adapter for flash writing is used.
Figure 19-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O
VDD (2.7 to 5.5 V)
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PD78F9488,
PD78F9489
µ
µ
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
VDD
VDD2 (LVDD)
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
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CHAPTER 19 FLASH MEMORY VERSION
Figure 19-9. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O with Handshake
VDD (2.7 ‘5.5 V)
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
µ
µ
PD78F9488,
PD78F9489
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
VDD
VDD2 (LVDD)
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
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CHAPTER 19 FLASH MEMORY VERSION
Figure 19-10. Wiring Example for Flash Writing Adapter with UART
VDD (2.7 to 5.5 V)
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PD78F9488,
PD78F9489
µ
µ
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
VDD
VDD2 (LVDD)
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
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CHAPTER 19 FLASH MEMORY VERSION
19.2 Cautions on µPD78F9488 and 78F9489
(1) When using HALT mode with subclock multiplied by four
Observe the following constraints when using the flash version (µPD78F9488 and 78F9489) in the HALT
mode with the subclock multiplied by 4 as the CPU clock.
• Be sure to insert the following number of NOP instructions immediately after the HALT instruction.
Operating Temperature
TA = −40 to +45°C
Number of NOP Instructions
2
3
4
TA = −40 to +80°C
TA = −40 to +85°C
• Save the value of the A register to the internal high-speed RAM area before the HALT instruction is
executed (because the value of the A register may be changed when the HALT mode is released).
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CHAPTER 20 MASK OPTIONS
The µPD789488 and 789489 have the following mask options.
• Pin function
The segment pins of the LCD and port 7 (input port) can be selected in 1-bit units.
<1> S (16 + n)
<2> P7n (n = 0 to 3)
The segment pins of the LCD and port 8 (I/O port) can be selected in 1-bit units.
<1> S (20 + m)
<2> P8m (m = 0 to 7)
• Subsystem clock ×4 multiplication circuit
The use of a circuit to multiply the subsystem clock (32.768 kHz) by 4 (131 kHz) is selected.
<1> ×4 multiplication circuit is used
<2> ×4 multiplication circuit is not used
• Pull-up resistor
The connection of on-chip pull-up resistors for port 5 (I/O port) can be switched in 1-bit units.
<1> Pull-up resistor is connected
<2> Pull-up resistor is not connected
Caution The flash memory products (µPD78F9488 and 78F9489) do not have mask options.
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CHAPTER 21 INSTRUCTION SET
This chapter lists the instruction set of the µPD789489 Subseries. For details of the operation and machine
language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E).
21.1 Operation
21.1.1 Operand identifiers and description methods
Operands are described in the “Operand” column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specification
• !: Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers, r and rp, either functional names (X, A, C, etc.) or absolute names (names in
parenthesis in the table below, R0, R1, R2, etc.) can be used for description.
Table 21-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
saddr
FE20H to FF1FH Immediate data or labels
saddrp
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark See Table 3-4 Special Function Registers for symbols of special function registers.
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21.1.2 Description of “Operation” column
A:
X:
A register; 8-bit accumulator
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
PSW:
CY:
AC:
Z:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
Program status word
Carry flag
Auxiliary carry flag
Zero flag
IE:
( ):
XH, XL:
∧:
Interrupt request enable flag
Memory contents indicated by address or register contents in parenthesis
Higher 8 bits and lower 8 bits of 16-bit register
Logical product (AND)
∨:
Logical sum (OR)
V:
:
Exclusive logical sum (exclusive OR)
Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
21.1.3 Description of “Flag” column
(Blank): Unchanged
0:
1:
x:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is restored
R:
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CHAPTER 21 INSTRUCTION SET
21.2 Operation List
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
AC CY
MOV
r, #byte
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
r ← byte
saddr, #byte
sfr, #byte
A, r
(saddr) ← byte
sfr ← byte
A ← r
Note 1
Note 1
r, A
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
x
x
x
x
x
x
[DE], A
A, [HL]
[HL], A
(HL) ← A
A, [HL+byte]
[HL+byte], A
A, X
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
XCH
Note 2
A, r
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ sfr
A, [DE]
A ↔ (DE)
A ↔ (HL)
A ↔ (HL + byte)
A, [HL]
A, [HL+byte]
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 21 INSTRUCTION SET
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
AC CY
MOVW
rp, #word
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
rp ← word
AX, saddrp
saddrp, AX
AX, rp
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
Note
Note
Note
rp, AX
rp ← AX
XCHW
ADD
AX, rp
AX ↔ rp
A, #byte
saddr, #byte
A, r
A, CY ← A + byte
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
ADDC
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
A, [HL+byte]
A, #byte
saddr, #byte
A, r
SUB
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, [HL+byte]
A, CY ← A − (HL + byte)
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 21 INSTRUCTION SET
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
AC CY
SUBC
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY ← A − byte − CY
x
x
x
x
x
x
x
x
x
x
x
x
x
x
saddr, #byte
A, r
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A ← A ∧ byte
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
AND
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
A, saddr
A, !addr16
A, [HL]
A ← A ∧ (saddr)
A ← A ∧ (addr16)
A ← A ∧ (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A ← A ∧ (HL + byte)
A ← A ∨ byte
OR
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A ← A ∨ (HL + byte)
A ← A V byte
XOR
(saddr) ← (saddr) V byte
A ← A V r
A, saddr
A, !addr16
A, [HL]
A ← A V (saddr)
A ← A V (addr16)
A ← A V (HL)
A, [HL+byte]
A ← A V (HL + byte)
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 21 INSTRUCTION SET
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
AC CY
CMP
A, #byte
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
10
6
6
4
6
10
2
2
2
A − byte
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
saddr, #byte
A, r
(saddr) − byte
A − r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
AX, #word
AX, #word
AX, #word
r
A − (saddr)
A − (addr16)
A − (HL)
A − (HL + byte)
ADDW
SUBW
CMPW
INC
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
r ← r + 1
saddr
r
(saddr) ← (saddr) + 1
r ← r − 1
DEC
saddr
rp
(saddr) ← (saddr) − 1
rp ← rp + 1
INCW
DECW
ROR
rp
rp ← rp − 1
A, 1
(CY, A7 ← A0, Am−1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
(saddr.bit) ← 1
sfr.bit ← 1
x
x
x
x
ROL
A, 1
RORC
ROLC
SET1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
A.bit ← 1
PSW.bit
[HL].bit
saddr.bit
sfr.bit
PSW.bit ← 1
x
x
x
x
x
(HL).bit ← 1
CLR1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit
A.bit ← 0
PSW.bit
[HL].bit
CY
PSW.bit ← 0
x
(HL).bit ← 0
SET1
CLR1
NOT1
CY ← 1
1
0
x
CY
CY ← 0
CY
CY ← CY
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 21 INSTRUCTION SET
Mnemonic
Operands
Operation
Flag
Bytes Clocks
Z
AC CY
CALL
!addr16
[addr5]
3
1
6
8
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3
R
R
R
R
R
R
PUSH
POP
PSW
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
2
4
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW ← (SP), SP ← SP + 1
rp
PSW
4
rp
6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP ← AX
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
8
6
AX ← SP
6
PC ← addr16
6
PC ← PC + 2 + jdisp8
6
PCH ← A, PCL ← X
BC
$saddr16
$saddr16
$saddr16
$saddr16
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
BNC
BZ
6
6
BNZ
BT
6
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
10
10
8
10
10
10
8
BF
10
6
DBNZ
C, $addr16
6
saddr, $addr16
8
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable interrupt)
IE ← 0 (Disable interrupt)
Set HALT mode
DI
HALT
STOP
Set STOP mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 21 INSTRUCTION SET
21.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
A
#byte
A
r
sfr
saddr
PSW
MOV
[DE]
[HL]
1
None
!addr16
[HL+byte] $addr1
6
ADD
ADDC
SUB
SUBC
AND
OR
MOVNote MOV
XCHNote XCH
ADD
ADDC
SUB
MOV
XCH
ADD
ADDC ADDC
SUB SUB
SUBC SUBC
MOV
ADD
MOV
XCH
MOV
XCH
ADD
ADDC ADDC
SUB SUB
SUBC SUBC
MOV
XCH
ADD
ROR
ROL
RORC
ROLC
SUBC
XOR
CMP
AND
OR
AND
OR
AND
OR
AND
OR
AND
OR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV
MOV
INC
DEC
B, C
sfr
DBNZ
DBNZ
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
MOV
MOV
[HL]
[HL+byte]
Note Except r = A.
User’s Manual U15331EJ4V1UD
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CHAPTER 21 INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
AX
rpNote
saddrp
SP
None
AX
ADDW
SUBW
CMPW
MOVW
XCHW
MOVW
MOVW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
saddrp
sp
MOVW
MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
$addr16
None
1st Operand
A.bit
BT
BF
SET1
CLR1
sfr.bit
BT
BF
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BT
BF
SET1
CLR1
BT
BF
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
340
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CHAPTER 21 INSTRUCTION SET
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX
!addr16
[addr5]
$addr16
Basic Instructions
BR
CALL
BR
CALLT
BR
BC
BNC
BZ
BNZ
Compound Instructions
DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
User’s Manual U15331EJ4V1UD
341
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Conditions
Ratings
Unit
Power supply voltage
VDD
VDD = AVDD
−0.3 to +6.5
V
AVDD
VPP
VI1
µPD78F9488, 78F9489 only, Note 1
−0.3 to +10.5
−0.3 to VDD + 0.3Note 3
V
V
Input voltage
P00 to P07, P10, P11, P20 to P25, P30 to
P34, P60 to P67, P70 to P73Note 2
,
P80 to P87Note 2, X1, X2, XT1, XT2, RESET
VI2
P50 to P53
N-ch open drain
−0.3 to +13
V
V
V
On-chip pull-up resistor
−0.3 to VDD + 0.3Note 3
−0.3 to VDD + 0.3Note 3
Output voltage
VO
P00 to P07, P10, P11, P20 to P25,
P30 to P34, P50 to P53, P80 to P87 Note 2
S0 to S15, S16 to S27Note 2, COM0 to COM3
−0.3 to VLC0 + 0.3
−10
V
Output current, high
IOH
IOL
TA
Per pin
mA
mA
mA
mA
°C
Total for all pins
−30
Output current, low
Per pin
30
Total for all pins
160
Operating ambient temperature
Storage temperature
Normal operation
−40 to +85
10 to 40
−65 to +150
−40 to +125
Flash memory programming
µPD789488, 789489
µPD78F9488, 78F9489
°C
Tstg
°C
°C
Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
a
b
VPP
1.8 V
0 V
2. Only when selected by a mask option or port function register
3. 6.5 V or less
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
User’s Manual U15331EJ4V1UD
343
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit
Parameter
Oscillation frequency (fX)Note 1
Conditions
MIN.
TYP.
MAX.
5.0
4
Unit
MHz
ms
V
SS X1
X2
Ceramic
1.0
resonator
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage
range MIN.
C1
C2
V
SS X1
X2
Crystal
resonator
Oscillation frequency(fX)Note 1
1.0
5.0
10
30
MHz
ms
Oscillation stabilization
timeNote 2
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
C1
C2
ms
External
clock
X1 input frequency (fX)Note 1
1.0
85
5.0
MHz
ns
X2
X1
X1 input high-/low-level width
(tXH, tXL)
500
X1 input frequency (fX)Note 1
VDD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
X2
X1
X1 input high-/low-level width VDD = 2.7 to 5.5 V
(tXH, tXL)
500
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit
Parameter
Conditions
MIN.
32
TYP.
MAX.
35
Unit
kHz
Crystal
resonator
Oscillation frequency
(fXT)Note 1
32.768
(VSS
)
XT1 XT2
R1
Oscillation stabilization
timeNote 2
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
1.2
2
s
C4
C3
10
External
clock
XT1 input frequency
(fXT)Note 1
32
35
kHz
XT2
XT1
XT1 input high-/low-level
width (tXTH, tXTL)
14.3
15.6
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
User’s Manual U15331EJ4V1UD
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/6)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
10
Unit
mA
mA
mA
mA
V
Output current, low
IOL
Per pin
All pins
Per pin
All pins
80
Output current, high
Input voltage, high
IOH
–1
–15
VDD
VDD
12
VIH1
VIH2
P10, P11, P60 to P67
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.8VDD
0.9VDD
V
P50 to
P53
N-ch open
drain
V
12
V
On-chip pull- VDD = 2.7 to 5.5 V
VDD
VDD
VDD
VDD
V
up resistor
VDD = 1.8 to 5.5 V
V
VIH3
RESET, P00 to P07,
P20 to P25, P30 to P34,
P70 to P73Note, P80 to
P87 Note
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
V
V
VIH4
VIL1
VIL2
VIL3
X1, X2, XT1, XT2
P10, P11, P60 to P67
P50 to P53
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD – 0.5
VDD
V
V
V
V
V
V
V
V
VDD – 0.1
VDD
Input voltage, low
0
0
0
0
0
0
0.3VDD
0.1VDD
0.3VDD
0.1VDD
0.2VDD
0.1VDD
RESET, P00 to P07,
P20 to P25, P30 to P34,
P70 to P73Note, P80 to
P87 Note
VIL4
VOH
VOL1
X1, X2, XT1, XT2
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
0
0.4
0.1
V
V
V
V
V
0
Output voltage, high
Output voltage, low
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD – 0.5
VDD = 1.8 to 5.5 V, IOH = –100 µA
P00 to P07, P10, P11,
P20 to P25, P30 to P34,
P80 to P87Note
4.5 ≤ VDD ≤ 5.5 V,
IOL = 10 mA
1.0
1.8 ≤ VDD < 4.5 V,
IOL = 400 µA
0.5
1.0
0.4
V
V
V
VOL2
P50 to P53
4.5 ≤ VDD ≤ 5.5 V,
IOL = 10 mA
1.8 ≤ VDD < 4.5 V,
IOL = 1.6 mA
Note Only when selected by a mask option or port function register
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/6)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage current,
high
ILIH1
VI = VDD
P00 to P07, P10, P11,
µA
P20 to P25, P30 to P34,
P60 to P67,
P70 to P73Note 1, P80 to
P87Note 1, RESET
ILIH2
X1, X2, XT1, XT2
20
20
µA
µA
ILIH3
VI = 12 V
VI = 0 V
P50 to P53
(N-ch open drain)
Input leakage current,
low
ILIL1
P00 to P07, P10, P11,
P20 to P25, P30 to P34,
P60 to P67,
–3
µA
P70 to P73Note 1, P80 to
P87Note 1, RESET
ILIL2
X1, X2, XT1, XT2
–20
–3Note 2
µA
µA
ILIL3
P50 to P53
(N-ch open drain)
Output leakage current, ILOH
high
VO = VDD
VO = 0 V
VI = 0 V
VI = 0 V
3
µA
µA
kΩ
kΩ
Output leakage current, ILOL
low
–3
Software pull-up
resistor
R1
P00 to P07, P10, P11,
P20 to P25, P30 to P34
50
10
100
30
200
60
Mask option pull-up
resistorNote 3
R2
P50 to P53
Notes 1. Only when selected by a mask option or port function register
2. If there is no on-chip pull-up resistor for P50 to P53 (specified by a mask option) and if P50 to P53
have been set to input mode when a read instruction is executed to read from P50 to P53, a low-level
input leakage current of up to –60 µA flows during only one cycle. At all other times, the maximum
leakage current is –3 µA.
3. Mask ROM version only
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
User’s Manual U15331EJ4V1UD
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (3/6)
Parameter
Symbol
Conditions
MIN.
TYP.
2
MAX.
3.5
1
0.5
1.92
0.76
0.34
67
Unit
mA
mA
mA
mA
mA
mA
µA
Power supply
IDD1
5.0 MHz crystal oscillation
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
VDD = 5.0 V 10%
currentNote 1
operation mode
0.4
0.2
0.96
0.26
0.1
33
(µPD789488)
(C1 = C2 = 22 pF)
IDD2
IDD3
5.0 MHz crystal oscillation
HALT modeNote 4
(C1 = C2 = 22 pF)
32.768 kHz crystal
oscillation operation
modeNote 5
VDD = 3.0 V 10%
10
5
31
16
µA
µA
VDD = 2.0 V 10%
(C3 = C4 = 22 pF, R1 =
220kΩ)
32.768 kHz crystal
oscillation operation × 4
multiplication operation
modeNote 5
(C3 = C4 = 22 pF, R1 =
220kΩ)
VDD = 5.0 V 10%
VDD = 3.0 V 10%
130
50
200
110
µA
µA
IDD4
32.768 kHz LCD not
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
25
8
5
28
10
7
60
28
13
69
36
20
µA
µA
µA
µA
µA
µA
crystal
operatingNote 4
oscillation
HALT
modeNote 5
(C3 = C4 =
22 pF, R1 =
220kΩ)
LCD
operatingNote 7
32.768 kHz LCD not
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
25
8
28
10
60
28
69
36
µA
µA
µA
µA
crystal
operatingNote 4
oscillation × 4
multiplication
HALT
LCD
operatingNote 7
modeNote 5
(C3 = C4 =
22 pF, R1 =
220kΩ)
IDD5
STOP modeNote 6
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
0.1
0.05
0.05
3
1.1
0.7
10
5
3
5.2
2
1.5
µA
µA
µA
mA
mA
mA
IDD6
5.0 MHz crystal oscillation
A/D operating modeNote 8
(C1 = C2 = 22 pF)
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
Notes 1. The port current (including the current that flows to on-chip pull-up resistors) is not included.
2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
4. When the LCD is not operating and the booster circuit is operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 1).
5. When the main system clock is stopped
6. When the LCD is not operating (LCDON0 = 0, VAON0 = 0, LIPS0 = 0)
7. Then the LCD is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1)
8. This is the total current that flows to VDD and AVDD.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (4/6)
Parameter
Symbol
Conditions
MIN.
TYP.
5.5
1.3
0.8
1.5
0.41
0.2
115
85
MAX.
9.0
2.3
1.6
2.1
0.85
0.43
200
140
110
Unit
mA
mA
mA
mA
mA
mA
µA
Power supply
IDD1
5.0 MHz crystal oscillation
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
VDD = 5.0 V 10%
currentNote 1
operation mode
(µPD78F9488)
(C1 = C2 = 22 pF)
IDD2
IDD3
5.0 MHz crystal oscillation
HALT modeNote 4
(C1 = C2 = 22 pF)
32.768 kHz crystal
oscillation operation
modeNote 5
VDD = 3.0 V 10%
µA
µA
VDD = 2.0 V 10%
70
(C3 = C4 = 22 pF, R1 =
220kΩ)
32.768 kHz crystal
oscillation operation × 4
multiplication operation
modeNote 5
(C3 = C4 = 22 pF, R1 =
220kΩ)
VDD = 5.0 V 10%
VDD = 3.0 V 10%
315
200
480
300
µA
µA
IDD4
32.768 kHz LCD not
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
25
8
5
28
10
7
65
29
20
70
34
25
µA
µA
µA
µA
µA
µA
crystal
operatingNote 4
oscillation
HALT
modeNote 5
(C3 = C4 =
22 pF, R1 =
220kΩ)
LCD
operatingNote 7
32.768 kHz LCD not
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
25
8
28
10
65
29
70
34
µA
µA
µA
µA
crystal
operatingNote 4
oscillation × 4
multiplication
HALT
LCD
operatingNote 7
modeNote 5
(C3 = C4 =
22 pF, R1 =
220kΩ)
IDD5
STOP modeNote 6
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
0.1
0.05
0.05
6.5
2.0
1.3
10
5
3
10.2
3.3
2.6
µA
µA
µA
mA
mA
mA
IDD6
5.0 MHz crystal oscillation
A/D operating modeNote 8
(C1 = C2 = 22 pF)
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
Notes 1. The port current (including the current that flows to on-chip pull-up resistors) is not included.
2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
4. When the LCD is not operating and the booster circuit is operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 1).
5. When the main system clock is stopped
6. When the LCD is not operating (LCDON0 = 0, VAON0 = 0, LIPS0 = 0)
7. Then the LCD is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1)
8. This is the total current that flows to VDD and AVDD.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
User’s Manual U15331EJ4V1UD
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (5/6)
Parameter
Symbol
Conditions
MIN.
TYP.
2.5
0.5
0.3
1.0
0.35
0.1
38
MAX.
5.0
1.2
0.6
2.0
0.8
0.4
100
50
Unit
mA
mA
mA
mA
mA
mA
µA
Power supply
IDD1
5.0 MHz crystal oscillation
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
VDD = 5.0 V 10%
currentNote 1
operation mode
(µPD789489)
(C1 = C2 = 22 pF)
IDD2
IDD3
5.0 MHz crystal oscillation
HALT modeNote 4
(C1 = C2 = 22 pF)
32.768 kHz crystal
oscillation operation
modeNote 5
VDD = 3.0 V 10%
13
7
µA
µA
VDD = 2.0 V 10%
25
(C3 = C4 = 22 pF, R1 =
220kΩ)
32.768 kHz crystal
oscillation operation × 4
multiplication operation
modeNote 5
(C3 = C4 = 22 pF, R1 =
220kΩ)
VDD = 5.0 V 10%
VDD = 3.0 V 10%
150
75
250
160
µA
µA
IDD4
32.768 kHz LCD not
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
25
8
5
28
10
7
70
32
15
79
40
27
µA
µA
µA
µA
µA
µA
crystal
operatingNote 4
oscillation
HALT
modeNote 5
(C3 = C4 =
22 pF, R1 =
220kΩ)
LCD
operatingNote 7
32.768 kHz LCD not
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
25
8
28
10
70
32
79
40
µA
µA
µA
µA
crystal
operatingNote 4
oscillation × 4
multiplication
HALT
LCD
operatingNote 7
modeNote 5
(C3 = C4 =
22 pF, R1 =
220kΩ)
IDD5
STOP modeNote 6
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
0.1
0.05
0.05
5.0
1.5
0.8
10
5
3
6.7
2.2
1.6
µA
µA
µA
mA
mA
mA
IDD6
5.0 MHz crystal oscillation
A/D operating modeNote 8
(C1 = C2 = 22 pF)
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
Notes 1. The port current (including the current that flows to on-chip pull-up resistors) is not included.
2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
4. When the LCD is not operating and the booster circuit is operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 1).
5. When the main system clock is stopped
6. When the LCD is not operating (LCDON0 = 0, VAON0 = 0, LIPS0 = 0)
7. Then the LCD is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1)
8. This is the total current that flows to VDD and AVDD.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
350
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (6/6)
Parameter
Symbol
Conditions
MIN.
TYP.
6.0
1.6
1.0
1.6
0.5
0.3
130
90
MAX.
12.0
3.2
2.5
3.0
1.2
0.6
250
180
160
Unit
mA
mA
mA
mA
mA
mA
µA
Power supply
IDD1
5.0 MHz crystal oscillation
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
VDD = 5.0 V 10%
currentNote 1
operation mode
(µPD78F9489)
(C1 = C2 = 22 pF)
IDD2
IDD3
5.0 MHz crystal oscillation
HALT modeNote 4
(C1 = C2 = 22 pF)
32.768 kHz crystal
oscillation operation
modeNote 5
VDD = 3.0 V 10%
µA
µA
VDD = 2.0 V 10%
80
(C3 = C4 = 22 pF, R1 =
220kΩ)
32.768 kHz crystal
oscillation operation × 4
multiplication operation
modeNote 5
(C3 = C4 = 22 pF, R1 =
220kΩ)
VDD = 5.0 V 10%
VDD = 3.0 V 10%
330
250
550
400
µA
µA
IDD4
32.768 kHz LCD not
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
25
8
5
28
10
7
70
32
15
79
40
27
µA
µA
µA
µA
µA
µA
crystal
operatingNote 4
oscillation
HALT
modeNote 5
(C3 = C4 =
22 pF, R1 =
220kΩ)
LCD
operatingNote 7
32.768 kHz LCD not
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 5.0 V 10%
VDD = 3.0 V 10%
25
8
28
10
70
32
79
40
µA
µA
µA
µA
crystal
operatingNote 4
oscillation × 4
multiplication
HALT
LCD
operatingNote 7
modeNote 5
(C3 = C4 =
22 pF, R1 =
220kΩ)
IDD5
STOP modeNote 6
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
0.1
0.05
0.05
7.0
2.3
1.5
10
5
3
14.0
4.2
3.5
µA
µA
µA
mA
mA
mA
IDD6
5.0 MHz crystal oscillation
A/D operating modeNote 8
(C1 = C2 = 22 pF)
VDD = 5.0 V 10%Note 2
VDD = 3.0 V 10%Note 3
VDD = 2.0 V 10%Note 3
Notes 1. The port current (including the current that flows to on-chip pull-up resistors) is not included.
2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
4. When the LCD is not operating and the booster circuit is operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 1).
5. When the main system clock is stopped
6. When the LCD is not operating (LCDON0 = 0, VAON0 = 0, LIPS0 = 0)
7. Then the LCD is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1)
8. This is the total current that flows to VDD and AVDD.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
User’s Manual U15331EJ4V1UD
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
8.0
Unit
µs
Cycle time (minimum
instruction execution
time)
TCY
Operating with main system VDD = 2.7 to 5.5 V
clock
VDD = 1.8 to 5.5 V
1.6
8.0
µs
Operating
with
subsystem
clock
Original
VDD = 1.8 to 5.5 V
114
122
125
µs
oscillation
operation
× 4
VDD = 2.7 to 5.5 V
14.3
10
15.3
15.6
µs
µs
multiplication
operation
Capture input high-/low- tCPTH,
CPT20
level width
tCPTL
TMI60, TMI61 input
frequency
fTI
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
INTP0 to INTP3
0
0
4
MHz
kHz
µs
275
TMI60, TMI61 input
high-/low-level width
tTIH,
tTIL
0.125
1.8
10
µs
Interrupt input high-
/low-level width
tINTH,
tINTL
µs
Key return input low-
level width
tKRL
tRSL
KR0 to KR7(µPD789488, 78F9488)
10
10
µs
µs
KR00 to KR07, KR10 to KR17 (µ789489,
78F9489)
RESET low-level width
10
µs
TCY vs. VDD (main system clock)
60
10
8.0
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Power supply voltage VDD (V)
352
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
(2) Serial interface 20 (SIO20) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (internal clock output)
Parameter
Symbol
Conditions
MIN.
800
TYP.
TYP.
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY1
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
SCK20 high-/low-level
width
tKH1,
tKL1
t
KCY1/2–50
t
KCY1/2–150
150
500
400
600
0
SI20 setup time
(to SCK20↑)
tSIK1
tKSI1
SI20 hold time
(from SCK20↑)
Delay time from SCK20↓ tKSO1
to SO20 output
R = 1 kΩ, C = 100 pFNote VDD = 2.7 to 5.5 V
250
VDD = 1.8 to 5.5 V
0
1000
Note R and C are the load resistance and load capacitance of the SO20 output line.
(b) 3-wire serial I/O mode (external clock input)
Parameter
Symbol
Conditions
MIN.
800
3200
400
1600
100
150
400
600
0
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK20 high-/low-level
width
tKH2,
tKL2
SI20 setup time
(to SCK20↑)
tSIK2
tKSI2
SI20 hold time
(from SCK20↑)
Delay time from SCK20↓ tKSO2
to SO20 output
R = 1 kΩ, C = 100 pFNote VDD = 2.7 to 5.5 V
300
VDD = 1.8 to 5.5 V
0
1000
Note R and C are the load resistance and load capacitance of the SO20 output line.
(c) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
MAX.
78125
19531
Unit
bps
bps
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
User’s Manual U15331EJ4V1UD
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
(d) UART mode (external clock input)
Parameter
Symbol
Conditions
MIN.
800
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
400
ns
ASCK20 high-/low-level tKH3,
ns
width
tKL3
1600
ns
Transfer rate
39063
9766
1
bps
bps
µs
ASCK20 rise/fall time
tR,
tF
354
User’s Manual U15331EJ4V1UD
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
(3) Serial interface 1A0 (SIO1A0) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode, 3-wire serial I/O mode with automatic transmit/receive function
(internal clock output)
Parameter
Symbol
Conditions
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK10 cycle time
tKCY4
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
SCK10 high-/low-level
width
tKH4,
tKL4
tKCY4/2–50
t
KCY4/2–150
150
500
400
600
0
SI10 setup time
(to SCK10↑)
tSIK4
tKSI4
SI10 hold time
(from SCK10↑)
Delay time from SCK10↓ tKSO4
to SO10 output
R = 1 kΩ, C = 100 pFNote VDD = 2.7 to 5.5 V
250
VDD = 1.8 to 5.5 V
0
1000
Note R and C are the load resistance and load capacitance of the SO10 output line.
(b) 3-wire serial I/O mode, 3-wire serial I/O mode with automatic transmit/receive function
(external clock input)
Parameter
Symbol
Conditions
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK10 cycle time
tKCY5
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK10 high-/low-level
width
tKH5,
tKL5
SI10 setup time
(to SCK10↑)
tSIK5
tKSI5
SI10 hold time
(from SCK10↑)
Delay time from SCK10↓ tKSO5
to SO10 output
R = 1 kΩ, C = 100 pFNote VDD = 2.7 to 5.5 V
300
VDD = 1.8 to 5.5 V
0
1000
Note R and C are the load resistance and load capacitance of the SO10 output line.
User’s Manual U15331EJ4V1UD
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
AC Timing Measurement Points (Excluding X1 and XT1 Inputs)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Point of measurement
Clock Timing
1/f
X
t
XL
t
XH
V
IH4 (MIN.)
X1 input
V
IL4 (MAX.)
1/fXT
t
XTL
t
XTH
V
IH4 (MIN.)
XT1 input
V
IL4 (MAX.)
Capture Input Timing
t
CPTH
t
CPTL
CPT20
TMI Timing
1/fTI
t
TIL
t
TIH
TMI60, TMI61
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP3
356
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
Key Return Input Timing
t
KRL
KR0 to KR7
µ
(
PD789488, 78F9488) ,
KR00 to KR07, KR10 to KR17
( µPD789489, 78F9489)
RESET Input Timing
t
RSL
RESET
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK10, SCK20
t
SIKm
t
KSIm
SI10, SI20
Input data
t
KSOm
Output data
SO10, SO20
Remark m = 1, 2, 4, 5
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
User’s Manual U15331EJ4V1UD
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
10-Bit A/D Converter Characteristics
(TA = –40 to +85°C, 1.8 V ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions
Resolution
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Overall errorNote
4.5 V ≤ AVDD ≤ 5.5 V
0.2
0.4
0.8
0.4
0.6
1.2
100
100
100
0.4
0.6
1.2
0.4
0.6
1.2
2.5
4.5
8.5
1.5
2.0
3.5
AVDD
%FSR
%FSR
%FSR
µs
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
4.5 V ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
4.5 V ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
4.5 V ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
4.5 V ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
4.5 V ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
Conversion time
tCONV
14
14
28
µs
µs
Zero-scale errorNote
Full-scale errorNote
Non-integral linearityNote
AINL
AINL
INL
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
Non-differential
linearityNote
DNL
LSB
LSB
LSB
Analog input voltage
VIAN
0
V
Note Excludes quantization error ( 0.05%)
Remark FSR: Full scale range
358
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
LCD Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
C1 to C4Note 1 = 0.47 µF GAIN = 1
GAIN = 0
C1 to C4Note 1 = 0.47 µF
C1 to C4Note 1 = 0.47 µF
MIN.
TYP.
1.0
MAX.
1.165
1.74
Unit
V
V
V
V
s
LCD output voltage
variation range
VLCD2
0.84
1.26
1.5
Doubler output
Tripler output
VLCD1
VLCD0
tVAWAIT
2VLCD2 –0.1
2VLCD2
3VLCD2
2VLCD2
3VLCD2
3VLCD2 –0.15
Voltage boost wait
timeNote 2
GAIN = 0
GAIN = 1
1.8 ≤ VDD < 5.5 V
0.5
2.0
1.0
0.5
0
5.0 ≤ VDD ≤ 5.5 V
4.5 ≤ VDD < 5.0 V
1.8 ≤ VDD < 4.5 V
s
s
s
LCD output voltage
VODC
IO = 5 µA
IO = 1 µA
0.2
0.2
V
differentialNote 3 (common)
LCD output voltage
VODS
0
V
differentialNote 3 (segment)
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VLC0 and VSS
C3: A capacitor connected between VLC1 and VSS
C4: A capacitor connected between VLC2 and VSS
2. This is the wait time from when voltage boosting is started (VAON0 = 1) until display is enabled
(LCDON0 = 1).
3. The voltage differential is the difference between the segment and common signal output’s actual and
ideal output voltages.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention power
supply voltage
VDDDR
Release signal set time
tSREL
0
µs
User’s Manual U15331EJ4V1UD
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operation mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
STOP mode
Operation mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
Oscillation Stabilization Wait Time (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions
Release by RESET
Release by interrupt
MIN.
TYP.
215/fX
MAX.
Unit
Oscillation stabilization wait tWAIT
timeNote 1
s
s
Note 2
Notes 1. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time.
2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time selection register (OSTS).
Remark fX: Main system clock oscillation frequency
360
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489)
Flash Memory Writing and Erasing Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V)
(µPD78F9488, 78F9489 only)
Parameter
Symbol
Conditions
2.7 V ≤ VDD ≤ 5.5 V
MIN.
1.0
TYP.
MAX.
5
Unit
MHz
MHz
mA
Write/erase operating frequency
fX
1.8 V ≤ VDD ≤ 5.5 V
1.0
1.25
7
Write current (VDD pin)Note
IDDW
When VPP supply voltage = VPP1
(at 5.0 MHz operation)
Write current (VPP pin)Note
Erase current (VDD pin)Note
IPPW
IDDE
When VPP supply voltage = VPP1
13
7
mA
mA
When VPP supply voltage = VPP1
(at 5.0 MHz operation)
Erase current (VPP pin)Note
Unit erase time
IPPE
ter
When VPP supply voltage = VPP1
100
1
mA
0.5
1
s
s
Total erase time
tera
20
20
Number of overwrites
Erase and write is considered as 1
cycle
Times
VPP supply voltage
VPP0
Normal operation
0
0.2VDD
10.3
V
V
VPP1
Flash memory programming
9.7
10.0
Note Excludes current flowing through ports (including on-chip pull-up resistors)
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CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER
(REFERENCE VALUES)
(1) Characteristics curves of voltage boosting stabilization time
The following shows the characteristics curves of the time from the start of voltage boosting (VAON0 = 1) and
the changes in the LCD output voltage (when GAIN is set as 1 (using the 3 V display panel)).
LCD output voltage/Voltage boosting time
5.5
5
4.5
4
V
DD = 4.5 V
V
DD = 5 V
VDD = 5.5 V
3.5
3
V
LCD0
2.5
2
V
V
LCD1
LCD2
1.5
1
0.5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Voltage boosting time [ms]
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CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES)
(2) Temperature characteristics of LCD output voltage
The following shows the temperature characteristics curves of LCD output voltage.
LCD output voltage/Temperature (When GAIN = 1)
V
LCD2
V
LCD1
V
LCD0
5
4
3
2
1
0
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
Temperature [˚C]
LCD output voltage/Temperature (When GAIN = 0)
5
4
3
2
1
0
V
LCD2
V
LCD1
V
LCD0
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
Temperature [˚C]
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CHAPTER 24 PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
21
20
1
F
J
M
G
H
I
P
K
S
N
S
L
M
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
G
H
I
17.20 0.20
14.00 0.20
14.00 0.20
17.20 0.20
0.825
0.825
0.32 0.06
0.13
J
0.65 (T.P.)
1.60 0.20
0.80 0.20
K
L
+0.03
0.17
M
−0.07
N
P
0.10
1.40 0.10
0.125 0.075
Q
+7°
3°
R
S
−3°
1.70 MAX.
P80GC-65-8BT-1
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CHAPTER 24 PACKAGE DRAWINGS
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A
B
60
41
61
40
detail of lead end
S
C
D
P
T
R
80
21
L
1
20
U
Q
F
M
G
J
H
I
K
S
M
N
S
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
G
H
I
14.0 0.2
12.0 0.2
12.0 0.2
14.0 0.2
1.25
1.25
0.22 0.05
0.08
J
0.5 (T.P.)
1.0 0.2
0.5
K
L
M
N
P
Q
0.145 0.05
0.08
1.0
0.1 0.05
+4°
3°
R
−3°
S
T
1.1 0.1
0.25
U
0.6 0.15
P80GK-50-9EU-1
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365
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS
The µPD789489 subseries should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 25-1. Surface Mounting Type Soldering Conditions (1/3)
(1) µ PD789488GC-×××-8BT: 80-pin plastic QFP (14x14)
µ PD78F9488GC-8BT:
80-pin plastic QFP (14x14)
µ PD789489GC-×××-8BT: 80-pin plastic QFP (14x14)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
VPS
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Twice or less
IR35-00-2
VP15-00-2
WS60-00-1
–
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Twice or less
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
(2) µ PD789488GK-×××-9EU: 80-pin plastic TQFP (fine pitch) (12x12)
µ PD78F9488GK-9EU:
80-pin plastic TQFP (fine pitch) (12x12)
µ PD789489GK-×××-9EU: 80-pin plastic TQFP (fine pitch) (12x12)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Interface reflow
VPS
Package peak temperature: 235°C, Time:30 seconds max. (at 210°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 hours)
IR35-107-2
VP15-107-2
−
Package peak temperature: 215°C, Time:40 seconds max. (at 200°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 hours)
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry peak, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
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CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS
Table 25-1. Surface Mounting Type Soldering Conditions (2/3)
(3) µ PD78F9489GC-8BT:
80-pin plastic QFP (14x14)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Interface reflow
Package peak temperature: 235°C, Time:30 seconds max. (at 210°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Time:40 seconds max. (at 200°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 hours)
VP15-107-2
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
WS60-107-1
–
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry peak, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(4) µ PD78F9489GK-9EU:
Soldering Method
80-pin plastic TQFP (fine pitch) (12x12)
Soldering Conditions
Recommended
Condition Symbol
Interface reflow
VPS
Package peak temperature: 235°C, Time:30 seconds max. (at 210°C or higher),
Count: Twice or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
10 hours)
IR35-103-2
VP15-103-2
–
Package peak temperature: 215°C, Time:40 seconds max. (at 200°C or higher),
Count: Twice or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
10 hours)
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry peak, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
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CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS
Table 25-1. Surface Mounting Type Soldering Conditions (3/3)
(5) µ PD789488GC-×××-8BT-A: 80-pin plastic QFP (14x14)
µ PD78F9488GC-8BT-A: 80-pin plastic QFP (14x14)
µ PD789489GC-×××-8BT-A: 80-pin plastic QFP (14x14)
µ PD78F9489GC-8BT-A: 80-pin plastic QFP (14x14)
µ PD789488GK-×××-9EU-A: 80-pin plastic TQFP (fine pitch) (12x12)
µ PD78F9488GK-9EU-A: 80-pin plastic TQFP (fine pitch) (12x12)
µ PD789489GK-×××-9EU-A: 80-pin plastic TQFP (fine pitch) (12x12)
µ PD78F9489GK-9EU-A:
80-pin plastic TQFP (fine pitch) (12x12)
Recommended Condition
Symbol
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C
or higher), Count: Three times or less, Exposure limit: 7 daysNote (after
that, prebake at 125°C for 20 to 72 hours)
IR60-207-3
Wave soldering
When the pin pitch of the package is 0.65 mm or more, wave soldering
can also be performed.
−
For details, contact an NEC Electronics sales representative.
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
−
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remarks 1. Products that have the part numbers suffixed by "-A" are lead-free products.
2. For soldering methods and conditions other than those recommended above, contact an NEC
Electronics sales representative.
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APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD789489 Subseries.
Figure A-1 shows development tools.
• Support for PC98-NX Series
Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in the PC98-NX
Series. When using the PC98-NX Series, refer to the explanation of IBM PC/AT compatibles.
• Windows™
Unless specified otherwise, “Windows” indicates the following operating systems.
• Windows 3.1
• Windows 95
• Windows 98
• Windows 2000
• Windows NT™ Ver.4.0
• Windows XP
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tools
Software package
·
Software package
Language processing software
Debugging software
·
·
·
·
Assembler package
C compiler package
Device file
·
Integrated debugger
System simulator
·
C library source fileNote 1
Control software
Project manager
(Windows version only)Note 2
·
Host machine
(PC or EWS)
Interface adapter
Power supply unit
Flash memory writing environment
Flash programmer
In-circuit emulator
Emulation board
Flash memory
writing adapter
Flash memory
Emulation probe
Conversion socket or
conversion adapter
Target system
Notes 1. C library source file is not included in the software package.
2. The project manager is included in the assembler package.
The project manager is used only in the Windows environment.
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370
APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0S
Software package
Software tools for development of the 78K/0S Series are combined in this package.
The following tools are included.
RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files
Part number: µS××××SP78K0S
Remark ×××× in the part number differs depending on the OS used
µS××××SP78K0S
××××
AB17
BB17
Host Machine
OS
Supply Medium
CD-ROM
PC-9800 series, IBM PC/AT
compatibles
Japanese Windows
English Windows
A.2 Language Processing Software
RA78K0S
Assembler package
Program that converts program written in mnemonic into object codes that can be executed
by a microcontroller.
In addition, automatic functions to generate symbol tables and optimize branch instructions
are also provided.
Used in combination with a device file (DF789488) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows
environment by using the project manager of Windows (included in the assembler package).
Part number: µS××××RA78K0S
CC78K0S
C compiler package
Program that converts program written in C language into object codes that can be executed
by a microcontroller.
Used in combination with an assembler package (RA78K0S) and device file (DF789488)
(both sold separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows
environment by using the project manager of Windows (included in the assembler package).
Part number: µS××××CC78K0S
DF789488Note 1
Device file
File containing information inherent to the device.
Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold
separately).
Part number: µS××××DF789488
CC78K0S-LNote 2
C library source file
Source file of functions for generating object library included in the C compiler package.
Necessary for changing the object library included in the C compiler package according to
the customer’s specifications. Since this is a source file, its working environment does not
depend on any particular operating system.
Part number: µS××××CC78K0S-L
Notes 1. DF789488 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and
SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
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APPENDIX A DEVELOPMENT TOOLS
Remark ×××× in the part number differs depending on the host machine and operating system to be used.
µS××××RA78K0S
µS××××CC78K0S
××××
AB13
BB13
AB17
BB17
3P17
3K17
Host Machine
PC-9800 series,
IBM PC/AT compatible
OS
Supply Medium
3.5" 2HD FD
Japanese Windows
English Windows
Japanese Windows
CD-ROM
English Windows
HP9000 series 700TM
SPARCstationTM
HP-UXTM (Rel. 10.10)
SunOSTM (Rel. 4.1.4),
SolarisTM (Rel. 2.5.1)
µS××××DF789488
µS××××CC78K0S-L
××××
Host Machine
OS
Supply Medium
AB13
BB13
3P16
3K13
3K15
PC-9800 series,
IBM PC/AT compatible
Japanese Windows
Japanese Windows
HP-UXTM (Rel. 10.10)
SunOSTM (Rel. 4.1.4),
SolarisTM (Rel. 2.5.1)
3.5" 2HD FD
HP9000 series 700
SPARCstation
DAT
3.5" 2HD FD
1/4-inch CGMT
A.3 Control Software
PM plus
Control software created for efficient development of the user program in the Windows
environment. User program development operations such as editor startup, build, and
debugger startup can be performed from the PM plus.
Project manager
<Caution>
The PM plus is included in the assembler package (RA78K0S).
The PM plus is used only in the Windows environment.
A.4 Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3)
Flashpro IV (FL-PR4, PG-FP4)
Flash programmer
Dedicated flash programmer for microcontrollers incorporating flash memory
FA-80GC-8BT
FA-80GK-9EU
Adapter for writing to flash memory and connected to Flashpro III or Flashpro IV.
• FA-80GC-8BT: For 80-pin plastic QFP (GC-8BT type)
Flash memory writing adapter
• FA-80GK-9EU: For 80-pin plastic TQFP (GK-9EU type)
Remark The FL-PR3, FL-PR4, FA-80GC-8BT, and FA-80GK-9EU are products made by Naito Densei Machida
Mfg. Co., Ltd. (TEL +81-45-475-4191).
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APPENDIX A DEVELOPMENT TOOLS
A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator
In-circuit emulator for debugging hardware and software of an application system using the
78K/0S Series. Can be used with the integrated the debugger ID78K0S-NS. Used in
combination with an AC adapter, emulation probe, and interface adapter for connecting the host
machine.
IE-78K0S-NS-A
In-circuit emulator
The IE-78K0S-NS-A provides a coverage function in addition to the IE-78K0S-NS functions, thus
enhancing the debug functions, including the tracer and timer functions.
IE-70000-MC-PS-B
AC adapter
Adapter for supplying power from AC 100 to 240 V outlet.
IE-70000-98-IF-C
Interface adapter
Adapter necessary when using a PC-9800 series PC (except notebook type) as the host machine
(C bus supported)
IE-70000-CD-IF-A
PC card interface
PC card and interface cable necessary when using a notebook PC as the host machine
(PCMCIA socket supported)
IE-70000-PC-IF-C
Interface adapter
Interface adapter necessary when using an IBM PC/AT compatible as the host machine (ISA bus
supported)
IE-70000-PCI-IF-A
Interface adapter
Adapter necessary when using a personal computer incorporating a PCI bus as the host machine
IE-789488-NS-EM1
Emulation board
Board for emulating the peripheral hardware inherent to the device. Used in combination with an
in-circuit emulator.
NP-80GC
Emulation probe
Cable to connect the in-circuit emulator and target system.
Used in combination with the EV-9200GC-80.
EV-9200GC-80 Conversion socket to connect the NP-80GC and a target system board on which an 80-pin plastic
Conversion
socket
QFP (GC-8BT type) can be mounted.
NP-80GC-TQ
NP-H80GC-TQ
Emulation prove
Cable to connect the in-circuit emulator and target system.
Used in combination with the TGC-080SBP.
TGC-080SBP
Conversion
adapter
Conversion adapter to connect the NP-80GC-TQ or NP-H80GC-TQ and a target system board on
which an 80-pin plastic QFP (GC-8BT type) can be mounted.
NP-80GK
NP-H80GK-TQ
Emulation prove
Cable to connect the in-circuit emulator and target system.
Used in combination with the TGK-080SDW.
TGK-080SDW
Conversion
adapter
Conversion adapter to connect the NP-80GK or NP-H80GK-TQ and a target system board on
which an 80-pin plastic TQFP (GK-9EU type) can be mounted
Remarks 1. The NP-80GC, NP-80GC-TQ, NP-H80GC-TQ, NP-80GK, and NP-H80GK-TQ are products of Naito
Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191).
2. The TGC-080SBP and TGK-080SDW are products of TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
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APPENDIX A DEVELOPMENT TOOLS
A.6 Debugging Tools (Software)
ID78K0S-NS
Integrated debugger
This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the
78K/0S Series. The ID78K0S-NS is Windows-based software.
It has improved C-compatible debugging functions and can display the results of tracing with
the source program using an integrating window function that associates the source
program, disassemble display, and memory display with the trace result.
Used in combination with a device file (DF789488) (sold separately).
Part number: µS××××ID78K0S-NS
SM78K0S
System simulator
This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based
software.
It can be used to debug the target system at C source level or assembler level while
simulating the operation of the target system on the host machine.
Using SM78K0S, the logic and performance of the application can be verified independently
of hardware development. Therefore, the development efficiency can be enhanced and the
software quality can be improved.
in combination with a device file (DF789488) (sold separately).
Used
Part number: µS××××SM78K0S
DF789488Note
Device file
File containing the information inherent to the device.
Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold
separately).
Part number: µS××××DF789488
Note DF789488 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Remark ×××× in the part number differs depending on the operating system and supply medium to be used.
µS××××ID78K0S-NS
µS××××SM78K0S
××××
AB13
BB13
AB17
BB17
Host Machine
PC-9800 series
IBM PC/AT compatibles
OS
Japanese Windows
English Windows
Japanese Windows
English Windows
Supply Media
3.5" 2HD FD
CD-ROM
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Figures B-1 to B-6 show the conditions when connecting the emulation probe to the conversion adapter or
conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target
system when designing a system.
Of the products described in this chapter, the NP-80GC, NP-80GC-TQ, NP-H80GC-TQ, NP-80GK and NP-H80GK-
TQ are products of Naito Densei Machida Mfg. Co., Ltd, and the TGC-080SBP and TGK-080SDP are products of
TOKYO ELETECH CORPORATION.
Table B-1. Distance Between IE System and Conversion Adapter
Emulation Probe
NP-80GC-TQ
NP-H80GC-TQ
NP-80GK
Conversion Adapter
TGC-080SBP
Distance Between IE System and Conversion Adapter
170 mm
370 mm
170 mm
370 mm
TGK-080SDP
NP-H80GK-TQ
(1) NP-80GC, NP-80GC-TQ, NP-H80GC-TQ
Figure B-1. Distance Between In-Circuit Emulator and Conversion Socket (80GC)
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Target system
Emulation board
IE-789488-NS-EM1
170 mmNote
TGCN1
Emulation probe
NP-80GC-TQ
Conversion adapter: TGC-080SBP
NP-H80GC-TQ
Note Distance when NP-80GC-TQ is used. When NP-H80GC-TQ is used, the distance is 370 mm.
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Figure B-2. Connection Conditions of Target System (When NP-80GC-TQ Is Used)
Emulation board
IE-789488-NS-EM1
Emulation probe
NP-80GC-TQ
24.8 mm
Conversion adapter
TGC-080SBP
11 mm
25 mm
21 mm
Pin 1
21 mm
40 mm
34 mm
Target system
Figure B-3. Connection Conditions of Target System (When NP-H80GC-TQ Is Used)
Emulation board
IE-789488-NS-EM1
Emulation probe
NP-H80GC-TQ
25.3 mm
Conversion adapter
TGC-080SBP
11 mm
25 mm
21 mm
Pin 1
21 mm
42 mm
45 mm
Target system
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
(2) NP-80GK, NP-H80GK-TQ
Figure B-4. Distance Between In-Circuit Emulator and Conversion Adapter (80GK)
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Target system
Emulation board
IE-789488-NS-EM1
170 mmNote
TGCN1
Emulation probe
NP-80GK, NP-H80GK-TQ
Conversion adapter
TGK-080SDP
Note Distance when NP-80GK is used. When NP-H80GK-TQ is used, the distance is 370 mm.
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Figure B-5. Connection Conditions of Target System (When NP-80GK Is Used)
Emulation board
IE-789488-NS-EM1
Emulation probe
NP-80GK
23 mm
Conversion adapter
TGK-080SDP
11 mm
25 mm
16 mm
Pin 1
16 mm
40 mm
34 mm
Target system
Figure B-6. Connection Conditions of Target System (When NP-H80GK-TQ Is Used)
Emulation board
IE-789488-NS-EM1
Emulation probe
NP-H80GK-TQ
23 mm
Conversion adapter
11 mm
TGK-080SDP
10 mm
16 mm
Pin 1
16 mm
42 mm
45 mm
Target system
378
User’s Manual U15331EJ4V1UD
APPENDIX C REGISTER INDEX
C.1 Register Index (Register Names in Alphabetic Order)
[A]
A/D conversion result register 0 (ADCRL0)..........................................................................................................174
A/D converter mode register 0 (ADML0) ..............................................................................................................176
Analog input channel specification register 0 (ADS0)...........................................................................................177
Asynchronous serial interface mode register 20 (ASIM20)...................................................................................191
Asynchronous serial interface status register 20 (ASIS20)...................................................................................193
Automatic data transmit/receive address pointer 0 (ADTP0)................................................................................218
Automatic data transmit/receive control register 0 (ADTC0).................................................................................221
Automatic data transmit/receive interval specification register 0 (ADTI0).............................................................222
[B]
Baud rate generator control register 20 (BRGC20) ..............................................................................................194
[C]
Carrier generator output control register 60 (TCA60)...........................................................................................131
[E]
8-bit compare register 50 (CR50).........................................................................................................................126
8-bit compare register 60 (CR60).........................................................................................................................126
8-bit compare register 61 (CR61).........................................................................................................................126
8-bit H width compare register 60 (CRH60)..........................................................................................................127
8-bit H width compare register 61 (CRH61)..........................................................................................................127
8-bit timer counter 50 (TM50)...............................................................................................................................127
8-bit timer counter 60 (TM60)...............................................................................................................................127
8-bit timer counter 61 (TM61)...............................................................................................................................127
8-bit timer mode control register 50 (TMC50).......................................................................................................128
8-bit timer mode control register 60 (TMC60).......................................................................................................129
8-bit timer mode control register 61 (TMC61).......................................................................................................130
External interrupt mode register 0 (INTM0) ..........................................................................................................297
External interrupt mode register 1 (INTM1) ..........................................................................................................297
[ I ]
Interrupt mask flag register 0 (MK0).....................................................................................................................296
Interrupt mask flag register 1 (MK1).....................................................................................................................296
Interrupt mask flag register 2 (MK2).....................................................................................................................296
Interrupt request flag register 0 (IF0)....................................................................................................................295
Interrupt request flag register 1 (IF1)....................................................................................................................295
Interrupt request flag register 2 (IF2)....................................................................................................................295
[K]
Key return mode register 00 (KRM00)..................................................................................................................299
Key return mode register 01 (KRM01)..................................................................................................................300
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APPENDIX C REGISTER INDEX
[L]
LCD clock control register 0 (LCDC0) ..................................................................................................................256
LCD display mode register 0 (LCDM0).................................................................................................................256
LCD voltage boost control register 0 (LCDVA0) ...................................................................................................256
[M]
Multiplication data register A0 (MRA0) .................................................................................................................267
Multiplication data register B0 (MRB0) .................................................................................................................267
Multiplier control register 0 (MULC0)....................................................................................................................269
[O]
Oscillation stabilization time select register (OSTS) .............................................................................................308
[P]
Port 0 (P0)..............................................................................................................................................................77
Port 1 (P1)..............................................................................................................................................................78
Port 2 (P2)..............................................................................................................................................................79
Port 3 (P3)..............................................................................................................................................................84
Port 5 (P5)..............................................................................................................................................................86
Port 6 (P6)..............................................................................................................................................................87
Port 7 (P7)..............................................................................................................................................................89
Port 8 (P8)..............................................................................................................................................................90
Port function register 7 (PF7) .................................................................................................................................93
Port function register 8 (PF8) .................................................................................................................................93
Port mode register 0 (PM0) ....................................................................................................................................91
Port mode register 1 (PM1) ....................................................................................................................................91
Port mode register 2 (PM2) ....................................................................................................................................91
Port mode register 3 (PM3) ....................................................................................................................91, 112, 133
Port mode register 5 (PM5) ....................................................................................................................................91
Port mode register 8 (PM8) ....................................................................................................................................91
Processor clock control register (PCC)...................................................................................................................98
Pull-up resistor option register B0 (PUB0)..............................................................................................................93
Pull-up resistor option register B1 (PUB1)..............................................................................................................93
Pull-up resistor option register B2 (PUB2)..............................................................................................................93
Pull-up resistor option register B3 (PUB3)..............................................................................................................93
[R]
Receive buffer register 20 (RXB20)......................................................................................................................189
Remote controller DH0L compare register (RMDH0L) .........................................................................................275
Remote controller DH1L compare register (RMDH1L) .........................................................................................275
Remote controller receive control register (RMCN)..............................................................................................277
Remote controller receive data register (RMDR)..................................................................................................273
Remote controller receive DH0S compare register (RMDH0S)............................................................................275
Remote controller receive DH1S compare register (RMDH1S)............................................................................275
Remote controller receive DLS compare register (RMDLS) .................................................................................274
Remote controller receive DLL compare register (RMDLL)..................................................................................274
Remote controller receive GPHS compare register (RMGPHS)...........................................................................274
Remote controller receive GPHL compare register (RMGPHL)............................................................................274
380
User’s Manual U15331EJ4V1UD
APPENDIX C REGISTER INDEX
Remote controller receive end width select register (RMER) ...............................................................................276
Remote controller receive shift receive (RMSR)...................................................................................................272
Remote controller shift register receive counter register (RMSCR)......................................................................273
[S]
16-bit capture register 20 (TCP20).......................................................................................................................109
16-bit compare register 20 (CR20).......................................................................................................................109
16-bit multiplication result storage register H (MUL0H) ........................................................................................267
16-bit multiplication result storage register L (MUL0L) .........................................................................................267
16-bit timer counter 20 (TM20).............................................................................................................................109
16-bit timer mode control register 20 (TMC20).....................................................................................................109
Serial I/O shift register 1A0 (SIO1A0)...................................................................................................................218
Serial operation mode register 1A0 (CSIM1A0) ...................................................................................................219
Serial operation mode register 20 (CSIM20) ........................................................................................................190
Subclock control register (CSS) .............................................................................................................................99
Subclock oscillation mode register (SCKM)............................................................................................................99
Subclock selection register (SSCK)......................................................................................................................100
[T]
Transmit shift register 20 (TXS20)........................................................................................................................189
[W]
Watch timer interrupt selection register (WTIM)...................................................................................................164
Watch timer mode control register (WTM)............................................................................................................163
Watchdog timer clock selection register (WDCS).................................................................................................169
Watchdog timer mode register (WDTM)...............................................................................................................170
User’s Manual U15331EJ4V1UD
381
APPENDIX C REGISTER INDEX
C.2 Register Index (Register Symbols Alphabetic Order)
[A]
ADCRL0: A/D conversion result register 0........................................................................................................174
ADML0:
ADS0:
ADTC0:
ADTI0:
ADTP0:
ASIM20:
ASIS20:
A/D converter mode register 0..........................................................................................................176
Analog input channel specification register 0....................................................................................177
Automatic data transmit/receive control register 0............................................................................221
Automatic data transmit/receive interval specification register 0.......................................................222
Automatic data transmit/receive address pointer 0...........................................................................218
Asynchronous serial interface mode register 20 ...............................................................................191
Asynchronous serial interface status register 20...............................................................................193
[B]
BRGC20: Baud rate generator control register 20 ............................................................................................194
[C]
CR20:
CR50:
CR60:
CR61:
CRH60:
CRH61:
16-bit compare register 20................................................................................................................109
8-bit compare register 50..................................................................................................................126
8-bit compare register 60..................................................................................................................126
8-bit compare register 61..................................................................................................................126
8-bit H width compare register 60 .....................................................................................................127
8-bit H width compare register 61 .....................................................................................................127
CSIM1A0: Serial operation mode register 1A0...................................................................................................219
CSIM20:
CSS:
Serial operation mode register 20.....................................................................................................190
Subclock control register.....................................................................................................................99
[ I ]
IF0:
IF1:
IF2:
INTM0:
INTM1:
Interrupt request flag register 0.........................................................................................................295
Interrupt request flag register 1.........................................................................................................295
Interrupt request flag register 2.........................................................................................................295
External interrupt mode register 0.....................................................................................................297
External interrupt mode register 1.....................................................................................................297
[K]
KRM00:
KRM01:
Key return mode register 00 .............................................................................................................299
Key return mode register 01 .............................................................................................................300
[L]
LCDC0:
LCDM0:
LCD clock control register 0..............................................................................................................255
LCD display mode register 0.............................................................................................................254
LCDVA0: LCD voltage boost control register 0.................................................................................................256
[M]
MK0:
MK1:
MK2:
MRA0:
MRB0:
Interrupt mask flag register 0 ............................................................................................................296
Interrupt mask flag register 1 ............................................................................................................296
Interrupt mask flag register 2 ............................................................................................................296
Multiplication data register A0...........................................................................................................297
Multiplication data register B0...........................................................................................................297
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User’s Manual U15331EJ4V1UD
APPENDIX C REGISTER INDEX
MUL0H:
MUL0L:
MULC0:
16-bit multiplication result storage register H....................................................................................267
16-bit multiplication result storage register L.....................................................................................267
Multiplier control register 0................................................................................................................269
[O]
OSTS:
Oscillation stabilization time select register ......................................................................................308
[P]
P0:
P1:
P2:
P3:
P5:
P6:
P7:
P8:
PCC:
PF7:
PF8:
PM0:
PM1:
PM2:
PM3:
PM5:
PM8:
PUB0:
PUB1:
PUB2:
PUB3:
Port 0..................................................................................................................................................77
Port 1..................................................................................................................................................78
Port 2..................................................................................................................................................79
Port 3..................................................................................................................................................84
Port 5..................................................................................................................................................86
Port 6..................................................................................................................................................87
Port 7..................................................................................................................................................89
Port 8..................................................................................................................................................90
Processor clock control register..........................................................................................................98
Port function register 7........................................................................................................................93
Port function register 8........................................................................................................................93
Port mode register 0 ...........................................................................................................................91
Port mode register 1 ...........................................................................................................................91
Port mode register 2 ...........................................................................................................................91
Port mode register 3 ........................................................................................................... 91, 112, 133
Port mode register 5 ...........................................................................................................................91
Port mode register 8 ...........................................................................................................................91
Pull-up resistor option register B0.......................................................................................................93
Pull-up resistor option register B1.......................................................................................................93
Pull-up resistor option register B2.......................................................................................................93
Pull-up resistor option register B3.......................................................................................................93
[R]
RMCN:
Remote controller receive control register ........................................................................................277
RMDH0L: Remote controller DH0L compare register ......................................................................................275
RMDH0S: Remote controller receive DH0S compare register...........................................................................275
RMDH1L: Remote controller DH1L compare register .......................................................................................275
RMDH1S: Remote controller receive DH1S compare register...........................................................................275
RMDLL:
RMDLS:
RMDR:
RMER:
Remote controller receive DLL compare register..............................................................................274
Remote controller receive DLS compare register .............................................................................274
Remote controller receive data register............................................................................................273
Remote controller receive end width select register .........................................................................276
RMGPHL: Remote controller receive GPHL compare register ..........................................................................274
RMGPHS: Remote controller receive GPHS compare register..........................................................................274
RMSCR:
RMSR:
RXB20:
Remote controller shift register receive counter register...................................................................273
Remote controller receive shift register ............................................................................................272
Receive buffer register 20.................................................................................................................189
[S]
SCKM:
Subclock oscillation mode register......................................................................................................99
User’s Manual U15331EJ4V1UD
383
APPENDIX C REGISTER INDEX
SIO1A0:
SSCK:
Serial I/O shift register 1A0...............................................................................................................218
Subclock selection register ...............................................................................................................100
[T]
TCA60:
TCP20:
TM20:
TM50:
TM60:
TM61:
TMC20:
TMC50:
TMC60:
TMC61:
TXS20:
Carrier generator output control register 60......................................................................................131
16-bit capture register 20..................................................................................................................109
16-bit timer counter 20......................................................................................................................109
8-bit timer counter 50........................................................................................................................127
8-bit timer counter 60........................................................................................................................127
8-bit timer counter 61........................................................................................................................127
16-bit timer mode control register 20 ................................................................................................110
8-bit timer mode control register 50 ..................................................................................................128
8-bit timer mode control register 60 ..................................................................................................129
8-bit timer mode control register 61 ..................................................................................................132
Transmit shift register 20 ..................................................................................................................189
[W]
WDCS:
WDTM:
WTIM:
WTM:
Watchdog timer clock selection register............................................................................................169
Watchdog timer mode register..........................................................................................................170
Watch timer interrupt selection register.............................................................................................164
Watch timer mode control register....................................................................................................163
384
User’s Manual U15331EJ4V1UD
APPENDIX D REVISION HISTORY
The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of
each edition in which the revision was applied.
(1/4)
Edition
2nd
Major Revision from Previous Edition
Applied to:
Correction of number of vectored interrupt sources in 1.7
Overview of Functions
CHAPTER 1 GENERAL
Change of VPP pin handling
CHAPTER 2 PIN FUNCTIONS
CHAPTER 4 PORT FUNCTIONS
CHAPTER 5 CLOCK GENERATOR
Change of block diagrams of P23 and P24
Addition of Note on feedback resistor
Correction of bit name of bit 0 of timer mode control registers 60
and 61 (TMC60, TMC61)
CHAPTER 7 8-BIT TIMERS 50, 60,
AND 61
Addition of Caution on carrier generator output control register 60
(TCA60)
Correction of values in Table 7-8 Square-Wave Output Range of
Timer 61
Change of Figure 10-4 Basic Operation of 10-Bit A/D Converter
and Figure 10-5 Relationship Between Analog Input Voltage
and A/D Conversion Result
CHAPTER 10 10-BIT A/D
CONVERTER
Modification of Figure 11-1 Block Diagram of Serial Interface 20
CHAPTER 11 SERIAL INTERFACE
20
Modification of description on PE20 flag in Figure 11-5 Format of
Asynchronous Serial Interface Status Register 20
Addition of description on UART receive data read
Change of Figure 13-2 LCD Controller/Driver Block Diagram
CHAPTER 13 LCD
CONTROLLER/DRIVER
Addition of 13.8 Supplying LCD Drive Voltages VLC0, VLC1, and
VLC2
Modification of description on serial interface 20 in Table 17-1
CHAPTER 17 RESET FUNCTION
Status of Hardware After Reset
Addition of description on subsystem clock ×4 multiplier and pull-up
resistor of port 5 in Table 18-1 Differences Between
µPD78F9488 and Mask ROM Version
CHAPTER 18 µPD78F9488
Revision of contents about flash memory programming as 18.1
Flash Memory Characteristics
Addition of 18.2 Cautions on µPD78F9488
Addition of electrical specifications
CHAPTER 21 ELECTRICAL
SPECIFICATIONS
Addition of characteristics curves of LCD controller/driver
(reference values)
CHAPTER 22 CHARACTERISTICS
CURVES OF LCD
CONTROLLER/DRIVER
(REFERENCE VALUES)
Addition of package drawings
CHAPTER 23 PACKAGE
DRAWINGS
Addition of recommended soldering conditions
CHAPTER 24 RECOMMENDED
SOLDERING CONDITIONS
APPENDIX A DEVELOPMENT
TOOLS
Revision of APPENDIX A DEVELOPMENT TOOLS
Deletion of description on embedded software
Addition of revision history
APPENDIX C REVISION HISTORY
385
User’s Manual U15331EJ4V1UD
APPENDIX D REVISION HISTORY
(2/4)
Edition
3rd
Major Revision from Previous Edition
Addition of descriptions of µPD789489, 78F9489 (under
development)
Applied to:
Throughout
• Key return detection function added to port 6 (µPD789489,
78F9489 only)
• Key return pin name of port 0 changed (µPD789489, 78F9489
only)
• Remote controller receiver added (µPD789489, 78F9489 only)
Addition of description in 2.2.20 VPP (Flash Memory Version Only)
CHAPTER 2 PIN FUNCTIONS
Addition of description about AVDD, AVSS in Table 2-1 Types of Pin
I/O Circuits
Addition of internal low-speed RAM to 3.1.2 Internal data memory
space
CHAPTER 3 CPU ARCHITECTURE
Modification of Figure 4-2 Block Diagram of P00 to P07
Addition of 5.4.6 Subsystem clock ×4 multiplication circuit
CHAPTER 4 PORT FUNCTIONS
CHAPTER 5 CLOCK GENERATOR
Modification of descriptions in 6.4.1 Operation as timer interrupt
and 6.4.2 Operation as timer output
CHAPTER 6 16-BIT TIMER 20
Addition of 6.5 Cautions on 16-bit timer 20
Correction of maximum intervals in Table 7-4 Interval Time of
Timer 60 and Table 7-5 Interval Time of Timer 61
CHAPTER 7 8-BIT TIMERS 50, 60,
61
Correction of maximum pulse widths in Table 7-7 Square-Wave
Output Range of Timer 60 and Table 7-8 Square-Wave Output
Range of Timer 61
Modification of Caution in Figure 8-4 Watch Timer/Interval Timer
Operation Timing
CHAPTER 8 WATCH TIMER
Addition of descriptions in (2) A/D conversion result register 0
(ADCRL0) in 10.2 10-Bit A/D Converter Configuration
CHAPTER 10 10-BIT A/D
CONVERTER
Addition of (8) Input impedance of ANI0 to ANI7 pins in 10.5
Cautions Related to 10-Bit A/D Converter
Addition of the remote controller receiver chapter
CHAPTER 15 REMOTE
CONTROLLER RECEIVER
(µPD789489, 78F9489 ONLY)
Modification of Caution in Figure 16-6 Format of Key Return
Mode Register 00
CHAPTER 16 INTERRUPT
FUNCTIONS
Addition of descriptions about remote controller receiver and key
return signal detection pin in Table 19-1 Difference Between
µPD78F9488, 78F9489, and Mask ROM Version
CHAPTER 19 FLASH MEMORY
VERSION
Modification of descriptions about CPU Clock in Table 19-2
Communication Mode List
Modification of Notes in Figure 19-3 Example of connection with
Dedicated Flash Programmer
Addition of Note to Absolute Maximum Ratings
CHAPTER 22 ELECTRICAL
SPECIFICATIONS (µPD789488,
78F9488)
Addition of electrical specifications of µPD789489, 78F9489
(target)
CHAPTER 23 ELECTRICAL
SPECIFICATIONS (TARGET)
(µPD789489, 78F9489)
Modification of A.5 Debugging Tools (Hardware)
Addition of cautions on designing target system
APPENDIX A DEVELOPMENT
TOOLS
APPENDIX B NOTES ON TARGET
SYSTEM DESIGN
User’s Manual U15331EJ4V1UD
386
APPENDIX D REVISION HISTORY
(3/4)
Edition
4th
Major Revision from Previous Edition
Applied to:
Throughout
Change of descriptions of µPD789489, 78F9489
•
Change of status from under development to development
completed
• Change of the subseries name to “µPD789489 subseries”
CHAPTER 1 GENERAL
Update of 1.5 78K/0S Series Lineup to latest version
Modification of Figure 7-2 Block Diagram of Timer 50
Modification of Figure 7-3 Block Diagram of Timer 60
CHAPTER 7 8-BIT TIMERS 50, 60,
61
Modification of Figure 7-5 Block Diagram of Output control
circuit (Timer 60)
Addition of descriptions in 7.2 (2) 8-bit compare register 60
Addition of descriptions in 7.2 (4) 8-bit H width compare registers
60 and 61
Modification of Figure 7-11 8-bit Timing of Interval Timer
Operation with 8-Bit Resolution (Basic Operation)
Modification of Figure 7-13. Timing of Interval Timer Operation
with 8-Bit Resolution (When CRnm Is Set to FFH)
Modification of Figure 7-17. Timing of Operation of External
Event Counter with 8-Bit Resolution
Addition of descriptions of setting sequence in 7.4.3 Operation as
carrier generator
Modification of Figure 7-22. Timing of Carrier Generator
Operation (When CR60 = N, CRH60 = M (M > N))
Modification of Figure 7-23. Timing of Carrier Generator
Operation (When CR60 = N, CRH60 = M (M < N))
Modification of Figure 7-24. Timing of Carrier Generator
Operation (When CR60 = CRH60 = N)
Modification of the mode name in 7.4.4 PWM output mode
operation (timer 50)
Modification of the mode name in 7.4.5 PPG output mode
operation (timer 60 and 61)
Modification of (1) Error on starting timer in 7.5 Cautions on
Using 8-Bit Timers 50, 60, and 61
CHAPTER 10 10-BIT A/D
CONVERTER
Modification of Figure 10-1. Block Diagram of 10-bit A/D
converter
Modification of (1) Current consumption in standby mode in 10.5
Cautions Related to 10-Bit A/D Converter
CHAPTER 11 SERIAL INTERFACE
20
Modification of Figure 11-1. Block Diagram of Serial Interface 20
Addition of Caution in Figure 11-3 Format of Serial Operation
Mode Register 20
Addition of descriptions about remote controller receiver and key
return signal detection pin in Figure 11-6 Format of Baud Rate
Generator Control Register 20
Modification of descriptions about CPU Clock in Table 11-3 and
11-5. Example of Relationship Between System Clock and
Baud Rate
387
User’s Manual U15331EJ4V1UD
APPENDIX D REVISION HISTORY
(4/4)
Edition
4th
Major Revision from Previous Edition
Applied to:
CHAPTER 12 SERIAL INTERFACE
1A0
Modification of descriptions in Figure 12-4. Format of Automatic
Data Transmit/Receive Interval Specification Register 0
CHAPTER 22 ELECTRICAL
SPECIFICATIONS (µPD789488,
78F9488, 789489, 78F9489)
Addition of formal specifications of µPD789489 and 78F9489 to
µPD789489, 78F9489
CHAPTER 25 RECOMMENDED
SOLDERING CONDITIONS
Addition of recommended conditions for µPD789489 and 78F9489
4th
Addition of the lead-free products
Throughout
(Modified
version)
Modification of descriptions of the voltage boost wait time
CHAPTER 13
LCD CONTROLLER/DRIVER
Modification of Figure 19-9. Wiring Example for Flash Writing
Adapter with 3-Wire Serial I/O with Handshake
CHAPTER 19
FLASH MEMORY VERSION
User’s Manual U15331EJ4V1UD
388
相关型号：
UPD789489GK-XXX-9EU
Microcontroller, 8-Bit, MROM, 5MHz, CMOS, PQFP80, 12 X 12 MM, PLASTIC, TQFP-80
NEC
UPD789800CU-XXX
Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PDIP42, 0.600 INCH, SHRINK, PLASTIC, DIP-42
NEC
UPD789800GB-XXX-3BS
Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
NEC
UPD789800GB-XXX-8ES
Microcontroller, 8-Bit, MROM, 6MHz, MOS, PQFP44, 10 X 10 MM, PLASTIC, LQFP-44
NEC
UPD789800GB-XXX-8ES-A
Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PQFP44, 10 X 10 MM, LEAD FREE, PLASTIC, LQFP-44
NEC
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