UPD78F9136BMC(A1)-5A4 [NEC]
Microcontroller, 8-Bit, FLASH, 5MHz, CMOS, PDSO30, 0.300 INCH, PLASTIC, SSOP-30;型号: | UPD78F9136BMC(A1)-5A4 |
厂家: | NEC |
描述: | Microcontroller, 8-Bit, FLASH, 5MHz, CMOS, PDSO30, 0.300 INCH, PLASTIC, SSOP-30 时钟 微控制器 光电二极管 外围集成电路 |
文件: | 总413页 (文件大小:4136K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
User’s Manual
µPD789104A, 789114A, 789124A,
789134A Subseries
8-Bit Single-Chip Microcontrollers
µPD789101A
µPD789102A
µPD789104A
µPD789111A
µPD789112A
µPD789114A
µPD78F9116A
µPD78F9116B
µPD789101A(A1) µPD789121A
µPD789102A(A1) µPD789122A
µPD789104A(A1) µPD789124A
µPD789111A(A1) µPD789131A
µPD789112A(A1) µPD789132A
µPD789114A(A1) µPD789134A
µPD78F9116B(A1) µPD78F9136A
µPD789101A(A2) µPD78F9136B
µPD789121A(A1)
µPD789122A(A1)
µPD789124A(A1)
µPD789131A(A1)
µPD789132A(A1)
µPD789134A(A1)
µPD78F9136B(A1)
µPD789121A(A2)
µPD789101A(A) µPD789102A(A2) µPD789121A(A) µPD789122A(A2)
µPD789102A(A) µPD789104A(A2) µPD789122A(A) µPD789124A(A2)
µPD789104A(A) µPD789111A(A2) µPD789124A(A) µPD789131A(A2)
µPD789111A(A) µPD789112A(A2) µPD789131A(A) µPD789132A(A2)
µPD789112A(A) µPD789114A(A2) µPD789132A(A) µPD789134A(A2)
µPD789114A(A)
µPD78F9116B(A)
µPD789134A(A)
µPD78F9136B(A)
Document No. U14643EJ2V0UD00 (2nd edition)
Date Published December 2003 N CP(K)
2000, 2003
Printed in Japan
[MEMO]
2
User’s Manual U14643EJ2V0UD
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
EEPROM and FIP are trademarks of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
3
User’s Manual U14643EJ2V0UD
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of March, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
4
User’s Manual U14643EJ2V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
800-366-9782
NEC Electronics Hong Kong Ltd.
Seoul Branch
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Seoul, Korea
Tel: 02-558-3737
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
• Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-2445845
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J03.4
5
User’s Manual U14643EJ2V0UD
Major Revisions in This Edition
Pages
Throughout
Description
• Addition of µPD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), 789114A(A1),
789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1), 789101A(A2),
789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2),
789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2), 78F9116B, 78F9136B, 78F9116B(A),
78F9136B(A), 78F9116B(A1), 78F9136B(A1)
• Addition of description related to expanded-specification products
pp.24, 36
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
• Addition of 1.1 Expanded-Specification Products and Conventional-Specification Products
• Addition of 1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2)
Products
p.48
CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
• Addition of 2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2)
Products
pp.116 to 118, 121
CHAPTER 8 16-BIT TIMER 20
• Modification of description in 8.4.1 Operation as timer interrupt
• Modification of Figure 8-5 Timing of Timer Interrupt Operation
• Modification of description in 8.4.2 Operation as timer output
• Modification of description in Figure 8-7 Timer Output Timing
• Addition of 8.5 Notes on Using 16-Bit Timer 20
p.134
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
• Addition of description to 9.5 Notes on Using 8-Bit Timer/Event Counter 80
p.152
CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)
• Addition of 11.5 (8) Input impedance of ANI0 to ANI3 pins
pp.155, 164
CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)
• Modification of description in 12.2 (2) A/D conversion result register 0 (ADCR0)
• Addition of 12.5 (8) Input impedance of ANI0 to ANI3 pins
pp.167, 177, 190
CHAPTER 13 SERIAL INTERFACE 20
• Modification of Figure 13-1 Block Diagram of Serial Interface 20
• Addition of 13.3 (4) (c) Generation of serial clock from system clock in 3-wire serial I/O mode
• Addition of 13.4.2 (2) (f) Reading receive data
p.210
CHAPTER 15 INTERRUPT FUNCTIONS
• Addition of Caution 3 in Figure 15-2 Format of Interrupt Request Flag Register
Revision of CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
p.233
p.258
p.387
p.393
Addition of CHAPTER 21 to CHAPTER 31 ELECTRICAL SPECIFICATIONS
Addition of CHAPTER 32 and CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES)
Addition of CHAPTER 34 and CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY
CHARACTERISTICS (REFERENCE VALUES)
p.397
Addition of CHAPTER 36 PACKAGE DRAWING
p.398
Addition of CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS
Revision of APPENDIX A DEVELOPMENT TOOLS
Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Addition of APPENDIX D REVISION HISTORY
p.400
p.406
p.412
p.257 in 1st edition
Deletion of APPENDIX B EMBEDDED SOFTWARE
The mark shows major revised points.
6
User’s Manual U14643EJ2V0UD
INTRODUCTION
Target Readers
This manual is intended for users who wish to understand the functions of the
µPD789104A, 789114A, 789124A, 789134A Subseries and to design and develop
application systems and programs using these microcontrollers.
The target devices are shown as follows:
• µPD789104A Subseries: µPD789101A, 789102A, 789104A, 789101A(A),
789102A(A), 789104A(A), 789101A(A1), 789102A(A1),
789104A(A1), 789101A(A2), 789102A(A2), 789104A(A2)
• µPD789114A Subseries: µPD789111A, 789112A, 789114A, 78F9116A, 78F9116B,
789111A(A), 789112A(A), 789114A(A), 78F9116B(A),
789111A(A1), 789112A(A1), 789114A(A1), 78F9116B(A1),
789111A(A2), 789112A(A2), 789114A(A2)
• µPD789124A Subseries: µPD789121A, 789122A, 789124A, 789121A(A),
789122A(A), 789124A(A), 789121A(A1), 789122A(A1),
789124A(A1), 789121A(A2), 789122A(A2), 789124A(A2)
• µPD789134A Subseries: µPD789131A, 789132A, 789134A, 78F9136A, 78F9136B,
789131A(A), 789132A(A), 789134A(A), 78F9136B(A),
789131A(A1), 789132A(A1), 789134A(A1), 78F9136B(A1),
789131A(A2), 789132A(A2), 789134A(A2)
The µPD789104A/114A/124A/134A Subseries is a generic term for all the target devices
in this manual.
Generic names in this document indicate the following products.
[Standard quality grade products] µPD789101A, 789102A, 789104A, 789111A,
789112A, 789114A, 78F9116A, 78F9116B,
789121A, 789122A, 789124A, 789131A, 789132A,
789134A, 78F9136A, 78F9136B
[(A) products]
µPD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A),
789114A(A), 78F9116B(A), 789121A(A), 789122A(A), 789124A(A),
789131A(A), 789132A(A), 789134A(A), 78F9136B(A)
[(A1) products] µPD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1),
789112A(A1), 789114A(A1), 78F9116B(A1), 789121A(A1),
789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1),
789134A(A1), 78F9136B(A1)
[(A2) products] µPD789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2),
789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2), 789124A(A2),
789131A(A2), 789132A(A2), 789134A(A2)
7
User’s Manual U14643EJ2V0UD
[Mask ROM products]
µPD789101A, 789102A, 789104A, 789111A, 789112A,
789114A, 789121A, 789122A, 789124A, 789131A, 789132A,
789134A, 789101A(A), 789102A(A), 789104A(A), 789111A(A),
789112A(A), 789114A(A), 789121A(A), 789122A(A),
789124A(A), 789131A(A), 789132A(A), 789134A(A),
789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1),
789112A(A1), 789114A(A1), 789121A(A1), 789122A(A1),
789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1),
789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2),
789112A(A2), 789114A(A2), 789121A(A2), 789122A(A2),
789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2)
[Flash memory products] µPD78F9116A, 78F9116B, 78F9116B(A), 78F9116B(A1),
78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1)
The oscillation frequency of the system clock is regarded as fX for ceramic/crystal
oscillation (µPD789104A and 789114A Subseries), and regarded as fCC for an RC
oscillation (µPD789124A and 789134A Subseries).
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
The µPD789104A, 789114A, 789124A, 789134A Subseries User’s Manual is divided into
two parts: this manual and instructions (common to the 78K/0S Series).
µPD789104A, 789114A, 789124A,
789134A Subseries
78K/0S Series
Instructions
User’s Manual (This manual)
User’s Manual
• Pin functions
• CPU function
• Internal block functions
• Interrupts
• Instruction set
• Instruction description
• Other internal peripheral functions
• Electrical specifications
8
User’s Manual U14643EJ2V0UD
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
ꢀ When using this manual as a manual for the µPD789101A(A), 789102A(A),
789104A(A), 789111A(A), 789112A(A), 789114A(A), 78F9116B(A), 789121A(A),
789122A(A), 789124A(A), 789131A(A), 789132A(A), 789134A(A), 78F9136B(A),
789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1),
789114A(A1), 78F9116B(A1), 789121A(A1), 789122A(A1), 789124A(A1),
789131A(A1), 789132A(A1), 789134A(A1), 78F9136B(A1), 789101A(A2),
789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2),
789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2), and
789134A(A2)
→ Only the quality grade, supply voltage, operating ambient temperature, minimum
instruction execution time, and electrical specifications differ from the
µPD789101A, 789102A, 789104A, 789111A, 789112A, 789114A, 78F9116B,
789121A, 789122A, 789124A, 789131A, 789132A, 789134A, and 78F9136B (refer
to 1.10 Differences Between Standard Quality Grade Products and (A), (A1),
(A2) Products, 2.9 Differences Between Standard Quality Grade Products
and (A), (A1), (A2) Products). For the (A), (A1), and (A2) products, read the part
numbers in CHAPTER 3 to CHAPTER 20 as follows.
µPD789101A → µPD789101A(A), 789101A(A1), 789101A(A2)
µPD789102A → µPD789102A(A), 789102A(A1), 789102A(A2)
µPD789104A → µPD789104A(A), 789104A(A1), 789104A(A2)
µPD789111A → µPD789111A(A), 789111A(A1), 789111A(A2)
µPD789112A → µPD789112A(A), 789112A(A1), 789112A(A2)
µPD789114A → µPD789114A(A), 789114A(A1), 789114A(A2)
µPD78F9116B → µPD78F9116B(A), 78F9116B(A1)
µPD789121A → µPD789121A(A), 789121A(A1), 789121A(A2)
µPD789122A → µPD789122A(A), 789122A(A1), 789122A(A2)
µPD789124A → µPD789124A(A), 789124A(A1), 789124A(A2)
µPD789131A → µPD789131A(A), 789131A(A1), 789131A(A2)
µPD789132A → µPD789132A(A), 789132A(A1), 789132A(A2)
µPD789134A → µPD789134A(A), 789134A(A1), 789134A(A2)
µPD78F9136B → µPD78F9136B(A), 78F9136B(A1)
ꢀ To understand the overall functions in general
→ Read this manual in the order of the CONTENTS.
ꢀ How to interpret register formats
→ The name of a bit whose number is in angle brackets (<>) is reserved in the
assembler and is defined in the C compiler by the header file sfrbit.h.
ꢀ To learn the detailed functions of a register whose register name is known
→ Refer to APPENDIX C REGISTER INDEX.
ꢀ To learn the details of the instruction functions of the 78K/0S Series
→ Refer to 78K/0S Series Instructions User’s Manual (U11047E).
ꢀ To know the electrical specifications of the µPD789104A/114A/124A/134A Subseries
→ Refer to CHAPTER 21 to CHAPTER 31 ELECTRICAL SPECIFICATIONS.
Caution The application examples in this manual are created for “Standard”
quality grade products for general electric equipment. When using the
application examples in this manual for purposes which require
“Special” quality grades, thoroughly examine the quality grade of each
part and circuit actually used.
9
User’s Manual U14643EJ2V0UD
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note:
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
This manual
U11047E
µPD789104A, 789114A, 789124A, 789134A Subseries User’s Manual
78K/0S Series Instructions User’s Manual
Documents Related to Development Software Tools (User’s Manuals)
Document Name
Document No.
U14876E
U14877E
U11623E
U14871E
U14872E
U15373E
U15802E
U15185E
U14610E
RA78K0S Assembler Package
Operation
Language
Structured Assembly Language
Operation
CC78K0S C Compiler
Language
SM78K Series System Simulator Ver. 2.30 or Later
Operation (WindowsTM Based)
External Part User Open Interface Specification
Operation (Windows Based)
ID78K Series Integrated Debugger Ver. 2.30 or Later
Project Manager Ver. 3.12 or Later (Windows Based)
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name
IE-78K0S-NS In-Circuit Emulator
Document No.
U13549E
IE-78K0S-NS-A In-Circuit Emulator
U15207E
IE-789136-NS-EM1 Emulation Board
U14363E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
10
User’s Manual U14643EJ2V0UD
Documents Related to Flash Memory Writing
Document Name
Document No.
U13502E
PG-FP3 Flash Memory Programmer User's Manual
PG-FP4 Flash Memory Programmer User's Manual
U15260E
Other Related Documents
Document Name
Document No.
X13769X
Note
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Quality Grades on NEC Semiconductor Devices
C11531E
C10983E
C11892E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
11
User’s Manual U14643EJ2V0UD
CONTENTS
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)........................................................ 24
1.1 Expanded-Specification Products and Conventional-Specification Products...................... 24
1.2 Features......................................................................................................................................... 25
1.3 Applications .................................................................................................................................. 25
1.4 Ordering Information.................................................................................................................... 26
1.5 Quality Grade ................................................................................................................................ 27
1.6 Pin Configuration (Top View) ...................................................................................................... 28
1.7 78K/0S Series Lineup................................................................................................................... 30
1.8 Block Diagram............................................................................................................................... 33
1.9 Outline of Functions..................................................................................................................... 34
1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products ......... 36
CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)........................................................ 37
2.1 Features......................................................................................................................................... 37
2.2 Applications .................................................................................................................................. 37
2.3 Ordering Information.................................................................................................................... 38
2.4 Quality Grade ................................................................................................................................ 39
2.5 Pin Configuration (Top View) ...................................................................................................... 40
2.6 78K/0S Series Lineup................................................................................................................... 42
2.7 Block Diagram............................................................................................................................... 45
2.8 Outline of Functions..................................................................................................................... 46
2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products ......... 48
CHAPTER 3 PIN FUNCTIONS ............................................................................................................... 49
3.1 Pin Function List........................................................................................................................... 49
3.2 Description of Pin Functions....................................................................................................... 51
3.2.1 P00 to P03 (Port 0) .............................................................................................................................51
3.2.2 P10, P11 (Port 1) ................................................................................................................................51
3.2.3 P20 to P25 (Port 2) .............................................................................................................................51
3.2.4 P50 to P53 (Port 5) .............................................................................................................................52
3.2.5 P60 to P63 (Port 6) .............................................................................................................................52
3.2.6 RESET................................................................................................................................................52
3.2.7 X1, X2 (µPD789104A, 789114A Subseries) .......................................................................................52
3.2.8 CL1, CL2 (µPD789124A, 789134A Subseries)...................................................................................52
3.2.9 AVDD ...................................................................................................................................................52
3.2.10 AVSS ...................................................................................................................................................52
3.2.11 VDD .....................................................................................................................................................52
3.2.12 VSS .....................................................................................................................................................52
3.2.13 VPP (µPD78F9116A, 78F9116B, 78F9136A, 78F9136B only).............................................................53
3.2.14 IC0 (pin No.20) (mask ROM versions only).........................................................................................53
3.2.15 IC0 (pins No.10 and No.21) ................................................................................................................53
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................... 54
CHAPTER 4 CPU ARCHITECTURE...................................................................................................... 56
4.1 Memory Space .............................................................................................................................. 56
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User’s Manual U14643EJ2V0UD
4.1.1 Internal program memory space.........................................................................................................60
4.1.2 Internal data memory (internal high-speed RAM) space.....................................................................61
4.1.3 Special-function register (SFR) area...................................................................................................61
4.1.4 Data memory addressing....................................................................................................................61
4.2 Processor Registers .....................................................................................................................65
4.2.1 Control registers .................................................................................................................................65
4.2.2 General-purpose registers ..................................................................................................................67
4.2.3 Special-function registers (SFRs) .......................................................................................................68
4.3 Instruction Address Addressing .................................................................................................71
4.3.1 Relative addressing ............................................................................................................................71
4.3.2 Immediate addressing.........................................................................................................................72
4.3.3 Table indirect addressing....................................................................................................................73
4.3.4 Register addressing............................................................................................................................73
4.4 Operand Address Addressing .....................................................................................................74
4.4.1 Direct addressing................................................................................................................................74
4.4.2 Short direct addressing.......................................................................................................................75
4.4.3 Special-function register (SFR) addressing ........................................................................................76
4.4.4 Register addressing............................................................................................................................77
4.4.5 Register indirect addressing ...............................................................................................................78
4.4.6 Based addressing...............................................................................................................................79
4.4.7 Stack addressing ................................................................................................................................79
CHAPTER 5 PORT FUNCTIONS............................................................................................................80
5.1 Functions of Ports.........................................................................................................................80
5.2 Port Configuration.........................................................................................................................82
5.2.1 Port 0..................................................................................................................................................82
5.2.2 Port 1..................................................................................................................................................83
5.2.3 Port 2..................................................................................................................................................84
5.2.4 Port 5..................................................................................................................................................88
5.2.5 Port 6..................................................................................................................................................89
5.3 Port Function Control Registers..................................................................................................90
5.4 Operation of Port Functions ........................................................................................................93
5.4.1 Writing to I/O port................................................................................................................................93
5.4.2 Reading from I/O port .........................................................................................................................93
5.4.3 Arithmetic operation of I/O port...........................................................................................................94
CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)....................................95
6.1 Function of Clock Generator........................................................................................................95
6.2 Configuration of Clock Generator ...............................................................................................95
6.3 Register Controlling Clock Generator ........................................................................................96
6.4 System Clock Oscillator...............................................................................................................97
6.4.1 System clock oscillator .......................................................................................................................97
6.4.2 Divider ................................................................................................................................................99
6.5 Operation of Clock Generator....................................................................................................100
6.6 Changing Setting of CPU Clock.................................................................................................101
6.6.1 Time required for switching CPU clock .............................................................................................101
6.6.2 Switching CPU clock.........................................................................................................................101
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User’s Manual U14643EJ2V0UD
CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES) ................................. 102
7.1 Function of Clock Generator..................................................................................................... 102
7.2 Configuration of Clock Generator ............................................................................................ 102
7.3 Register Controlling Clock Generator...................................................................................... 103
7.4 System Clock Oscillator ............................................................................................................ 104
7.4.1 System clock oscillator......................................................................................................................104
7.4.2 Examples of incorrect resonator connection .....................................................................................105
7.4.3 Divider...............................................................................................................................................106
7.5 Operation of Clock Generator................................................................................................... 107
7.6 Changing Setting of CPU Clock................................................................................................ 108
7.6.1 Time required for switching CPU clock .............................................................................................108
7.6.2 Switching CPU clock.........................................................................................................................109
CHAPTER 8 16-BIT TIMER 20............................................................................................................ 110
8.1 16-Bit Timer 20 Functions.......................................................................................................... 110
8.2 16-Bit Timer 20 Configuration................................................................................................... 111
8.3 Registers Controlling 16-Bit Timer 20...................................................................................... 113
8.4 16-Bit Timer 20 Operation.......................................................................................................... 116
8.4.1 Operation as timer interrupt ..............................................................................................................116
8.4.2 Operation as timer output..................................................................................................................118
8.4.3 Capture operation .............................................................................................................................119
8.4.4 16-bit timer counter 20 readout.........................................................................................................120
8.5 Notes on Using 16-Bit Timer 20 ................................................................................................ 121
8.5.1 Restrictions on rewriting 16-bit compare register 20 .........................................................................121
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80............................................................................. 123
9.1 Functions of 8-Bit Timer/Event Counter 80 ............................................................................. 123
9.2 8-Bit Timer/Event Counter 80 Configuration ........................................................................... 124
9.3 Registers Controlling 8-Bit Timer/Event Counter 80 .............................................................. 126
9.4 Operation of 8-Bit Timer/Event Counter 80.............................................................................. 128
9.4.1 Operation as interval timer................................................................................................................128
9.4.2 Operation as external event counter .................................................................................................130
9.4.3 Operation as square-wave output .....................................................................................................131
9.4.4 Operation as PWM output.................................................................................................................133
9.5 Notes on Using 8-Bit Timer/Event Counter 80 ........................................................................ 134
CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 136
10.1 Functions of Watchdog Timer................................................................................................... 136
10.2 Configuration of Watchdog Timer ............................................................................................ 137
10.3 Watchdog Timer Control Registers.......................................................................................... 138
10.4 Operation of Watchdog Timer................................................................................................... 140
10.4.1 Operation as watchdog timer ............................................................................................................140
10.4.2 Operation as interval timer................................................................................................................141
CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES) ........................... 142
11.1 8-Bit A/D Converter Functions.................................................................................................. 142
11.2 8-Bit A/D Converter Configuration............................................................................................ 142
11.3 Registers Controlling 8-Bit A/D Converter .............................................................................. 144
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User’s Manual U14643EJ2V0UD
11.4 8-Bit A/D Converter Operation...................................................................................................146
11.4.1 Basic operation of 8-bit A/D converter ..............................................................................................146
11.4.2 Input voltage and conversion result ..................................................................................................147
11.4.3 Operation mode of 8-bit A/D converter .............................................................................................149
11.5 Notes on Using 8-Bit A/D Converter .........................................................................................150
CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)..........................154
12.1 10-Bit A/D Converter Functions.................................................................................................154
12.2 10-Bit A/D Converter Configuration ..........................................................................................154
12.3 Registers Controlling 10-Bit A/D Converter .............................................................................156
12.4 10-Bit A/D Converter Operation.................................................................................................158
12.4.1 Basic operation of 10-bit A/D converter ............................................................................................158
12.4.2 Input voltage and conversion result ..................................................................................................159
12.4.3 Operation mode of 10-bit A/D converter ...........................................................................................161
12.5 Notes on Using 10-Bit A/D Converter .......................................................................................162
CHAPTER 13 SERIAL INTERFACE 20...............................................................................................166
13.1 Functions of Serial Interface 20.................................................................................................166
13.2 Serial Interface 20 Configuration...............................................................................................166
13.3 Serial Interface 20 Control Registers........................................................................................170
13.4 Operation of Serial Interface 20.................................................................................................178
13.4.1 Operation stop mode ........................................................................................................................178
13.4.2 Asynchronous serial interface (UART) mode....................................................................................179
13.4.3 3-wire serial I/O mode.......................................................................................................................192
CHAPTER 14 MULTIPLIER ...................................................................................................................202
14.1 Multiplier Function ......................................................................................................................202
14.2 Multiplier Configuration..............................................................................................................202
14.3 Multiplier Control Register.........................................................................................................204
14.4 Multiplier Operation ....................................................................................................................205
CHAPTER 15 INTERRUPT FUNCTIONS.............................................................................................206
15.1 Interrupt Function Types............................................................................................................206
15.2 Interrupt Sources and Configuration ........................................................................................207
15.3 Interrupt Function Control Registers........................................................................................209
15.4 Interrupt Servicing Operation ....................................................................................................214
15.4.1 Non-maskable interrupt request acknowledgment operation............................................................214
15.4.2 Maskable interrupt request acknowledgment operation....................................................................216
15.4.3 Multiple interrupt servicing ................................................................................................................218
15.4.4 Interrupt request hold........................................................................................................................220
CHAPTER 16 STANDBY FUNCTION...................................................................................................221
16.1 Standby Function and Configuration........................................................................................221
16.1.1 Standby function...............................................................................................................................221
16.1.2 Standby function control register (µPD789104A, 789114A Subseries).............................................222
16.2 Operation of Standby Function .................................................................................................223
16.2.1 HALT mode.......................................................................................................................................223
16.2.2 STOP mode......................................................................................................................................226
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User’s Manual U14643EJ2V0UD
CHAPTER 17 RESET FUNCTION ....................................................................................................... 229
CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B .................................................... 233
18.1 Flash Memory Characteristics .................................................................................................. 234
18.1.1 Programming environment................................................................................................................234
18.1.2 Communication mode .......................................................................................................................235
18.1.3 On-board pin processing...................................................................................................................240
18.1.4 Connection when using flash memory writing adapter......................................................................243
CHAPTER 19 MASK OPTION (MASK ROM VERSION).................................................................. 247
CHAPTER 20 INSTRUCTION SET ...................................................................................................... 248
20.1 Operation..................................................................................................................................... 248
20.1.1 Operand identifiers and description methods....................................................................................248
20.1.2 Description of “operation” column .....................................................................................................249
20.1.3 Description of “flag operation” column...............................................................................................249
20.2 Operation List ............................................................................................................................. 250
20.3 Instructions Listed by Addressing Type.................................................................................. 255
CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A))
(EXPANDED-SPECIFICATION PRODUCTS)............................................................... 258
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A))
(CONVENTIONAL-SPECIFICATION PRODUCTS)...................................................... 271
CHAPTER 23 ELECTRICAL SPECIFICATIONS
(µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2)).................................. 283
CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A)) ............................ 294
CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1)) ............................................. 307
CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A) .................................................... 318
CHAPTER 27 ELECTRICAL SPECIFICATIONS
(µPD78912xA, 78913xA, 78912xA(A), 78913xA(A)) .................................................... 330
CHAPTER 28 ELECTRICAL SPECIFICATIONS
(µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2)).................................. 341
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A)) ............................ 352
CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1)) ............................................. 364
CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A) .................................................... 375
CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES)
(µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) .................................................... 387
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User’s Manual U14643EJ2V0UD
CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES)
(µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))...................................390
CHAPTER 34 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS
(REFERENCE VALUES) (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A),
78F9136A) .......................................................................................................................393
CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS
(REFERENCE VALUES) (µPD78912xA(A1), 78913xA(A1), 78912xA(A2),
78913xA(A2))...................................................................................................................395
CHAPTER 36 PACKAGE DRAWING ...................................................................................................397
CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS ...........................................................398
APPENDIX A DEVELOPMENT TOOLS ...............................................................................................400
A.1 Software Package........................................................................................................................402
A.2 Language Processing Software.................................................................................................402
A.3 Control Software .........................................................................................................................403
A.4 Flash Memory Writing Tools......................................................................................................403
A.5 Debugging Tools (Hardware).....................................................................................................404
A.6 Debugging Tools (Software) ......................................................................................................405
APPENDIX B NOTES ON TARGET SYSTEM DESIGN....................................................................406
APPENDIX C REGISTER INDEX..........................................................................................................408
C.1 Register Name Index (Alphabetical Order)...............................................................................408
C.2 Register Symbol Index (Alphabetical Order)............................................................................410
APPENDIX D REVISION HISTORY......................................................................................................412
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User’s Manual U14643EJ2V0UD
LIST OF FIGURES (1/4)
Figure No.
3-1
Title
Page
Pin I/O Circuits..............................................................................................................................................55
4-1
Memory Map (µPD789101A, 789111A, 789121A, 789131A) .......................................................................56
Memory Map (µPD789102A, 789112A, 789122A, 789132A) .......................................................................57
Memory Map (µPD789104A, 789114A, 789124A, 789134A) .......................................................................58
Memory Map (µPD78F9116A, 78F9116B, 78F9136A, 78F9136B) ..............................................................59
Data Memory Addressing (µPD789101A, 789111A, 789121A, 789131A)....................................................61
Data Memory Addressing (µPD789102A, 789112A, 789122A, 789132A)....................................................62
Data Memory Addressing (µPD789104A, 789114A, 789124A, 789134A)....................................................63
Data Memory Addressing (µPD78F9116A, 78F9116B, 78F9136A, 78F9136B)...........................................64
Program Counter Configuration....................................................................................................................65
Program Status Word Configuration.............................................................................................................65
Stack Pointer Configuration..........................................................................................................................66
Data to Be Saved to Stack Memory..............................................................................................................66
Data to Be Restored from Stack Memory.....................................................................................................66
General-Purpose Register Configuration......................................................................................................67
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
Port Types....................................................................................................................................................80
Block Diagram of P00 to P03........................................................................................................................82
Block Diagram of P10 and P11.....................................................................................................................83
Block Diagram of P20...................................................................................................................................84
Block Diagram of P21...................................................................................................................................85
Block Diagram of P22, P23, and P25 ...........................................................................................................86
Block Diagram of P24...................................................................................................................................87
Block Diagram of P50 to P53........................................................................................................................88
Block Diagram of P60 to P63........................................................................................................................89
Port Mode Register Format ..........................................................................................................................91
Format of Pull-up Resistor Option Register 0 ...............................................................................................91
Format of Pull-up Resistor Option Register B2.............................................................................................92
6-1
6-2
6-3
6-4
6-5
Block Diagram of Clock Generator ...............................................................................................................95
Format of Processor Clock Control Register ................................................................................................96
External Circuit of System Clock Oscillator...................................................................................................97
Examples of Incorrect Resonator Connection .............................................................................................98
Switching CPU Clock..................................................................................................................................101
7-1
7-2
7-3
7-4
7-5
Block Diagram of Clock Generator .............................................................................................................102
Format of Processor Clock Control Register ..............................................................................................103
External Circuit of System Clock Oscillator.................................................................................................104
Examples of Incorrect Resonator Connection ...........................................................................................105
Switching CPU Clock..................................................................................................................................109
8-1
Block Diagram of 16-Bit Timer 20...............................................................................................................111
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LIST OF FIGURES (2/4)
Figure No.
Title
Page
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
Format of 16-Bit Timer Mode Control Register 20......................................................................................114
Format of Port Mode Register 2.................................................................................................................115
Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation .......................................116
Timing of Timer Interrupt Operation ...........................................................................................................117
Settings of 16-Bit Timer Mode Control Register 20 for Timer Output Operation.........................................118
Timer Output Timing...................................................................................................................................118
Settings of 16-Bit Timer Mode Control Register 20 for Capture Operation.................................................119
Capture Operation Timing (Both Edges of CPT20 Pin Are Specified)........................................................119
16-Bit Timer Counter 20 Readout Timing...................................................................................................120
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
Block Diagram of 8-Bit Timer/Event Counter 80.........................................................................................125
Format of 8-Bit Timer Mode Control Register 80........................................................................................126
Format of Port Mode Register 2.................................................................................................................127
Interval Timer Operation Timing.................................................................................................................129
External Event Counter Operation Timing (with Rising Edge Specified) ....................................................130
Square-Wave Output Timing......................................................................................................................132
PWM Output Timing...................................................................................................................................133
Start Timing of 8-Bit Timer Counter............................................................................................................134
External Event Counter Operation Timing..................................................................................................134
Timing After Writing Compare Register During PWM Output.....................................................................135
10-1
10-2
10-3
Block Diagram of Watchdog Timer.............................................................................................................137
Format of Timer Clock Select Register 2....................................................................................................138
Format of Watchdog Timer Mode Register ................................................................................................139
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
Block Diagram of 8-Bit A/D Converter........................................................................................................142
Format of A/D Converter Mode Register 0.................................................................................................144
Format of Analog Input Channel Specification Register 0 ..........................................................................145
Basic Operation of 8-Bit A/D Converter......................................................................................................147
Relationship Between Analog Input Voltage and A/D Conversion Result...................................................148
Software-Started A/D Conversion ..............................................................................................................149
How to Reduce Current Consumption in Standby Mode ............................................................................150
Conversion Result Readout Timing (When Conversion Result Is Undefined Value)..................................151
Conversion Result Readout Timing (When Conversion Result Is Normal Value).......................................151
Analog Input Pin Treatment........................................................................................................................151
A/D Conversion End Interrupt Request Generation Timing........................................................................152
AVDD Pin Treatment ...................................................................................................................................153
12-1
12-2
12-3
12-4
12-5
Block Diagram of 10-Bit A/D Converter......................................................................................................154
Format of A/D Converter Mode Register 0.................................................................................................156
Format of Analog Input Channel Specification Register 0 ..........................................................................157
Basic Operation of 10-Bit A/D Converter....................................................................................................159
Relationship Between Analog Input Voltage and A/D Conversion Result...................................................160
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LIST OF FIGURES (3/4)
Figure No.
Title
Page
12-6
Software-Started A/D Conversion...............................................................................................................161
How to Reduce Current Consumption in Standby Mode ............................................................................162
Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ..................................163
Conversion Result Readout Timing (When Conversion Result Is Normal Value).......................................163
Analog Input Pin Treatment........................................................................................................................163
A/D Conversion End Interrupt Request Generation Timing ........................................................................164
AVDD Pin Treatment....................................................................................................................................165
12-7
12-8
12-9
12-10
12-11
12-12
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
Block Diagram of Serial Interface 20 ..........................................................................................................167
Baud Rate Generator Block Diagram .........................................................................................................168
Format of Serial Operating Mode Register 20 ............................................................................................171
Format of Asynchronous Serial Interface Mode Register 20 ......................................................................172
Format of Asynchronous Serial Interface Status Register 20 .....................................................................174
Format of Baud Rate Generator Control Register 20 .................................................................................175
Asynchronous Serial Interface Transmit/Receive Data Format ..................................................................185
Asynchronous Serial Interface Transmission Completion Interrupt Timing.................................................187
Asynchronous Serial Interface Reception Completion Interrupt Timing......................................................188
Receive Error Timing..................................................................................................................................189
3-Wire Serial I/O Mode Timing ...................................................................................................................195
14-1
14-2
14-3
Block Diagram of Multiplier.........................................................................................................................203
Format of Multiplier Control Register 0.......................................................................................................204
Multiplier Operation Timing.........................................................................................................................205
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
Basic Configuration of Interrupt Function....................................................................................................208
Format of Interrupt Request Flag Register .................................................................................................210
Format of Interrupt Mask Flag Register......................................................................................................211
Format of External Interrupt Mode Register 0.............................................................................................212
Program Status Word Configuration...........................................................................................................213
Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment.....................................215
Timing of Non-Maskable Interrupt Request Acknowledgment....................................................................215
Acknowledging Non-Maskable Interrupt Request.......................................................................................215
Interrupt Acknowledgment Program Algorithm ...........................................................................................217
Interrupt Request Acknowledgment Timing (Example of MOV A,r)............................................................218
Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated at Last Clock During Instruction Execution) ..........................218
Example of Multiple Interrupt Servicing ......................................................................................................219
15-12
16-1
16-2
16-3
16-4
16-5
Format of Oscillation Stabilization Time Select Register ............................................................................222
Releasing HALT Mode by Interrupt ............................................................................................................224
Releasing HALT Mode by RESET Input.....................................................................................................225
Releasing STOP Mode by Interrupt............................................................................................................227
Releasing STOP Mode by RESET Input ....................................................................................................228
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Figure No.
Title
Page
17-1
17-2
17-3
17-4
Block Diagram of Reset Function...............................................................................................................229
Reset Timing by RESET Input ...................................................................................................................230
Reset Timing by Overflow in Watchdog Timer ...........................................................................................230
Reset Timing by RESET Input in STOP Mode...........................................................................................230
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
Environment for Writing Program to Flash Memory....................................................................................234
Communication Mode Selection Format ....................................................................................................236
Example of Connection with Dedicated Flash Programmer ......................................................................237
VPP Pin Connection Example......................................................................................................................240
Signal Conflict (Input Pin of Serial Interface)..............................................................................................241
Abnormal Operation of Other Device .........................................................................................................241
Signal Conflict (RESET Pin).......................................................................................................................242
Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch0)...243
Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode (SIO-ch1)...244
Example of Flash Memory Writing Adapter Connection When Using UART Mode....................................245
Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode ......................246
A-1
Development Tools ....................................................................................................................................401
B-1
B-2
Distance Between In-Circuit Emulator and Conversion Adapter ................................................................406
Connection Condition of Target System (NP-H44GB-TQ) .........................................................................407
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User’s Manual U14643EJ2V0UD
LIST OF TABLES (1/2)
Table No.
Title
Page
1-1
1-2
Differences Between Expanded-Specification Products and Conventional-Specification Products..............24
Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products..................................36
2-1
3-1
Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products..................................48
Types of Pin I/O Circuits and Recommended Connection of Unused Pins...................................................54
4-1
4-2
4-3
Internal ROM Capacity .................................................................................................................................60
Vector Table .................................................................................................................................................60
Special-Function Register List .....................................................................................................................69
5-1
5-2
5-3
Port Functions ..............................................................................................................................................81
Configuration of Port.....................................................................................................................................82
Port Mode Register and Output Latch Settings When Using Alternate Functions ........................................90
6-1
6-2
Configuration of Clock Generator .................................................................................................................95
Maximum Time Required for Switching CPU Clock....................................................................................101
7-1
7-2
Configuration of Clock Generator ...............................................................................................................102
Maximum Time Required for Switching CPU Clock....................................................................................108
8-1
8-2
8-3
Configuration of 16-Bit Timer 20.................................................................................................................111
Interval Time of 16-Bit Timer 20 .................................................................................................................116
Settings of Capture Edge............................................................................................................................119
9-1
9-2
9-3
9-4
9-5
9-6
9-7
Interval Time of 8-Bit Timer/Event Counter 80............................................................................................123
Square-Wave Output Range of 8-Bit Timer/Event Counter 80 ...................................................................124
8-Bit Timer/Event Counter 80 Configuration...............................................................................................124
Interval Time of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation) ..............................128
Interval Time of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation)..............................................128
Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation)......131
Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation) .....................131
10-1
10-2
10-3
10-4
10-5
Program Loop Detection Time of Watchdog Timer.....................................................................................136
Interval Time...............................................................................................................................................136
Configuration of Watchdog Timer...............................................................................................................137
Program Loop Detection Time of Watchdog Timer.....................................................................................140
Interval Time of Interval Timer....................................................................................................................141
11-1
12-1
Configuration of 8-Bit A/D Converter ..........................................................................................................142
Configuration of 10-Bit A/D Converter ........................................................................................................154
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User’s Manual U14643EJ2V0UD
LIST OF TABLES (2/2)
Table No.
Title
Page
13-1
13-2
13-3
13-4
13-5
13-6
13-7
Configuration of Serial Interface 20............................................................................................................166
Serial Interface 20 Operating Mode Settings..............................................................................................173
Example of Relationship Between System Clock and Baud Rate ..............................................................176
Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H).......177
Example of Relationship Between System Clock and Baud Rate ..............................................................184
Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H).......184
Receive Error Causes ................................................................................................................................189
15-1
15-2
15-3
Interrupt Source List...................................................................................................................................207
Flags Corresponding to Interrupt Request Signals.....................................................................................209
Time from Generation of Maskable Interrupt Request to Servicing............................................................216
16-1
16-2
16-3
16-4
HALT Mode Operating Status ....................................................................................................................223
Operation After Release of HALT Mode.....................................................................................................225
STOP Mode Operating Status....................................................................................................................226
Operation After Release of STOP Mode ....................................................................................................228
17-1
Hardware Status After Reset .....................................................................................................................231
18-1
18-2
18-3
18-4
Differences Between Flash Memory and Mask ROM Versions..................................................................233
Communication Mode List (µPD78F9116A, 78F9136A).............................................................................235
Communication Mode List (µPD78F9116B, 78F9136B).............................................................................235
Pin Connection List ....................................................................................................................................239
19-1
20-1
37-1
Selection of Mask Option for Pins ..............................................................................................................247
Operand Identifiers and Description Methods ............................................................................................248
Surface Mounting Type Soldering Conditions ...........................................................................................398
23
User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
1.1 Expanded-Specification Products and Conventional-Specification Products
The expanded-specification products and the conventional-specification products indicate the following products.
Expanded-specification products......... Products other than rankNote 1
• Mask ROM products ordered on or later than December 1, 2001
(excluding (A1) and (A2) productsNote 2
K
)
• Flash memory products shipped on or later than January 1, 2002
(excluding (A1), (A2) productsNote 2 and the µPD78F9116A)
Conventional-specification products.....RankNote 1 K products
• Products other than above
Notes 1. The rank is indicated by the letter at the 5th digit from the left in the lot number in the package marking.
Lot number
○ ○ ○ ○ △
Year code Week code
Rank
2. For (A1) and (A2) products, refer to 1.10 Differences Between Standard Quality Grade Products
and (A), (A1), (A2) Products.
The operating frequency specification differs between the expanded-specification products and the conventional-
specification products as shown in Table 1-1.
Table 1-1. Differences Between Expanded-Specification Products and Conventional-Specification Products
Supply Voltage (VDD)
Guaranteed Operating Speed (Operating Frequency)
Conventional-Specification
Products
Expanded-Specification
Products
4.5 to 5.5 V
3.0 to 5.5 V
2.7 to 5.5 V
1.8 to 5.5 V
5 MHz (0.4 µs)
5 MHz (0.4 µs)
5 MHz (0.4 µs)
1.25 MHz (1.6 µs)
10 MHz (0.2 µs)
6 MHz (0.33 µs)
5 MHz (0.4 µs)
1.25 MHz (1.6 µs)
Remark The figures in parentheses indicate the minimum instruction execution time.
24
User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
1.2 Features
• ROM and RAM capacities
Item
Program Memory
Data Memory
(Internal High-Speed RAM)
Part Number
µPD789101A, 789111A, 789101A(A), 789111A(A),
Mask ROM
2 KB
4 KB
8 KB
16 KB
256 bytes
789101A(A1), 789111A(A1), 789101A(A2), 789111A(A2)
µPD789102A, 789112A, 789102A(A), 789112A(A),
789102A(A1), 789112A(A1), 789102A(A2), 789112A(A2)
µPD789104A, 789114A, 789104A(A), 789114A(A),
789104A(A1), 789114A(A1), 789104A(A2), 789114A(A2)
µPD78F9116A, 78F9116B, 78F9116B(A), 78F9116B(A1)
• System clock: Crystal/ceramic oscillation
Flash memory
• Minimum instruction execution times switchable between high speed (0.2 µs) and low speed (0.8 µs) (system
clock: 10.0 MHzNote
)
• 20 I/O ports
• Serial interface: 1 channel
3-wire serial I/O mode/UART mode selectable
• 8-bit resolution A/D converter: 4 channels (µPD789104A Subseries)
• 10-bit resolution A/D converter: 4 channels (µPD789114A Subseries)
• 3 timers
• 16-bit timer:
• 8-bit timer/event counter: 1 channel
• Watchdog timer: 1 channel
1 channel
• Multiplier: 8 bits × 8 bits = 16 bits
• Vectored interrupt sources: 10
• Supply voltage
• VDD = 1.8 to 5.5 V (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A, 78F9116B, 78F9116B(A))
• VDD = 4.5 to 5.5 V (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2), 78F9116B(A1))
• Operating ambient temperature
• TA = −40 to + 85°C (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A, 78F9116B, 78F9116B(A))
• TA = −40 to +105°C (µPD78F9116B(A1))
• TA = −40 to +110°C (µPD78910xA(A1), 78911xA(A1))
• TA = −40 to +125°C (µPD78910xA(A2), 78911xA(A2))
Note When VDD = 4.5 to 5.5 V and for expanded-specification products only
1.3 Applications
Vacuum cleaners, washing machines, refrigerators, battery chargers, etc.
25
User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
1.4 Ordering Information
Part Number
Package
Internal ROM
µPD789101AMC-×××-5A4
µPD789102AMC-×××-5A4
µPD789104AMC-×××-5A4
µPD789111AMC-×××-5A4
µPD789112AMC-×××-5A4
µPD789114AMC-×××-5A4
µPD78F9116AMC-5A4
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
Flash memory
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
µPD78F9116BMC-5A4
µPD789101AMC(A)-×××-5A4
µPD789102AMC(A)-×××-5A4
µPD789104AMC(A)-×××-5A4
µPD789111AMC(A)-×××-5A4
µPD789112AMC(A)-×××-5A4
µPD789114AMC(A)-×××-5A4
µPD78F9116BMC(A)-5A4
µPD789101AMC(A1)-×××-5A4
µPD789102AMC(A1)-×××-5A4
µPD789104AMC(A1)-×××-5A4
µPD789111AMC(A1)-×××-5A4
µPD789112AMC(A1)-×××-5A4
µPD789114AMC(A1)-×××-5A4
µPD78F9116BMC(A1)-5A4
µPD789101AMC(A2)-×××-5A4
µPD789102AMC(A2)-×××-5A4
µPD789104AMC(A2)-×××-5A4
µPD789111AMC(A2)-×××-5A4
µPD789112AMC(A2)-×××-5A4
µPD789114AMC(A2)-×××-5A4
Remark ××× indicates ROM code suffix.
26
User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
1.5 Quality Grade
Part Number
Package
Quality Grade
µPD789101AMC-×××-5A4
µPD789102AMC-×××-5A4
µPD789104AMC-×××-5A4
µPD789111AMC-×××-5A4
µPD789112AMC-×××-5A4
µPD789114AMC-×××-5A4
µPD78F9116AMC-5A4
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
µPD78F9116BMC-5A4
µPD789101AMC(A)-×××-5A4
µPD789102AMC(A)-×××-5A4
µPD789104AMC(A)-×××-5A4
µPD789111AMC(A)-×××-5A4
µPD789112AMC(A)-×××-5A4
µPD789114AMC(A)-×××-5A4
µPD78F9116BMC(A)-5A4
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
µPD789101AMC(A1)-×××-5A4
µPD789102AMC(A1)-×××-5A4
µPD789104AMC(A1)-×××-5A4
µPD789111AMC(A1)-×××-5A4
µPD789112AMC(A1)-×××-5A4
µPD789114AMC(A1)-×××-5A4
µPD78F9116BMC(A1)-5A4
µPD789101AMC(A2)-×××-5A4
µPD789102AMC(A2)-×××-5A4
µPD789104AMC(A2)-×××-5A4
µPD789111AMC(A2)-×××-5A4
µPD789112AMC(A2)-×××-5A4
µPD789114AMC(A2)-×××-5A4
Remark ××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
27
User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
1.6 Pin Configuration (Top View)
• 30-pin plastic SSOP (7.62 mm (300))
µPD789101AMC-×××-5A4
µPD789102AMC-×××-5A4
µPD789112AMC-×××-5A4
µPD78F9116BMC-5A4
µPD789104AMC-×××-5A4
µPD789114AMC-×××-5A4
µPD789111AMC-×××-5A4
µPD78F9116AMC-5A4
µPD789101AMC(A)-×××-5A4
µPD789111AMC(A)-×××-5A4
µPD78F9116BMC(A)-5A4
µPD789102AMC(A)-×××-5A4
µPD789112AMC(A)-×××-5A4
µPD789104AMC(A)-×××-5A4
µPD789114AMC(A)-×××-5A4
µPD789101AMC(A1)-×××-5A4
µPD789111AMC(A1)-×××-5A4
µPD78F9116BMC(A1)-5A4
µPD789101AMC(A2)-×××-5A4
µPD789111AMC(A2)-×××-5A4
µPD789102AMC(A1)-×××-5A4
µPD789112AMC(A1)-×××-5A4
µPD789104AMC(A1)-×××-5A4
µPD789114AMC(A1)-×××-5A4
µPD789102AMC(A2)-×××-5A4
µPD789112AMC(A2)-×××-5A4
µPD789104AMC(A2)-×××-5A4
µPD789114AMC(A2)-×××-5A4
P23/INTP0/CPT20/SS20
1
P22/SI20/RXD20
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P24/INTP1/TO80/TO20
2
P21/SO20/TXD20
P25/INTP2/TI80
AVDD
3
P20/SCK20/ASCK20
4
P11
P10
VDD
P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
AVSS
5
6
7
VSS
8
X1
9
X2
IC0
10
11
12
13
14
15
IC0
P50
IC0 (VPP)
RESET
P03
P02
P01
P51
P52
P53
P00
Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pin.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.
Remark The pin connection in parentheses is intended for the µPD78F9116A, 78F9116B, 78F9116B(A), and
78F9116B(A1).
28
User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
ANI0 to ANI3:
ASCK20:
AVDD:
Analog input
RxD20:
SCK20:
SI20:
Receive data
Asynchronous serial input
Analog power supply
Analog ground
Capture trigger input
Internally connected
External interrupt input
Port 0
Serial clock
Serial input
AVSS:
SO20:
SS20:
TI80:
Serial output
Chip select input
Timer input
CPT20:
IC0:
INTP0 to INTP2:
P00 to P03:
P10, P11:
P20 to P25:
P50 to P53:
P60 to P63:
RESET:
TO20, TO80:
TxD20:
VDD:
Timer output
Transmit data
Power supply
Programming power supply
Ground
Port 1
Port 2
VPP:
Port 5
VSS:
Port 6
X1, X2:
Crystal 1, 2
Reset
29
User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
1.7 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y Subseries products support SMB.
Small-scale package, general-purpose applications
44-pin
42-/44-pin
µ
PD789074 with added subsystem clock
PD789046
µ
µ
µ
µ
PD789014 with enhanced timer and increased ROM, RAM capacity
PD789074 with enhanced timer and increased ROM, RAM capacity
PD789026 with enhanced timer
µ
µ
µ
µ
µ
µ
PD789026
PD789088
PD789074
PD789014
PD789062
PD789052
30-pin
30-pin
28-pin
20-pin
20-pin
On-chip UART and capable of low voltage (1.8 V) operation
RC oscillation version of the PD789052
µ
µ
PD789860 without EEPROMTM, POC, and LVI
Small-scale package, general-purpose applications and A/D converter
PD789177Y
PD789167Y
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789167 with enhanced A/D converter (10 bits)
PD789104A with enhanced timer
PD789146 with enhanced A/D converter (10 bits)
PD789104A with added EEPROM
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
30-pin
30-pin
PD789177
PD789167
PD789156
PD789146
PD789134A
PD789124A
PD789114A
PD789104A
µ
µ
µ
µ
µ
PD789124A with enhanced A/D converter (10 bits)
RC oscillation version of the
µ
PD789104A
µ
µ
PD789104A with enhanced A/D converter (10 bits)
PD789026 with added 8-bit A/D converter and multiplier
µ
LCD drive
144-pin
88-pin
80-pin
µ
µ
µ
PD789835
UART, 8-bit A/D, and dot LCD (Total display output pins: 96)
UART and dot LCD (40 16)
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28
PD789830
PD789488
×
×
4)
SIO, 8-bit A/D converter, and resistance division type LCD (28
PD789407A with enhanced A/D converter (10 bits)
SIO, 8-bit A/D converter, and resistance division type LCD (28
×
4)
µ
µ
µ
µ
µ
µ
µ
µ
PD789478
PD789417A
PD789407A
PD789456
PD789446
PD789436
PD789426
PD789316
PD789306
PD789467
80-pin
80-pin
µ
78K/0S
Series
×
4)
80-pin
64-pin
64-pin
64-pin
64-pin
µ
PD789446 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (15
×
4)
µ
PD789426 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (5
×
4)
RC oscillation version of the PD789306
64-pin
64-pin
52-pin
52-pin
µ
µ
µ
µ
SIO and on-chip voltage booster type LCD (24
× 4)
8-bit A/D and on-chip voltage booster type LCD (23
SIO and resistance division type LCD (24 4)
× 4)
×
PD789327
USB
44-pin
44-pin
µ
PD789800
For PC keyboard and on-chip USB function
On-chip inverter controller and UART
Inverter control
PD789842
µ
On-chip bus controller
PD789852
44-pin
30-pin
µ
PD789850A with enhanced functions such as timer and A/D converter
µ
PD789850A
µ
On-chip CAN controller
Keyless entry
30-pin
20-pin
20-pin
µ
µ
µ
PD789862
µPD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity
µ
RC oscillation version of the PD789860
PD789861
PD789860
On-chip POC and key return circuit
VFD drive
µ
52-pin
64-pin
PD789871
Meter control
PD789881
On-chip VFD controller (Total display output pins: 25)
µ
UART and resistance division type LCD (26
× 4)
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
30
User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
The major functional differences between the subseries are listed below.
Series for general-purpose applications and LCD drive
Function
ROM
Timer
8-Bit 10-Bit
A/D A/D
Serial
I/O
VDD
Remarks
Capacity
Interface
8-Bit 16-Bit Watch WDT
MIN.
Subseries Name
Value
Small-scale µPD789046 16 KB
1 ch 1 ch 1 ch 1 ch
−
−
1 ch
34
24
1.8 V
−
package,
(UART: 1 ch)
µPD789026 4 KB to 16 KB
−
general-
µPD789088 16 KB to
3 ch
purpose
32 KB
applications
µPD789074 2 KB to 8 KB 1 ch
µPD789014 2 KB to 4 KB 2 ch
µPD789062 4 KB
−
22
14
−
RC oscillation
version
µPD789052
−
−
Small-scale µPD789177 16 KB to
3 ch 1 ch 1 ch 1 ch
−
8 ch
−
8 ch 1 ch
31
20
1.8 V
package,
general-
24 KB
(UART: 1 ch)
µPD789167
−
4 ch
−
µPD789156 8 KB to 16 KB 1 ch
µPD789146
−
On-chip
purpose
EEPROM
applications
and A/D
4 ch
−
µPD789134A 2 KB to 8 KB
µPD789124A
4 ch
−
RC oscillation
version
converter
4 ch
−
µPD789114A
4 ch
−
−
µPD789104A
4 ch
LCD drive
µPD789835 24 KB to
6 ch
−
1 ch 1 ch 3 ch
−
1 ch
37 1.8 VNote Dot LCD
supported
60 KB
(UART: 1 ch)
µPD789830 24 KB
1 ch 1 ch
3 ch
−
30
45
2.7 V
1.8 V
µPD789488 32 KB to
8 ch 2 ch
(UART: 1 ch)
−
48 KB
µPD789478 24 KB to
8 ch
−
48 KB
µPD789417A 12 KB to
−
7 ch
−
7 ch 1 ch
43
30
40
23
24 KB
(UART: 1 ch)
µPD789407A
−
6 ch
−
µPD789456 12 KB to
2 ch
16 KB
µPD789446
6 ch
−
µPD789436
6 ch
−
µPD789426
6 ch
−
µPD789316 8 KB to 16 KB
2 ch
RC oscillation
version
(UART: 1 ch)
µPD789306
−
µPD789467 4 KB to 24 KB
µPD789327
−
1 ch
−
18
21
−
1 ch
Note Flash memory version: 3.0 V
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User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
Series for ASSP
Function
ROM
Timer
8-Bit 10-Bit
A/D A/D
Serial
I/O
VDD
Remarks
Capacity
Interface
8-Bit 16-Bit Watch WDT
MIN.
Value
Subseries Name
USB
µPD789800
8 KB
2 ch
−
−
1 ch
−
−
−
2 ch
31
30
31
18
14
4.0 V
4.0 V
4.0 V
−
−
−
(USB: 1 ch)
Inverter
control
µPD789842
8 KB to 16 KB 3 ch
1 ch 1 ch 8 ch
1 ch
Note 1
(UART: 1 ch)
On-chip bus µPD789852
24 KB to
32 KB
3 ch 1 ch
1 ch
−
1 ch
−
4 ch
−
8 ch 3 ch
(UART: 2 ch)
controller
µPD789850A 16 KB
−
2 ch
(UART: 1 ch)
Keyless
entry
µPD789861
4 KB
2 ch
−
−
1 ch
−
−
1.8 V RC oscillation
version, on-
chip EEPROM
µPD789860
µPD789862
On-chip
EEPROM
16 KB
1 ch 2 ch
1 ch
22
33
(UART: 1 ch)
VFD drive
µPD789871
µPD789881
4 KB to 8 KB 3 ch
−
1 ch 1 ch
1 ch
−
−
−
−
1 ch
2.7 V
−
−
Meter
16 KB 2 ch 1 ch
−
1 ch
28 2.7 VNote 2
control
(UART: 1 ch)
Notes 1. 10-bit timer: 1 channel
2. Flash memory version: 3.0 V
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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
1.8 Block Diagram
TI80/INTP2/P25
8-bit timer/
event counter 80
P00 to P03
P10, P11
Port 0
Port 1
Port 2
Port 5
Port 6
TO80/TO20
/INTP1/P24
TO20/TO80
/INTP1/P24
16-bit timer 20
CPT20/INTP0
/SS20/P23
P20 to P25
P50 to P53
P60 to P63
Watchdog timer
ROM
(flash
memory)
78K/0S
CPU core
SCK20/ASCK20
/P20
Serial
interface 20
SO20/TxD20/P21
SI20/RxD20/P22
SS20/INTP0
/CPT20/P23
RAM
ANI0/P60 to
ANI3/P63
RESET
X1
A/D converter
AVDD
AVSS
System control
Interrupt control
X2
INTP0/CPT20
/P23/SS20
INTP1/TO80
/TO20/P24
IC0
(VPP
VDD
VSS
INTP2/TI80/P25
)
Remarks 1. The size of the internal ROM varies depending on the product.
2. Items in parentheses apply to the µPD78F9116A, 78F9116B, 78F9116B(A), and 78F9116B(A1).
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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
1.9 Outline of Functions
Item
µ
PD789101A, 789111A,
µ
PD789102A, 789112A,
µ
PD789104A, 789114A,
µ
PD78F9116A, 78F9116B,
78F9116B(A),
789101A(A), 789111A(A),
789102A(A), 789112A(A),
789104A(A), 789114A(A),
789101A(A1), 789111A(A1), 789102A(A1), 789112A(A1), 789104A(A1), 789114A(A1),
789101A(A2), 789111A(A2) 789102A(A2), 789112A(A2) 789104A(A2), 789114A(A2)
78F9116B(A1)
Internal memory
System clock
ROM
Mask ROM
Flash memory
16 KB
2 KB
4 KB
8 KB
High-speed RAM
256 bytes
Crystal/ceramic oscillation
Minimum instruction execution time
Expanded-specification products of the µPD78910xA, 78910xA(A), 78911xA,
78911xA(A), 78F9116B, 78F9116B(A)
• 0.2 µs/0.8 µs (@ system clock: 10.0 MHz operation, VDD = 4.5 to 5.5 V)
Other
• 0.4 µs/1.6 µs (@ system clock: 5.0 MHz operation)
General-purpose registers
Instruction set
8 bits × 8 registers
• 16-bit operations
• Bit manipulations (such as set, reset, and test)
Multiplier
I/O ports
8 bits × 8 bits = 16 bits
Total:
20
4
• CMOS input:
• CMOS I/O:
• N-ch open-drain:
12
4
A/D converter
8-bit resolution × 4 channels (µPD789104A Subseries)
10-bit resolution × 4 channels (µPD789114A Subseries)
Serial interface
Timer
3-wire serial I/O mode/UART mode selectable: 1 channel
16-bit timer:
1 channel
1 channel
1 channel
8-bit timer/event counter:
Watchdog timer:
Timer outputs
One output
Vectored
interrupts
Maskable
Internal: 6, External: 3
Internal: 1
Non-maskable
Supply voltage
VDD = 1.8 to 5.5 V (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A,
78F9116B, 78F9116B(A))
VDD = 4.5 to 5.5 V (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2),
78F9116B(A1))
Operating ambient temperature
TA = −40 to +85°C (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A), 78F9116A,
78F9116B, 78F9116B(A))
TA = −40 to +105°C (µPD78F9116B(A1))
TA = −40 to +110°C (µPD78910xA(A1), 78911xA(A1))
TA = −40 to +125°C (µPD78910xA(A2), 78911xA(A2))
Package
30-pin plastic SSOP (7.62 mm (300))
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CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
An outline of the timers is shown below.
16-Bit Timer 20
8-Bit Timer/Event Counter 80
Watchdog Timer
Operating
Mode
Interval timer
−
1 channel
1 channel
1 output
1 output
1 output
−
1 channelNote
External event timer
Timer output
−
−
−
−
−
−
1
Function
1 output
PWM output
−
Square-wave output
Capture
−
1 input
1
Interrupt sources
1
Note The watchdog timer provides a watchdog timer function and an interval timer function, but only one of the
two functions can be used at a time.
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User’s Manual U14643EJ2V0UD
CHAPTER 1 GENERAL (µPD789104A, 789114A SUBSERIES)
1.10 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products
The standard quality grade products and the (A), (A1), and (A2) products refer to the following products.
[Standard quality grade products]... µPD789101A, 789102A, 789104A, 789111A, 789112A, 789114A, 78F9116A,
78F9116B
[(A) products]....µPD789101A(A), 789102A(A), 789104A(A), 789111A(A), 789112A(A), 789114A(A), 78F9116B(A)
[(A1) products]....µPD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), 789114A(A1),
78F9116B(A1)
[(A2) products]....µPD789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2), 789114A(A2)
The differences between the standard quality grade products and the (A), (A1), and (A2) products are shown in
Table 1-2.
Table 1-2. Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products
Products
Standard Quality Grade
Products
(A) Products
(A1) Products
(A2) Products
Item
Quality grade
Standard
Special
Supply voltage
VDD = 1.8 to 5.5 V
TA = −40 to +85°C
VDD = 4.5 to 5.5 V
Operating
ambient
• µPD78F9116B(A1)
TA = −40 to +105°C
• Other than
TA = −40 to +125°C
temperature
µPD78F9116B(A1)
TA = −40 to +110°C
Minimum
Expanded-specification productsNote
0.2 µs (@ 10.0 MHz operation)
:
0.4 µs (@ 5.0 MHz operation)
instruction
execution time
Conventional-specification productsNote
:
0.4 µs (@ 5.0 MHz operation)
Electrical
Refer to the relevant electrical specifications chapter.
specifications
Note Refer to 1.1 Expanded-Specification Products and Conventional-Specification Products.
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User’s Manual U14643EJ2V0UD
CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
Caution All µPD789124A, 789134A Subseries products are conventional-specification products. No
expanded-specification products are available in the µPD789124A, 789134A Subseries.
2.1 Features
• ROM and RAM capacities
Item
Program Memory
Data Memory
(Internal High-Speed RAM)
Part Number
µPD789121A, 789131A, 789121A(A), 789131A(A),
Mask ROM
2 KB
4 KB
8 KB
16 KB
256 bytes
789121A(A1), 789131A(A1), 789121A(A2), 789131A(A2)
µPD789122A, 789132A, 789122A(A), 789132A(A),
789122A(A1), 789132A(A1), 789122A(A2), 789132A(A2)
µPD789124A, 789134A, 789124A(A), 789134A(A),
789124A(A1), 789134A(A1), 789124A(A2), 789134A(A2)
µPD78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1)
Flash memory
• System clock: RC oscillation
• Minimum instruction execution times switchable between high speed (0.5 µs) and low speed (2.0 µs) (system
clock: 4.0 MHz)
• 20 I/O ports
• Serial interface: 1 channel
3-wire serial I/O mode/UART mode selectable
• 8-bit resolution A/D converter: 4 channels (µPD789124A Subseries)
• 10-bit resolution A/D converter: 4 channels (µPD789134A Subseries)
• 3 timers
• 16-bit timer:
• 8-bit timer/event counter: 1 channel
• Watchdog timer: 1 channel
1 channel
• Multiplier: 8 bits × 8 bits = 16 bits
• Vectored interrupt sources: 10
• Supply voltage
• VDD = 1.8 to 5.5 V (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A, 78F9136B, 78F9136B(A))
• VDD = 4.5 to 5.5 V (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2), 78F9136B(A1))
• Operating ambient temperature
• TA = −40 to + 85°C (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A, 78F9136B, 78F9136B(A))
• TA = −40 to +105°C (µPD78F9136B(A1))
• TA = −40 to +110°C (µPD78912xA(A1), 78913xA(A1))
• TA = −40 to +125°C (µPD78912xA(A2), 78913xA(A2))
2.2 Applications
Vacuum cleaners, washing machines, refrigerators, battery chargers, etc.
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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
2.3 Ordering Information
Part Number
Package
Internal ROM
µPD789121AMC-×××-5A4
µPD789122AMC-×××-5A4
µPD789124AMC-×××-5A4
µPD789131AMC-×××-5A4
µPD789132AMC-×××-5A4
µPD789134AMC-×××-5A4
µPD78F9136AMC-5A4
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
Flash memory
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
µPD78F9136BMC-5A4
µPD789121AMC(A)-×××-5A4
µPD789122AMC(A)-×××-5A4
µPD789124AMC(A)-×××-5A4
µPD789131AMC(A)-×××-5A4
µPD789132AMC(A)-×××-5A4
µPD789134AMC(A)-×××-5A4
µPD78F9136BMC(A)-5A4
µPD789121AMC(A1)-×××-5A4
µPD789122AMC(A1)-×××-5A4
µPD789124AMC(A1)-×××-5A4
µPD789131AMC(A1)-×××-5A4
µPD789132AMC(A1)-×××-5A4
µPD789134AMC(A1)-×××-5A4
µPD78F9136BMC(A1)-5A4
µPD789121AMC(A2)-×××-5A4
µPD789122AMC(A2)-×××-5A4
µPD789124AMC(A2)-×××-5A4
µPD789131AMC(A2)-×××-5A4
µPD789132AMC(A2)-×××-5A4
µPD789134AMC(A2)-×××-5A4
Remark ××× indicates ROM code suffix.
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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
2.4 Quality Grade
Part Number
Package
Quality Grade
µPD789121AMC-×××-5A4
µPD789122AMC-×××-5A4
µPD789124AMC-×××-5A4
µPD789131AMC-×××-5A4
µPD789132AMC-×××-5A4
µPD789134AMC-×××-5A4
µPD78F9136AMC-5A4
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
Special
µPD78F9136BMC-5A4
µPD789121AMC(A)-×××-5A4
µPD789122AMC(A)-×××-5A4
µPD789124AMC(A)-×××-5A4
µPD789131AMC(A)-×××-5A4
µPD789132AMC(A)-×××-5A4
µPD789134AMC(A)-×××-5A4
µPD78F9136BMC(A)-5A4
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
µPD789121AMC(A1)-×××-5A4
µPD789122AMC(A1)-×××-5A4
µPD789124AMC(A1)-×××-5A4
µPD789131AMC(A1)-×××-5A4
µPD789132AMC(A1)-×××-5A4
µPD789134AMC(A1)-×××-5A4
µPD78F9136BMC(A1)-5A4
µPD789121AMC(A2)-×××-5A4
µPD789122AMC(A2)-×××-5A4
µPD789124AMC(A2)-×××-5A4
µPD789131AMC(A2)-×××-5A4
µPD789132AMC(A2)-×××-5A4
µPD789134AMC(A2)-×××-5A4
Remark ××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
2.5 Pin Configuration (Top View)
• 30-pin plastic SSOP (7.62 mm (300))
µPD789121AMC-×××-5A4
µPD789122AMC-×××-5A4
µPD789132AMC-×××-5A4
µPD78F9136BMC-5A4
µPD789124AMC-×××-5A4
µPD789134AMC-×××-5A4
µPD789131AMC-×××-5A4
µPD78F9136AMC-5A4
µPD789121AMC(A)-×××-5A4
µPD789131AMC(A)-×××-5A4
µPD78F9136BMC(A)-5A4
µPD789122AMC(A)-×××-5A4
µPD789132AMC(A)-×××-5A4
µPD789124AMC(A)-×××-5A4
µPD789134AMC(A)-×××-5A4
µPD789121AMC(A1)-×××-5A4
µPD789131AMC(A1)-×××-5A4
µPD78F9136BMC(A1)-5A4
µPD789121AMC(A2)-×××-5A4
µPD789131AMC(A2)-×××-5A4
µPD789122AMC(A1)-×××-5A4
µPD789132AMC(A1)-×××-5A4
µPD789124AMC(A1)-×××-5A4
µPD789134AMC(A1)-×××-5A4
µPD789122AMC(A2)-×××-5A4
µPD789132AMC(A2)-×××-5A4
µPD789124AMC(A2)-×××-5A4
µPD789134AMC(A2)-×××-5A4
P23/INTP0/CPT20/SS20
1
P22/SI20/RXD20
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P24/INTP1/TO80/TO20
2
P21/SO20/TXD20
P25/INTP2/TI80
AVDD
3
P20/SCK20/ASCK20
4
P11
P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
AVSS
5
P10
6
VDD
7
VSS
8
CL1
9
CL2
IC0
10
11
12
13
14
15
IC0
P50
IC0 (VPP)
RESET
P03
P51
P52
P53
P02
P00
P01
Cautions 1. Connect the IC0 (internally connected) pin directly to the VSS pin.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.
Remark The pin connection in parentheses is intended for the µPD78F9136A, 78F9136B, 78F9136B(A), and
78F9136B(A1).
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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
ANI0 to ANI3:
ASCK20:
AVDD:
Analog input
RESET:
RxD20:
SCK20:
SI20:
Reset
Asynchronous serial input
Analog power supply
Analog ground
RC oscillator
Capture trigger input
Internally connected
External interrupt input
Port 0
Receive data
Serial clock
AVSS:
Serial input
CL1, CL2:
CPT20:
SO20:
SS20:
TI80:
Serial output
Chip select input
Timer input
IC0:
INTP0 to INTP2:
P00 to P03:
P10, P11:
P20 to P25:
P50 to P53:
P60 to P63:
TO20, TO80:
TxD20:
VDD:
Timer output
Transmit data
Power supply
Programming power supply
Ground
Port 1
Port 2
VPP:
Port 5
VSS:
Port 6
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CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
2.6 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y Subseries products support SMB.
Small-scale package, general-purpose applications
44-pin
µ
PD789074 with added subsystem clock
PD789046
µ
µ
42-/44-pin
PD789014 with enhanced timer and increased ROM, RAM capacity
µ
µ
µ
µ
µ
µ
PD789026
PD789088
PD789074
PD789014
PD789062
PD789052
30-pin
30-pin
28-pin
20-pin
20-pin
PD789074 with enhanced timer and increased ROM, RAM capacity
PD789026 with enhanced timer
µ
µ
On-chip UART and capable of low voltage (1.8 V) operation
RC oscillation version of the PD789052
µ
µ
PD789860 without EEPROM, POC, and LVI
Small-scale package, general-purpose applications and A/D converter
PD789177Y
PD789167Y
µ
µ
µ
µ
PD789167 with enhanced A/D converter (10 bits)
PD789104A with enhanced timer
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
30-pin
30-pin
PD789177
PD789167
PD789156
PD789146
PD789134A
PD789124A
PD789114A
PD789104A
µ
µ
µ
µ
µ
PD789146 with enhanced A/D converter (10 bits)
PD789104A with added EEPROM
PD789124A with enhanced A/D converter (10 bits)
µ
µ
µ
µ
µ
RC oscillation version of the
µ
PD789104A
µ
µ
PD789104A with enhanced A/D converter (10 bits)
PD789026 with added 8-bit A/D converter and multiplier
µ
LCD drive
144-pin
88-pin
80-pin
µ
µ
µ
PD789835
UART, 8-bit A/D, and dot LCD (Total display output pins: 96)
UART and dot LCD (40 16)
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28
PD789830
PD789488
×
×
4)
SIO, 8-bit A/D converter, and resistance division type LCD (28
PD789407A with enhanced A/D converter (10 bits)
SIO, 8-bit A/D converter, and resistance division type LCD (28
×
4)
µ
µ
µ
µ
PD789478
PD789417A
PD789407A
PD789456
PD789446
PD789436
PD789426
PD789316
PD789306
PD789467
80-pin
80-pin
µ
78K/0S
Series
×
4)
80-pin
64-pin
64-pin
64-pin
64-pin
µ
PD789446 with enhanced A/D converter (10 bits)
µ
µ
µ
µ
SIO, 8-bit A/D, and on-chip voltage booster type LCD (15
×
4)
µ
PD789426 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (5
×
4)
RC oscillation version of the PD789306
64-pin
64-pin
52-pin
52-pin
µ
µ
µ
µ
SIO and on-chip voltage booster type LCD (24
× 4)
8-bit A/D and on-chip voltage booster type LCD (23
SIO and resistance division type LCD (24 4)
× 4)
×
PD789327
USB
44-pin
44-pin
µ
PD789800
For PC keyboard and on-chip USB function
On-chip inverter controller and UART
Inverter control
PD789842
µ
On-chip bus controller
PD789852
44-pin
30-pin
µ
PD789850A with enhanced functions such as timer and A/D converter
µ
PD789850A
µ
On-chip CAN controller
Keyless entry
30-pin
20-pin
20-pin
µ
µ
µ
PD789862
µPD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity
µ
RC oscillation version of the PD789860
PD789861
PD789860
On-chip POC and key return circuit
VFD drive
µ
52-pin
64-pin
PD789871
Meter control
PD789881
On-chip VFD controller (Total display output pins: 25)
µ
UART and resistance division type LCD (26
× 4)
Remark VFD (Vacuum Fluorescent Display) is referred to as FIP (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
42
User’s Manual U14643EJ2V0UD
CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
The major functional differences between the subseries are listed below.
Series for general-purpose applications and LCD drive
Function
ROM
Timer
8-Bit 10-Bit
A/D A/D
Serial
I/O
VDD
Remarks
Capacity
Interface
8-Bit 16-Bit Watch WDT
MIN.
Subseries Name
Value
Small-scale µPD789046 16 KB
1 ch 1 ch 1 ch 1 ch
−
−
1 ch
34
24
1.8 V
−
package,
(UART: 1 ch)
µPD789026 4 KB to 16 KB
−
general-
µPD789088 16 KB to
3 ch
purpose
32 KB
applications
µPD789074 2 KB to 8 KB 1 ch
µPD789014 2 KB to 4 KB 2 ch
µPD789062 4 KB
−
22
14
−
RC oscillation
version
µPD789052
−
−
Small-scale µPD789177 16 KB to
3 ch 1 ch 1 ch 1 ch
−
8 ch
−
8 ch 1 ch
31
20
1.8 V
package,
general-
24 KB
(UART: 1 ch)
µPD789167
−
4 ch
−
µPD789156 8 KB to 16 KB 1 ch
µPD789146
−
On-chip
purpose
EEPROM
applications
and A/D
4 ch
−
µPD789134A 2 KB to 8 KB
µPD789124A
4 ch
−
RC oscillation
version
converter
4 ch
−
µPD789114A
4 ch
−
−
µPD789104A
4 ch
LCD drive
µPD789835 24 KB to
6 ch
−
1 ch 1 ch 3 ch
−
1 ch
37 1.8 VNote Dot LCD
supported
60 KB
(UART: 1 ch)
µPD789830 24 KB
1 ch 1 ch
3 ch
−
30
45
2.7 V
1.8 V
µPD789488 32 KB to
8 ch 2 ch
(UART: 1 ch)
−
48 KB
µPD789478 24 KB to
8 ch
−
48 KB
µPD789417A 12 KB to
−
7 ch
−
7 ch 1 ch
43
30
40
23
24 KB
(UART: 1 ch)
µPD789407A
−
6 ch
−
µPD789456 12 KB to
2 ch
16 KB
µPD789446
6 ch
−
µPD789436
6 ch
−
µPD789426
6 ch
−
µPD789316 8 KB to 16 KB
2 ch
RC oscillation
version
(UART: 1 ch)
µPD789306
−
µPD789467 4 KB to 24 KB
µPD789327
−
1 ch
−
18
21
−
1 ch
Note Flash memory version: 3.0 V
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User’s Manual U14643EJ2V0UD
CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
Series for ASSP
Function
ROM
Timer
8-Bit 10-Bit
A/D A/D
Serial
I/O
VDD
Remarks
Capacity
Interface
8-Bit 16-Bit Watch WDT
MIN.
Value
Subseries Name
USB
µPD789800
8 KB
2 ch
−
−
1 ch
−
−
−
2 ch
31
30
31
18
14
4.0 V
4.0 V
4.0 V
−
−
−
(USB: 1 ch)
Inverter
control
µPD789842
8 KB to 16 KB 3 ch
1 ch 1 ch 8 ch
1 ch
Note 1
(UART: 1 ch)
On-chip bus µPD789852
24 KB to
32 KB
3 ch 1 ch
1 ch
−
1 ch
−
4 ch
−
8 ch 3 ch
(UART: 2 ch)
controller
µPD789850A 16 KB
−
2 ch
(UART: 1 ch)
Keyless
entry
µPD789861
4 KB
2 ch
−
−
1 ch
−
−
1.8 V RC oscillation
version, on-
chip EEPROM
µPD789860
µPD789862
On-chip
EEPROM
16 KB
1 ch 2 ch
1 ch
22
33
(UART: 1 ch)
VFD drive
µPD789871
µPD789881
4 KB to 8 KB 3 ch
−
1 ch 1 ch
1 ch
−
−
−
−
1 ch
2.7 V
−
−
Meter
16 KB 2 ch 1 ch
−
1 ch
28 2.7 VNote 2
control
(UART: 1 ch)
Notes 1. 10-bit timer: 1 channel
2. Flash memory version: 3.0 V
44
User’s Manual U14643EJ2V0UD
CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
2.7 Block Diagram
TI80/INTP2/P25
8-bit timer/
event counter 80
P00 to P03
P10, P11
Port 0
Port 1
Port 2
Port 5
Port 6
TO80/TO20
/INTP1/P24
TO20/TO80
/INTP1/P24
16-bit timer 20
CPT20/INTP0
/SS20/P23
P20 to P25
P50 to P53
P60 to P63
Watchdog timer
ROM
(flash
memory)
78K/0S
CPU core
SCK20/ASCK20
/P20
Serial
interface 20
SO20/TxD20/P21
SI20/RxD20/P22
SS20/INTP0
/CPT20/P23
RAM
ANI0/P60 to
ANI3/P63
RESET
CL1
A/D converter
AVDD
AVSS
System control
Interrupt control
CL2
INTP0/CPT20
/P23/SS20
INTP1/TO80
/TO20/P24
V
DD
V
SS
IC0
(VPP
INTP2/TI80/P25
)
Remarks 1. The size of the internal ROM varies depending on the product.
2. Items in parentheses apply to the µPD78F9136A, 78F9136B, 78F9136B(A), 78F9136B(A1).
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User’s Manual U14643EJ2V0UD
CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
2.8 Outline of Functions
Item
µ
PD789121A, 789131A,
µ
PD789122A, 789132A,
µ
PD789124A, 789134A,
µ
PD78F9136A, 78F9136B,
78F9136B(A),
789121A(A), 789131A(A),
789122A(A), 789132A(A),
789124A(A), 789134A(A),
789121A(A1), 789131A(A1), 789122A(A1), 789132A(A1), 789124A(A1), 789134A(A1),
789121A(A2), 789131A(A2) 789122A(A2), 789132A(A2) 789124A(A2), 789134A(A2)
78F9136B(A1)
Internal memory
System clock
ROM
Mask ROM
Flash memory
16 KB
2 KB
4 KB
8 KB
High-speed RAM
256 bytes
RC oscillation
Minimum instruction execution time
General-purpose registers
Instruction set
0.5/2.0 µs (@ system clock: 4.0 MHz operation)
8 bits × 8 registers
• 16-bit operations
• Bit manipulations (such as set, reset, and test)
Multiplier
I/O ports
8 bits × 8 bits = 16 bits
Total:
20
4
• CMOS input:
• CMOS I/O:
• N-ch open-drain:
12
4
A/D converter
8-bit resolution × 4 channels (µPD789124A Subseries)
10-bit resolution × 4 channels (µPD789134A Subseries)
Serial interface
Timer
3-wire serial I/O mode/UART mode selectable: 1 channel
16-bit timer:
1 channel
1 channel
1 channel
8-bit timer/event counter:
Watchdog timer:
Timer outputs
One output
Vectored
interrupts
Maskable
Internal: 6, External: 3
Internal: 1
Non-maskable
Supply voltage
VDD = 1.8 to 5.5 V (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A,
78F9136B, 78F9136B(A))
VDD = 4.5 to 5.5 V (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2),
78F9136B(A1))
Operating ambient temperature
TA = −40 to +85°C (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A,
78F9136B, 78F9136B(A))
TA = −40 to +105°C (µPD78F9136B(A1))
TA = −40 to +110°C (µPD78912xA(A1), 78913xA(A1))
TA = −40 to +125°C (µPD78912xA(A2), 78913xA(A2))
Package
30-pin plastic SSOP (7.62 mm (300))
46
User’s Manual U14643EJ2V0UD
CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
An outline of the timers is shown below.
16-Bit Timer 20
8-Bit Timer/Event Counter 80
Watchdog Timer
Operating
Mode
Interval timer
−
1 channel
1 channel
1 output
1 output
1 output
−
1 channelNote
External event timer
Timer output
−
−
−
−
−
−
1
Function
1 output
PWM output
−
Square-wave output
Capture
−
1 input
1
Interrupt sources
1
Note The watchdog timer provides a watchdog timer function and an interval timer function, but only one of the
two functions can be used at a time.
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User’s Manual U14643EJ2V0UD
CHAPTER 2 GENERAL (µPD789124A, 789134A SUBSERIES)
2.9 Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products
The standard quality grade products and the (A), (A1), and (A2) products refer to the following products.
[Standard quality grade products]... µPD789121A, 789122A, 789124A, 789131A, 789132A, 789134A, 78F9136A,
78F9136B
[(A) products]....µPD789121A(A), 789122A(A), 789124A(A), 789131A(A), 789132A(A), 789134A(A) , 78F9136B(A)
[(A1) products]....µPD789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1), 789134A(A1),
78F9136B(A1)
[(A2) products]....µPD789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2), 789134A(A2)
The differences between the standard quality grade products and the (A), (A1), and (A2) products are shown in
Table 2-1.
Table 2-1. Differences Between Standard Quality Grade Products and (A), (A1), (A2) Products
Products
Standard Quality Grade
Products
(A) Products
(A1) Products
(A2) Products
Item
Quality grade
Standard
Special
Supply voltage
VDD = 1.8 to 5.5 V
TA = −40 to +85°C
VDD = 4.5 to 5.5 V
Operating
ambient
• µPD78F9136B(A1)
TA = −40 to +105°C
• Other than
TA = −40 to +125°C
temperature
µPD78F9136B(A1)
TA = −40 to +110°C
Electrical
Refer to the relevant electrical specifications chapter.
specifications
48
User’s Manual U14643EJ2V0UD
CHAPTER 3 PIN FUNCTIONS
3.1 Pin Function List
(1) Port pins
Pin Name
I/O
I/O
Function
After Reset
Input
Alternate Function
P00 to P03
Port 0
−
4-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by pull-up resistor option register 0 (PU0).
P10, P11
I/O
I/O
Port 1
Input
Input
−
2-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by pull-up resistor option register 0 (PU0).
P20
Port 2
SCK20/ASCK20
SO20/TxD20
SI20/RxD20
INTP0/CPT20/SS20
INTP1/TO80/TO20
INTP2/TI80
6-bit I/O port
P21
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by pull-up
resistor option register B2 (PUB2).
P22
P23
P24
P25
P50 to P53
I/O
Port 5
Input
Input
−
4-bit N-channel open-drain I/O port
Input/output can be specified in 1-bit units.
For a mask ROM version, use of an on-chip pull-up resistor
can be specified by a mask option.
P60 to P63
Input
Port 6
ANI0 to ANI3
4-bit input-only port
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User’s Manual U14643EJ2V0UD
CHAPTER 3 PIN FUNCTIONS
(2) Non-port pins
Pin Name
INTP0
I/O
Function
After Reset
Input
Alternate Function
Input
External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified.
P23/CPT20/SS20
INTP1
INTP2
SI20
P24/TO80/TO20
P25/TI80
Input
Serial data input to serial interface
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
−
P22/RxD20
SO20
SCK20
ASCK20
SS20
RxD20
TxD20
TI80
Output Serial data output from serial interface
P21/TxD20
I/O
Serial clock I/O for serial interface
P20/ASCK20
Input
Input
Input
Serial clock input to asynchronous serial interface
Chip select input to serial interface
P20/SCK20
P23/CPT20/INTP0
Serial data input to asynchronous serial interface
P22/SI20
Output Serial data output from asynchronous serial interface
Input External count clock input to 8-bit timer/event counter 80
P21/SO20
P25/INTP2
TO80
TO20
CPT20
ANI0 to ANI3
AVSS
Output 8-bit timer/event counter 80 output
Output 16-bit timer 20 output
P24/INTP1/TO20
P24/INTP1/TO80
Input
Capture edge input
P23/INTP0/SS20
Input
A/D converter analog input
A/D converter ground potential
A/D converter analog power supply
P60 to P63
−
−
−
−
−
−
−
−
−
−
−
−
AVDD
−
−
X1
Input
Connecting ceramic resonator/crystal resonator for system
−
clock oscillation (µPD789104A, 789114A Subseries)
X2
−
−
CL1
Input
Connecting resistor (R) and capacitor (C) for system clock
−
oscillation (µPD789124A and 789134A Subseries)
CL2
−
−
RESET
VDD
Input
System reset input
Input
−
−
−
−
−
Positive power supply
VSS
Ground potential
−
IC0
Internally connected. Directly connect to the VSS pin.
−
VPP
Sets flash memory programming mode. Applies a high voltage
when a program is written or verified.
−
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CHAPTER 3 PIN FUNCTIONS
3.2 Description of Pin Functions
3.2.1 P00 to P03 (Port 0)
These pins constitute a 4-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode
register 0 (PM0). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by
means of pull-up resistor option register 0 (PU0).
3.2.2 P10, P11 (Port 1)
These pins constitute a 2-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode
register 1 (PM1). When these pins are used as an input port, use of an on-chip pull-up resistor can be specified by
means of pull-up resistor option register 0 (PU0).
3.2.3 P20 to P25 (Port 2)
These pins constitute a 6-bit I/O port. In addition, they function as timer I/O, external interrupt inputs, and serial
interface data and clock I/O.
Port 2 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, P20 to P25 function as a 6-bit I/O port. Port 2 can be specified as input or output mode in 1-bit
units by using port mode register 2 (PM2). Use of an on-chip pull-up resistor can be specified in 1-bit units by
using pull-up resistor option register B2 (PUB2), regardless of the setting of port mode register 2 (PM2).
(2) Control mode
In this mode, P20 to P25 function as timer I/O, external interrupt input, clock I/O of the serial interface and the
data I/O.
(a) TI80
This is the external clock input pin for 8-bit timer/event counter 80.
(b) TO20,TO80
TO20 is the output pin of 16-bit timer 20. TO80 is the output pin of 8-bit timer/event counter 80.
(c) CPT20
This is the input pin of the capture edge.
(d) INTP0 to INTP2
These are external interrupt input pins for which the valid edge (rising edge, falling edge, and both rising
and falling edges) can be specified.
(e) SI20, SO20
These are the serial data I/O pins of the serial interface.
(f) SCK20
These are the serial clock I/O pins of the serial interface.
(g) SS20
This is the chip select input pin of the serial interface.
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User’s Manual U14643EJ2V0UD
CHAPTER 3 PIN FUNCTIONS
(h) RxD20,TxD20
These are the serial data I/O pins of the asynchronous serial interface.
(i) ASCK20
This is the serial clock input pin of the asynchronous serial interface.
Caution When using these pins as serial interface pins, the I/O mode and output latch must be set
according to the function to be used. For details of the setting, refer to Table 13-2 Serial
Interface 20 Operating Mode Settings.
3.2.4 P50 to P53 (Port 5)
These pins constitute a 4-bit N-ch open-drain I/O port and can be specified in input or output mode in 1-bit units by
using port mode register 5 (TM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by a
mask option.
3.2.5 P60 to P63 (Port 6)
These pins constitute a 4-bit input-only port. In addition to general-purpose input ports, these pins function as the
A/D converter input pins.
(1) Port mode
In the port mode, these pins function as a 4-bit input-only port.
(2) Control mode
In the control mode, the pins of port 6 can be used as A/D converter analog inputs (ANI0 to ANI3).
3.2.6 RESET
This pin inputs an active-low system reset signal.
3.2.7 X1, X2 (µPD789104A, 789114A Subseries)
These pins are used to connect a ceramic resonator/crystal resonator for system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
3.2.8 CL1, CL2 (µPD789124A, 789134A Subseries)
These are resistor (R) and capacitor (C) connection pins for system clock oscillation.
3.2.9 AVDD
This is the analog power supply pin of the A/D converter. Always use the same potential as that of the VDD pin even
when the A/D converter is not used.
3.2.10 AVSS
This is the ground potential pin of the A/D converter. Always use the same potential as that of the VSS pin even
when the A/D converter is not used.
3.2.11 VDD
This is the positive power supply pin.
3.2.12 VSS
This is the ground pin.
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CHAPTER 3 PIN FUNCTIONS
3.2.13 VPP (µPD78F9116A, 78F9116B, 78F9136A, 78F9136B only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Connect this pin in either of the following ways.
• Independently connect to a 10 kΩ pull-down resistor.
• By using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode or
to VSS in the normal operation mode.
If the wiring between the VPP and VSS pins is long or external noise is superimposed on the VPP pin, the user
program may malfunction.
3.2.14 IC0 (pin No.20) (mask ROM versions only)
The IC0 (internally connected) pin (No. 20) (refer to 1.6 Pin Configuration (Top View), 2.5 Pin Configuration
(Top View)) is used to set the µPD789104A/114A/124A/134A Subseries in the test mode before shipment. In the
normal operation mode, connect this pin directly to the VSS pin with as short a wiring length as possible.
If a potential difference is generated between the IC0 pin and VSS pin due to a long wiring length between the IC0
pin and VSS pin or external noise superimposed on the IC0 pin, the user program may malfunction.
○ Connect the IC0 pin directly to the VSS pin.
(pin No.20)
Keep short
V
SS IC0
3.2.15 IC0 (pins No.10 and No.21)
The IC0 pins (No.10 and No.21) (refer to 1.6 Pin Configuration (Top View), 2.5 Pin Configuration (Top View)
are internally connected.
Connect the IC0 pins directly to VSS.
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CHAPTER 3 PIN FUNCTIONS
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type for each pin and the recommended connection of pins are shown in Table 3-1.
For the I/O circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name
P00 to P03
I/O Circuit Type
5-A
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect these pins to VDD or VSS via a
resistor.
P10, P11
Output: Leave open
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/INTP0/CPT20/SS20
P24/INTP1/TO80/TO20
P25/INTP2/TI80
8-A
Input: Independently connect these pins to VSS via a resistor.
Output: Leave open
P50 to P53
13-W
13-V
Input: Directly connect these pins to VSS.
Output: Leave these pins open at low-level output after setting
the port output latch to 0.
(Mask ROM version)
P50 to P53
(µPD78F9116A, 78F9116B,
78F9136A, 78F9136B)
P60/ANI0 to P63/ANI3
9-C
Input
Directly connect to VDD or VSS.
Directly connect to VDD.
Directly connect to VSS.
−
AVDD
AVSS
RESET
IC0
−
−
2
Input
−
−
Directly connect to VSS.
Independently connect 10 kΩ pull-down resistor to this pin or
VPP
connect this pin directly to VSS.
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User’s Manual U14643EJ2V0UD
CHAPTER 3 PIN FUNCTIONS
Figure 3-1. Pin I/O Circuits
Type 2
Type 9-C
Comparator
P-ch
N-ch
+
IN
−
IN
AVSS
V
REF
(Threshold voltage)
Schmitt-triggered input with hysteresis characteristics
Input
enable
Type 13-V
Type 5-A
V
DD
Pull-up
enable
P-ch
IN/OUT
Output data
Output disable
N-ch
VDD
Data
P-ch
V
SS
IN/OUT
Input enable
Output
disable
N-ch
Middle-voltage input buffer
V
SS
Input
enable
Type 8-A
Type 13-W
V
DD
VDD
Pull-up resistor
(mask option)
Pull-up
enable
P-ch
IN/OUT
V
DD
Output data
Output disable
N-ch
Data
P-ch
IN/OUT
V
SS
Output
disable
N-ch
Input enable
V
SS
Middle-voltage input buffer
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4.1 Memory Space
The µPD789104A/114A/124A/134A Subseries can access 64 KB of memory space. Figures 4-1 to 4-4 show the
memory maps.
Figure 4-1. Memory Map (µPD789101A, 789111A, 789121A, 789131A)
FFFFH
Special-function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
256 × 8 bits
FE00H
FDFFH
Reserved
Data
memory space
07FFH
0800H
07FFH
Program area
0080H
007FH
Program
memory space
Internal ROM
2,048 × 8 bits
CALLT table area
Program area
0040H
003FH
0016H
0015H
Vector table area
0000H
0000H
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Figure 4-2. Memory Map (µPD789102A, 789112A, 789122A, 789132A)
FFFFH
Special-function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
256 × 8 bits
FE00H
FDFFH
Reserved
Data
memory space
0FFFH
1000H
0FFFH
Program area
0080H
007FH
Program
memory space
Internal ROM
4,096 × 8 bits
CALLT table area
Program area
0040H
003FH
0016H
0015H
Vector table area
0000H
0000H
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Figure 4-3. Memory Map (µPD789104A, 789114A, 789124A, 789134A)
FFFFH
Special-function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
256 × 8 bits
FE00H
FDFFH
Reserved
Data
memory space
1FFFH
2000H
1FFFH
Program area
0080H
007FH
Program
memory space
Internal ROM
8,192 × 8 bits
CALLT table area
Program area
0040H
003FH
0016H
0015H
Vector table area
0000H
0000H
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Figure 4-4. Memory Map (µPD78F9116A, 78F9116B, 78F9136A, 78F9136B)
FFFFH
Special-function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
256 × 8 bits
FE00H
FDFFH
Reserved
Data
memory space
3FFFH
4000H
3FFFH
Program area
0080H
007FH
Program
memory space
Flash memory
16,384 × 8 bits
CALLT table area
Program area
0040H
003FH
0016H
0015H
Vector table area
0000H
0000H
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4.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The µPD789104A/114A/124A/134A Subseries provides the following internal ROMs (or flash memory) containing
the following capacities.
Table 4-1. Internal ROM Capacity
Part Number
Internal ROM
Structure
Mask ROM
Capacity
µPD789101A, 789111A, 789121A, 789131A
µPD789102A, 789112A, 789122A, 789132A
µPD789104A, 789114A, 789124A, 789134A
µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
2,048 × 8 bits
4,096 × 8 bits
8,192 × 8 bits
16,384 × 8 bits
Flash memory
The following areas are allocated to the internal program memory space.
(1) Vector table area
The 22-byte area of addresses 0000H to 0015H is reserved as a vector table area. This area stores program
start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit
program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd
address.
Table 4-2. Vector Table
Vector Table Address
0000H
Interrupt Request
RESET input
Vector Table Address
000CH
Interrupt Request
INTSR20/INTCSI20
INTST20
0004H
0006H
0008H
000AH
INTWDT
INTP0
INTP1
INTP2
000EH
0010H
0012H
0014H
INTTM80
INTTM20
INTAD0
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
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4.1.2 Internal data memory (internal high-speed RAM) space
The µPD789104A/114A/124A/134A Subseries provides a 256-byte internal high-speed RAM.
The internal high-speed RAM can also be used as a stack memory.
4.1.3 Special-function register (SFR) area
Special-function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH
(refer to Table 4-3).
4.1.4 Data memory addressing
The µPD789104A/114A/124A/134A Subseries provides a variety of addressing modes which take account of
memory manipulability, etc. Especially at addresses corresponding to data memory area (FE00H to FEFFH),
particular addressing modes can be used to meet the functions of the special-function registers (SFRs) and general-
purpose registers. Figures 4-5 to 4-8 show the data memory addressing modes.
Figure 4-5. Data Memory Addressing (µPD789101A, 789111A, 789121A, 789131A)
FFFFH
Special-function registers (SFRs)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
256 × 8 bits
FE20H
FE1FH
FE00H
FDFFH
Direct addressing
Register indirect
addressing
Based addressing
Reserved
0800H
07FFH
Internal ROM
2,048 × 8 bits
0000H
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Figure 4-6. Data Memory Addressing (µPD789102A, 789112A, 789122A, 789132A)
FFFFH
Special-function registers (SFRs)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
256 × 8 bits
FE20H
FE1FH
FE00H
FDFFH
Direct addressing
Register indirect
addressing
Based addressing
Reserved
1000H
0FFFH
Internal ROM
4,096 × 8 bits
0000H
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Figure 4-7. Data Memory Addressing (µPD789104A, 789114A, 789124A, 789134A)
FFFFH
Special-function registers (SFRs)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
256 × 8 bits
FE20H
FE1FH
FE00H
FDFFH
Direct addressing
Register indirect
addressing
Based addressing
Reserved
2000H
1FFFH
Internal ROM
8,192 × 8 bits
0000H
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Figure 4-8. Data Memory Addressing (µPD78F9116A, 78F9116B, 78F9136A, 78F9136B)
FFFFH
Special-function registers (SFRs)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct
addressing
Internal high-speed RAM
256 × 8 bits
FE20H
FE1FH
FE00H
FDFFH
Direct addressing
Register indirect
addressing
Based addressing
Reserved
4000H
3FFFH
Flash memory
16,384 × 8 bits
0000H
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4.2 Processor Registers
The µPD789104A/114A/124A/134A Subseries provides the following on-chip processor registers.
4.2.1 Control registers
The control registers contain special functions to control the program sequence statuses and stack memory. The
program counter, program status word, and stack pointer are control registers.
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to
be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 4-9. Program Counter Configuration
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 4-10. Program Status Word Configuration
7
0
IE
Z
0
AC
0
0
1
CY
PSW
(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledgment operations of CPU.
When IE = 0, the IE flag is set to the interrupt disabled (DI) status. All interrupt requests except non-
maskable interrupts are disabled.
When IE = 1, the IE flag is set to the interrupt enabled (EI) status and interrupt request acknowledgment is
controlled by the interrupt mask flag for each interrupt source.
This flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(d) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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(3) Stack pointer (SP)
This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 4-11. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of a write (save) to the stack memory and is incremented after a read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 4-12 and 4-13.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 4-12. Data to Be Saved to Stack Memory
Interrupt
PUSH rp
instruction
CALL, CALLT
instructions
_
_
_
_
SP SP
SP
3
3
2
1
_
_
_
_
_
_
SP SP
SP
2
2
1
SP SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Register pair
lower
SP
PC7 to PC0
Register pair
higher
SP
SP
PC15 to PC8
SP
SP
SP
SP
Figure 4-13. Data to Be Restored from Stack Memory
POP rp
RET instruction
RETI instruction
instruction
Register pair
lower
SP
SP
SP + 1
PC7 to PC0
SP
PC7 to PC0
PC15 to PC8
PSW
Register pair
higher
PC15 to PC8
SP + 1
SP + 1
SP + 2
SP SP + 2
SP SP + 2
SP SP + 3
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4.2.2 General-purpose registers
The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and in addition, two 8-bit registers in pairs can be used as a 16-bit
register (AX, BC, DE, and HL).
They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Figure 4-14. General-Purpose Register Configuration
(a) Absolute names
16-bit processing
RP3
8-bit processing
R7
R6
R5
R4
RP2
RP1
RP0
R3
R2
R1
R0
15
0
7
0
(b) Functional names
16-bit processing
HL
8-bit processing
H
L
D
E
DE
BC
AX
B
C
A
X
15
0
7
0
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4.2.3 Special-function registers (SFRs)
Unlike general-purpose registers, special-function registers have their own functions and are allocated to the 256-
byte area FF00H to FFFFH.
Special-function registers can be manipulated, like general-purpose registers, with operation, transfer, and bit
manipulation instructions. The bit units in which one register can be manipulated (1, 8, and 16) differ depending on
the special-function register type.
Each bit unit for manipulation can be specified as follows.
• 1-bit manipulation
A symbol reserved by the assembler is described as the operand (sfr.bit) of a 1-bit manipulation instruction. This
manipulation can also be specified with an address.
• 8-bit manipulation
A symbol reserved by the assembler is described as the operand (sfr) of an 8-bit manipulation instruction. This
manipulation can also be specified with an address.
• 16-bit manipulation
A symbol reserved by the assembler is described as the operand of a 16-bit manipulation instruction. When
specifying an address, describe an even address.
Table 4-3 lists the special-function registers. The meanings of the symbols in this table are as follows.
• Symbol
Indicates the addresses of the implemented special-function register. The symbols shown in this column are the
reserved words of the assembler, and have already been defined in the header file “sfrbit.h” in the C compiler.
Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used.
• R/W
Indicates whether the special-function register in question can be read or written.
R/W: Read/write
R:
Read only
Write only
W:
• Bit units for manipulation
Indicates the bit units (1, 8, and 16) in which the special-function register in question can be manipulated.
• After reset
Indicates the status of the special-function register when the RESET signal is input.
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Table 4-3. Special-Function Register List (1/2)
Address
Special-Function Register (SFR) Name
Symbol
R/W Bit Units for Manipulation After Reset
1 Bit
8 Bits 16 Bits
FF00H
FF01H
FF02H
FF05H
FF06H
FF10H
FF11H
FF14H
FF15H
FF16H
FF17H
FF18H
FF19H
FF1AH
FF1BH
FF20H
FF21H
FF22H
FF25H
FF32H
FF42H
FF48H
FF50H
FF51H
FF53H
Port 0
P0
P1
P2
P5
P6
R/W
√
√
√
√
√
−
√
√
√
√
−
−
−
−
00H
Port 1
Port 2
Port 5
Port 6
R
√
−
Note 1
Note 2
16-bit multiplication result storage register 0
√
√
√
√
√
√
Undefined
MUL0L MUL0
MUL0H
A/D conversion result registerNote 3
16-bit compare register 20
16-bit timer counter 20
ADCR0
−
−
−
−
√
Note 2
Note 2
Note 2
Note 2
Note 1
W
R
√
√
√
FFFFH
0000H
Undefined
FFH
CR20L
CR20H
TM20L
TM20H
CR20
TM20
Note 1
Note 1
16-bit capture register 20
TCP20L TCP20
TCP20H
PM0
Port mode register 0
R/W
√
√
√
√
√
−
√
−
−
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
Port mode register 1
PM1
Port mode register 2
PM2
Port mode register 5
PM5
Pull-up resistor option register B2
Time clock select register 2
16-bit timer mode control register 20
8-bit compare register 80
8-bit timer counter 80
PUB2
00H
TCL2
TMC20
CR80
W
R
TM80
Undefined
00H
8-bit timer mode control register 80
TMC80
R/W
Notes 1. Although these registers are usually accessed in 16-bit units, they can also be accessed in 8-bit units.
Access these registers in 8-bit units by means of direct addressing.
2. These registers can be accessed in 16-bit units only by means of short direct addressing.
3. When this register is used for an 8-bit A/D converter (µPD789104A and 789124A Subseries), it can be
accessed only in 8-bit units. At this time, the register address is FF15H. When this register is used for a
10-bit A/D converter (µPD789114A and 789134A Subseries), it can be accessed only in 16-bit units.
When using the µPD78F9116A and 78F9116B as the flash memory versions of the µPD789101A,
789102A, or 789104A, or when using the µPD78F9136A and 78F9136B as the flash memory versions
of the µPD789121A, 789122A, or 789124A, this register can be accessed in 8-bit units. However, only
the object file assembled with the µPD789101A, 789102A, or 789104A, or object file assembled with the
µPD789121A, 789122A, or 789124A can be used.
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Table 4-3. Special-Function Register List (2/2)
Address
Special-Function Register (SFR) Name
Symbol
R/W Bit Units for Manipulation After Reset
1 Bit
√
8 Bits 16 Bits
FF70H
FF71H
FF72H
FF73H
FF74H
Asynchronous serial interface mode register 20
Asynchronous serial interface status register 20
Serial operating mode register 20
Baud rate generator control register 20
Transmit shift register 20
ASIM20
R/W
R
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
00H
ASIS20
CSIM20
BRGC20
TXS20 SIO20
RXB20
ADM0
ADS0
√
R/W
√
−
W
R
−
FFH
Receive buffer register 20
−
Undefined
00H
FF80H
FF84H
A/D converter mode register 0
R/W
√
Analog input channel specification register 0
√
FFD0H Multiplication data register A0
FFD1H Multiplication data register B0
FFD2H Multiplier control register 0
MRA0
MRB0
MULC0
IF0
W
√
Undefined
00H
√
R/W
√
FFE0H
FFE1H
FFE4H
FFE5H
Interrupt request flag register 0
Interrupt request flag register 1
Interrupt mask flag register 0
Interrupt mask flag register 1
√
IF1
√
MK0
√
FFH
00H
MK1
√
FFECH External interrupt mode register 0
INTM0
PU0
−
FFF7H
FFF9H
FFFAH
Pull-up resistor option register 0
√
Watchdog timer mode register
WDTM
OSTS
PCC
√
Oscillation stabilization time select registerNote
−
04H
02H
FFFBH Processor clock control register
√
Note µPD789104A, 789114A Subseries only
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4.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of the instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination information is set
to the PC and branched by the following addressing (for details of each instruction, refer to the 78K/0S Series
Instructions User’s Manual (U11047E)).
4.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start
address of the following instruction is transferred to the program counter (PC) and branched. The displacement
value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit. In other words, the
range of branch in relative addressing is between −128 and +127 of the start address of the following instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
0
0
...
PC is the start address of
the next instruction of
a BR instruction.
PC
+
8
7
6
α
S
jdisp8
15
0
PC
When S = 0, α indicates all bits “0”.
When S = 1, α indicates all bits “1”.
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4.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.
The CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces.
[Illustration]
In case of CALL !addr16, BR !addr16 instruction
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
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4.3.3 Table indirect addressing
[Function]
The table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer
to the address stored in the memory table 40H to 7FH and branch to all the memory spaces.
[Illustration]
7
6
1
5
1
0
1
Instruction code
Effective address
1
ta4–0
15
8
0
7
0
6
1
5
1
0
0
0
0
0
0
0
0
0
7
Memory (Table)
Low Addr.
0
High Addr.
Effective address + 1
15
8
7
0
PC
4.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
8
7
7
0
0
rp
A
X
15
PC
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4.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
4.4.1 Direct addressing
[Function]
The memory indicated by immediate data in an instruction word is directly addressed.
[Operand format]
Identifier
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
OP code
00H
FEH
[Illustration]
7
0
OP code
addr16 (low)
addr16 (high)
Memory
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4.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal high-
speed RAM and special-function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the total SFR area. In this
area, ports which are frequently accessed in a program and a compare register of the timer/event counter are
mapped, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit
8 is set to 1. Refer to [Illustration].
[Operand format]
Identifier
saddr
Description
Label or FE20H to FF1FH immediate data
saddrp
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
OP code
90H (saddr-offset)
50H (immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
15
1
8
0
Effective
address
1
1
1
1
1
1
α
α
When 8-bit immediate data is 20H to FFH, = 0.
α
When 8-bit immediate data is 00H to 1FH, = 1.
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4.4.3 Special-function register (SFR) addressing
[Function]
Memory-mapped special-function registers (SFRs) are addressed with 8-bit immediate data in an instruction
word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier
sfr
Description
Special-function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code
1
0
1
0
1
1
0
0
0
0
1
0
1
0
1
0
[Illustration]
7
0
OP code
sfr-offset
SFR
15
1
8 7
0
Effective
address
1
1
1
1
1
1
1
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CHAPTER 4 CPU ARCHITECTURE
4.4.4 Register addressing
[Function]
General-purpose registers are accessed as operands. The general-purpose register to be accessed is specified
with the register specify code and functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an 8-
bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
AX, BC, DE, HL
rp
‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
Register specify code
INCW DE; When selecting the DE register pair for rp
Instruction code
1
0
0
0
1
0
0
0
Register specify code
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CHAPTER 4 CPU ARCHITECTURE
4.4.5 Register indirect addressing
[Function]
The memory is addressed with the contents of the register pair specified as an operand. The register pair to be
accessed is specified with the register pair specify code in the instruction code. This addressing can be carried
out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code
0
0
1
0
1
0
1
1
[Illustration]
15
8
7
0
0
DE
D
E
Memory address specified
by register pair DE
7
The contents of addressed
memory are transferred
7
0
A
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4.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
4.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN
instructions are executed or the register is saved/reset upon generation of an interrupt request.
Stack addressing can be used to address the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Instruction code
1
0
1
0
1
0
1
0
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CHAPTER 5 PORT FUNCTIONS
5.1 Functions of Ports
The µPD789104A/114A/124A/134A Subseries provides the ports shown in Figure 5-1, enabling various methods of
control.
Numerous other functions are provided that can be used in addition to the digital I/O port function. For more
information on these additional functions, refer to CHAPTER 3 PIN FUNCTIONS.
Figure 5-1. Port Types
P50
P53
P00
P03
Port 0
Port 1
Port 5
Port 6
P10
P11
P60
P63
P20
P25
Port 2
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CHAPTER 5 PORT FUNCTIONS
Table 5-1. Port Functions
Pin Name
I/O
I/O
Function
After Reset
Input
Alternate Function
P00 to P03
Port 0
−
4-bit I/O port
Input/output can be specified in 1-bit units.
When used as input port, use of an on-chip pull-up resistor
can be specified by means of pull-up resistor option register 0
(PU0).
P10, P11
I/O
I/O
Port 1
Input
Input
−
2-bit I/O port
Input/output can be specified in 1-bit units.
When used as input port, use of an on-chip pull-up resistor
can be specified by means of pull-up resistor option register 0
(PU0).
P20
Port 2
ASCK20/SCK20
TxD20/SO20
RxD20/SI20
INTP0/CPT20/SS20
INTP1/TO80/TO20
INTP2/TI80
6-bit I/O port
P21
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by means
of pull-up resistor option register B2 (PUB2).
P22
P23
P24
P25
P50 to P53
I/O
Port 5
Input
Input
−
4-bit N-ch open-drain I/O port
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified for mask
ROM versions by a mask option.
P60 to 63
Input
Port 6
ANI0 to ANI3
4-bit input-only port
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5.2 Port Configuration
A port consists of the following hardware.
Table 5-2. Configuration of Port
Item
Configuration
Control register
Port mode register (PM0 to PM2, PM5)
Pull-up resistor option register 0 (PU0)
Pull-up option register B2 (PUB2)
Port
Total: 20 (input: 4, I/O: 16)
Pull-up resistor
• Mask ROM versions
Total: 16 (software control: 12, mask option specification: 4)
• Flash memory versions
Total: 12 (software control only)
5.2.1 Port 0
This is a 4-bit I/O port with output latches. Port 0 can be set to input or output mode in 1-bit units by using port
mode register 0 (PM0). When pins P00 to P03 are used as input port pins, on-chip pull-up resistors can be connected
in 4-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 0 to input mode.
Figure 5-2 shows the block diagram of port 0.
Figure 5-2. Block Diagram of P00 to P03
V
DD
WRPU0
PU00
P-ch
RD
WRPORT
Output latch
(P00 to P03)
P00 to P03
WRPM
PM00 to PM03
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 0 read signal
WR: Port 0 write signal
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5.2.2 Port 1
This is a 2-bit I/O port with output latches. Port 1 can be set to input or output mode in 1-bit units by using port
mode register 1 (PM1). When pins P10 and P11 are used as input port pins, on-chip pull-up resistors can be
connected in 2-bit units by using pull-up resistor option register 0 (PU0).
RESET input sets port 1 to input mode.
Figure 5-3 shows the block diagram of port 1.
Figure 5-3. Block Diagram of P10 and P11
VDD
WRPU0
PU01
P-ch
RD
WRPORT
Output latch
(P10, P11)
P10, P11
WRPM
PM10, PM11
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 1 read signal
WR: Port 1 write signal
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5.2.3 Port 2
This is a 6-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port
mode register 2 (PM2). Use of on-chip pull-up resistors can be specified for pins P20 to P25 in 1-bit units by using
pull-up resistor option register B2 (PUB2).
The port is also used as the serial interface data I/O, clock I/O, timer I/O, and external interrupt input.
RESET input sets port 2 to input mode.
Figures 5-4 to 5-7 show block diagrams of port 2.
Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set
according to the function to be used. For how to set the latches, see Table 13-2 Serial Interface
20 Operating Mode Settings.
Figure 5-4. Block Diagram of P20
V
DD
WRPUB2
PUB20
P-ch
Alternate
function
RD
WRPORT
Output latch
(P20)
P20/ASCK20/
SCK20
WRPM
PM20
Alternate
function
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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Figure 5-5. Block Diagram of P21
VDD
WRPUB2
PUB21
P-ch
RD
WRPORT
Output latch
(P21)
P21/TxD20/
SO20
WRPM
PM21
Alternate
function
Serial output
enable signal
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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Figure 5-6. Block Diagram of P22, P23, and P25
VDD
WRPUB2
PUB22, PUB23,
P-ch
PUB25
Alternate
function
RD
WRPORT
Output latch
(P22, P23, P25)
P22/RxD20/SI20
P23/INTP0/CPT20/
SS20
WRPM
P25/INTP2/TI80
PM22, PM23,
PM25
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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Figure 5-7. Block Diagram of P24
V
DD
WRPUB2
PUB24
P-ch
Alternate
function
RD
P24/INTP1/
TO80/TO20
WRPORT
Output latch
(P24)
WRPM
PM24
Alternate
function
Alternate
function
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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5.2.4 Port 5
This is a 4-bit N-ch open-drain I/O port with output latches. Port 5 can be set to input or output mode in 1-bit units
by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be
specified by a mask option.
RESET input sets port 5 to input mode.
Figure 5-8 shows a block diagram of port 5.
Figure 5-8. Block Diagram of P50 to P53
VDD
RD
Mask option resistor
Mask ROM versions only.
For flash memory versions,
a pull-up resistor is not
incorporated.
P50 to P53
WRPORT
Output latch
(P50 to P53)
N-ch
WRPM
PM50 to PM53
PM: Port mode register
RD: Port 5 read signal
WR: Port 5 write signal
Caution When using port 5 of the µPD78F9116A and 78F9136A as an input port, be sure to observe the
restrictions listed below.
<1> When VDD = 1.8 to 5.5 V
Use within the range of TA = 25 to 85°C
<2> When TA = −40 to +85°C
Use within the range of VDD = 2.7 to 5.5 V
<3> When TA = −40 to +85°C and VDD = 1.8 to 5.5 V
Issue three consecutive read instructions when reading port 5.
If the above restrictions are not observed, the input value may be read incorrectly.
Note, however, that these restrictions do not apply when port 5 pins are used as output pins, or
when the product is other than µPD78F9116A or 78F9136A.
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5.2.5 Port 6
This is a 4-bit input port.
The port is also used for analog input to the A/D converter.
RESET input sets port 6 to input mode.
Figure 5-9 shows a block diagram of port 6.
Figure 5-9. Block Diagram of P60 to P63
RD
+
P60/ANI0 to P63/ANI3
A/D converter
−
V
REF
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CHAPTER 5 PORT FUNCTIONS
5.3 Port Function Control Registers
The following three types of registers control the ports.
• Port mode registers (PM0 to PM2, PM5)
• Pull-up resistor option register 0 (PU0)
• Pull-up resistor option register B2 (PUB2)
(1) Port mode registers (PM0 to PM2, PM5)
These registers are used to set port I/O in 1-bit units.
Port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch according to
Table 5-3.
Caution As port 2 has an alternate function as external interrupt input, when the port function output
mode is specified and the output level is changed, the interrupt request flag is set. When the
output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.
Table 5-3. Port Mode Register and Output Latch Settings When Using Alternate Functions
Pin Name
Alternate Function
Name
PM××
P××
I/O
P23
INTP0
CPT20
INTP1
TO80
TO20
INTP2
TI80
Input
Input
Input
Output
Output
Input
Input
1
1
1
0
0
1
1
×
×
×
0
0
×
×
P24
P25
Caution When Port 2 is used for serial interface pins, the I/O latch or output latch must be set according
to its function. For the setting method, refer to Table 13-2 Serial Interface 20 Operating Mode
Settings.
Remark ×:
don’t care
PM××: Port mode register
P××: Port output latch
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Figure 5-10. Port Mode Register Format
After reset
FFH
Symbol
PM0
7
1
6
1
5
1
4
1
3
2
1
0
Address
FF20H
R/W
R/W
PM03 PM02 PM01 PM00
PM1
PM2
PM5
1
1
1
1
1
1
1
1
1
1
PM11 PM10
FF21H
FF22H
FF25H
FFH
FFH
FFH
R/W
R/W
R/W
PM25 PM24 PM23 PM22 PM21 PM20
1
1
PM53 PM52 PM51 PM50
Pmn pin input/output mode selection (m = 0 to 2, 5, n = 0 to 7)
PMmn
0
1
Output mode (output buffer on)
Input mode (output buffer off)
(2) Pull-up resistor option register 0 (PU0)
Pull-up resistor option register 0 (PU0) sets whether to use on-chip pull-up resistors at each port or not.
At a port where use of on-chip pull-up resistors has been specified by PU0, the pull-up resistors can be
internally used only for the bits set in input mode. No on-chip pull-up resistors can be used for the bits set in
output mode, in spite of the setting of PU0. On-chip pull-up resistors can also not be used when the pins are
used as the alternate-function output pins.
PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PU0 to 00H.
Figure 5-11. Format of Pull-up Resistor Option Register 0
7
0
6
0
5
0
4
0
3
0
2
0
<1> <0>
Symbol
PU0
R/W
R/W
Address
FFF7H
After reset
00H
PU01 PU00
PU0m
Pm on-chip pull-up resistor selection (m = 0, 1)
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
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(3) Pull-up resistor option register B2 (PUB2)
This register specifies whether an on-chip pull-up resistor is connected to each pin of port 2. A pin so specified
by PUB2 is connected to an on-chip pull-up resistor regardless of the setting of the port mode register.
PUB2 is set with a 1-bit or 8-bit manipulation instruction.
RESET input sets this register to 00H.
Figure 5-12. Format of Pull-up Resistor Option Register B2
7
0
6
0
<5> <4> <3> <2> <1> <0>
PUB25 PUB24 PUB23 PUB22 PUB21 PUB20
Symbol
PUB2
R/W
R/W
Address
FF32H
After reset
00H
PUB2n
P2n on-chip pull-up resistor selection (n = 0 to 5)
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
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CHAPTER 5 PORT FUNCTIONS
5.4 Operation of Port Functions
The operation of a port differs depending on whether the port is set in input or output mode, as described below.
5.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is
not changed because the output buffer is off.
Once data is written to the output latch, it is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an I/O port, therefore, the contents of the output latch of the pin that is set
in the input mode and not subject to manipulation become undefined.
5.4.2 Reading from I/O port
(1) In output mode
The contents of the output latch can be read by using a transfer instruction. The contents of the output latch
are not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
Caution When using port 5 of µPD78F9116A and 78F9136A as an input port, be sure to observe the
restrictions listed below.
<1> When VDD = 1.8 to 5.5 V
Use within the range of TA = 25 to 85°C
<2> When TA = −40 to +85°C
Use within the range of VDD = 2.7 to 5.5 V
<3> When TA = −40 to +85°C and VDD = 1.8 to 5.5 V
Issue three consecutive read instructions when reading port 5.
If the above restrictions are not observed, the input value may be read incorrectly.
Note, however, that these restrictions do not apply when port 5 pins are used as output pins,
or when the product is other than µPD78F9116A or 78F9136A.
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5.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed on the contents of the output latch. The result of the operation is
written to the output latch. The contents of the output latch are output from the port pins.
Once data is written to the output latch, it is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because the
output buffer is off.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However,
this instruction accesses the port in 8-bit units. When this instruction is executed to
manipulate a bit of an I/O port, therefore, the contents of the output latch of the pin that is set
in the input mode and not subject to manipulation become undefined.
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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)
6.1 Function of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. Oscillation is stopped
by executing the STOP instruction.
The system clock oscillator is as follows.
• System clock (crystal/ceramic) oscillator
<Expanded-specification products>
This circuit oscillates a clock at a frequency of 1.0 to 10.0 MHz.
<Conventional-specification products>
This circuit oscillates a clock at a frequency of 1.0 to 5.0 MHz.
6.2 Configuration of Clock Generator
The clock generator consists of the following hardware.
Table 6-1. Configuration of Clock Generator
Item
Control register
Oscillator
Configuration
Processor clock control register (PCC)
Crystal/ceramic oscillator
Figure 6-1. Block Diagram of Clock Generator
Prescaler
Clock to peripheral
hardware
X1
X2
System clock
oscillator
Prescaler
f
X
f
X
22
Standby
controller
STOP
Wait
controller
CPU clock (fCPU
)
PCC1
Processor clock control register (PCC)
Internal bus
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6.3 Register Controlling Clock Generator
The clock generator is controlled by the following register.
• Processor clock control register (PCC)
(1) Processor clock control register (PCC)
PCC sets the CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 6-2. Format of Processor Clock Control Register
7
0
6
0
5
4
3
2
1
0
R/W
R/W
Symbol
PCC
Address
FFFBH
After reset
02H
0
0
0
0
PCC1
0
PCC1
CPU clock (fCPU) selection
Minimum instruction execution time: 2/fCPU
= 10.0 MHzNote operation
@ f = 5.0 MHz operation
@ f
X
X
0.4
1.6
s
s
0
1
µ
µ
f
X
X
0.2
s
µ
µ
f
/22
0.8
s
Note Expanded-specification products only
Caution Bit 0 and bits 2 to 7 must be set to 0.
Remark fX: System clock oscillation frequency
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6.4 System Clock Oscillator
6.4.1 System clock oscillator
The system clock oscillator is oscillated by the crystal or ceramic resonator connected across the X1 and X2 pins.
An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the X1 pin,
and leave the X2 pin open.
Figure 6-3 shows the external circuit of the system clock oscillator.
Figure 6-3. External Circuit of System Clock Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
V
X1
SS
External
clock
X1
X2
X2
Crystal
or
ceramic resonator
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Figure 6-4 shows examples of incorrect resonator connection.
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Figure 6-4. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORTn
(n = 0 to 2, 5, 6)
VSS
X1
X2
VSS
X1
X2
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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)
Figure 6-4. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
VDD
Pmn
V
SS
X1
X2
V
SS
X1
X2
High current
A
B
C
High current
(e) Signal is fetched
VSS
X1
X2
6.4.2 Divider
The divider divides the output of the system clock oscillator (fX) to generate various clocks.
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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)
6.5 Operation of Clock Generator
The clock generator generates the following clocks and controls the operating modes of the CPU, such as the
standby mode.
• System clock fX
• CPU clock
fCPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC), as follows.
(a) The slow mode (0.8 µs: at 10.0 MHz operation, 1.6 µs: at 5.0 MHz operation) of the system clock is
selected when the RESET signal is generated (PCC = 02H). While a low level is being input to the RESET
pin, oscillation of the system clock is stopped.
(b) Two types of minimum instruction execution time (0.2 µs and 0.8 µs: at 10.0 MHz operation, 0.4 µs and 1.6
µs: at 5.0 MHz operation) can be selected by setting the PCC register.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral
hardware is stopped when the system clock is stopped (except the external clock input operation).
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CHAPTER 6 CLOCK GENERATOR (µPD789104A, 789114A SUBSERIES)
6.6 Changing Setting of CPU Clock
6.6.1 Time required for switching CPU clock
The CPU clock can be switched by using bit 1 (PCC1) of the processor clock control register (PCC).
Actually, the specified clock is not switched immediately after the setting of PCC has been changed; the old clock is
used for the duration of several instructions after that (refer to Table 6-2).
Table 6-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching
PCC1
Set Value After Switching
PCC1
0
PCC1
1
0
1
4 clocks
2 clocks
Remark Two clocks are the minimum instruction execution
time of the CPU clock before switching.
6.6.2 Switching CPU clock
The following figure illustrates how the CPU clock is switched.
Figure 6-5. Switching CPU Clock
VDD
RESET
CPU clock
Slow
Fastest
operation
operation
Wait (3.28 ms: at 10.0 MHz operation,
6.55 ms: at 5.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during
which oscillation stabilizes (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the low speed of the system clock (8.0 µs: at 10.0 MHz
operation, 1.6 µs: at 5.0 MHz operation).
<2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest
speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can be
selected.
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)
7.1 Function of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The system clock
oscillator is as follows.
• System clock (RC) oscillator
This circuit oscillates a clock at a frequency of 2.0 to 4.0 MHz. Oscillation can be stopped by executing the
STOP instruction.
7.2 Configuration of Clock Generator
The clock generator consists of the following hardware.
Table 7-1. Configuration of Clock Generator
Item
Control register
Oscillator
Configuration
Processor clock control register (PCC)
RC oscillator
Figure 7-1. Block Diagram of Clock Generator
Prescaler
Clock to peripheral
hardware
CL1
CL2
System clock
oscillator
Prescaler
f
CC
f
CC
22
Wait
controller
Standby
controller
STOP
CPU clock (fCPU
)
PCC1
Processor clock control register (PCC)
Internal bus
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)
7.3 Register Controlling Clock Generator
The clock generator is controlled by the following register.
• Processor clock control register (PCC)
(1) Processor clock control register (PCC)
PCC sets the CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 02H.
Figure 7-2. Format of Processor Clock Control Register
7
0
6
0
5
4
3
2
1
0
R/W
R/W
Symbol
PCC
Address
FFFBH
After reset
02H
0
0
0
0
PCC1
0
PCC1
CPU clock (fCPU) selection
Minimum instruction execution time: 2/fCPU
@ fCC = 4.0 MHz operation
0.5
2.0
s
s
0
1
µ
µ
f
CC
f
CC/22
Caution Bit 0 and bits 2 to 7 must be set to 0.
Remark fCC: System clock oscillation frequency
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)
7.4 System Clock Oscillator
7.4.1 System clock oscillator
The system clock oscillator is oscillated by the resistor (R) and capacitor (C) (4.0 MHz TYP.) connected across the
CL1 and CL2 pins.
An external clock can also be input to the system clock oscillator. In this case, input the clock signal to the CL1 pin,
and leave the CL2 pin open.
Figure 7-3 shows the external circuit of the system clock oscillator.
Figure 7-3. External Circuit of System Clock Oscillator
(a) RC oscillation
(b) External clock
External
clock
CL1
CL1
C
R
CL2
CL2
V
SS
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)
7.4.2 Examples of incorrect resonator connection
Figure 7-4 shows examples of incorrect resonator connection.
Figure 7-4. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORTn
(n = 0 to 2, 5, 6)
CL1
CL2
V
SS
CL1
CL2
V
SS
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)
Figure 7-4. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator
(potential at points A and B fluctuates)
VDD
PORTn
(n = 0 to 2, 5, 6)
CL1
CL2
V
SS
CL1
CL2
VSS
A
B
High current
(e) Signal is fetched
CL1
CL2
V
SS
7.4.3 Divider
The divider divides the output of the system clock oscillator (fCC) to generate various clocks.
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)
7.5 Operation of Clock Generator
The clock generator generates the following clocks and controls the operating modes of the CPU, such as the
standby mode.
• System clock fCC
• CPU clock
fCPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC), as follows.
(a) The slow mode (2.0 µs: at 4.0 MHz operation) of the system clock is selected when the RESET signal is
generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the system clock
is stopped.
(b) Two types of minimum instruction execution time (0.5 µs and 2.0 µs: at 4.0 MHz operation) can be selected
by setting the PCC register.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral
hardware is stopped when the system clock is stopped (except the external clock input operation).
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)
7.6 Changing Setting of CPU Clock
7.6.1 Time required for switching CPU clock
The CPU clock can be switched by using bit 1 (PCC1) of the processor clock control register (PCC).
Actually, the specified clock is not switched immediately after the setting of PCC has been changed; the old clock is
used for the duration of several instructions after that (refer to Table 7-2).
Table 7-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching
PCC1
Set Value After Switching
PCC1
0
PCC1
1
0
1
4 clocks
2 clocks
Remark Two clocks are the minimum instruction execution
time of the CPU clock before switching.
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CHAPTER 7 CLOCK GENERATOR (µPD789124A, 789134A SUBSERIES)
7.6.2 Switching CPU clock
The following figure illustrates how the CPU clock is switched.
Figure 7-5. Switching CPU Clock
VDD
RESET
CPU clock
Slow
Fastest
operation
operation
Wait (32
µ
s: at 4.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the system clock starts oscillating. At this time, the time during
which oscillation stabilizes (27/fCC) is automatically secured.
After that, the CPU starts instruction execution at the low speed of the system clock (2.0 µs: at 4.0 MHz
operation).
<2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest
speed has elapsed, the processor clock control register (PCC) is rewritten so that the highest speed can be
selected.
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CHAPTER 8 16-BIT TIMER 20
The 16-bit timer counter references the free-running counter and provides functions such as timer interrupt and
timer output. In addition, the count value can be captured by a capture trigger pin.
8.1 16-Bit Timer 20 Functions
16-bit timer 20 has the following functions.
• Timer interrupt
• Timer output
• Count value capture
(1) Timer interrupt
An interrupt is generated when the count value and compare value match.
(2) Timer output
Timer output control is possible when the count value and compare value match.
(3) Count value capture
The TM20 count value is latched in synchronization with the capture trigger and held.
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CHAPTER 8 16-BIT TIMER 20
8.2 16-Bit Timer 20 Configuration
16-bit timer 20 consists of the following hardware.
Table 8-1. Configuration of 16-Bit Timer 20
Item
Timer counter
Registers
Configuration
16 bits × 1 (TM20)
Compare register: 16 bits × 1 (CR20)
Capture register: 16 bits × 1 (TCP20)
Timer output
1 (TO20)
Control registers
16-bit timer mode control register 20 (TMC20)
Port mode register 2 (PM2)
Port 2 (P2)
Figure 8-1. Block Diagram of 16-Bit Timer 20
Internal bus
16-bit timer mode
control register 20
(TMC20)
P24
output latch
PM24
TOF20 CPT201CPT200TOC20 TCL201TCL200 TOE20
TO20/P24/
INTP1/TO80
F/F
TOD20
16-bit compare register 20 (CR20)
16-bit timer mode
control register 20
Match
INTTM20
f
f
CLK/22
CLK/26
OVF
16-bit timer counter 20 (TM20)
16-bit capture
register 20 (TCP20)
CPT20/P23/
INTP0/SS20
Edge
detector
16-bit counter
read buffer
Internal bus
Remark fCLK: fX or fCC
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CHAPTER 8 16-BIT TIMER 20
(1) 16-bit compare register 20 (CR20)
This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and when
they match, generates an interrupt request (INTTM20).
CR20 is set with a 16-bit memory manipulation instruction. The values 0000H to FFFFH can be set.
RESET input sets this register to FFFFH.
Cautions 1. Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-
bit memory manipulation instruction can also be used. When manipulating with an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
2. When rewriting CR20 during a count operation, set CR20 to the interrupt-disabled state
using interrupt mask flag register 0 (MK10) beforehand. Also, set the timer output data to
inversion disabled using 16-bit timer mode control register 20 (TMC20).
When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at
the moment of rewrite.
(2) 16-bit timer counter 20 (TM20)
This is a 16-bit register that counts count pulses.
TM20 is read with a 16-bit memory manipulation instruction.
This register is free running during count clock input.
RESET input clears this register to 0000H and after which it resumes free running.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during the oscillation stabilization time.
2. Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-
bit memory manipulation instruction can also be used. When manipulating with an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
3. When manipulating with an 8-bit memory manipulation instruction, readout should be
performed in the order of lower byte to higher byte and must be performed in pairs.
(3) 16-bit capture register 20 (TCP20)
This is a 16-bit register that captures the contents of 16-bit timer counter 20 (TM20).
TCP20 is set with a 16-bit memory manipulation instruction.
RESET input makes this register undefined.
Caution Although this register is manipulated with a 16-bit memory manipulation instruction, an 8-bit
memory manipulation instruction can also be used. When manipulating with an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
(4) 16-bit counter read buffer
This buffer latches the counter value and holds the count value of 16-bit timer counter 20 (TM20).
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CHAPTER 8 16-BIT TIMER 20
8.3 Registers Controlling 16-Bit Timer 20
The following three registers control 16-bit timer 20.
• 16-bit timer mode control register 20 (TMC20)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1) 16-bit timer mode control register 20 (TMC20)
16-bit timer mode control register 20 (TMC20) controls the setting of the counter clock, capture edge, etc.
TMC20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC20 to 00H.
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CHAPTER 8 16-BIT TIMER 20
Figure 8-2. Format of 16-Bit Timer Mode Control Register 20
7
<6>
5
4
3
2
1
<0>
Symbol
Address
FF48H
After reset
00H
R/W
TMC20 TOD20 TOF20 CPT201CPT200 TOC20 TCL201 TCL200 TOE20
R/WNote 1
TOD20
0
Timer output data
Timer output of 0
Timer output of 1
1
1
TOF20
Overflow flag set
0
1
Clear by reset and software
Set by overflow of 16-bit timer
CPT201 CPT200
Capture edge selection
0
0
1
1
0
1
0
1
Capture operation disabled
Rising edge of CPT20
Falling edge of CPT20
Both edges of CPT20
TOC20
Timer output data inversion control
0
1
Inversion disabled
Inversion enabled
TCL201 TCL200
16-bit timer counter 20 count clock selection
@ fX
= 10.0 MHzNote 2 operation @ f
= 5.0 MHz operation
@ fCC = 4.0 MHz operation
X
/22 or fCC/22
/26 or fCC/26
2.5 MHz
1.25 MHz
78.1 kHz
1.0 MHz
62.5 kHz
0
0
0
1
f
X
156.2 kHz
f
X
Other than above Setting prohibited
TOE20
16-bit timer 20 output control
0
1
Output disabled (port mode)
Output enabled
Notes 1. Bit 7 is read-only.
2. Expanded-specification products only.
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 8 16-BIT TIMER 20
(2) Port mode register 2 (PM2)
This register sets the input/output of port 2 in 1-bit units.
To use the P24/TO20/INTP1/TO80 pin for timer output, set the output latch of PM24 and P24 to 0.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 8-3. Format of Port Mode Register 2
7
1
6
1
5
4
3
2
1
0
Symbol
PM2
Address
FF22H
After reset
FFH
R/W
R/W
PM25 PM24 PM23 PM22 PM21 PM20
PM24
P24 pin I/O mode selection
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 8 16-BIT TIMER 20
8.4 16-Bit Timer 20 Operation
8.4.1 Operation as timer interrupt
An interrupt is generated repeatedly each time the free-running counter value reaches the value set to CR20. After
interrupt occurs, the counter is not cleared and continues counting. Therefore, the interval time is equivalent to one
count clock cycle set by TCL201 and TCL200.
To operate the 16-bit timer 20 as a timer interrupt, the following settings are required.
• Set count values to CR20.
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 8-4.
Figure 8-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
−
TMC20
0/1
0/1
0/1
0/1
0
0/1
0/1
Setting of count clock (see Table 8-2)
Caution If both the CPT201 and CPT200 flags are set to 0, the capture edge becomes setting prohibited.
When the count value of 16-bit timer counter 20 (TM20) coincides with the value set to CR20, counting of TM20
continues and an interrupt request signal (INTTM20) is generated.
Table 8-2 shows the interval time, and Figure 8-5 shows the timing of the timer interrupt operation.
Caution When rewriting CR20 during count operation, be sure to follow the procedure below.
<1> Set CR20 to interrupt disable (by setting bit 7 of interrupt mask flag register 0 (MK0) to 1).
<2> Set inversion control of timer output data to disable (TOC20 = 0)
When CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the
moment of rewrite.
Table 8-2. Interval Time of 16-Bit Timer 20
TCL201 TCL200
Count Clock
Interval Time
@ fX = 10.0
MHzNote
@ fX = 5.0
MHz
@ fCC = 4.0
MHz
@ fX = 10.0
MHzNote
@ fX = 5.0
MHz
@ fCC = 4.0
MHz
Operation
Operation
Operation
Operation
Operation
Operation
0
0
0
1
22/fX or
22/fCC
0.4 µs
0.8 µs
1.0 µs
218/fX or
218/fCC
26.2 ms
52.4 ms
65.5 ms
26/fX or
26/fCC
6.4 µs
12.8 µs
16 µs
222/fX or
222/fCC
419.4 ms
838.9 ms
1048 ms
Other than above Setting prohibited
Note Expanded-specification products only.
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 8 16-BIT TIMER 20
Figure 8-5. Timing of Timer Interrupt Operation
t
Count clock
TM20 count value
CR20
0000H
0001H
N
0000H 0001H
N
N
FFFFH
N
N
N
N
INTTM20
Interrupt acknowledged
Interrupt
acknowledged
TO20
TOF20
Overflow flag set
Remark N = 0000H to FFFFH
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CHAPTER 8 16-BIT TIMER 20
8.4.2 Operation as timer output
The timer output is inverted repeatedly each time the free-running counter value reaches the value set to CR20.
After the timer output is inverted, the counter is not cleared and continues counting. Therefore, the interval time is
equivalent to one count clock cycle set by TCL201 and TCL200.
To operate the 16-bit timer 20 as a timer output, the following settings are required.
• Set P24 to output mode (PM24 = 0).
• Set the P24 output latch to 0.
• Set the count value to CR20.
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 8-6.
Figure 8-6. Settings of 16-Bit Timer Mode Control Register 20 for Timer Output Operation
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TMC20
–
0/1
0/1
0/1
1
0
0/1
1
TO20 output enable
Setting of count clock (see Table 8-2)
Inversion enable for timer output data
Caution If both the CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation
prohibited.
When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of the
TO20/P24/INTP1/TO80 pin is inverted. This enables timer output. At that time, TM20 continues counting and an
interrupt request signal (INTTM20) is generated.
Figure 8-7 shows the timing of timer output (refer to Table 8-2 for the interval time of 16-bit timer 20).
Figure 8-7. Timer Output Timing
t
Count clock
0000H
0001H
N
0000H 0001H
N
N
FFFFH
TM20 count value
CR20
N
N
N
N
INTTM20
Interrupt acknowledged
Interrupt
acknowledged
TO20Note
TOF20
Overflow flag set
Note The TO20 initial value becomes low level while output is enabled (TOE20 = 1).
Remark N = 0000H to FFFFH
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CHAPTER 8 16-BIT TIMER 20
8.4.3 Capture operation
The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20) in
synchronization with a capture trigger.
Set as shown in Figure 8-8 to allow 16-bit timer 20 to start the capture operation.
Figure 8-8. Settings of 16-Bit Timer Mode Control Register 20 for Capture Operation
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TMC20
−
0/1
0/1
0/1
0/1
0
0/1
0/1
Count clock selection
Capture edge selection (see Table 8-3)
16-bit capture register 20 (TCP20) starts the capture operation after the CPT20 capture trigger edge has been
detected, and latches and holds the count value of 16-bit timer counter 20. TCP20 fetches the count value within 2
clocks and holds the count value until the next capture edge detection.
Table 8-3 and Figure 8-9 show the setting contents of the capture edge and the capture operation timing,
respectively.
Table 8-3. Settings of Capture Edge
CPT201
CPT200
Capture Edge Selection
0
0
1
1
0
1
0
1
Capture operation prohibited
CPT20 pin rising edge
CPT20 pin falling edge
CPT20 pin both edges
Caution Because TCP20 is rewritten when a capture trigger edge is detected during TCP20 read, disable
capture trigger detection during TCP20 read.
Figure 8-9. Capture Operation Timing (Both Edges of CPT20 Pin Are Specified)
Count clock
TM20
Count read buffer
TCP20
0000H 0001H
0000H 0001H
N
N
M – 1
M
M
Undefined
N
M
Capture start
Capture start
CPT20
Capture edge detection
Capture edge detection
Remark N, M = 0000H to FFFFH
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CHAPTER 8 16-BIT TIMER 20
8.4.4 16-bit timer counter 20 readout
The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction.
TM20 readout is performed via a counter read buffer. The counter read buffer latches the TM20 count value. The
buffer operation is then held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises
and the count value is held. The counter read buffer value in the hold state can be read out as the count value.
Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM20
higher byte falls.
RESET input clears TM20 to 0000H and restarts free running.
Figure 8-10 shows the timing of 16-bit timer counter 20 readout.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during oscillation stabilization time.
2. Although TM20 is a dedicated 16-bit transfer instruction register, an 8-bit transfer instruction
can also be used.
Execute an 8-bit transfer instruction by direct addressing.
3. When using an 8-bit transfer instruction, execute in the order of lower byte to higher byte in
pairs. If the only lower byte is read, the pending state of the counter read buffer is not
canceled, and if the only higher byte is read, an undefined count value is read.
Figure 8-10. 16-Bit Timer Counter 20 Readout Timing
CPU clock
Count clock
TM20
Count read buffer
TM20 read signal
0000H
0000H
0001H
0001H
N
N + 1
N
Read signal latch
prohibited period
Remark N = 0000H to FFFFH
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CHAPTER 8 16-BIT TIMER 20
8.5 Notes on Using 16-Bit Timer 20
8.5.1 Restrictions on rewriting 16-bit compare register 20
(1) When rewriting the compare register (CR20), be sure to disable interrupts (TMMK20 = 1), and disable
inversion control of timer output (TOC20 = 0) first.
If CR20 is rewritten with interrupts enabled, an interrupt request may be generated at the point of rewrite.
(2) The interval time may be double the intended time depending on the timing at which the compare register
(CR20) is rewritten. Likewise, the timer output waveform may be shorter or double the intended output.
To avoid this, rewrite using one of the following procedures.
<Prevention method A> Rewriting by 8-bit access
<1> Disable interrupts (TMMK20 = 1), and disable inversion control of timer output (TOC20 = 0).
<2> Rewrite the higher byte of CR20 (16 bits) first.
<3> Next, rewrite the lower byte of CR20 (16 bits).
<4> Clear the interrupt request flag (TMIF20).
<5> After more than half the cycle of the count clock has passed from the start of the interrupt, enable timer
interrupts and timer output inversion.
<Program example A> (When count clock = 64/fX, CPU clock = fX)
TM20_VCT: SET1
TMMK20
TMC20.3
A,#xxH
;Timer interrupt disable (6 clocks)
CLR1
MOV
;Timer output inversion disable (6 clocks)
;Higher byte rewrite value setting (6 clocks)
MOV
!0FF17H,A ;CR20 higher byte rewriting (8 clocks)
A,#yyH ;Lower byte rewrite value setting (6 clocks)
!0FF16H,A ;CR20 lower byte rewriting (8 clocks)
More than 32 clocks
in totalNote
MOV
MOV
CLR1
CLR1
SET1
TMIF20
TMMK20
TMC20.3
;Interrupt request flag clearing (6 clocks)
;Timer interrupt enable (6 clocks)
;Timer output inversion enable
Note This is because the INTTM20 signal is set to the high level for a period of half the cycle of the count
clock after an interrupt is generated, so the output will be inverted if TOC20 is set to 1 during this
period.
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CHAPTER 8 16-BIT TIMER 20
<Prevention method B> Rewriting by 16-bit access
<1> Disable interrupts (TMMK20 = 1), and disable inversion control of timer output (TOC20 = 0).
<2> Rewrite CR20 (16 bits).
<3> Wait for more than one cycle of the count clock.
<4> Clear the interrupt request flag (TMIF20).
<5> Enable timer interrupts and timer output inversion
<Program example B> (When count clock = 64/fX, CPU clock = fX)
TM20_VCT: SET1
TMMK20
;Timer interrupt disable
CLR1
MOVW
MOVW
NOP
TMC20.3
;Timer output inversion disable
AX,#xxyyH ;CR20 rewrite value setting
CR20,AX
;CR20 rewriting
NOP
;32 NOP (Wait for 64/fX)Note
:
NOP
NOP
CLR1
CLR1
SET1
TMIF20
TMMK20
TMC20.3
;Interrupt request flag clearing
;Timer interrupt enable
;Timer output inversion enable
Note Wait for more than one cycle of the count clock after the instruction rewriting CR20 (MOVW CR20, AX)
before clearing the interrupt request flag (TMIF20).
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
The 8-bit timer/event counter can be used as an interval timer, external event counter, and for square-wave output
and PWM output of arbitrary frequency.
9.1 Functions of 8-Bit Timer/Event Counter 80
8-bit timer/event counter 80 has the following functions.
• Interval timer
• External event counter
• Square-wave output
• PWM output
(1) 8-bit interval timer
When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time
interval set in advance.
Table 9-1. Interval Time of 8-Bit Timer/Event Counter 80
Minimum Interval Time
1/fX (100 ns)
Maximum Interval Time
28/fX (25.6 µs)
Resolution
1/fX (100 ns)
At fX = 10.0 MHzNote
At fX = 5.0 MHz
23/fX (0.8 µs)
211/fX (204.8 µs)
28/fX (51.2 µs)
23/fX (0.8 µs)
1/fX (200 ns)
23/fX (1.6 µs)
1/fCC (250 ns)
23/fCC (2.0 µs)
1/fX (200 ns)
23/fX (1.6 µs)
211/fX (409.6 µs)
28/fCC (64 µs)
At fCC = 4.0 MHz
1/fCC (250 ns)
23/fCC (2.0 µs)
211/fCC (512 µs)
Note Expanded-specification products only
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
(2) External event counter
The number of pulses of an externally input signal can be measured.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
(3) Square-wave output
A square wave of arbitrary frequency can be output.
Table 9-2. Square-Wave Output Range of 8-Bit Timer/Event Counter 80
Minimum Pulse Width
1/fX (100 ns)
Maximum Pulse Width
28/fX (25.6 µs)
Resolution
1/fX (100 ns)
At fX = 10.0 MHzNote
At fX = 5.0 MHz
23/fX (0.8 µs)
211/fX (204.8 µs)
28/fX (51.2 µs)
23/fX (0.8 µs)
1/fX (200 ns)
23/fX (1.6 µs)
1/fCC (250 ns)
23/fCC (2.0 µs)
1/fX (200 ns)
23/fX (1.6 µs)
211/fX (409.6 µs)
28/fCC (64 µs)
At fCC = 4.0 MHz
1/fCC (250 ns)
23/fCC (2.0 µs)
211/fCC (512 µs)
Note Expanded-specification products only
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
(4) PWM output
8-bit resolution PWM output can be produced.
9.2 8-Bit Timer/Event Counter 80 Configuration
8-bit timer/event counter 80 consists of the following hardware.
Table 9-3. 8-Bit Timer/Event Counter 80 Configuration
Item
Timer counter
Register
Configuration
8 bits × 1 (TM80)
Compare register: 8 bits × 1 (CR80)
Timer output
Control registers
1 (TO80)
8-bit timer mode control register 80 (TMC80)
Port mode register 2 (PM2)
Port 2 (P2)
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 80
Internal bus
8-bit compare register 80
(CR80)
Match
INTTM80
TO20
output Note
f
CLK
Clear
8-bit timer counter 80
f
CLK/23
(TM80)
R
INV
Q
Q
TI80/P25/
INTP2
S
OVF
TO80/P24/
INTP1/TO20
P24 output
latch
PM24
TCE80 PWME80 TCL801 TCL800 TOE80
8-bit timer mode control
register 80 (TMC80)
Internal bus
Note Refer to block diagram of 16-bit timer 20
Remark fCLK: fX or fCC
(1) 8-bit compare register 80 (CR80)
This is an 8-bit register that compares the value set to CR80 with the 8-bit timer counter 80 (TM80) count
value, and if they match, generates an interrupt request (INTTM80).
CR80 is set with an 8-bit memory manipulation instruction. The values 00H to FFH can be set.
RESET input makes CR80 undefined.
Cautions 1. When rewriting CR80 in timer counter operation mode (i.e., PWME80 (bit 6 of 8-bit timer
mode control register 80 (TMC80)) is set to 0), be sure to stop the timer operation before
hand. If CR80 is rewritten in the timer operation-enabled state, a match interrupt request
signal may occur at the moment of rewrite.
2. Do not set CR80 to 00H in the PWM output mode (when PWME80 = 1); otherwise, PWM
may not be output normally.
(2) 8-bit timer counter 80 (TM80)
This is an 8-bit register used to count count pulses.
TM80 is read with an 8-bit memory manipulation instruction.
RESET input clears TM80 to 00H.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
9.3 Registers Controlling 8-Bit Timer/Event Counter 80
The following three registers are used to control 8-bit timer/event counter 80.
• 8-bit timer mode control register 80 (TMC80)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1) 8-bit timer mode control register 80 (TMC80)
This register enables/stops operation of 8-bit timer counter 80 (TM80), sets the counter clock of TM80, and
controls the operation of the output controller of 8-bit timer/event counter 80.
TMC80 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC80 to 00H.
Figure 9-2. Format of 8-Bit Timer Mode Control Register 80
<7> <6>
5
0
4
0
3
0
2
1
<0>
Symbol
Address
FF53H
After reset
00H
R/W
R/W
TMC80 TCE80 PWME80
TCL801TCL800 TOE80
TCE80
8-bit timer counter 80 operation control
0
1
Operation stop (TM80 cleared to 0)
Operation enable
PWME80
Operation mode selection
0
1
Timer counter operating mode
PWM output operating mode
TCL801 TCL800
8-bit timer counter 80 count clock selection
@ f
X
= 10.0 MHzNote operation @ f
= 5.0 MHz operation
@ fCC = 4.0 MHz operation
X
0
0
1
1
0
1
0
1
10.0 MHz
1.25 MHz
5.0 MHz
625 kHz
4.0 MHz
500 kHz
f
f
X
X
or fCC
/23 or fCC/23
Rising edge of TI80
Falling edge of TI80
TOE80
8-bit timer/event counter 80 output control
0
1
Output disable (port mode)
Output enable
Note Expanded-specification products only
Caution Be sure to set TMC80 after stopping timer operation.
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
(2) Port mode register 2 (PM2)
This register sets port 2 to input/output in 1-bit units.
When using the P24/TO80/INTP1/TO20 pin for timer output, set the output latch of PM24 and P24 to 0. When
using it for timer input, set PM24 to 1.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 9-3. Format of Port Mode Register 2
7
1
6
1
5
4
3
2
1
0
Symbol
PM2
Address
FF22H
After reset
FFH
R/W
R/W
PM25 PM24 PM23 PM22 PM21 PM20
PM2n
P2n pin I/O mode selection (n = 0 to 5)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
9.4 Operation of 8-Bit Timer/Event Counter 80
9.4.1 Operation as interval timer
The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit
compare register 80 (CR80) in advance.
To operate the 8-bit timer/event counter as an interval timer, the following settings are required.
<1> Set 8-bit timer counter 80 (TM80) to operation disabled (by setting TCE80 (bit 7 of 8-bit timer mode control
register 80 (TMC80)) to 0).
<2> Set the count clock of 8-bit timer/event counter 80 (refer to Figure 9-2)
<3> Set the count value to CR80
<4> Set TM80 to operation enable (TCE80 = 1)
When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, the value of TM80 is
cleared to 0 and TM80 continues counting. At the same time, an interrupt request signal (INTTM80) is generated.
Tables 9-4 and 9-5 show the interval time, and Figure 9-4 shows the timing of interval timer operation.
Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer
operation-enabled state, a match interrupt request signal may occur at the moment of rewrite.
2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts.
Therefore, always follow the above procedure when operating the 8-bit timer/event counter as
an interval timer.
Table 9-4. Interval Time of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation)
TCL801
TCL800
Minimum Interval Time
1/fX (100 ns) [200 ns]
23/fX (0.8 µs) [1.6 µs]
TI80 input cycle
Maximum Interval Time
28/fX (25.6 µs) [51.2 µs]
211/fX (204.8 µs) [409.6 µs]
28 × TI80 input cycle
Resolution
0
0
1
1
0
1
0
1
1/fX (100 ns) [200 ns]
23/fX (0.8 µs) [1.6 µs]
TI80 input edge cycle
TI80 input edge cycle
TI80 input cycle
28 × TI80 input cycle
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. The values in parentheses ( ) are for operation at fX = 10.0 MHz (expanded-specification products
only).
3. The values in square brackets [ ] are for operation at fX = 5.0 MHz.
Table 9-5. Interval Time of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation)
TCL801
TCL800
Minimum Interval Time
1/fCC (250 ns)
Maximum Interval Time
28/fCC (64 µs)
Resolution
1/fCC (250 ns)
0
0
1
1
0
1
0
1
23/fCC (2.0 µs)
211/fCC (512 µs)
23/fCC (2.0 µs)
TI80 input cycle
TI80 input cycle
28 × TI80 input cycle
28 × TI80 input cycle
TI80 input edge cycle
TI80 input edge cycle
Remark fCC: System clock oscillation frequency (RC oscillation)
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Figure 9-4. Interval Timer Operation Timing
t
Count clock
TM80 count value
00H
01H
N
00H 01H
Clear
N
00H 01H
Clear
N
CR80
N
N
N
N
TCE80
Count start
INTTM80
Interrupt acknowledged
Interval time
Interrupt acknowledged
Interval time
TO80
Interval time
Remark Interval time = (N + 1) × t : N = 00H to FFH
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
9.4.2 Operation as external event counter
The external event counter counts the number of external clock pulses input to the TI80/P25/INTP2 pin by using 8-
bit timer counter 80 (TM80).
To operate 8-bit timer/event counter 80 as an external event counter, the following settings are required.
<1> Set P25 to input mode (PM25 = 1).
<2> Set 8-bit timer counter 80 (TM80) to operation disabled (by setting TCE80 (bit 7 of 8-bit timer mode control
register 80 (TMC80)) to 0).
<3> Specify the rising/falling edges of TI80 (refer to Figure 9-2), and set TO80 to output disabled (i.e., set TOE80
(bit 0 of TMC80) to 0) and PWM output to disabled (i.e., set PWME80 (bit 6 of TMC80) to 0).
<4> Set the count value to CR80.
<5> Set TM80 to operation enabled (TCE80 = 1).
Each time the valid edge specified by bit 1 (TCL800) of TMC80 is input, the value of 8-bit timer counter 80 (TM80)
is incremented.
When the count value of TM80 matches the value set to CR80, the value of TM80 is cleared to 0 and TM80
continues counting. At the same time, an interrupt request signal (INTTM80) is generated.
Figure 9-5 shows the timing of the external event counter operation (with the rising edge specified).
Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer
operation-enabled state, a match interrupt request signal may occur at the moment of rewrite.
2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts.
Therefore, always follow the above procedure when operating the 8-bit timer/event counter as
an external event counter.
Figure 9-5. External Event Counter Operation Timing (with Rising Edge Specified)
TI80 pin input
TM80 count value
CR80
00H
02H
04H 05H
N
00H
02H 03H
01H
03H
N − 1
01H
N
TCE80
INTTM80
Remark N = 00H to FFH
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
9.4.3 Operation as square-wave output
The 8-bit timer/event counter can output square waves of a given frequency at intervals specified by the count
value set to 8-bit compare register 80 (CR80) in advance.
To operate 8-bit timer/event counter 80 as square-wave output, the following settings are required.
<1> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0.
<2> Set 8-bit timer counter 80 (TM80) to operation disabled (TCE80 = 0).
<3> Set the count clock of 8-bit timer/event counter 80 (refer to Figure 9-2), TO80 to output enabled (TOE80 = 1),
and PWM output to disabled (PWME80 = 0).
<4> Set the count value to CR80.
<5> Set TM80 to operation enabled (TCE80 = 1).
When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, the TO80/P24/INTP1/TO20
pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As
soon as a match occurs, the TM80 value is cleared to 0 and TM80 continues counting. At the same time, an interrupt
request signal (INTTM80) is generated.
Square-wave output is cleared (0) when bit 7 (TCE80) of TMC80 is set to 0.
Tables 9-6 and 9-7 show the square-wave output range, and Figure 9-6 shows the timing of square-wave output.
Cautions 1. Before rewriting CR80, stop the timer operation once. If CR80 is rewritten in the timer
operation-enabled state, a match interrupt request signal may occur at the moment of rewrite.
2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts.
Therefore, always follow the above procedure when operating the 8-bit timer/event counter as
square-wave output.
Table 9-6. Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz, 10.0 MHz Operation)
TCL801
TCL800
Minimum Pulse Width
1/fX (100 ns) [200 ns]
23/fX (0.8 µs) [1.6 µs]
Maximum Pulse Width
28/fX (25.6 µs) [51.2 µs]
211/fX (204.8 µs) [409.6 µs]
Resolution
1/fX (100 ns) [200 ns]
23/fX (0.8 µs) [1.6 µs]
0
0
0
1
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. The values in parentheses ( ) are for operation at fX = 10.0 MHz (expanded-specification products
only).
3. The values in square brackets [ ] are for operation at fX = 5.0 MHz.
Table 9-7. Square-Wave Output Range of 8-Bit Timer/Event Counter 80 (at fCC = 4.0 MHz Operation)
TCL801
TCL800
Minimum Interval Time
1/fCC (250 ns)
Maximum Interval Time
28/fCC (64 µs)
Resolution
0
0
0
1
1/fCC (250 ns)
23/fCC (2.0 µs)
23/fCC (2.0 µs)
211/fCC (512 µs)
Remark fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
Figure 9-6. Square-Wave Output Timing
Count clock
TM80 count value
00H
01H
N
00H 01H
Clear
N
00H 01H
Clear
N
CR80
N
N
N
N
TCE80
Count start
INTTM80
Interrupt acknowledged
Interrupt acknowledged
TO80Note
Note The TO80 initial value becomes low level while output is enabled (TOE80 = 1).
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
9.4.4 Operation as PWM output
PWM output enables interrupt generation repeatedly at intervals specified by the count value set to 8-bit compare
register 80 (CR80) in advance.
To use 8-bit timer/counter 80 for PWM output, the following settings are required.
<1> Set P24 to output mode (PM24 = 0) and the P24 output latch to 0.
<2> Set 8-bit timer counter 80 (TM80) to operation disabled (TCE80 = 0).
<3> Set the count clock of 8-bit timer/event counter 80 (refer to Figure 9-2), TO80 to output enabled (TOE80 = 1),
and PWM output to enabled (PWME80 = 1).
<4> Set the count value to CR80.
<5> Set TM80 to operation enabled (TCE80 = 1).
When the count value of 8-bit timer counter 80 (TM80) matches the value set to CR80, TM80 continues counting,
and an interrupt request signal (INTTM80) is generated.
Cautions 1. When CR80 is rewritten during timer operation, a high level may be output for the next cycle
(refer to 9.5 (2) Setting of 8-bit compare register 80).
2. If the count clock setting and TM80 operation-enabled are set in TMC80 simultaneously using
an 8-bit memory manipulation instruction, an error of more than one clock in one cycle may
occur after the timer starts. Therefore, always follow the above procedure when operating 8-
bit compare register 80 as a PWM output.
Figure 9-7. PWM Output Timing
Count clock
TM80 00H 01H • • •
M
• • • FFH 00H 01H 02H • • •
M
M + 1 M + 2 • • • FFH 00H 01H • • •
M
• • • • • •
CR80
M
TCE80
OVF
INTTM80
TO80Note
M = 01H to FFH
Note The TO80 initial value becomes low level while output is enabled (TOE80 = 1).
Caution Do not set CR80 to 00H in the PWM output mode; otherwise PWM may not be output normally.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
9.5 Notes on Using 8-Bit Timer/Event Counter 80
(1) Error on starting timer
An error of up to 1 clock occurs after the timer is started until a match signal is generated. This is because 8-
bit timer counter 80 (TM80) is started asynchronous to the count pulse.
Figure 9-8. Start Timing of 8-Bit Timer Counter
Count pulse
TM80
00H
01H
02H
03H
04H
count value
Timer start
(2) Setting of 8-bit compare register 80
8-bit compare register 80 (CR80) can be set to 00H.
Therefore, one pulse can be counted when the 8-bit timer/event counter operates as an event counter.
Figure 9-9. External Event Counter Operation Timing
Tl80 input
CR80
00H
TM80
count value
00H
00H
00H
00H
Interrupt request flag
Cautions 1. When rewriting CR80 in timer counter operation mode (i.e., PWME80 (bit 6 of 8-bit timer mode
control register 80 (TMC80)) is set to 0), be sure to stop the timer operation before hand. If
CR80 is rewritten in the timer operation-enabled state, a match interrupt request signal may
occur at the moment of rewrite.
2. If CR80 is rewritten while the timer is operating in PWM output operation mode (PWME80 = 1),
a pulse may not be generated just in the cycle immediately after the rewrite.
3. Do not set CR80 to 00H in the PWM output mode; otherwise PWM may not be output normally.
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CHAPTER 9 8-BIT TIMER/EVENT COUNTER 80
(3) Operation after rewriting compare register during PWM output
When 8-bit compare register 80 (CR80) is rewritten during PWM output, a high level may be output for a cycle
after rewriting CR80 (count pulse × 256) if the 8-bit compare register 80 value is smaller than the 8-bit timer
counter 80 (TM80) value. The timing in this case is shown in Figure 9-10.
Figure 9-10. Timing After Rewriting Compare Register During PWM Output
Count clock
...
...
...
...
...
...
...
TM80 00H 01H
M
FFH 00H 01H 02H
FFH 00H 01H
CR80
M
01H
H
TCE80
OVF
INTTM80
TO80
Rewriting CR80
M = 02H to FFH
(4) Notes on STOP mode setting
Before executing the STOP instruction, be sure to set the timer to operation stopped (TCE80 = 0).
(5) External event counter start timing
When the rising edge of TI80 is selected as the count clock, start the timer (TCE80 = 0 → 1) at the timing when
TI80 changes to low level. Similarly, when the falling edge of TI80 is selected as the count clock, start the timer
(TCE80 = 0 → 1) at the timing when TI80 changes to high level.
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CHAPTER 10 WATCHDOG TIMER
The watchdog timer can generate non-maskable interrupts, maskable interrupts and RESET at arbitrary preset
intervals.
10.1 Functions of Watchdog Timer
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect a program loop. When a program loop is detected, a non-maskable
interrupt or the RESET signal can be generated.
Table 10-1. Program Loop Detection Time of Watchdog Timer
Program Loop Detection
Time
At fX = 10.0 MHzNote
Operation
At fX = 5.0 MHz
Operation
At fCC = 4.0 MHz
Operation
211 × 1/fW
213 × 1/fW
215 × 1/fW
217 × 1/fW
205 µs
410 µs
512 µs
819 µs
1.64 ms
6.55 ms
26.2 ms
2.05 ms
8.19 ms
32.8 ms
3.28 ms
13.1 ms
Note Expanded-specification products only
Remark fW: fX or fCC
fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
(2) Interval timer
The interval timer generates an interrupt at a given interval set in advance.
Table 10-2. Interval Time
Interval Time
211 × 1/fW
At fX = 10.0 MHzNote
Operation
At fX = 5.0 MHz
Operation
At fCC = 4.0 MHz
Operation
205 µs
410 µs
512 µs
213 × 1/fW
215 × 1/fW
217 × 1/fW
819 µs
1.64 ms
6.55 ms
26.2 ms
2.05 ms
8.19 ms
32.8 ms
3.28 ms
13.1 ms
Note Expanded-specification products only
Remark fW: fX or fCC
fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
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10.2 Configuration of Watchdog Timer
The watchdog timer consists of the following hardware.
Table 10-3. Configuration of Watchdog Timer
Item
Configuration
Control registers
Timer clock select register 2 (TCL2)
Watchdog timer mode register (WDTM)
Figure 10-1. Block Diagram of Watchdog Timer
Internal bus
f
W
24
TMMK4
Prescaler
f
W
26
f
W
28
f
W
210
INTWDT
maskable
TMIF4
interrupt request
7-bit counter
Clear
RESET
INTWDT
non-maskable
interrupt request
3
WDTM3
RUN WDTM4
TCL22 TCL21 TCL20
Timer clock select register 2
(TCL2)
Watchdog timer mode register (WDTM)
Internal bus
Remark fW: fX or fCC
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CHAPTER 10 WATCHDOG TIMER
10.3 Watchdog Timer Control Registers
The following two registers are used to control the watchdog timer.
• Timer clock select register 2 (TCL2)
• Watchdog timer mode register (WDTM)
(1) Timer clock select register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Figure 10-2. Format of Timer Clock Select Register 2
Symbol
TCL2
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF42H
After reset
00H
R/W
R/W
TCL22 TCL21TCL20
TCL22 TCL21 TCL20
Interval time
Watchdog timer count clock selection
@ f
X
= 10.0 MHzNote
operation
@ f
X
= 5.0
@ fCC = 4.0
@ f
X
= 10.0 MHzNote
operation
@ f
X
= 5.0
@ fCC = 4.0
MHz operation MHz operation
MHz operation MHz operation
f
f
f
X
X
X
/24 or fCC/24 625 kHz
312.5 kHz 250 kHz
211/f
X
X
X
X
or 211/fCC 205
or 213/fCC 819
µ
µ
s
s
410
µ
s
512 s
µ
0
0
1
1
0
1
0
1
0
0
0
0
/26 or fCC/26 156.2 kHz 78.1 kHz 62.5 kHz 213/f
/28 or fCC/28 39.0 kHz 19.5 kHz 15.6 kHz 215/f
/210 or fCC/210 9.76 kHz 4.88 kHz 3.91 kHz 217/f
1.64 ms
6.55 ms
26.2 ms
2.05 ms
8.19 ms
32.8 ms
or 215/fCC 3.28 ms
or 217/fCC 13.1 ms
f
X
Other than above Setting prohibited
Note Expanded-specification products only
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 10 WATCHDOG TIMER
(2) Watchdog timer mode register (WDTM)
This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 10-3. Format of Watchdog Timer Mode Register
<7>
6
0
5
0
4
3
2
0
1
0
0
0
Address
FFF9H
After reset
00H
R/W
R/W
Symbol
WDTM RUN
WDTM4 WDTM3
Selection of operation of watchdog timerNote 1
RUN
0
1
Stop counting
Clear counter and start counting
Selection of operation mode of watchdog timerNote 2
WDTM4 WDTM3
0
0
1
1
0
1
0
1
Operation stop
Interval timer mode (overflow and maskable interrupt occur)Note 3
Watchdog timer mode 1 (overflow and non-maskable interrupt occur)
Watchdog timer mode 2 (overflow occurs and reset operation started)
Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is started, it
cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.
3. The watchdog timer starts operations as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to
0.8% shorter than the time set by timer clock select register 2 (TCL2).
2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of interrupt
request flag 0) has been set to 0. When watchdog timer mode 1 or 2 is selected under the
condition that TMIF4 is 1, a non-maskable interrupt occurs at the completion of rewriting.
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10.4 Operation of Watchdog Timer
10.4.1 Operation as watchdog timer
The watchdog timer operates to detect a program loop when bit 4 (WDTM4) of the watchdog timer mode register
(WDTM) is set to 1.
The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20
to TCL22) of timer clock select register 2 (TCL2). The watchdog timer is started by setting bit 7 (RUN) of WDTM to 1.
Set RUN to 1 within the set program loop detection time interval after the watchdog timer has been started. By setting
RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the program loop
detection time is exceeded, the system is reset or a non-maskable interrupt is generated according to the value of bit
3 (WDTM3) of WDTM.
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
Caution The actual program loop detection time may be up to 0.8% shorter than the set time.
Table 10-4. Program Loop Detection Time of Watchdog Timer
TCL22 TCL21 TCL20
Program Loop
Detection Time
At fX = 10.0 MHzNote
Operation
At fX = 5.0 MHz
Operation
At fCC = 4.0 MHz
Operation
0
0
1
1
0
1
0
1
0
0
0
0
2
2
2
2
11 × 1/fW
13 × 1/fW
15 × 1/fW
17 × 1/fW
205 µs
819 µs
3.28 ms
13.1 ms
410 µs
512 µs
1.64 ms
6.55 ms
26.2 ms
2.05 ms
8.19 ms
32.8 ms
Note Expanded-specification products only
Remark fW: fX or fCC
fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
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10.4.2 Operation as interval timer
When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 1, the watchdog
timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by the count
value set in advance.
Select the count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2
(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.
In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the
interval timer mode is not set, unless the RESET signal is input.
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the
set time.
Table 10-5. Interval Time of Interval Timer
TCL22 TCL21 TCL20
Interval Time
At fX = 10.0 MHzNote
Operation
At fX = 5.0 MHz
Operation
At fCC = 4.0 MHz
Operation
0
0
1
1
0
1
0
1
0
0
0
0
2
2
2
2
11 × 1/fW
13 × 1/fW
15 × 1/fW
17 × 1/fW
205 µs
819 µs
3.28 ms
13.1 ms
410 µs
512 µs
1.64 ms
6.55 ms
26.2 ms
2.05 ms
8.19 ms
32.8 ms
Note Expanded-specification products only
Remark fW: fX or fCC
fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)
11.1 8-Bit A/D Converter Functions
The 8-bit A/D converter is an 8-bit resolution converter that converts analog inputs into digital signals. This
converter can control up to four channels of analog inputs (ANI0 to ANI3).
A/D conversion can only be started by software.
One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with an
interrupt request (INTAD0) being issued each time an A/D session is completed.
11.2 8-Bit A/D Converter Configuration
The 8-bit A/D converter consists of the following hardware.
Table 11-1. Configuration of 8-Bit A/D Converter
Item
Analog input
Registers
Configuration
4 channels (ANI0 to ANI3)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
Control registers
A/D converter mode register 0 (ADM0)
Analog input channel specification register 0 (ADS0)
Figure 11-1. Block Diagram of 8-Bit A/D Converter
AVDD
P-ch
Sample & hold circuit
ANI0/P60
ANI1/P61
ANI2/P62
ANI3/P63
Voltage comparator
AVSS
AVSS
Successive
approximation
register (SAR)
INTAD0
Controller
A/D conversion result
register 0 (ADCR0)
2
ADS01 ADS00
Analog input channel
specification register 0
(ADS0)
ADCS0 FR02 FR01 FR00
A/D converter mode register 0
(ADM0)
Internal bus
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(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at the voltage tap
(comparison voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).
(2) A/D conversion result register 0 (ADCR0)
Each time A/D conversion ends, the conversion result received from the successive approximation register is
loaded into ADCR0, which is an 8-bit register that holds the result of A/D conversion.
ADCR0 can be read with an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
(3) Sample & hold circuit
The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the series resistor string.
(5) Series resistor string
The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 to ANI3 pins
Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the
analog signals for A/D conversion.
Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage
of AVDD or greater or AVSS or lower (even if within the absolute maximum ratings) is supplied
to any of these pins, the conversion value for the corresponding channel will be undefined.
Furthermore, the conversion values for the other channels may also be affected.
(7) AVSS pin
The AVSS pin is the ground potential pin for the A/D converter. This pin must be held at the same potential as
the VSS pin, even while the A/D converter is not being used.
(8) AVDD pin
The AVDD pin is the analog power supply pin for the A/D converter. This pin must be held at the same potential
as the VDD pin, even while the A/D converter is not being used.
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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)
11.3 Registers Controlling 8-Bit A/D Converter
The following two registers are used to control the 8-bit A/D converter.
• A/D converter mode register 0 (ADM0)
• Analog input channel specification register 0 (ADS0)
(1) A/D converter mode register 0 (ADM0)
ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADM0 to 00H.
Figure 11-2. Format of A/D Converter Mode Register 0
Symbol <7>
6
0
5
4
3
2
0
1
0
0
0
Address
FF80H
After reset
00H
R/W
R/W
ADM0 ADCS0
FR02 FR01 FR00
ADCS0
A/D conversion control
0
1
Conversion disabled
Conversion enabled
A/D conversion time selectionNote 1
FR02 FR01 FR00
@ f
X
= 10.0 MHzNote 2 operation @ f
= 5.0 MHz operation @ fCC = 4.0 MHz operation
X
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
144/f
120/f
X
X
or 144/fCC
or 120/fCC
14.4
µ
s
28.8
µ
s
36 µs
30 µs
24 µs
18 µs
15 µs
µ
µ
12
s
24
s
Setting prohibitedNote 3 19.2 µs
Setting prohibitedNote 3 14.4 µs
Setting prohibitedNote 3 12 µsNote 4
96/f
72/f
60/f
48/f
X
X
X
X
or 96/fCC
or 72/fCC
or 60/fCC
or 48/fCC
Setting prohibitedNote 3 Setting prohibitedNote 3 Setting prohibitedNote 3
Other than above
Setting prohibited
Notes 1. Set the A/D conversion time to satisfy the following specifications.
<Expanded-specification products>
When 4.5 V ≤ VDD ≤ 5.5 V: 12 µs min.
When 2.7 V ≤ VDD < 4.5 V: 14 µs min.
When 1.8 V ≤ VDD < 2.7 V: 28 µs min.
<Conventional-specification products>
When 2.7 V ≤ VDD ≤ 5.5 V: 14 µs min.
When 1.8 V ≤ VDD < 2.7 V: 28 µs min.
2. Expanded-specification products only
3. Setting prohibited because the A/D conversion time does not satisfy the rating shown in Note 1.
4. Can be set only for expanded-specification products when 4.5 V ≤ VDD ≤ 5.5 V. Otherwise, setting
prohibited.
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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)
Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to
11.5 (5) Timing when A/D conversion result become undefined).
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
(2) Analog input channel specification register 0 (ADS0)
The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal.
ADS0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADS0 to 00H.
Figure 11-3. Format of Analog Input Channel Specification Register 0
Symbol
ADS0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address
FF84H
After reset
00H
R/W
R/W
ADS01 ADS00
Analog input channel specification
ADS01 ADS00
ANI0
ANI1
ANI2
ANI3
0
0
1
1
0
1
0
1
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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)
11.4 8-Bit A/D Converter Operation
11.4.1 Basic operation of 8-bit A/D converter
<1> Select the channel for A/D conversion using analog input channel specification register 0 (ADS0).
<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.
<3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input
analog voltage until A/D conversion is completed.
<4> Bit 7 of the successive approximation register (SAR) is set. The tap selector sets the series resistor string
voltage tap to half AVDD.
<5> The series resistor string voltage tap is compared with the analog input voltage using the voltage comparator.
If the analog input voltage is higher than half AVDD, the MSB of the SAR is left set. If it is lower than half
AVDD, the MSB is reset.
<6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the
series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows.
• Bit 7 = 1: Three quarters of AVDD
• Bit 7 = 0: One quarter of AVDD
The voltage tap is compared with the analog input voltage. Bit 6 is set or reset according to the result of
comparison.
• Analog input voltage ≥ voltage tap: Bit 6 = 1
• Analog input voltage < voltage tap: Bit 6 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
<8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value is
sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate
an A/D conversion end interrupt request (INTAD0).
Cautions 1. The first A/D conversion value immediately after starting the A/D conversion operation
may be undefined.
2. When in standby mode, the A/D converter stops operation.
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Figure 11-4. Basic Operation of 8-Bit A/D Converter
Conversion
time
Sampling
time
A/D converter
operation
Sampling
A/D conversion
C0H
or 40H
Conversion
result
Undefined
SAR
ADCR0
INTAD0
80H
Conversion
result
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D
conversion, the A/D conversion in progress is canceled. In this case, if ADCS0 is set (1), A/D conversion is restarted
from the beginning.
RESET input makes A/D conversion result register 0 (ADCR0) undefined.
11.4.2 Input voltage and conversion result
The relationship between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion
result (A/D conversion result register 0 (ADCR0)) is represented by:
VIN
ADCR0 = INT (
× 256 + 0.5)
AVDD
or
AVDD
AVDD
(ADCR0 − 0.5) ×
≤ VIN < (ADCR0 + 0.5) ×
256
256
INT( ): Function that returns the integer part of the parenthesized value
VIN:
Analog input voltage
AVDD:
A/D converter supply voltage
ADCR0: Value in A/D conversion result register 0 (ADCR0)
Figure 11-5 shows the relationship between the analog input voltage and the A/D conversion result.
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Figure 11-5. Relationship Between Analog Input Voltage and A/D Conversion Result
255
254
253
A/D conversion
result (ADCR0)
3
2
1
0
1
1
3
2
5
3
507 254 509 255 511
512 256 512 256 512
1
512 256 512 256 512 256
Input voltage/AVDD
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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)
11.4.3 Operation mode of 8-bit A/D converter
The 8-bit A/D converter is initially in the select mode. In this mode, analog input channel specification register 0
(ADS0) is used to select the analog input channel from ANI0 to ANI3 for A/D conversion.
A/D conversion can only be started by software; that is, by setting A/D converter mode register 0 (ADM0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt
request signal (INTAD0) is generated.
• Software-started A/D conversion
Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for the voltage applied to
the analog input pin specified by analog input channel specification register 0 (ADS0). Upon completion of A/D
conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an
interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another
session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data
where ADCS0 is 1 is written to ADM0 again during A/D conversion, the session of A/D conversion in progress is
discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0 is 0 is written
to ADM0 again during A/D conversion, A/D conversion is completely stopped.
Figure 11-6. Software-Started A/D Conversion
Rewriting ADM0
ADCS0 = 1
Rewriting ADM0
ADCS0 = 1
ADCS0 = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion is
discontinued;
no conversion
Stop
result is preserved.
ADCR0
INTAD0
ANIn
ANIn
ANIm
Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3
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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)
11.5 Notes on Using 8-Bit A/D Converter
(1) Current consumption in the standby mode
When the A/D converter enters the standby mode, it stops operating. Clearing bit 7 (ADCS0) of A/D converter
mode register 0 (ADM0) to 0 can reduce the current consumption.
Figure 11-7 shows how to reduce the current consumption in the standby mode.
Figure 11-7. How to Reduce Current Consumption in Standby Mode
AVDD
ADCS0
P-ch
Series resistor string
AVSS
(2) Input range for the ANI0 to ANI3 pins
Be sure to keep the input voltage at ANI0 to ANI3 within the rated values. If a voltage of AVDD or grater or AVSS
or lower (even if within the absolute maximum ratings) is input to a conversion channel, the conversion output
of the channel becomes undefined, and the conversion output of the other channels may also be affected.
(3) Conflict
<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and
reading from ADCR0
Reading from ADCR0 takes precedence. After reading, the new conversion result is written to ADCR0.
<2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register 0
(ADM0) or analog input channel specification register 0 (ADS0)
Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion end
interrupt request signal (INTAD0) is generated.
(4) Conversion results immediately following start of A/D conversion
The first A/D conversion value immediately following the start of A/D converter operation may be undefined.
Be sure to perform processing such as polling the A/D conversion end interrupt request (INTAD0) and
discarding the first conversion result.
(5) Timing that makes the A/D conversion result undefined
If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is operating. Furthermore, when reading out an A/D conversion result after A/D
converter operation has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 11-8 and 11-9.
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Figure 11-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end
A/D conversion end
ADCR0
INTAD0
ADCS0
Normal conversion result
Undefined value
Normal conversion result read out
A/D operation stopped
Undefined value read out
Figure 11-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
A/D conversion end
ADCR0
Normal conversion result
INTAD0
ADCS0
A/D operation stopped Normal conversion result read out
(6) Noise prevention
To maintain a resolution of 8 bits, watch for noise at the AVDD and ANI0 to ANI3 pins. The higher the output
impedance of the analog input source is, the larger the effect by noise. To reduce noise, attach an external
capacitor to the relevant pins as shown in Figure 11-10.
Figure 11-10. Analog Input Pin Treatment
If noise of AVDD or greater or AVSS or lower is
likely to come to the AVDD pin, clamp the voltage
at the pin by attaching a diode with a small V
F
(0.3 V or lower).
VDD
AVDD
ANI0 to ANI3
AVSS
C = 100 to 1000 pF
VSS
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CHAPTER 11 8-BIT A/D CONVERTER (µPD789104A, 789124A SUBSERIES)
(7) ANI0 to ANI3
The analog input pins (ANI0 to ANI3) are alternate-function pins. They are also used as port pins (P60 to
P63).
If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports;
otherwise the conversion resolution may become lower.
If a digital pulse is applied to a pin adjacent to the analog input pin being A/D converted, coupling noise may
occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse
to pins adjacent to the analog input pin being A/D converted.
(8) Input impedance of ANI0 to ANI3 pins
This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs
sampling.
Therefore at times other than sampling, only the leakage current flows. During sampling, the current for
charging the capacitor also flows, so the input impedance fluctuates and has no meaning.
However, to ensure adequate sampling, it is recommend that the output impedance of the analog input source
be set to 10 kΩ or lower, or a capacitor of about 100 pF be connected to the ANI0 to ANI3 pins (refer to Figure
11-10).
(9) Interrupt request flag (ADIF0)
Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag
(ADIF0).
If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion
end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In
this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed, even
when A/D conversion has not been completed for the new analog input.
In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand.
Figure 11-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting to ADM0
(to begin conversion
for ANIn)
Rewriting to ADM0
(to begin conversion
for ANIm)
ADIF0 has been set, but conversion
for ANIm has not been completed.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ANIn
ANIn
ANIm
ANIm
ADCR0
INTAD0
Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3
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(10)AVDD pin
The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3
input circuit.
Therefore, if the application is designed to be switched to backup power, the AVDD pin must be supplied with
the same voltage level as for the VDD pin, as shown in Figure 11-12.
Figure 11-12. AVDD Pin Treatment
VDD
AVDD
Main power
source
Backup
capacitor
V
SS
AVSS
(11)Input impedance of the AVDD pin
A series resistor string of several 10 kΩ is connected across the AVDD and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually
connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher
reference voltage error.
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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)
12.1 10-Bit A/D Converter Functions
The 10-bit A/D converter is a 10-bit resolution converter that converts analog inputs into digital signals. This
converter can control up to four channels of analog inputs (ANI0 to ANI3).
A/D conversion can only be started by software.
One of analog inputs ANI0 to ANI3 is selected for A/D conversion. A/D conversion is performed repeatedly, with an
interrupt request (INTAD0) being issued each time an A/D session is completed.
12.2 10-Bit A/D Converter Configuration
The A/D converter consists of the following hardware.
Table 12-1. Configuration of 10-Bit A/D Converter
Item
Analog input
Registers
Configuration
4 channels (ANI0 to ANI3)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
Control registers
A/D converter mode register 0 (ADM0)
Analog input channel specification register 0 (ADS0)
Figure 12-1. Block Diagram of 10-Bit A/D Converter
AVDD
P-ch
Sample & hold circuit
ANI0/P60
ANI1/P61
ANI2/P62
ANI3/P63
Voltage comparator
AVSS
AVSS
Successive
approximation
register (SAR)
INTAD0
Controller
A/D conversion result
register 0 (ADCR0)
2
ADS01 ADS00
Analog input channel
specification register 0
(ADS0)
ADCS0 FR02 FR01 FR00
A/D converter mode register 0
(ADM0)
Internal bus
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(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at the voltage tap
(comparison voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).
(2) A/D conversion result register 0 (ADCR0)
ADCR0 is a 16-bit register that holds the result of A/D conversion. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result in the successive approximation register is loaded into ADCR0.
The results are stored in ADCR0 from the most significant bit.
The higher 8 bits of the conversion result are stored in FF15H and the lower 2 bits of the conversion result are
stored in FF14H.
ADCR0 can be read with a 16-bit memory manipulation instruction.
RESET input makes ADCR0 undefined.
FF14H
FF15H
Address
After reset R/W
Symbol
ADCR0
FF14H,
FF15H
0
0
0
0
0
0
Undefined
R
Caution When using the µPD78F9116A and 78F9116B as flash memory versions of the µPD789101A,
789102A, and 789104A, or the µPD78F9136A and 78F9136B as flash memory versions of the
µPD789121A, 789122A, and 789124A, an 8-bit access can be made by ADCR0. However, it is
performed only with the object file assembled by the µPD789101A, 789102A, or 789104A, or
by the µPD789121A, 789122A, or 789124A, respectively.
(3) Sample & hold circuit
The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the series resistor string.
(5) Series resistor string
The series resistor string is configured between AVDD and AVSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 to ANI3 pins
Pins ANI0 to ANI3 are the 4-channel analog input pins for the A/D converter. They are used to receive the
analog signals for A/D conversion.
Caution Do not supply pins ANI0 to ANI3 with voltages that fall outside the rated range. If a voltage
of AVDD or greater or AVSS or lower (even if within the absolute maximum ratings) is supplied
to any of these pins, the conversion value for the corresponding channel will be undefined.
Furthermore, the conversion values for the other channels may also be affected.
(7) AVSS pin
The AVSS pin is the ground potential pin for the A/D converter. This pin must be held at the same potential as
the VSS pin, even while the A/D converter is not being used.
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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)
(8) AVDD pin
The AVDD pin is the analog power supply pin for the A/D converter. This pin must be held at the same potential
as the VDD pin, even while the A/D converter is not being used.
12.3 Registers Controlling 10-Bit A/D Converter
The following two registers are used to control the 10-bit A/D converter.
• A/D converter mode register 0 (ADM0)
• Analog input channel specification register 0 (ADS0)
(1) A/D converter mode register 0 (ADM0)
ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears the ADM0 to 00H.
Figure 12-2. Format of A/D Converter Mode Register 0
Symbol <7>
6
0
5
4
3
2
0
1
0
0
0
Address
FF80H
After reset
00H
R/W
R/W
ADM0 ADCS0
FR02 FR01 FR00
ADCS0
A/D conversion control
0
1
Conversion disabled
Conversion enabled
A/D conversion time selectionNote 1
FR02 FR01 FR00
@ f
X
= 10.0 MHzNote 2 operation @ f
= 5.0 MHz operation @ fCC = 4.0 MHz operation
X
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
144/f
120/f
X
X
or 144/fCC
or 120/fCC
14.4
µ
s
28.8
µ
s
36 µs
30 µs
24 µs
18 µs
15 µs
µ
µ
12
s
24
s
Setting prohibitedNote 3 19.2 µs
Setting prohibitedNote 3 14.4 µs
Setting prohibitedNote 3 12 µsNote 4
96/f
72/f
60/f
48/f
X
X
X
X
or 96/fCC
or 72/fCC
or 60/fCC
or 48/fCC
Setting prohibitedNote 3 Setting prohibitedNote 3 Setting prohibitedNote 3
Other than above
Setting prohibited
Notes 1. Set the A/D conversion time to satisfy the following specifications.
<Expanded-specification products>
When 4.5 V ≤ VDD ≤ 5.5 V: 12 µs min.
When 2.7 V ≤ VDD < 4.5 V: 14 µs min.
When 1.8 V ≤ VDD < 2.7 V: 28 µs min.
<Conventional-specification products>
When 2.7 V ≤ VDD ≤ 5.5 V: 14 µs min.
When 1.8 V ≤ VDD < 2.7 V: 28 µs min.
2. Expanded-specification products only
3. Setting prohibited because the A/D conversion time does not satisfy the rating shown in Note 1.
4. Can be set only for expanded-specification products when 4.5 V ≤ VDD ≤ 5.5 V. Otherwise, setting
prohibited.
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Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. The result of conversion after ADCS0 is cleared may be undefined (for details, refer to
12.5 (5) Timing when A/D conversion result becomes undefined).
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
(2) Analog input channel specification register 0 (ADS0)
The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal.
ADS0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADS0 to 00H.
Figure 12-3. Format of Analog Input Channel Specification Register 0
Symbol
ADS0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address
FF84H
After reset
00H
R/W
R/W
ADS01 ADS00
Analog input channel specification
ADS01 ADS00
ANI0
ANI1
ANI2
ANI3
0
0
1
1
0
1
0
1
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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)
12.4 10-Bit A/D Converter Operation
12.4.1 Basic operation of 10-bit A/D converter
<1> Select the channel for A/D conversion, using analog input channel specification register 0 (ADS0).
<2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit.
<3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input
analog voltage until A/D conversion is completed.
<4> Bit 9 of the successive approximation A/D conversion register (SAR) is set. The tap selector sets the series
resistor string voltage tap to half AVDD.
<5> The series resistor string voltage tap is compared with the analog input voltage using the voltage comparator.
If the analog input voltage is higher than half AVDD, the MSB of the SAR is left set. If it is lower than half
AVDD, the MSB is reset.
<6> Bit 8 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the
series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows.
• Bit 9 = 1: Three quarters of AVDD
• Bit 9 = 0: One quarter of AVDD
The voltage tap is compared with the analog input voltage. Bit 8 is set or reset according to the result of
comparison.
• Analog input voltage ≥ voltage tap: Bit 8 = 1
• Analog input voltage < voltage tap: Bit 8 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
<8> When comparison is completed for all of the 10 bits, a significant digital result is left in the SAR. This value is
sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate
an A/D conversion end interrupt request (INTAD0).
Cautions 1. The A/D conversion value immediately after starting the A/D conversion operation may
be undefined.
2. When in standby mode, the A/D converter stops operation.
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Figure 12-4. Basic Operation of 10-Bit A/D Converter
Conversion
time
Sampling
time
A/D converter
operation
A/D conversion
Sampling
Conversion
result
SAR
ADCR0
INTAD0
Undefined
Conversion
result
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software.
If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D
conversion, the A/D conversion in progress is canceled. In this case, A/D conversion is restarted from the beginning, if
ADCS0 is set (1).
RESET input makes A/D conversion result register 0 (ADCR0) undefined.
12.4.2 Input voltage and conversion result
The relationship between the analog input voltage at the analog input pins (ANI0 to ANI3) and the A/D conversion
result (A/D conversion result register 0 (ADCR0)) is represented by:
VIN
ADCR0 = INT (
× 1,024 + 0.5)
AVDD
or
AVDD
AVDD
(ADCR0 − 0.5) ×
≤ VIN < (ADCR0 + 0.5) ×
1,024
1,024
INT( ): Function that returns the integer part of the parenthesized value
VIN:
Analog input voltage
AVDD:
A/D converter supply voltage
ADCR0: Value in A/D conversion result register 0 (ADCR0)
Figure 12-5 shows the relationship between the analog input voltage and the A/D conversion result.
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Figure 12-5. Relationship Between Analog Input Voltage and A/D Conversion Result
1,023
1,022
1,021
A/D conversion
result (ADCR0)
3
2
1
0
1
1
3
2
5
3
2,043 1,022 2,045 1,023 2,047
2,048 1,024 2,048 1,024 2,048
1
2,048 1,024 2,048 1,024 2,048 1,024
Input voltage/AVDD
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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)
12.4.3 Operation mode of 10-bit A/D converter
The 10-bit A/D converter is initially in the select mode. In this mode, analog input channel specification register 0
(ADS0) is used to select the analog input channel from ANI0 to ANI3 for A/D conversion.
A/D conversion can be started only by software; that is, by setting A/D converter mode register 0 (ADM0).
The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt
request signal (INTAD0) is generated.
• Software-started A/D conversion
Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for the voltage applied to
the analog input pin specified by analog input channel specification register 0 (ADS0).
Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0).
At the same time, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and
completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to
ADM0. If data where ADCS0 is 1 is written to ADM0 again during A/D conversion, the session of A/D conversion
in progress is discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0
is 0 is written to ADM0 again during A/D conversion, A/D conversion is completely stopped.
Figure 12-6. Software-Started A/D Conversion
Rewriting ADM0
ADCS0 = 1
Rewriting ADM0
ADCS0 = 1
ADCS0 = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion is
discontinued;
no conversion
Stop
result is preserved.
ADCR0
INTAD0
ANIn
ANIn
ANIm
Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3
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12.5 Notes on Using 10-Bit A/D Converter
(1) Current consumption in the standby mode
When the A/D converter enters the standby mode, it stops operating. Clearing bit 7 (ADCS0) of A/D converter
mode register 0 (ADM0) to 0 can reduce the current consumption.
Figure 12-7 shows how to reduce the current consumption in the standby mode.
Figure 12-7. How to Reduce Current Consumption in Standby Mode
AVDD
ADCS0
P-ch
Series resistor string
AVSS
(2) Input range for the ANI0 to ANI3 pins
Be sure to keep the input voltage at ANI0 to ANI3 within the rated values. If a voltage of AVDD or greater or
AVSS or lower (even if within the absolute maximum ratings) is input a conversion channel, the conversion
output of the channel becomes undefined, and the conversion output of the other channels may also be
affected.
(3) Conflict
<1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and
reading from ADCR0
Reading from ADCR0 takes precedence. After reading, the new conversion result is written to ADCR0.
<2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register 0
(ADM0) or analog input channel specification register 0 (ADS0)
Writing to ADM0 or ADS0 takes precedence. A request to write to ADCR0 is ignored. No conversion end
interrupt request signal (INTAD0) is generated.
(4) Conversion results immediately following start of A/D conversion
The first A/D conversion value immediately following the start of A/D converter operation may be undefined.
Be sure to perform processing such as polling the A/D conversion end interrupt request (INTAD0) and
discarding the first conversion result.
(5) Timing that makes the A/D conversion result undefined
If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is operating. Furthermore, when reading out an A/D conversion result after A/D
converter operation has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 12-8 and 12-9.
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Figure 12-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end
A/D conversion end
ADCR0
INTAD0
ADCS0
Normal conversion result
Undefined value
Normal conversion result read out
A/D operation stopped
Undefined value read out
Figure 12-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
A/D conversion end
ADCR0
Normal conversion result
INTAD0
ADCS0
A/D operation stopped Normal conversion result read out
(6) Noise prevention
To maintain a resolution of 10 bits, watch for noise at the AVDD and ANI0 to ANI3 pins. The higher the output
impedance of the analog input source is, the larger the effect by noise is. To reduce noise, attach an external
capacitor to the relevant pins as shown in Figure 12-10.
Figure 12-10. Analog Input Pin Treatment
If noise of AVDD or greater or AVSS or lower is
likely to come to the AVDD pin, clamp the voltage
at the pin by attaching a diode with a small V
F
(0.3 V or lower).
VDD
AVDD
ANI0 to ANI3
AVSS
C = 100 to 1000 pF
VSS
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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)
(7) ANI0 to ANI3
The analog input pins (ANI0 to ANI3) are alternate-function pins. They are also used as port pins (P60 to
P63).
If any of ANI0 to ANI3 has been selected for A/D conversion, do not execute input instructions for the ports;
otherwise, the conversion resolution may become lower.
If a digital pulse is applied to a pin adjacent to the analog input pin being A/D converted, coupling noise may
occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse
to pins adjacent to the analog input pin being A/D converted.
(8) Input impedance of ANI0 to ANI3 pins
This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs
sampling.
Therefore at times other than sampling, only the leakage current flows. During sampling, the current for
charging the capacitor also flows, so the input impedance fluctuates and has no meaning.
However, to ensure adequate sampling, it is recommend that the output impedance of the analog input source
be set to 10 kΩ or lower, or a capacitor of about 100 pF be connected to the ANI0 to ANI3 pins (refer to Figure
12-10).
(9) Interrupt request flag (ADIF0)
Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag
(ADIF0).
If the analog input pins are changed during A/D conversion, therefore, the conversion result and the conversion
end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In
this case, ADIF0 may appear to be set if it is read-accessed immediately after ADM0 is write-accessed, even
when A/D conversion has not been completed for the new analog input.
In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand.
Figure 12-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting to ADM0
(to begin conversion
for ANIn)
Rewriting to ADM0
(to begin conversion
for ANIm)
ADIF0 has been set, but conversion
for ANIm has not been completed.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ANIn
ANIn
ANIm
ANIm
ADCR0
INTAD0
Remarks 1. n = 0, 1, 2, 3
2. m = 0, 1, 2, 3
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CHAPTER 12 10-BIT A/D CONVERTER (µPD789114A, 789134A SUBSERIES)
(10)AVDD pin
The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI3
input circuit.
Therefore, if the application is designed to be changed to backup power, the AVDD pin must be supplied with
the same voltage level as for the VDD pin, as shown in Figure 12-12.
Figure 12-12. AVDD Pin Treatment
VDD
AVDD
Backup
Main power
source
capacitor
V
SS
AVSS
(11)Input impedance of the AVDD pin
A series resistor string of several 10 kΩ is connected across the AVDD and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually
connected in parallel with the series resistor string across the AVDD and AVSS pins, leading to a higher
reference voltage error.
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CHAPTER 13 SERIAL INTERFACE 20
13.1 Functions of Serial Interface 20
Serial interface 20 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.
(2) Asynchronous serial interface (UART) mode
This mode is used to transmit and receive the one byte of data that follows a start bit. It supports full-duplex
communication.
Serial interface channel 0 contains a dedicated UART baud rate generator, enabling communication over a
wide range of baud rates. It is also possible to define baud rates by dividing the frequency of the input clock
pulse at the ASCK20 pin.
It is recommended that ceramic/crystal oscillation be used for the system clock in the UART mode. Because
the frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the
baud rate generator, there may be problems in transmit/receive operations.
(3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission)
This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data lines
(SI20 and SO20).
As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing time
for data transmission than asynchronous serial interface mode.
Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB
or LSB, channel 0 can be connected to any device regardless of whether that device is designed for MSB-first
or LSB-first transmission.
3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having
conventional clocked serial interfaces, such as those of the 75XL, 78K, and 17K Series devices.
13.2 Serial Interface 20 Configuration
Serial interface 20 consists of the following hardware.
Table 13-1. Configuration of Serial Interface 20
Item
Registers
Configuration
Transmit shift register 20 (TXS20)
Receive shift register 20 (RXS20)
Receive buffer register 20 (RXB20)
Control registers
Serial operating mode register 20 (CSIM20)
Asynchronous serial interface mode register 20 (ASIM20)
Asynchronous serial interface status register 20 (ASIS20)
Baud rate generator control register 20 (BRGC20)
Port mode register 2 (PM2)
Port 2 (P2)
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Figure 13-1. Block Diagram of Serial Interface 20
Internal bus
Serial operation mode
register 20 (CSIM20)
Asynchronous serial
interface status register 20
Asynchronous serial
interface mode register 20
(ASIS20)
(ASIM20)
Receive buffer
register 20 (RXB20)
TXE20 RXE20 PS201 PS200 CL20 SL20
CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20
PE20 FE20 OVE20
Switching of first bit
Transmit shift
Transmit
register 20 (TXS20)
shift clock
SI20/P22/
RxD20
Receive shift
register 20 (RXS20)
Selector
CSIE20
DAP20
Reception
shift clock
Output latch
Port mode
(P21)
Data phase
control
register (PM21)
SO20/P21/
TxD20
Parity operation
Stop bit addition
INTST20
4
Transmission data counter
Parity detection
SL20, CL20, PS200, PS201
INTSR20/INTCSI20
Stop bit detection
Reception data counter
Reception enabled
Reception clock
Transmission
and reception
clock control
CSIE20
CSCK20
/2 to f
/28
Baud rate
generatorNote
Start bit
detection
Detection clock
f
X
X
Reception detected
TPS203
4
SS20/P23/
CPT20/INTP0
CSIE20
TPS202 TPS201 TPS200
Internal clock output
CSCK20
Baud rate generator
control register 20 (BRGC20)
Clock phase
control
SCK20/P20/
ASCK20
External clock input
Internal bus
Note Refer to Figure 13-2 for the configuration of the baud rate generator.
Figure 13-2. Baud Rate Generator Block Diagram
Reception detection clock
Transmission shift clock
Transmission
clock counter
1/2
f
X
/2
f
f
f
f
f
f
f
X
X
X
X
X
X
X
/22
/23
/24
/25
/26
/27
/28
1/2
Reception shift clock
Reception
clock counter
TXE20
SCK20/ASCK20/P20
RXE20
CSIE20
Reception detection
4
TPS203 TPS202 TPS201 TPS200
Baud rate generator
control register 20
(BRGC20)
Internal bus
CHAPTER 13 SERIAL INTERFACE 20
(1) Transmit shift register 20 (TXS20)
TXS20 is a register in which transmit data is prepared. The transmit data is output from TXS20 bit-serially.
When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmit data. Writing data to TXS20
triggers transmission.
TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read.
RESET input sets TXS20 to FFH.
Caution Do not write to TXS20 during transmission.
TXS20 and receive buffer register 20 (RXB20) are mapped at the same address, so that any
attempt to read from TXS20 results in a value being read from RXB20.
(2) Receive shift register 20 (RXS20)
RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one
entire byte has been received, RXS20 transfers the receive data to receive buffer register 20 (RXB20).
RXS20 cannot be manipulated directly by a program.
(3) Receive buffer register 20 (RXB20)
RXB20 holds receive data. New receive data is transferred from receive shift register 0 (RXS20) per 1 byte of
data received.
When the data length is specified as seven bits, the receive data is sent to bits 0 to 6 of RXB20, in which the
MSB is always fixed to 0.
RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written to.
RESET input makes RXB20 undefined.
Caution RXB20 and transmit shift register 20 (TXS20) are mapped at the same address, so that any
attempt to write to RXB20 results in a value being written to TXS20.
(4) Transmission controller
The transmission controller controls transmission. For example, it adds start, parity, and stop bits to the data in
transmit shift register 20 (TXS20), according to the setting of asynchronous serial interface mode register 20
(ASIM20).
(5) Reception controller
The reception controller controls reception according to the setting of asynchronous serial interface mode
register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is detected,
asynchronous serial interface status register 20 (ASIS20) is set according to the status of the error.
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CHAPTER 13 SERIAL INTERFACE 20
13.3 Serial Interface 20 Control Registers
Serial interface 20 is controlled by the following six registers.
• Serial operating mode register 20 (CSIM20)
• Asynchronous serial interface mode register 20 (ASIM20)
• Asynchronous serial interface status register 20 (ASIS20)
• Baud rate generator control register 20 (BRGC20)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1) Serial operating mode register 20 (CSIM20)
CSIM20 is used to make the settings related to 3-wire serial I/O mode.
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
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CHAPTER 13 SERIAL INTERFACE 20
Figure 13-3. Format of Serial Operating Mode Register 20
Symbol <7>
6
5
0
4
0
3
2
1
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20 SSE20
DAP20 DIR20 CSCK20 CKP20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
SSE20
Communication status
Function of SS20/P23 pin
Port function
SS20-pin selection
0
1
Not used
Used
Communication enabled
0
1
Communication enabled
Communication disabled
DAP20
3-wire serial I/O mode data phase selection
0
1
Output at falling edge of SCK20
Output at rising edge of SCK20
DIR20
First-bit specification
0
1
MSB
LSB
3-wire serial I/O mode clock selection
CSCK20
External clock pulse input to SCK20 pin
Output of dedicated baud rate generator
0
1
CKP20
3-wire serial I/O mode clock phase selection
0
1
Clock is active low, and SCK20 is at high level in the idle state
Clock is active high, and SCK20 is at low level in the idle state
Cautions 1. Bits 4 and 5 must be fixed to 0.
2. CSIM20 must be cleared to 00H if UART mode is selected.
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(2) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is used to make the settings related to asynchronous serial interface mode.
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Figure 13-4. Format of Asynchronous Serial Interface Mode Register 20
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20
TXE20
Transmit operation control
0
1
Transmit operation stop
Transmit operation enable
RXE20
Receive operation control
0
1
Receive operation stop
Receive operation enable
PS201 PS200
Parity bit specification
0
0
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (no parity error is generated).
1
1
0
1
Odd parity
Even parity
CL20
Transmit data character length specification
0
1
7 bits
8 bits
SL20
Transmit data stop bit length
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must be fixed to 0.
2. If 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H.
3. Switch operating modes after halting the serial transmit/receive operation.
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Table 13-2. Serial Interface 20 Operating Mode Settings
(1) Operation stopped mode
ASIM20
CSIM20
PM22
P21
PM21
P21
PM20
P20
First Bit Shift P22/SI20/RxD20 P21/SO20/TxD20
P20/SCK20/
ASCK20 Pin
Function
Clock
Pin Function
Pin Function
TXE20 RXE20 CSIE20 DIR20 CSCK20
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
×
×
×
×
×
×
0
0
0
×
×
−
−
P22
P21
P20
Other than above
Setting prohibited
(2) 3-wire serial I/O mode
ASIM20
CSIM20
PM22
P21
PM21
P21
1
PM20
P20
First Bit Shift P22/SI20/RxD20 P21/SO20/TxD20
P20/SCK20/
ASCK20 Pin
Function
Clock
Pin Function
Pin Function
TXE20 RXE20 CSIE20 DIR20 CSCK20
Note 1
Note 2
×
×
SI20Note 2
0
0
1
1
0
1
0
0
1
×
MSB
LSB
External
clock
SCK20(CMOS
output)
SCK20 input
Internal
clock
1
0
1
0
1
0
1
×
1
SCK20 output
SCK20 input
SCK20 output
External
clock
Internal
clock
Other than above
Setting prohibited
(3) Asynchronous serial interface mode
ASIM20
CSIM20
PM22
P21
PM21
P21
1
PM20
P20
First Bit Shift P22/SI20/RxD20 P21/SO20/TxD20
Clock Pin Function Pin Function
P20/SCK20/
ASCK20 Pin
Function
TXE20 RXE20 CSIE20 DIR20 CSCK20
Note 1
Note 1
LSB
×
×
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
×
External P22
clock
TxD20
(CMOS output)
ASCK20 input
Note 1
Note 1
P20
×
×
Internal
clock
Note 1
Note 1
×
×
1
1
×
×
1
×
External RD20
clock
P21
ASCK20 input
P20
Note 1
Note 1
×
×
×
Internal
clock
0
1
1
×
External
clock
TxD20
ASCK20 input
P20
(CMOS output)
Note 1
Note 1
Internal
clock
×
Other than above
Setting prohibited
Notes 1. These pins can be used for port functions.
2. When only transmission is used, these pins can be used as P22 (CMOS I/O).
Remark ×: don’t care.
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CHAPTER 13 SERIAL INTERFACE 20
(3) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 is used to display the type of a reception error, if it occurs while asynchronous serial interface mode is
set.
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
The contents of ASIS20 are undefined in 3-wire serial I/O mode.
RESET input clears ASIS20 to 00H.
Figure 13-5. Format of Asynchronous Serial Interface Status Register 20
Symbol
ASIS20
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF71H
After reset
00H
R/W
R
PE20 FE20 OVE20
PE20
Parity error flag
0
1
No parity error has occurred.
A parity error has occurred (when the transmission parity and reception parity do not match).
FE20
Framing error flag
No framing error has occurred.
0
1
A framing error has occurred (when no stop bit is detected).Note 1
OVE20
Overrun error flag
0
1
No overrun error has occurred.
An overrun error has occurred.Note 2
(Before data was read from the reception buffer register, the subsequent reception sequence was
completed.)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface
mode register 20 (ASIM20), the stop bit detection in the case of reception is performed with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every time
the data is received an overrun error will occur.
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(4) Baud rate generator control register 20 (BRGC20)
BRGC20 is used to specify the serial clock for the serial interface.
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
Figure 13-6. Format of Baud Rate Generator Control Register 20
Symbol
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
BRGC20 TPS203 TPS202 TPS201 TPS200
TPS203 TPS202 TPS201 TPS200
Selection of source clock for baud rate generator
= 10.0 MHzNote 1 operation @ f
= 5.0 MHz operation
n
@ f
X
X
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
−
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/2
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
5.0 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
/22
/23
/24
/25
/26
/27
/28
External clock pulse input at the ASCK20 pinNote 2
Setting prohibited
Other than above
Notes 1. Expanded-specification products only
2. An external clock can only be used in UART mode.
Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of
baud rate generator is disrupted and communications cannot be performed normally. Be
sure not to write to BRGC20 during communication operations.
2. Be sure not to select n = 1 when fX > 2.5 MHz in UART mode because n = 1 exceeds the
rating of the baud rate.
3. Be sure not to select n = 2 when fX > 5.0 MHz in UART mode because n = 2 exceeds the
rating of the baud rate.
4. Be sure not to select n = 1 when fX > 5.0 MHz in 3-wire serial I/O mode because n = 1
exceeds the rating of the serial clock.
5. When the external input clock is selected, set port mode register 2 (PM2) in input mode.
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. n: Value specified in TPS200 to TPS203 (1 ≤ n ≤ 8)
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The baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a
signal divided from the clock input from the ASCK20 pin.
(a) Generation of baud rate UART transmit/receive clock by means of system clock
The transmit/receive clock is generated by dividing the system clock. The baud rate generated from the
system clock is estimated by using the following expression.
fX
n + 1 × 8
[Baud rate] =
[bps]
2
fX: System clock oscillation frequency (ceramic/crystal oscillation)
n: Values in Figure 13-6 specified by the setting in TPS200 to TPS203 (2 ≤ n ≤ 8)
Table 13-3. Example of Relationship Between System Clock and Baud Rate
Baud Rate
(bps)
fX = 10.0 MHzNote
fX = 5.0 MHz
fX = 4.9152 MHz
n
BRGC20
Setting
Error
(%)
n
BRGC20
Setting
Error
(%)
n
BRGC20
Setting
Error
(%)
1,200
−
8
7
6
5
4
3
−
1.73
8
7
6
5
4
3
2
70H
60H
50H
40H
30H
20H
10H
1.73
8
7
6
5
4
3
2
70H
60H
50H
40H
30H
20H
10H
0
2,400
70H
60H
50H
40H
30H
20H
4,800
9,600
19,200
38,400
76,800
Note Expanded-specification products only.
Cautions 1. Be sure not to select n = 1 when fX > 2.5 MHz because n = 1 exceeds the rating of the baud rate.
2. Be sure not to select n = 2 when fX > 5.0 MHz because n = 2 exceeds the rating of the baud rate.
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CHAPTER 13 SERIAL INTERFACE 20
(b) Generation of baud rate UART transmit/receive clock by means of external clock from ASCK20 pin
The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate
generated from the clock input from the ASCK20 pin is estimated by using the following expression.
fASCK
[Baud rate] =
[bps]
16
fASCK: Frequency of clock pulse received at the ASCK20 pin
Table 13-4. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps)
75
ASCK20 Pin Input Frequency (kHz)
1.2
2.4
150
300
4.8
600
9.6
1,200
2,400
4,800
9,600
19,200
31,250
38,400
19.2
38.4
76.8
153.6
307.2
500.0
614.4
(c) Generation of serial clock from system clock in 3-wire serial I/O mode
The serial clock is generated by dividing the system clock. The serial clock frequency is estimated by
using the following expression. BRGC20 does not need to be set when an external serial clock is input to
the SCK20 pin.
fX
2n + 1
Serial clock frequency =
[Hz]
fX: System clock oscillation frequency
n: Value determined by the settings of TPS200 to TPS203 as shown in Figure 13-6 (1 ≤ n ≤ 8)
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13.4 Operation of Serial Interface 20
Serial interface 20 provides the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
13.4.1 Operation stop mode
In the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. The
P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O port pins.
(1) Register setting
Operation stop mode is set by serial operating mode register 20 (CSIM20) and asynchronous serial interface
mode register 20 (ASIM20).
(a) Serial operating mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
<7>
6
5
0
4
0
3
2
1
0
Address
FF72H
After reset
00H
R/W
R/W
Symbol
CSIM20 CSIE20SSE20
DAP20 DIR20 CSCK20 CKP20
CSIE20
Operation control in 3-wire serial I/O mode
0
1
Operation disabled
Operation enabled
Caution Be sure to clear bits 4 and 5 to 0.
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20
TXE20
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE20
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
Caution Be sure to clear bits 0 and 1 to 0.
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13.4.2 Asynchronous serial interface (UART) mode
In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is
possible.
This device incorporates a UART-dedicated baud rate generator that enables communication at the desired transfer
rate from many options. In addition, the baud rate can also be defined by dividing the clock input to the ASCK pin.
The UART-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the MIDI
standard.
It is recommended that ceramic/crystal oscillation be used for the system clock in the UART mode. Because the
frequency deviation is large in RC oscillation, if an internal clock is selected as the source clock for the baud rate
generator, there may be problems in transmit/receive operations.
(1) Register setting
The UART mode is set by serial operating mode register 20 (CSIM20), asynchronous serial interface mode
register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), baud rate generator control
register 20 (BRGC20), port mode register 2 (PM2), and port 2 (P2).
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CHAPTER 13 SERIAL INTERFACE 20
(a) Serial operating mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Symbol <7>
6
5
0
4
0
3
2
1
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20 SSE20
DAP20 DIR20 CSCK20 CKP20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
SSE20
Communication status
Function of SS20/P23 pin
Port function
SS20-pin selection
0
1
Not used
Used
Communication enabled
0
1
Communication enabled
Communication disabled
DAP20
3-wire serial I/O mode data phase selection
0
1
Output at falling edge of SCK20
Output at rising edge of SCK20
DIR20
First-bit specification
0
1
MSB
LSB
3-wire serial I/O mode clock selection
CSCK20
External clock pulse input to SCK20 pin
Output of dedicated baud rate generator
0
1
CKP20
3-wire serial I/O mode clock phase selection
0
1
Clock is active low, and SCK20 is high level in the idle state
Clock is active high, and SCK20 is low level in the idle state
Cautions 1. Bits 4 and 5 must be fixed to 0.
2. When UART mode is selected, clear CSIM20 to 00H.
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CHAPTER 13 SERIAL INTERFACE 20
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20
TXE20
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE20
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
PS201 PS200
Parity bit specification
0
0
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (no parity error is generated).
Odd parity
Even parity
1
1
0
1
CL20
Character length specification
0
1
7 bits
8 bits
SL20
Transmit data stop bit length specification
0
1
1 bit
2 bits
Cautions 1. Be sure to clear bits 0 and 1 to 0.
2. Switch operating modes after halting the serial transmit/receive operation.
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CHAPTER 13 SERIAL INTERFACE 20
(c) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIS20 to 00H.
Symbol
ASIS20
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF71H
After reset
00H
R/W
R
PE20 FE20 OVE20
PE20
Parity error flag
0
1
No parity error has occurred.
A parity error has occurred (when the transmission parity and reception parity do not match).
FE20
Framing error flag
No framing error has occurred.
0
1
A framing error has occurred (when no stop bit is detected).Note 1
OVE20
Overrun error flag
0
1
No overrun error has occurred.
An overrun error has occurred.Note 2
(Before data was read from the reception buffer register, the subsequent reception sequence was
completed.)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial
interface mode register 20 (ASIM20), the stop bit detection in the case of reception is performed
with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every
time the data is received an overrun error will occur.
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(d) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
7
6
5
4
3
0
2
0
1
0
0
0
After reset
00H
Address
FF73H
R/W
R/W
Symbol
BRGC20 TPS203 TPS202 TPS201 TPS200
n
TPS203 TPS202 TPS201 TPS200
Selection of source clock for baud rate generator
@ f = 5.0 MHz operation
= 10.0 MHzNote operation @ f
X
X
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/2
5.0 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
1
2
3
4
5
6
7
8
−
/22
/23
/24
/25
/26
/27
/28
External clock input to ASCK20 pin
Setting prohibited
Other than above
Note Expanded-specification products only
Cautions 1. When writing to BRGC20 is performed during a communication operation, the output
of baud rate generator is disrupted and communications cannot be performed
normally. Be sure not to write to BRGC20 during communication operations.
2. Be sure not to select n = 1 when fX > 2.5 MHz because n = 1 exceeds the rating of the
baud rate.
3. Be sure not to select n = 2 when fX > 5.0 MHz because n = 2 exceeds the rating of the
baud rate.
4. When the external input clock is selected, set port mode register 2 (PM2) to input
mode.
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. n: Values specified by the setting in TPS200 to TPS203 (1 ≤ n ≤ 8)
The baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a
signal divided from the clock input from the ASCK20 pin.
(i) Generation of baud rate transmit/receive clock by means of system clock
The transmit/receive clock is generated by dividing the system clock. The baud rate generated from
the system clock is estimated by using the following expression.
fX
n + 1 × 8
[Baud rate] =
[bps]
2
fX: System clock oscillation frequency (ceramic/crystal oscillation)
n: Values in the above table specified by the setting in TPS200 to TPS203 (2 ≤ n ≤ 8)
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Table 13-5. Example of Relationship Between System Clock and Baud Rate
Baud Rate
(bps)
fX = 10.0 MHzNote
fX = 5.0 MHz
fX = 4.9152 MHz
n
BRGC20
Setting
Error
(%)
n
BRGC20
Setting
Error
(%)
n
BRGC20
Setting
Error
(%)
1,200
−
8
7
6
5
4
3
−
1.73
8
7
6
5
4
3
2
70H
60H
50H
40H
30H
20H
10H
1.73
8
7
6
5
4
3
2
70H
60H
50H
40H
30H
20H
10H
0
2,400
70H
60H
50H
40H
30H
20H
4,800
9,600
19,200
38,400
76,800
Note Expanded-specification products only.
Cautions 1. Be sure not to select n = 1 when fX > 2.5 MHz because n = 1 exceeds the rating of the baud rate.
2. Be sure not to select n = 2 when fX > 5.0 MHz because n = 2 exceeds the rating of the baud rate.
(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK20 pin
The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud
rate generated from the clock input from the ASCK20 pin is estimated by using the following
expression.
fASCK
[Baud rate] =
[bps]
16
fASCK: Frequency of clock input to ASCK20 pin
Table 13-6. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps)
75
ASCK20 Pin Input Frequency (kHz)
1.2
2.4
150
300
4.8
600
9.6
1,200
2,400
4,800
9,600
19,200
31,250
38,400
19.2
38.4
76.8
153.6
307.2
500.0
614.4
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CHAPTER 13 SERIAL INTERFACE 20
(2) Communication operation
(a) Data format
The transmit/receive data format is as shown in Figure 13-7. One data frame consists of a start bit,
character bits, parity bit and stop bit(s).
The specification of character bit length, parity selection, and specification of stop bit length for each data
frame is carried out using asynchronous serial interface mode register 20 (ASIM20).
Figure 13-7. Asynchronous Serial Interface Transmit/Receive Data Format
One data frame
Start
bit
Parity
bit
D0 D1 D2 D3 D4 D5 D6 D7
Stop bit
• Start bits .....................
• Character bits..............
• Parity bits.....................
• Stop bits ......................
1 bit
7 bits/8 bits
Even parity/odd parity/0 parity/no parity
1 bit/2 bits
When 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is
always “0”.
The serial transfer rate is selected by baud rate generator control register 20 (BRGC20).
If a serial data receive error occurs, the receive error contents can be determined by reading the status of
asynchronous serial interface status register 20 (ASIS20).
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit
is used on the transmitting side and the receiving side. With even parity and odd parity, a “1” bit (odd
number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
• At transmission
The transmission operation is controlled so that the number of bits with a value of “1” in the transmit
data including parity bit is even. The parity bit value should be as follows.
The number of bits with a value of “1” is an odd number in transmit data:
1
The number of bits with a value of “1” is an even number in transmit data: 0
• At reception
The number of bits with a value of “1” in the receive data including parity bit is counted, and if the
number is odd, a parity error is generated.
(ii) Odd parity
• At transmission
Opposite to even parity, the transmission operation is controlled so that the number of bits with a
value of “1” in the transmit data including parity bit is odd. The parity bit value should be as follows.
The number of bits with a value of “1” is an odd number in transmit data:
0
The number of bits with a value of “1” is an even number in transmit data: 1
• At reception
The number of bits with a value of “1” in the receive data including parity bit is counted, and if the
number is even, a parity error is generated.
(iii) 0 Parity
When transmitting, the parity bit is set to “0” irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error does not occur, irrespective
of whether the parity bit is set to “0” or “1”.
(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is no
parity bit. Since there is no parity bit, a parity error does not occur.
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(c) Transmission
A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start bit,
parity bit and stop bit(s) are added automatically.
When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a
transmission completion interrupt (INTST20) is generated.
Figure 13-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
STOP
TxD20 (Output)
INTST20
D0
D1
D2
D6
D7
Parity
START
(b) Stop bit length: 2
D0
D1
D2
D6
D7
Parity
TxD20 (Output)
STOP
START
INTST20
Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during a transmit
operation. If the ASIM20 register is rewritten during transmission, subsequent
transmission may not be performed (the normal state is restored by RESET input).
It is possible to determine whether transmission is in progress by software by using a
transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set by
INTST20.
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(d) Reception
When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive
operation is enabled and sampling of the RxD20 pin input is performed.
RxD20 pin input sampling is performed using the serial clock specified by BRGC20.
When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time
determined by the specified baud rate has passed, the data sampling start timing signal is output. If the
RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the
3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a
parity bit and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to receive
buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated.
If an error occurs, the receive data in which the error occurred is still transferred to RXB20, and INTSR20
is generated.
If the RXE20 bit is reset (0) during the receive operation, the receive operation is stopped immediately. In
this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are not
changed, and INTSR20 is not generated.
Figure 13-9. Asynchronous Serial Interface Reception Completion Interrupt Timing
STOP
D0
D1
D2
D6
D7
Parity
RxD20 (Input)
INTSR20
START
Caution Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will occur when the next data is received, and the
receive error state will continue indefinitely.
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(e) Receive errors
The following three errors may occur during a receive operation: a parity error, framing error, or overrun
error. The data reception result error flag is set in asynchronous serial interface status register 20
(ASIS20). Receive error causes are shown in Table 13-7.
It is possible to determine what kind of error occurred during reception by reading the contents of ASIS20
in the reception error interrupt servicing (refer to Table 13-7 and Figure 13-10).
The contents of ASIS20 are reset (0) by reading receive buffer register 20 (RXB20) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Table 13-7. Receive Error Causes
Receive Errors
Cause
Transmission-time parity specification and receive data parity do not match
Stop bit not detected
Parity error
Framing error
Overrun error
Reception of next data is completed before data is read from receive register buffer
Figure 13-10. Receive Error Timing
(a) Parity error occurred
STOP
D0
D1
D2
D6
D7
Parity
RxD20 (Input)
START
INTSR20
(b) Framing error or overrun error occurred
STOP
D0
D1
D2
D6
D7
Parity
RxD20 (Input)
INTSR20
START
Cautions 1. The contents of the ASIS20 register are reset (0) by reading receive buffer register 20
(RXB20) or receiving the next data. To ascertain the error contents, read ASIS20
before reading RXB20.
2. Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will occur when the next data is received, and the
receive error state will continue indefinitely.
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(f) Reading receive data
When the reception completion interrupt (INTSR20) occurs, receive data can be read by reading the value
of receive buffer register 20 (RXB20).
To read the receive data stored in receive buffer register 20 (RXB20), read while reception is enabled
(RXE20 = 1).
Remark However, if it is necessary to read receive data after reception has stopped (RXE20 = 0), read
using either of the following methods.
(a) Read after setting RXE20 = 0 after waiting for one cycle or more of the source clock
selected by BRGC20.
(b) Read after bit 2 (DIR20) of serial operating mode register 20 (CSIM20) is set (1).
Program example of (a) (BRGC20 = 00H (source clock = fX/2))
INTRXE:
;<Reception completion interrupt routine>
;2 clocks
NOP
CLR1 RXE20
MOV A, RXB20
;Reception stopped
;Read receive data
Program example of (b)
INTRXE:
;<Reception completion interrupt routine>
;DIR20 flag is set to LSB first
;Reception stopped
SET1 CSIM20.2
CLR1 RXE20
MOV A, RXB20
;Read receive data
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(3) UART mode cautions
(a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before
executing the next transmission.
(b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
reception, receive buffer register 20 (RXB20) and receive completion interrupt 20 (INTSR20) are as
follows.
RxD20 Pin
Parity
RXB20
INTSR20
<1>
<3>
<2>
When RXE20 is set to 0 at the time indicated by <1>, RXB20 holds the previous data and does not generate
INTSR20.
When RXE20 is set to 0 at the time indicated by <2>, RXB20 renews the data and does not generate
INTSR20.
When RXE20 is set to 0 at the time indicated by <3>, RXB20 renews the data and generates INTSR20.
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CHAPTER 13 SERIAL INTERFACE 20
13.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc. that incorporate a
conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series.
Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input
(SI20).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operating mode register 20 (CSIM20), asynchronous
serial interface mode register 20 (ASIM20), baud rate generator control register 20 (BRGC20), port mode
register 2 (PM2), and port 2 (P2).
(a) Serial operating mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Symbol <7>
6
5
0
4
0
3
2
1
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20 SSE20
DAP20 DIR20 CSCK20 CKP20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
SSE20
Communication status
Function of SS20/P23 pin
Port function
SS20-pin selection
0
1
Not used
Used
Communication enabled
0
1
Communication enabled
Communication disabled
DAP20
3-wire serial I/O mode data phase selection
0
1
Output at falling edge of SCK20
Output at rising edge of SCK20
DIR20
First-bit specification
0
1
MSB
LSB
3-wire serial I/O mode clock selection
CSCK20
External clock pulse input to SCK20 pin
Output of dedicated baud rate generator
0
1
CKP20
3-wire serial I/O mode clock phase selection
0
1
Clock is active low, and SCK20 is at high level in the idle state
Clock is active high, and SCK20 is at low level in the idle state
Caution Bits 4 and 5 must be fixed to 0.
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(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20
TXE20
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE20
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
PS201 PS200
Parity bit specification
0
0
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (no parity error is generated).
Odd parity
Even parity
1
1
0
1
CL20
Character length specification
0
1
7 bits
8 bits
SL20
Transmit data stop bit length specification
0
1
1 bit
2 bits
Cautions 1. Be sure to clear bits 0 and 1 to 0.
2. When the 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H.
3. Switching operation modes must be performed after the serial transmit/receive
operation is halted.
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(c) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
7
6
5
4
3
0
2
0
1
0
0
0
After reset
00H
Address
FF73H
R/W
R/W
Symbol
BRGC20 TPS203 TPS202 TPS201 TPS200
n
Selection of source clock for baud rate generator
@ f = 5.0 MHz operation
= 10.0 MHzNote operation @ f
TPS203 TPS202 TPS201 TPS200
X
X
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
5.0 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/2
1
2
3
4
5
6
7
8
/22
/23
/24
/25
/26
/27
/28
Other than above
Setting prohibited
Note Expanded-specification products only
Cautions 1. When writing to BRGC20 is performed during a communication operation, the baud
rate generator output is disrupted and communication cannot be performed normally.
Be sure not to write to BRGC20 during communication operations.
2. Be sure not to select n = 1 when fX > 5.0 MHz in 3-wire serial I/O mode because n = 1
exceeds the rating of the serial clock.
Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation)
2. n: Values specified by TPS200 to TPS203 (1 ≤ n ≤ 8)
If the internal clock is used as the serial clock for the 3-wire serial I/O mode, set the TPS200 to TPS203
bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula.
When the serial clock is input from off-chip, setting BRGC20 is not necessary.
fX
2n + 1
Serial clock frequency =
[Hz]
fX: System clock oscillation frequency (ceramic/crystal oscillation)
n: Values in the above table specified by the setting in TPS200 to TPS203 (1 ≤ n ≤ 8)
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(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.
transmitted/received bit by bit in synchronization with the serial clock.
Data is
The transmit shift register (TXS20/SIO20) and receive shift register (RXS20) shift operations are performed in
synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20 latch and
output from the SO20 pin. Also, receive data input to the SI0 pin is latched in the receive buffer register
(RXB20/SIO20) on the rise of SCK20.
At the end of an 8-bit transfer, the operation of TXS20/SIO20 or RXS20 stops automatically, and an interrupt
request signal (INTCSI20) is generated.
Figure 13-11. 3-Wire Serial I/O Mode Timing (1/7)
(i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)
SIO20
Write
SCK20
SO20
1
2
3
4
5
6
7
8
Note
DO7
DI7
DO6
DI6
DO5
DI5
DO4
DI4
DO3
DI3
DO2
DI2
DO1
DI1
DO0
DI0
SI20
INTCSI20
Note The value of the last bit previously output is output.
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Figure 13-11. 3-Wire Serial I/O Mode Timing (2/7)
(ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)
SIO20
Write
SCK20
SI20
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Note
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Note The value of the last bit previously output is output.
(iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1)
SS20
SIO20
Write
SCK20
SI20
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi-Z
Hi-Z
Note 1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0Note 2
SO20
INTCSI20
Notes 1. The value of the last bit previously output is output.
2. DO0 is output until SS20 rises.
When SS20 is high, SO20 is in a high-impedance state.
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CHAPTER 13 SERIAL INTERFACE 20
Figure 13-11. 3-Wire Serial I/O Mode Timing (3/7)
(iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0)
SIO20
Write
1
2
3
4
5
6
7
8
SCK20
SO20
DO7
DO6
DI6
DO5
DI5
DO4
DI4
DO3
DI3
DO2
DI2
DO1
DI1
DO0
DI0
DI7
SI20
INTCSI20
(v) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
SIO20
Write
1
2
3
4
5
6
7
8
SCK20
SIO20 Write (master)Note
SI20
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Note The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first
bit before the first rising of SCK20.
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CHAPTER 13 SERIAL INTERFACE 20
Figure 13-11. 3-Wire Serial I/O Mode Timing (4/7)
(vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1)
SS20
SIO20
Write
SCK20
1
DI7
2
3
4
5
6
7
8
SIO20 Write (master)Note 1
SI20
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi-Z
Hi-Z
Note 2
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Notes 1. The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the
first bit before the first rising of SCK20.
2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a
high-impedance state.
(vii) Master operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)
SIO20
Write
1
2
DO6
DI6
3
DO5
DI5
4
DO4
DI4
5
DO3
DI3
6
DO2
DI2
7
DO1
DI1
8
DO0
DI0
SCK20
SO20
DO7
DI7
SI20
INTCSI20
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Figure 13-11. 3-Wire Serial I/O Mode Timing (5/7)
(viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)
SIO20
Write
1
2
3
4
5
6
7
8
SCK20
SIO20 Write (master)Note
SI20
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first
bit before the first falling of SCK20.
(ix) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 1)
SS20
SIO20
Write
SCK20
1
2
3
4
5
6
7
8
SIO20 Write (master)Note 1
SI20
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi-Z
Hi-Z
Note 2
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Notes 1. The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the
first bit before the first falling of SCK20.
2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a
high-impedance state.
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Figure 13-11. 3-Wire Serial I/O Mode Timing (6/7)
(x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
SIO20
Write
SCK20
SO20
1
2
3
4
5
6
7
8
Note
DO7
DO6
DO5
DOI4
DI4
DO3
DO2
DO1
DO0
DI7
DI6
DI5
DI3
DI2
DI1
DI0
SI20
INTCSI20
Note The value of the last bit previously output is output.
(xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
SIO20
Write
SCK20
SI20
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Note
DO7
DO6
DO5
DOI4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Note The value of the last bit previously output is output.
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Figure 13-11. 3-Wire Serial I/O Mode Timing (7/7)
(xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1)
SS20
SIO20
Write
SCK20
SI20
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi-Z
Hi-Z
DO0Note 2
Note 1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
SO20
INTCSI20
Notes 1. The value of the last bit previously output is output.
2. DO0 is output until SS20 rises.
When SS20 is high, SO20 is in a high-impedance state.
(3) Transfer start
Serial transfer is started by setting transfer data to the transmit shift register (TXS20/SIO20) when the following
two conditions are satisfied.
• Serial operating mode register 20 (CSIM20) bit 7 (CSIE20) = 1
• Internal serial clock is stopped or SCK20 is a high level after 8-bit serial transfer.
Caution If CSIE20 is set to “1” after data is written to TXS20/SIO20, transfer does not start.
Termination of 8-bit transfer stops the serial transfer automatically and generates an interrupt request signal
(INTCSI20).
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CHAPTER 14 MULTIPLIER
14.1 Multiplier Function
The multiplier has the following function.
• Calculation of 8 bits × 8 bits = 16 bits
14.2 Multiplier Configuration
(1) 16-bit multiplication result storage register 0 (MUL0)
This register stores the 16-bit result of multiplication.
This register holds the result of multiplication after 16 CPU clocks have elapsed.
MUL0 is set with a 16-bit memory manipulation instruction.
RESET input makes this register undefined.
Caution Although this register is manipulated with a 16-bit memory manipulation instruction, it can
also be manipulated with an 8-bit memory manipulation instruction. When using an 8-bit
memory manipulation instruction, however, access the register by means of direct
addressing.
(2) Multiplication data registers A and B (MRA0 and MRB0)
These are 8-bit multiplication data storage registers. The multiplier multiplies the values of MRA0 and MRB0.
MRA0 and MRB0 are set with a 1-bit or 8-bit memory manipulation instructions.
RESET input makes these registers undefined.
Figure 14-1 shows the block diagram of the multiplier.
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Figure 14-1. Block Diagram of Multiplier
Internal bus
Multiplication data
register A (MRA0)
Multiplication data
register B (MRB0)
Counter value
CPU clock
Selector
3-bit counter
Start Clear
3
16-bit
adder
16-bit multiplication result
storage register 0 (Master) (MUL0)
16-bit multiplication result
storage register 0 (Slave)
Reset
MULST0
Multiplier control
register 0 (MULC0)
Internal bus
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14.3 Multiplier Control Register
The multiplier is controlled by the following register.
• Multiplier control register 0 (MULC0)
MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier.
MULC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 14-2. Format of Multiplier Control Register 0
Symbol
MULC0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Address
FFD2H
After reset
00H
R/W
R/W
MULST0
MULST0
Multiplier operation start control bit
Operating status of multiplier
Operation stopped
Operation in progress
0
1
Stop operation after resetting counter to 0.
Enable operation
Caution Be sure to clear bits 1 to 7 to 0.
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14.4 Multiplier Operation
The multiplier of the µPD789104A/114A/124A/134A Subseries can execute the calculation of 8 bits × 8 bits = 16
bits. Figure 14-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H.
<1> Counting is started by setting MULST0.
<2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter value is
incremented by one.
<3> If MULST0 is cleared when the counter value is 111B, the operation is stopped. At this time, MUL0 holds the
data.
<4> While MULST0 is low, the counter and slave are cleared.
Figure 14-3. Multiplier Operation Timing
CPU clock
MRA0
MRB0
AA
D3
MULST0
Counter
000B
001B 010B 011B 100B 101B 110B 111B
0154 0000 0000 0AA0 0000 2A80 5500
00AA 01FE 01FE 01FE 0C9E 0C9E 371E
00AA 01FE 01FE 01FE 0C9E 0C9E 371E
000B
00AA
00AA
Selector output
MUL0
(Master)
8C1E
0000
0000
(Slave)
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15.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top
priority over all other interrupt requests.
A standby release signal is generated.
There is one non-maskable interrupt source, which is from the watchdog timer.
(2) Maskable interrupt
These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously
generated, each interrupt has a predetermined priority as shown in Table 15-1.
A standby release signal is generated.
There are nine maskable interrupt sources: three external interrupts and six internal interrupts.
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15.2 Interrupt Sources and Configuration
There are total of 10 non-maskable and maskable interrupt sources (refer to Table 15-1).
Table 15-1. Interrupt Source List
Interrupt Type PriorityNote 1
Interrupt Source
Trigger
Internal/
External
Vector
Table
Basic
Configuration
TypeNote 2
Name
Address
Non-
−
INTWDT
Watchdog timer overflow (watchdog timer mode 1
selected)
Internal
0004H
(A)
(B)
(C)
maskable
Maskable
0
INTWDT
Watchdog timer overflow (interval timer mode
selected)
1
2
3
4
INTP0
Pin input edge detection
External
Internal
0006H
0008H
000AH
000CH
INTP1
INTP2
INTSR20
INTCSI20
INTST20
INTTM80
End of serial interface 20 UART reception
End of serial interface 20 3-wire transfer
End of serial interface 20 UART transmission
(B)
5
6
000EH
0010H
Generation of 8-bit timer/event counter 80 match
signal
7
8
INTTM20
INTAD0
Generation of 16-bit timer 20 match signal
A/D conversion completion signal
0012H
0014H
Notes 1. Priority is the priority applicable when two or more maskable interrupts are simultaneously generated. 0
is the highest priority and 8 is the lowest priority.
2. Basic configuration types A to C correspond to A to C in Figure 15-1.
Remark As the interrupt source of the watchdog timer (INTWDT), either a non-maskable interrupt or a maskable
interrupt (internal) can be selected.
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Figure 15-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Vector table
address generator
Interrupt request
Standby release signal
(B) Internal maskable interrupt
Internal bus
IE
MK
Vector table
address generator
Interrupt request
IF
Standby release signal
(C) External maskable interrupt
Internal bus
External interrupt mode
register (INTM0)
MK
IE
Vector table
address generator
Interrupt
request
Edge
detector
IF
Standby
release signal
IF:
Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
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15.3 Interrupt Function Control Registers
The following four registers are used to control the interrupt functions.
• Interrupt request flag registers (IF0, IF1)
• Interrupt mask flag registers (MK0, MK1)
• External interrupt mode register (INTM0)
• Program status word (PSW)
Table 15-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt
requests.
Table 15-2. Flags Corresponding to Interrupt Request Signals
Interrupt Request Signal Name
Interrupt Request Flag
Interrupt Mask Flag
INTWDT
INTP0
TMIF4
PIF0
TMMK4
PMK0
INTP1
PIF1
PMK1
INTP2
PIF2
PMK2
INTSR20/INTCSI20
INTST20
INTTM80
INTTM20
INTAD0
SRIF20
STIF20
TMIF80
TMIF20
ADIF0
SRMK20
STMK20
TMMK80
TMMK20
ADMK0
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(1) Interrupt request flag registers (IF0, IF1)
The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is
executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon RESET input.
IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 15-2. Format of Interrupt Request Flag Register
<7> <6> <5> <4> <3> <2> <1> <0>
Address
FFE0H
After reset
00H
R/W
R/W
Symbol
IF0 TMIF20TMIF80 STIF20 SRIF20 PIF2 PIF1 PIF0 TMIF4
7
0
6
0
5
0
4
0
3
0
2
0
1
0
<0>
Address
FFE1H
After reset
00H
R/W
R/W
Symbol
IF1
ADIF0
Interrupt request flag
××IF×
0
1
No interrupt request signal is generated
Interrupt request signal is generated; interrupt request state
Cautions 1. TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer. If
watchdog timer mode 1 and 2 are used, set the TMIF4 flag to 0.
2. Because port 2 has an alternate function as the external interrupt input, when the output
level is changed by specifying the output mode of the port function, an interrupt request
flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output
mode.
3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and
the interrupt routine is entered.
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(2) Interrupt mask flag registers (MK0, MK1)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing.
MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 15-3. Format of Interrupt Mask Flag Register
<7> <6> <5> <4> <3> <2> <1> <0>
R/W
R/W
Address
FFE4H
After reset
FFH
Symbol
MK0
TMMK20 TMMK80 STMK20 SRMK20 PMK2 PMK1 PMK0 TMMK4
7
1
6
1
5
1
4
1
3
1
2
1
1
1
<0>
R/W
R/W
Address
FFE5H
After reset
FFH
Symbol
MK1
ADMK0
××MK×
Interrupt servicing control
0
1
Interrupt servicing enabled
Interrupt servicing disabled
Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1 and
2, its value becomes undefined.
2. Because port 2 has an alternate function as the external interrupt input, when the output
level is changed by specifying the output mode of the port function, an interrupt request
flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output
mode.
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(3) External interrupt mode register 0 (INTM0)
This register is used to set the valid edge of INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 to 00H.
Figure 15-4. Format of External Interrupt Mode Register 0
Address
FFECH
7
6
5
4
3
2
1
0
0
0
After reset
00H
R/W
R/W
Symbol
INTM0
ES21 ES20 ES11 ES10 ES01 ES00
ES21 ES20
INTP2 valid edge selection
INTP1 valid edge selection
INTP0 valid edge selection
Falling edge
0
0
1
1
0
1
0
1
Rising edge
Setting prohibited
Both rising and falling edges
ES11 ES10
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES00
ES01
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Cautions 1. Be sure to clear bits 0 and 1 to 0.
2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will enable
interrupts.
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(4) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for
interrupt requests. The IE flag used to set maskable interrupt enable/disable is mapped to the PSW.
This register can be read/written in 8-bit units and can carry out operations using bit manipulation and
dedicated instructions (EI, DI). When a vectored interrupt request is acknowledged, the PSW is automatically
saved into a stack, and the IE flag is reset to 0. It is restored from the stack by the RETI and POP PSW
instructions.
RESET input sets the PSW to 02H.
Figure 15-5. Program Status Word Configuration
After reset
02H
7
6
Z
5
0
4
3
0
2
0
1
1
0
Symbol
PSW
IE
AC
CY
Used when normal instruction is executed
IE
0
Interrupt acknowledgment enable/disable
Disabled
Enabled
1
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15.4 Interrupt Servicing Operation
15.4.1 Non-maskable interrupt request acknowledgment operation
A non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not
subject to interrupt priority control and takes precedence over all other interrupts.
When a non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the
IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 15-6 shows the flowchart from non-maskable interrupt request generation to acknowledgment. Figure 15-7
shows the timing of non-maskable interrupt request acknowledgment. Figure 15-8 shows the acknowledgment
operation if multiple non-maskable interrupts are generated.
Caution During non-maskable interrupt servicing program execution, do not input another non-maskable
interrupt request; if it is input, the servicing program will be interrupted and the new interrupt
request will be acknowledged.
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Figure 15-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment
Start
WDTM4 = 1
No
(watchdog timer mode
is selected)
Interval timer
Yes
No
No
WDT
overflows
Yes
WDTM3 = 0
(non-maskable interrupt
is selected)
Reset processing
Yes
Interrupt request is generated
Interrupt servicing is started
WDTM: Watchdog timer mode register
WDT:
Watchdog timer
Figure 15-7. Timing of Non-Maskable Interrupt Request Acknowledgment
Interrupt servicing
program
Save PSW and PC, and
jump to interrupt servicing
CPU processing
TMIF4
Instruction
Instruction
Figure 15-8. Acknowledging Non-Maskable Interrupt Request
Main routine
First interrupt servicing
NMI request
(second)
NMI request
(first)
Second interrupt servicing
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15.4.2 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt
enabled status (when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in
Table 15-3.
Refer to Figures 15-10 and 15-11 for the interrupt request acknowledgment timing.
Table 15-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time
9 clocks
Maximum TimeNote
19 clocks
Note The wait time is maximum when an
interrupt request is generated
immediately before the BT or BF
instruction.
1
fCPU
Remark 1 clock:
(fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the interrupt request assigned the highest priority.
A pending interrupt is acknowledged when the status in which it can be acknowledged is set.
Figure 15-9 shows the algorithm of acknowledging interrupt requests.
When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in
that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to
the PC, and execution branches.
To return from interrupt servicing, use the RETI instruction.
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Figure 15-9. Interrupt Acknowledgment Program Algorithm
Start
No
××IF = 1 ?
Yes (Interrupt request generated)
No
××MK = 0 ?
Yes
Interrupt request pending
Interrupt request pending
No
IE = 1 ?
Yes
Vectored interrupt
servicing
××IF: Interrupt request flag
××MK: Interrupt mask flag
IE:
Flag to control maskable interrupt request acknowledgment (1 = Enable, 0 = Disable)
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Figure 15-10. Interrupt Request Acknowledgment Timing (Example of MOV A,r)
8 clocks
Clock
Save PSW and PC, jump
to interrupt servicing
Interrupt servicing program
CPU
MOV A,r
Interrupt
If an interrupt request flag (××IF) is set before instruction clock n (n = 4 to 10) under execution becomes n − 1, the
interrupt is acknowledged after the instruction under execution is complete. Figure 15-10 shows an example of the
interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is
executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment
processing is performed after the MOV A,r instruction is completed.
Figure 15-11. Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated at
Last Clock During Instruction Execution)
8 clocks
Clock
Interrupt
servicing
program
Save PSW and PC, jump
to interrupt servicing
CPU
NOP
MOV A,r
Interrupt
If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing
starts after the next instruction is executed.
Figure 15-11 shows an example of the interrupt acknowledgment timing for an interrupt request flag that is set at
the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is
executed, and then the interrupt acknowledgment processing is performed.
Caution Interrupt requests are held pending while the interrupt request flag register (IF0, IF1) or the
interrupt mask flag register (MK0, MK1) is being accessed.
15.4.3 Multiple interrupt servicing
Multiple interrupt servicing, in which an interrupt is acknowledged while another interrupt is being serviced, can be
executed by priority. When the priority is controlled by the default priority and two or more interrupts are generated at
the same time, interrupt servicing is performed according to the priority assigned to each interrupt request in advance
(refer to Table 15-1).
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Figure 15-12. Example of Multiple Interrupt Servicing
Example 1. Multiple interrupts are acknowledged
INTxx servicing
INTyy servicing
Main processing
IE = 0
IE = 0
EI
EI
INTxx
INTyy
RETI
RETI
During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupt servicing occurs.
The EI instruction is issued before each interrupt request acknowledgment, and the interrupt request acknowledgment
enabled state is set.
Example 2. Multiple interrupt servicing does not occur because interrupts are not enabled
INTxx servicing
INTyy servicing
Main processing
EI
IE = 0
INTyy is held pending
INTyy
RETI
INTxx
IE = 0
RETI
Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request
INTyy is not acknowledged, and a multiple interrupt servicing does not occur. The INTyy request is held pending and
acknowledged after the INTxx servicing is performed.
IE = 0: Interrupt request acknowledgment disabled
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15.4.4 Interrupt request hold
Some instructions may hold the acknowledgment of an instruction request pending until completion of the
execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external
interrupt) is generated during the execution. The following shows such instructions (interrupt request hold
instructions).
• Manipulation instruction for the interrupt request flag registers (IF0, IF1)
• Manipulation instruction for the interrupt mask flag registers (MK0, MK1)
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CHAPTER 16 STANDBY FUNCTION
16.1 Standby Function and Configuration
16.1.1 Standby function
The standby function is used to reduce the power consumption of the system and can be effected in the following
two modes.
(1) HALT mode
This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the
CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption as
much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in this
mode.
The low voltage of the data memory (VDD = 1.8 V) can be held. Therefore, this mode is useful for holding the
contents of the data memory at an extremely low current consumption.
The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent
operations. However, some time is required until the system clock oscillator stabilizes after the STOP mode
has been released. If processing must be resumed immediately by using an interrupt request, therefore, use
the HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode
are all held. In addition, the statuses of the output latches of the I/O ports and output buffers are also retained.
Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then
execute the STOP instruction.
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16.1.2 Standby function control register (µPD789104A, 789114A Subseries)
The wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled by
the oscillation stabilization time select register (OSTS)Note
.
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 215/fX, instead of
217/fX.
Note µPD789104A and 789114A Subseries only.
The µPD789124A and 789134A Subseries do not provide an oscillation stabilization time select register.
The oscillation stabilization time of the µPD789124A and 789134A Subseries is fixed to 27/fCC.
Figure 16-1. Format of Oscillation Stabilization Time Select Register
7
0
6
0
5
0
4
0
3
0
2
1
0
Symbol
OSTS
Address
FFFAH
R/W
R/W
After reset
04H
OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
= 10.0 MHzNote operation
@ f
409
X
@ f
X
= 5.0 MHz operation
212/f
215/f
217/f
X
X
X
0
0
1
0
1
0
0
0
0
µ
s
819
µ
s
3.28 ms
13.1 ms
6.55 ms
26.2 ms
Other than above Setting prohibited
Note Expanded-specification products only
Caution The wait time after the STOP mode is released when using a ceramic/crystal oscillator does not
include the time from STOP mode release to clock oscillation start (“a” in the figure below),
regardless of whether STOP mode was released by RESET input or by interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
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16.2 Operation of Standby Function
16.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operation status in the HALT mode is shown in the following table.
Table 16-1. HALT Mode Operating Status
Item
HALT Mode Operating Status
Clock generator
CPU
System clock can be oscillated.
Clock supply to CPU stops.
Operation stopped
Holds status before setting the HALT mode.
Operable
Port (output latch)
16-bit timer 20
8-bit timer/event counter 80
Watchdog timer
Serial interface 20
A/D converter
Operable
Operable
Operable
Operation stopped
Operation stopped
OperableNote
Multiplier
External interrupt
Note Maskable interrupt that is not masked
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(2) Releasing HALT mode
The HALT mode can be released by the following three sources.
(a) Releasing by unmasked interrupt request
The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is able
to be acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at
the next address is executed.
Figure 16-2. Releasing HALT Mode by Interrupt
HALT
instruction
Wait
Wait
Standby
release signal
Operating
mode
HALT mode
Operating mode
Oscillation
Clock
Remarks 1. The broken lines indicate the case where the interrupt request that has released the standby
mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is performed:
9 to 10 clocks
• When vectored interrupt servicing is not performed: 1 to 2 clocks
(b) Releasing by non-maskable interrupt request
The HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored
interrupt servicing is performed.
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(c) Releasing by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address in
the same manner as an ordinary reset operation, and program execution is started.
Figure 16-3. Releasing HALT Mode by RESET Input
HALT
instruction
WaitNote
RESET
signal
Oscillation
Reset
period
stabilization
wait status
Operating
mode
Operating
mode
HALT mode
Oscillation
Oscillation
stop
Oscillation
Clock
Note In the µPD789104A and 789114A Subseries,
215/fX: 6.55 ms (at fX = 5.0 MHz operation), 3.28 ms (at fX = 10.0 MHz operation)
In the µPD789124A and 789134A Subseries,
27/fCC: 32 µs (at fCC = 4.0 MHz operation)
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
Table 16-2. Operation After Release of HALT Mode
Releasing Source
MK××
IE
0
Operation
Next address instruction is executed
Maskable interrupt request
0
0
1
−
−
1
Interrupt servicing is executed
HALT mode is held
×
Non-maskable interrupt request
RESET input
×
Interrupt servicing is executed
Reset processing
−
×: don’t care
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16.2.2 STOP mode
(1) Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Because the standby mode can be released by an interrupt request signal, the standby mode
is released as soon as it is set if there is an interrupt source whose interrupt request flag is
set and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode is
set immediately after the STOP instruction has been executed, the wait time set by the
oscillation stabilization time select register (OSTS) elapses, and then an operation mode is
set.
The operation status in the STOP mode is shown in the following table.
Table 16-3. STOP Mode Operating Status
Item
STOP Mode Operating Status
System clock oscillation stopped
Clock generator
CPU
Operation stopped
Holds the status before setting the STOP mode
Operation stopped
OperableNote 1
Port (output latch)
16-bit timer 20
8-bit timer/event counter 80
Watchdog timer
Serial interface 20
A/D converter
Operation stopped
OperableNote 2
Operation stopped
Operation stopped
OperableNote 3
Multiplier
External interrupt
Notes 1. Operation is possible only when TI80 is selected as the count clock.
2. Operation is possible in both 3-wire serial I/O and UART modes while an external clock is being
used.
3. Maskable interrupt that is not masked
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(2) Releasing STOP mode
The STOP mode can be released by the following two sources.
(a) Releasing by unmasked interrupt request
The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is able to
be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has
elapsed. If interrupts are disabled, the instruction at the next address is executed.
Figure 16-4. Releasing STOP Mode by Interrupt
WaitNote
(set time by OSTS)
STOP
instruction
Standby
release signal
Oscillation stabilization
wait status
Operating
mode
Operating
mode
STOP mode
Oscillation
stop
Oscillation
Oscillation
Clock
Note OSTS is not provided in the µPD789124A and 789134A Subseries, and the wait time is fixed to
27/fCC.
Remark The broken lines indicate the case where the interrupt request that has released the standby
mode is acknowledged.
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(b) Releasing by RESET input
When the STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 16-5. Releasing STOP Mode by RESET Input
STOP
instruction
WaitNote
RESET
signal
Oscillation
stabilization
wait status
Operating
mode
Reset
period
Operating
mode
STOP mode
Oscillation
Oscillation
stop
Oscillation
Clock
Note In the µPD789104A and 789114A Subseries,
215/fX: 6.55 ms (at fX = 5.0 MHz operation), 3.28 ms (at fX = 10.0 MHz operation)
In the µPD789124A and 789134A Subseries,
27/fCC: 32 µs (at fCC = 4.0 MHz operation)
Remark fX: System clock oscillation frequency (ceramic/crystal oscillation)
fCC: System clock oscillation frequency (RC oscillation)
Table 16-4. Operation After Release of STOP Mode
Releasing Source
MK××
IE
0
Operation
Next address instruction is executed
Maskable interrupt request
0
0
1
−
1
Interrupt servicing is executed
STOP mode is held
×
RESET input
−
Reset processing
×: don’t care
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CHAPTER 17 RESET FUNCTION
The following two operations are available to generate reset signals.
(1) External reset input via RESET pin
(2) Internal reset by program loop time detection with watchdog timer
External and internal resets have no functional differences. In both cases, program execution starts at addresses
0000H and 0001H by reset signal input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
item is set to the status shown in Table 17-1. Each pin is high impedance during reset input or during the oscillation
stabilization time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution is started after the
oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared
after reset, and program execution is started after the oscillation stabilization time has elapsed (refer to Figures 17-2
to 17-4).
Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
Figure 17-1. Block Diagram of Reset Function
RESET
Reset signal
Reset controller
Over-
flow
Interrupt function
Count clock
Watchdog timer
Stop
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CHAPTER 17 RESET FUNCTION
Figure 17-2. Reset Timing by RESET Input
X1, CL1
RESET
Reset period
(oscillation
stops)
Oscillation
stabilization
time wait
During normal
operation
Normal operation
(reset processing)
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
Figure 17-3. Reset Timing by Overflow in Watchdog Timer
X1, CL1
Reset period
(oscillation
continues)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
During normal operation
Overflow in
watchdog timer
Internal
reset signal
Hi-Z
Port pin
Figure 17-4. Reset Timing by RESET Input in STOP Mode
X1, CL1
STOP instruction execution
Stop status
(oscillation
stops)
Reset period
(oscillation
stops)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
During normal operation
RESET
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
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CHAPTER 17 RESET FUNCTION
Table 17-1. Hardware Status After Reset (1/2)
Hardware
Status After Reset
Program counter (PC)Note 1
The contents of reset vector
tables (0000H and 0001H)
are set.
Stack pointer (SP)
Program status word (PSW)
RAM
Undefined
02H
Data memory
General-purpose registers
UndefinedNote 2
UndefinedNote 2
00H
Ports (P0 to P2, P5) (output latch)
Port mode registers (PM0 to PM2, PM5)
Pull-up resistor option register 0 (PU0)
Pull-up resistor option register B2 (PUB2)
Processor clock control register (PCC)
Oscillation stabilization time select register (OSTS)Note 3
FFH
00H
00H
02H
04H
16-bit timer 20
Timer counter (TM20)
0000H
FFFFH
00H
Compare register (CR20)
Mode control register (TMC20)
Capture register (TPC20)
Undefined
00H
8-bit timer/event counter 80
Timer counter (TM80)
Compare register (CR80)
Undefined
00H
Mode control register (TMC80)
Timer clock select register (TCL2)
Mode register (WDTM)
Watchdog timer
A/D converter
00H
00H
Mode register (ADM0)
00H
Input channel specification register (ADS0)
Conversion result register (ADCR0)
Mode register (CSIM20)
00H
Undefined
00H
Serial interface 20
Asynchronous serial interface mode register (ASIM20)
Asynchronous serial interface status register (ASIS20)
Baud rate generator control register (BRGC20)
Transmit shift register (TXS20)
Receive buffer register (RXB20)
00H
00H
00H
FFH
Undefined
Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined.
All other hardware remains unchanged after reset.
2. If the reset signal is input in the standby mode, the status before reset is retained even after reset.
3. µPD789104A, 789114A Subseries only
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Table 17-1. Hardware Status After Reset (2/2)
Hardware
Status After Reset
Undefined
Multiplier
Interrupts
16-bit multiplication result storage register (MUL0)
Data register A (MRA0)
Undefined
Undefined
00H
Data register B (MRB0)
Control register (MULC0)
Request flag register (IF0, IF1)
Mask flag register (MK0, MK1)
External interrupt mode register (INTM0)
00H
FFH
00H
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CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
The µPD78F9116A and 78F9116B are versions with flash memory instead of the internal ROM of the mask ROM
versions in the µPD789104A and 789114A Subseries. The µPD78F9136A and 78F9136B are versions with flash
memory instead of the internal ROM of the mask ROM versions in the µPD789124A and 789134A Subseries. The
differences between the flash memory and the mask ROM versions are shown in Table 18-1.
Table 18-1. Differences Between Flash Memory and Mask ROM Versions
Item
Flash Memory
Mask ROM
µPD78F9116A
µPD78F9116B
µPD789101A
µPD789111A
µPD789102A
µPD789112A
µPD789104A
µPD789114A
µPD78F9136A
µPD78F9136B
µPD789121A
µPD789131A
µPD789122A
µPD789132A
µPD789124A
µPD789134A
Internal
memory
ROM
16 KB
2 KB
4 KB
8 KB
(flash memory)
High-speed RAM
256 bytes
Pull-up resistors
12
16 (software control: 12, mask option specification: 4)
Not provided
(software control only)
VPP pin
Provided
Electrical specifications
Refer to the relevant electrical specifications chapter.
Cautions 1. There are differences in noise immunity and noise radiation between the flash memory
versions and mask ROM versions. When pre-producing an application set with the flash
memory version and then mass-producing it with the mask ROM version, be sure to conduct
sufficient evaluations for the commercial samples (not engineering samples) of the mask
ROM versions.
2. A/D conversion result register 0 (ADCR0) is manipulated by an 8-bit memory manipulation
instruction or a 16-bit memory manipulation instruction, when used as an 8-bit A/D converter
(µPD789104A, 789124A Subseries) or 10-bit A/D converter (µPD789114A, 789134A Subseries),
respectively.
However, if the µPD78F9116A and 78F9116B are used as the flash memory versions of the
µPD789101A, 789102A, and 789104A, ADCR0 can be manipulated by an 8-bit memory
manipulation instruction, providing an object file has been assembled in the µPD789101A,
789102A, 789104A. If the µPD78F9136A and 78F9136B are used as the flash memory versions
of the µPD789121A, 789122A, and 789124A, ADCR0 can be manipulated by an 8-bit memory
manipulation instruction, providing an object file has been assembled in the µPD789121A,
789122A, or 789124A.
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CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
18.1 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL-
PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the
target system (on-board programming). A flash memory writing adapter (program adapter), which is a target board
used exclusively for programming, is also provided.
Remark FL-PR3, FL-PR4, and the program adapter are products of Naito Densei Machida Mfg. Co., Ltd. (TEL
+81-45-475-4191).
Programming using flash memory has the following advantages.
• Software can be modified after the microcontroller is solder-mounted on the target system.
• Distinguishing software facilities low-quantity, varied model production
• Easy data adjustment when starting mass production
18.1.1 Programming environment
The following shows the environment required for µPD78F9116A, 78F9116B, 78F9136A, and 78F9136B flash
memory programming.
When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (Part no. FL-PR4, PG-FP4) is used as a dedicated
flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the
host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1).
For details, refer to the manuals for Flashpro III/Flashpro IV.
Remark USB is supported by Flashpro IV only.
Figure 18-1. Environment for Writing Program to Flash Memory
V
PP
V
DD
SS
RS-232C
USB
V
RESET
Dedicated flash programmer
PD78F9116A, 78F9116B,
µ
78F9136A, 78F9136B
3-wire serial I/O
or UART
Host machine
or pseudo 3-wire
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CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
18.1.2 Communication mode
Use the communication mode shown in Table 18-2 or 18-3 to perform communication between the dedicated flash
programmer and the µPD78F9116A, 78F9116B, 78F9136A, or 78F9136B.
Table 18-2. Communication Mode List (µPD78F9116A, 78F9136A)
Communication
Mode
TYPE SettingNote 1
CPU Clock
Pins UsedNote 2
Number of
VPP Pulses
COMM PORT
SIO ch-0
SIO Clock
100 Hz to
Flash Clock
Multiple Rate
3-wire serial
I/O (SIO3)
Optional
1 to 5 MHzNote 3 1.0
SCK20/ASCK20/P20
SO20/TxD20/P21
SI20/RxD20/P22
0
8
(3-wire, sync.) 1.25 MHzNote 3
UART
UART ch-0
4800 to 76800 OptionalNote 5 4.91 or 5
1.0
TxD20/SO20/P21
RxD20/SI20/P22
(UART0)
bpsNote 3, 4
MHzNote 3
Pseudo 3-wire Port A
(pseudo 3-
100 Hz to 1
MHzNote 3
Optional
1 to 5 MHzNote 3 1.0
P00
P01
P02
12
wire)
Table 18-3. Communication Mode List (µPD78F9116B, 78F9136B)
Communication
Mode
TYPE SettingNote 1
CPU Clock
Pins UsedNote 2
Number of
VPP Pulses
COMM PORT
SIO ch-0
SIO Clock
100 Hz to
Flash Clock
Multiple Rate
3-wire serial
I/O
Optional
1 to 10 MHzNote 3 1.0
SCK20/ASCK20/P20
SO20/TxD20/P21
SI20/RxD20/P22
0
1
8
(3-wire, sync.) 1.25 MHzNote 3
SIO ch-1
P00
P01
P02
(3-wire, sync.)
UART
UART ch-0
4800 to 76800 OptionalNote 5 4.91, 5, or 10
bpsNote 3, 4 MHzNote 3
1.0
TxD20/SO20/P21
RxD20/SI20/P22
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III/Flashpro IV).
2. When the system shifts to the flash memory programming mode, all the pins that are not used for flash
memory programming are in the same status as that immediately after reset. If the external device
connected to each port does not recognize the status of the port immediately after reset, pins require
appropriate processing, such as connecting to VDD or VSS via a resistor.
3. The possible setting range differs depending on the voltage. For details, refer to the relevant electrical
specifications chapter.
4. Because signal wave slew also affects UART communication, in addition to the baud rate error,
thoroughly evaluate the slew.
5. Only for Flashpro IV. However, when using Flashpro III, be sure to select the clock of the resonator on
the board. UART cannot be used with the clock supplied by Flashpro III.
Caution Be sure to select the communication mode according to the number of VPP pulses shown in Table
18-2 or 18-3.
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Figure 18-2. Communication Mode Selection Format
10 V
V
PP
V
DD
1
2
n
V
SS
V
PP pulses
V
DD
RESET
V
SS
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Figure 18-3. Example of Connection with Dedicated Flash Programmer (1/2)
(a) 3-wire serial I/O mode (SIO ch-0)
µ
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
Dedicated flash programmer
VPP1
VDD
V
V
PP
DD, AVDD
RESET
CLKNote 1
SCK
RESET
X1 (P03Note 2
SCK20
SI20
)
SO
SI
SO20
GND
VSS, AVSS
(b) 3-wire serial I/O mode (SIO ch-1) (µPD78F9116B, 78F9136B only)
Dedicated flash programmer
µ
PD78F9116B, 78F9136B
VPP1
VDD
V
PP
VDD, AVDD
RESET
CLKNote 1
SCK
RESET
X1 (P03Note 2
)
P00 (Serial clock)
P02 (Serial input)
P01 (Serial output)
SO
SI
GND
VSS, AVSS
Notes 1. Connect this pin when the system clock is supplied by the dedicated flash programmer. When a
resonator has already been connected to the X1 pin, the CLK pin does not need to be connected.
2. µPD78F9136A, 78F9136B only
Cautions 1. The VDD pin, if already connected to the power supply, must be connected to the VDD pin of
the dedicated flash programmer. Before using the power supply connected to the VDD pin,
supply voltage before starting programming.
2. In the µPD78F9136A and 78F9136B, use the P03 pin as the pin for system clock input from the
dedicated flash programmer.
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Figure 18-3. Example of Connection with Dedicated Flash Programmer (2/2)
(c) UART mode
µ
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
Dedicated flash programmer
VPP1
VDD
V
PP
VDD, AVDD
RESET
CLKNote 1
SO
RESET
X1 (P03Note 2
)
RxD20
SI
TxD20
GND
VSS, AVSS
(d) Pseudo 3-wire mode (µPD78F9116A, 78F9136A only)
Dedicated flash programmer
µ
PD78F9116A, 78F9136A
VPP1
VDD
V
PP
VDD, AVDD
RESET
CLKNote 1
SCK
RESET
X1 (P03Note 2
)
P00 (Serial clock)
P02 (Serial input)
P01 (Serial output)
SO
SI
GND
VSS, AVSS
Notes 1. Connect this pin when the system clock is supplied by the dedicated flash programmer. When a
resonator has already been connected to the X1 pin, the CLK pin does not need to be connected.
2. µPD78F9136A, 78F9136B only
Cautions 1. The VDD pin, if already connected to the power supply, must be connected to the VDD pin of
the dedicated flash programmer. Before using the power supply connected to the VDD pin,
supply voltage before starting programming.
2. In the µPD78F9136A and 78F9136B, use the P03 pin as the pin for system clock input from the
dedicated flash programmer.
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If Flashpro III/Flashpro IV is used as the dedicated flash programmer, the following signals are generated for the
µPD78F9116A, 78F9116B, 78F9136A, and 78F9136B. For details, refer to the manual of Flashpro III/Flashpro IV.
Table 18-4. Pin Connection List
Signal Name
VPP1
I/O
Pin Function
Write voltage
Pin Name
3-Wire Serial I/O
UART
Pseudo 3-Wire
Output
VPP
◎
◎
◎
VPP2
VDD
−
−
−
×
×
×
Note 1
Note 1
Note 1
I/O
VDD voltage generation/
voltage monitoring
VDD/AVDD
◎
◎
◎
GND
CLK
RESET
SI
−
Ground
VSS/AVSS
X1 (P03Note 2
RESET
◎
○
◎
◎
◎
◎
○
◎
◎
◎
○
◎
◎
◎
Output
Output
Input
Output
Output
−
Clock output
Reset signal
Reception signal
Transmit signal
Transfer clock
−
)
SO20/P01/TxD20
SI20/P02/RxD20
SCK20/P00
−
SO
◎
SCK
HS
×
◎
◎
×
×
×
Notes 1. VDD voltage must be supplied before programming is started.
2. µPD78F9136A, 78F9136B only
Remark ◎: Pin must be connected.
○: If the signal is supplied on the target board, pin does not need to be connected.
×: Pin does not need to be connected.
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CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
18.1.3 On-board pin processing
When performing programming on the target system, provide a connector on the target system to connect the
dedicated flash programmer.
An on-board function that allows switching between normal operation mode and flash memory programming mode
may be required in some cases.
<VPP pin>
In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0
V (TYP.) is supplied to the VPP pin, so perform the following.
(1) Connect a pull-down resistor (RVPP = 10 kΩ) to the VPP pin.
(2) Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND.
A VPP pin connection example is shown below.
Figure 18-4. VPP Pin Connection Example
µ
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
Connection pin of dedicated flash programmer
V
PP
Pull-down resistor (RVPP
)
<Serial interface pins>
The following shows the pins used by the serial interface.
<µPD78F9116A, 78F9136A>
Serial Interface
3-wire serial I/O
UART
Pins Used
SCK20, SO20, SI20
TxD20, RxD20
Pseudo 3-wire
P00, P01, P02
<µPD78F9116B, 78F9136B>
Serial Interface
3-wire serial I/O
Pins Used
SCK20, SO20, SI20
P00, P01, P02
UART
TxD20, RxD20
When connecting the dedicated flash programmer to a serial interface pin that is connected to another device on-
board, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with
such connections.
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(1) Signal conflict
If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to
another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or
set the other device to the output high impedance status.
Figure 18-5. Signal Conflict (Input Pin of Serial Interface)
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
µ
Connection pin of
dedicated flash
programmer
Signal conflict
Input pin
Other device
Output pin
In the flash memory programming mode, the signal output by another
device and the signal sent by the dedicated flash programmer conflict;
therefore, isolate the signal of the other device.
(2) Abnormal operation of other device
If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is
connected to another device (input), a signal is output to the device, and this may cause an abnormal
operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the
input signals to the other device are ignored.
Figure 18-6. Abnormal Operation of Other Device
µ
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
µ
If the signal output by the PD78F9116A, 78F9116B, 78F9136A, or
78F9136B affects another device in the flash memory programming mode,
isolate the signals of the other device.
µ
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device in the flash memory programming mode, isolate the signals of the
other device.
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CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
<RESET pin>
If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset
signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal
generator.
If the reset signal is input from the user system in the flash memory programming mode, a normal programming
operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash
programmer.
Figure 18-7. Signal Conflict (RESET Pin)
µ
PD78F9116A, 78F9116B,
78F9136A, 78F9136B
Connection pin of
dedicated flash
programmer
Signal Conflict
RESET
Reset signal generator
Output pin
The signal output by the reset signal generator and the signal output from
the dedicated flash programmer conflict in the flash memory programming
mode, so isolate the signal of the reset signal generator.
<Port pins>
When the flash memory programming mode is set, all the pins other than those that communicate with the flash
programmer are in the same status as immediately after reset.
If the external device does not recognize initial statuses such as the output high impedance status, therefore,
connect the external device to VDD or VSS.
<Oscillation pins>
When using the on-board clock, connect X1 and X2 as required in the normal operation mode.
When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main resonator
on-board, and leave the X2 pin open.
<Power supply>
When using the power supply output of the flash programmer, connect the VDD and VSS pins to VDD and GND of
the flash programmer, respectively.
When using the on-board power supply, connect it as required in the normal operation mode. Because the flash
programmer monitors the voltage, however, VDD of the flash programmer must be connected.
For the other power pins (AVDD and ASS), supply the same power supply as in the normal operation mode.
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CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
18.1.4 Connection when using flash memory writing adapter
The following shows an example of the recommended connection when using the flash memory writing adapter.
Figure 18-8. Example of Flash Memory Writing Adapter Connection
When Using 3-Wire Serial I/O Mode (SIO-ch0)
(a) µPD78F9116A, 78F9116B
VDD (2.7 to 5.5 V)
GND
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
µ
µ
GND
VDD
VDD2 (LVDD)
Flash programmer SI SO SCK CLKOUT RESET VPP RESERVE/HS
interface
(b) µPD78F9136A, 78F9136B
V
DD (2.7 to 5.5 V)
GND
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
µ
µ
GND
VDD
VDD2 (LVDD)
Flash programmer SI SO SCK CLKOUT RESET VPP RESERVE/HS
interface
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CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
Figure 18-9. Example of Flash Memory Writing Adapter Connection
When Using 3-Wire Serial I/O Mode (SIO-ch1)
(a) µPD78F9116B
VDD (2.7 to 5.5 V)
GND
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
µ
GND
VDD
VDD2 (LVDD)
SI SO SCK CLKOUT RESET VPP RESERVE/HS
Flash programmer
interface
(b) µPD78F9136B
VDD (2.7 to 5.5 V)
GND
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
µ
GND
VDD
VDD2 (LVDD)
SI SO SCK CLKOUT RESET VPP RESERVE/HS
Flash programmer
interface
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CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
Figure 18-10. Example of Flash Memory Writing Adapter Connection When Using UART Mode
(a) µPD78F9116A, 78F9116B
V
DD (2.7 to 5.5 V)
GND
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
µ
µ
GND
VDD
VDD2 (LVDD)
Flash programmer
interface
SI SO SCK CLKOUT RESET VPP RESERVE/HS
(b) µPD78F9136A, 78F9136B
V
DD (2.7 to 5.5 V)
GND
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
µ
µ
GND
VDD
VDD2 (LVDD)
Flash programmer
interface
SI SO SCK CLKOUT RESET VPP RESERVE/HS
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CHAPTER 18 µPD78F9116A, 78F9116B, 78F9136A, 78F9136B
Figure 18-11. Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode
(a) µPD78F9116A
VDD (2.7 to 5.5 V)
GND
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
µ
GND
VDD
VDD2 (LVDD)
SI SO SCK CLKOUT RESET VPP RESERVE/HS
Flash programmer
interface
(b) µPD78F9136A
VDD (2.7 to 5.5 V)
GND
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
µ
GND
VDD
VDD2 (LVDD)
SI SO SCK CLKOUT RESET VPP RESERVE/HS
Flash programmer
interface
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CHAPTER 19 MASK OPTION (MASK ROM VERSION)
Table 19-1. Selection of Mask Option for Pins
Pin
Mask Option
P50 to P53
On-chip pull-up resistor can be specified in 1-bit units.
For P50 to P53 (port 5), an on-chip pull-up resistor can be specified by the mask option. The mask option is
specified in 1-bit units.
Caution The flash memory versions do not provide the on-chip pull-up resistor function.
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CHAPTER 20 INSTRUCTION SET
This chapter lists the instruction set of the µPD789104A/114A/124A/134A Subseries. For details of the operation
and machine language (instruction code) of each instruction, refer to the 78K/0S Series Instructions User’s Manual
(U11047E).
20.1 Operation
20.1.1 Operand identifiers and description methods
Operands are described in the “Operand” column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specification
• !: Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For the operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 20-1. Operand Identifiers and Description Methods
Identifier
Description Method
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
r
rp
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol
sfr
saddr
FE20H to FF1FH Immediate data or labels
saddrp
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark Refer to Table 4-3 Special-Function Register List for the symbols of the special-function registers.
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CHAPTER 20 INSTRUCTION SET
20.1.2 Description of “operation” column
A:
A register; 8-bit accumulator
X register
X:
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
PSW:
CY:
AC:
Z:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
Program status word
Carry flag
Auxiliary carry flag
Zero flag
IE:
Interrupt request enable flag
NMIS: Flag indicating non-maskable interrupt servicing in progress
( ): Memory contents indicated by address or register contents in parentheses
×H, ×L: Higher 8 bits and lower 8 bits of 16-bit register
∧:
∨:
Logical product (AND)
Logical sum (OR)
∀:
Exclusive logical sum (exclusive OR)
Inverted data
:
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
20.1.3 Description of “flag operation” column
(Blank): Unchanged
0:
1:
×:
R:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is restored
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CHAPTER 20 INSTRUCTION SET
20.2 Operation List
Mnemonic
MOV
Operands
Bytes Clocks
Operation
Flag
Z
AC CY
r, #byte
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
r ← byte
saddr, #byte
sfr, #byte
A, rNote 1
(saddr) ← byte
sfr ← byte
A ← r
r, ANote 1
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
×
×
×
×
×
×
[DE], A
A, [HL]
[HL], A
(HL) ← A
A, [HL+byte]
[HL+byte], A
A, X
A ← (HL+byte)
(HL+byte) ← A
A ↔ X
XCH
A, rNote 2
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ sfr
A, [DE]
A ↔ (DE)
A ↔ (HL)
A ↔ (HL+byte)
A, [HL]
A, [HL+byte]
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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CHAPTER 20 INSTRUCTION SET
Mnemonic
MOVW
Operands
Bytes Clocks
Operation
Flag
Z
AC CY
rp, #word
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
rp ← word
AX, saddrp
saddrp, AX
AX, rpNote
rp, AXNote
AX, rpNote
A, #byte
saddr, #byte
A, r
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
rp ← AX
XCHW
ADD
AX ↔ rp
A, CY ← A + byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A, CY ← A + (HL+byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL+byte) + CY
A, CY ← A − byte
ADDC
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
SUB
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, [HL+byte]
A, CY ← A − (HL+byte)
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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CHAPTER 20 INSTRUCTION SET
Mnemonic
SUBC
Operands
Bytes Clocks
Operation
Flag
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL+byte) − CY
A ← A ∧ byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
AND
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
A, saddr
A, !addr16
A, [HL]
A ← A ∧ (saddr)
A ← A ∧ (addr16)
A ← A ∧ (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A ← A ∧ (HL+byte)
A ← A ∨ byte
OR
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A ← A ∨ (HL+byte)
A ← A ∀ byte
XOR
(saddr) ← (saddr) ∀ byte
A ← A ∀ r
A, saddr
A, !addr16
A, [HL]
A ← A ∀ (saddr)
A ← A ∀ (addr16)
A ← A ∀ (HL)
A, [HL+byte]
A ← A ∀ (HL+byte)
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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CHAPTER 20 INSTRUCTION SET
Mnemonic
CMP
Operands
Bytes Clocks
Operation
Flag
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
A, #byte
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
10
6
6
4
6
10
2
2
2
A − byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
(saddr) − byte
A − r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
AX, #word
AX, #word
AX, #word
r
A − (saddr)
A − (addr16)
A − (HL)
A − (HL+byte)
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
ADDW
SUBW
CMPW
INC
r ← r + 1
saddr
r
(saddr) ← (saddr) + 1
r ← r − 1
DEC
saddr
rp
(saddr) ← (saddr) − 1
rp ← rp + 1
INCW
DECW
ROR
rp
rp ← rp − 1
A, 1
(CY, A7 ← A0, Am−1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
(saddr.bit) ← 1
sfr.bit ← 1
×
×
×
×
ROL
A, 1
RORC
ROLC
SET1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
A.bit ← 1
PSW.bit
[HL].bit
saddr.bit
sfr.bit
PSW.bit ← 1
×
×
×
×
×
(HL).bit ← 1
CLR1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit
A.bit ← 0
PSW.bit
[HL].bit
CY
PSW.bit ← 0
×
(HL).bit ← 0
SET1
CLR1
NOT1
CY ← 1
1
0
×
CY
CY ← 0
CY
CY ← CY
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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CHAPTER 20 INSTRUCTION SET
Mnemonic
Operands
Bytes Clocks
Operation
Flag
Z
AC CY
CALL
!addr16
[addr5]
3
1
6
8
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI
PCH ← (SP + 1), PCL ← (SP),
R
R
R
R
R
R
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
PUSH
POP
PSW
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
2
4
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW ← (SP), SP ← SP + 1
rp
PSW
4
rp
6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP ← AX
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
8
6
AX ← SP
6
PC ← addr16
6
PC ← PC + 2 + jdisp8
6
PCH ← A, PCL ← X
BC
$addr16
$addr16
$saddr16
$saddr16
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
BNC
BZ
6
6
BNZ
BT
6
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
10
10
8
10
10
10
8
BF
10
6
DBNZ
C, $addr16
6
saddr, $addr16
8
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
Set HALT Mode
DI
HALT
STOP
Set STOP Mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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CHAPTER 20 INSTRUCTION SET
20.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
#byte
A
r
sfr
saddr
!addr16
MOV
PSW
[DE]
[HL] [HL+byte] $addr16
1
None
1st Operand
A
ADD
MOVNote MOV
XCHNote XCH
ADD
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
XCH
MOV
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROR
ADDC
SUB
SUBC
AND
OR
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROL
ADD
ADDC
SUB
SUBC
AND
OR
RORC
ROLC
ADDC
SUB
SUBC
XOR
CMP
AND
OR
XOR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
CMP
r
MOV
MOV
INC
DEC
B, C
sfr
DBNZ
DBNZ
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
MOV
MOV
[HL]
[HL+byte]
Note Except r = A.
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CHAPTER 20 INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
AX
rpNote
saddrp
MOVW
SP
None
AX
ADDW
SUBW
CMPW
MOVW
XCHW
MOVW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
saddrp
SP
MOVW
MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
1st Operand
$addr16
None
A.bit
BT
BF
SET1
CLR1
sfr.bit
BT
BF
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BT
BF
SET1
CLR1
BT
BF
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
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CHAPTER 20 INSTRUCTION SET
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX
!addr16
[addr5]
CALLT
$addr16
Basic instructions
BR
CALL
BR
BR
BC
BNC
BZ
BNZ
Compound instructions
DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A))
(EXPANDED-SPECIFICATION PRODUCTS)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VI1
Conditions
Ratings
–0.3 to +6.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–10
Unit
V
VDD = AVDD
Input voltage
Pins other than P50 to P53
V
VI2
P50 to P53
With N-ch open drain
V
With an on-chip pull-up resistor
V
Output voltage
VO
IOH
V
Output current, high
Per pin
µPD78910xA, 78911xA
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
Total for all pins
Per pin
–30
µPD78910xA(A),
–7
78911xA(A)
Total for all pins
Per pin
–22
Output current, low
IOL
µPD78910xA, 78911xA
30
Total for all pins
Per pin
160
µPD78910xA(A),
10
78911xA(A)
Total for all pins
120
Operating ambient temperature
Storage temperature
TA
–40 to +85
–65 to +150
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
Ceramic
Oscillation frequency (fX)Note 1
VDD = oscillation voltage
range
1.0
10
MHz
IC0 X1
X2
resonator
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage range
MIN.
4
ms
C1
C2
IC0 X1
X2
Crystal
Oscillation frequency (fX)Note 1
1.0
10
10
30
MHz
ms
resonator
Oscillation stabilization
timeNote 2
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
C1
X1
C2
ms
External
clock
X1 input frequency (fX)Note 1
1.0
45
10
MHz
ns
X2
X1 input high-/low-level
width (tXH, tXL)
VDD = 4.5 to 5.5 V
VDD = 3.0 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
500
500
500
5.0
75
ns
85
ns
X1 input frequency (fX)Note 1
1.0
MHz
X1
X2
X1 input high-/low-level
width (tXH, tXL)
85
500
ns
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscillation wait time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
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Recommended Oscillator Constant
Ceramic resonator (TA = −40 to +85°C)
(µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (Expanded-specification products)
Manufacturer
Part Number
Frequency
(MHz)
Recommended
Oscillation Voltage
Range (VDD)
Remark
Circuit Constant (pF)
C1
C2
MIN.
2.1
MAX.
5.5
Murata Mfg.
Co., Ltd.
CSBLA1M00J58-B0Note
CSBFB1M00J58-R1Note
CSTCC2M00G56-R0
CSTLS2M00G56-B0
CSTCR4M00G53-R0
CSTLS4M00GG53-B0
CSTCR4M19G53-R0
CSTLS4M19GG53-B0
CSTCR4M91G53-R0
CSTLS4M91GG53-B0
CSTCR5M00G53-R0
CSTLS5M00GG53-B0
CSTCR6M00G53-R0
CSTLS6M00GG53-B0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCE8M38G52-R0
CSTLS8M38G53-B0
CSTCE10M0G52-R0
CSTLS10M00G53-B0
1.0
2.0
100
100
Rd = 2.2 kΩ
–
–
1.8
On-chip capacitor
version
4.0
4.194
4.915
5.0
6.0
8.0
8.388
10.0
Note A limiting resistor (Rd = 2.2 kΩ) is required when the CSBLA1M00J58-B0 and CSBFB1M00J58-R1 (1.0
MHz) of Murata Mfg. Co., Ltd. are used as ceramic resonators (see the figure below). A limiting resistor is
not necessary when other recommended resonators are used.
X1
X2
CSBLA1M00J58-B0
CSBFB1M00J58-R1
Rd
C2
C1
Caution This oscillator constant is a reference value based on evaluation under a specific environment
by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the
actual application, apply to the resonator manufacturer for evaluation on the implementation
circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the
µPD78910xA, 78911xA, 78910xA(A), and 78911xA(A) so that the internal operating conditions are
within the specifications of the DC and AC characteristics.
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DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
Output current, high
IOH
Per pin
µPD78910xA, 78911xA
Total for all pins
Per pin
–15
–1
µPD78910xA(A), 78911xA(A)
µPD78910xA, 78911xA
Total for all pins
Per pin
–11
10
Output current, low
Input voltage, high
IOL
Total for all pins
Per pin
80
µPD78910xA(A), 78911xA(A)
3
Total for all pins
60
VIH1
VIH2
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.8VDD
0.9VDD
VDD
VDD
V
P50 to P53 With N-ch open VDD = 2.7 to 5.5 V
12
V
drain
VDD = 1.8 to 5.5 V
12
V
With on-chip
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD
V
pull-up resistor
VDD
V
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
RESET, P20 to P25
VDD
V
VDD
V
X1, X2
VDD = 4.5 to 5.5 V VDD – 0.5
VDD = 1.8 to 5.5 V VDD – 0.1
VDD
V
VDD
V
Input voltage, low
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
0
0.3VDD
0.1VDD
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.4
V
0
V
P50 to P53
0
V
0
V
RESET, P20 to P25
X1, X2
0
V
0
V
0
V
0
0.1
V
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD – 0.5
V
VDD = 1.8 to 5.5 V, IOH = –100 µA
V
Pins other
than P50 to
P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
1.0
V
(µPD78910xA, 78911xA)
VDD = 4.5 to 5.5 V, IOL = 3 mA
V
(µPD78910xA(A), 78911xA(A))
VDD = 1.8 to 5.5 V, IOL = 400 µA
0.5
1.0
V
V
VOL2
P50 to P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
(µPD78910xA, 78911xA)
VDD = 4.5 to 5.5 V, IOL = 3 mA
1.0
0.4
V
V
(µPD78910xA(A), 78911xA(A))
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage current,
high
ILIH1
Pins other than X1, X2,
VI = VDD
µA
or P50 to P53
ILIH2
X1, X2
20
20
µA
µA
ILIH3
P50 to P53 (N-ch open
drain)
VI = 12 V
VI = 0 V
Input leakage current,
low
ILIL1
Pins other than X1, X2,
or P50 to P53
–3
µA
ILIL2
X1, X2
–20
µA
µA
ILIL3
P50 to P53 (N-ch open
drain)
–3Note 1
µA
µA
kΩ
kΩ
mA
mA
Output leakage
current, high
ILOH
ILOL
R1
VO = VDD
3
Output leakage
current, low
VO = 0 V
–3
Software pull-up
resistance
VI = 0 V, for pins other than P50 to P53 or P60 to
P63
50
10
100
30
200
60
Mask option pull-up
resistance
R2
VI = 0 V, P50 to P53
Note 2
IDD1
Power supply
current
10.0 MHz crystal
VDD = 5.0 V ±10%Note 4
VDD = 5.0 V ±10%Note 4
3.2
2.0
8.0
4.7
oscillation operating mode
6.0 MHz crystal oscillation
operating mode
5.0 MHz crystal
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%Note 4
1.8
0.45
0.25
1.5
3.2
0.9
mA
mA
mA
mA
oscillation operating
mode (C1 = C2 = 22 pF)
0.45
3.0
Note 2
IDD2
10.0 MHz crystal
oscillation HALT mode
6.0 MHz crystal
VDD = 5.0 V ±10%Note 4
0.9
1.8
mA
oscillation HALT mode
5.0 MHz crystal
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%
0.8
0.3
1.6
0.6
0.3
10
mA
mA
mA
µA
oscillation HALT mode
(C1 = C2 = 22 pF)
0.15
0.1
Note 2
IDD3
STOP mode
µA
VDD = 3.0 V ±10%
0.05
0.05
4.4
5.0
5.0
10.3
µA
VDD = 2.0 V ±10%
Note 3
IDD4
10.0 MHz crystal oscillation
A/D operating mode
VDD = 5.0 V ±10%Note 4
mA
6.0 MHz crystal oscillation
A/D operating mode
VDD = 5.0 V ±10%Note 4
3.2
7.0
mA
5.0 MHz crystal
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
3.0
5.5
3.2
2.7
mA
mA
mA
oscillation A/D operating
mode (C1 = C2 = 22 pF)
1.65
1.25
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
Notes 1. When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5
is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle time after a
read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operation (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.2
0.33
0.4
1.6
0.1
1.8
0
TYP.
MAX.
Unit
TCY
VDD = 4.5 to 5.5 V
VDD = 3.0 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
INTP0 to INTP2
8
8
8
8
µs
µs
(minimum instruction
execution time)
µs
µs
TI80 input high-/low-
level width
tTIH,
µs
tTIL
µs
MHz
kHz
TI80 input frequency
fTI
4
0
275
Interrupt input high-
/low-level width
tINTH,
10
µs
µs
µs
tINTL
RESET low-level
width
tRSL
10
10
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY1
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
tKCY1/2 – 50
tKCY1/2 – 150
150
SCK20 high-/low-
level width
tKH1,
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
(to SCK20↑)
500
SI20 hold time
400
(from SCK20↑)
600
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
time from SCK20↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY2
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK20 high-/low-
level width
tKH2,
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
time from SCK20↓
0
1000
120
ns
ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
400
240
800
ns
ns
ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SS20 setup time
tSSK2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
100
150
400
ns
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V
600
ns
Note R and C are the load resistance and load capacitance of the SO output line.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
78125
19531
Unit
bps
bps
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
400
ns
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
1600
ns
Transfer rate
39063
9766
1
bps
bps
µs
ASCK20 rise/fall time
tR,
tF
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.8VDD
0.2VDD
Measurement points
0.2VDD
Clock Timing
1/f
X
t
XL
t
XH
V
IH4 (MIN.)
X1 input
V
IL4 (MAX.)
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
8-Bit A/D Converter Characteristics (µPD78910xA, 78910xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
Bits
%FSR
%FSR
µs
Overall errorNotes 1, 2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
±0.4
±0.8
±0.6
±1.2
100
100
100
AVDD
Conversion time
tCONV
12
14
28
0
µs
µs
Analog input
voltage
VIAN
V
Notes 1. Excludes quantization error (±0.2%).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (µPD78911xA, 78911xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1, 2
Conversion time
4.5 V ≤ VDD ≤ 5.5 V
±0.2
±0.4
±0.8
±0.4
±0.6
±1.2
100
%FSR
%FSR
%FSR
µs
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
tCONV
12
14
28
100
µs
100
µs
Zero-scale errorNotes 1, 2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
Full-scale errorNotes 1, 2
Integral linearity
errorNote 1
ILE
LSB
LSB
Differential linearity
errorNote 1
DLE
VIAN
LSB
LSB
LSB
Analog input voltage
0
V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (EXPANDED-SPECIFICATION PRODUCTS)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
tWAIT
Release by RESET
Release by interrupt request
215/fX
s
s
stabilization wait
timeNote 1
Note 2
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark fX: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
270
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A))
(CONVENTIONAL-SPECIFICATION PRODUCTS)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VI1
Conditions
Ratings
–0.3 to +6.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–10
Unit
V
VDD = AVDD
Input voltage
Pins other than P50 to P53
V
VI2
P50 to P53
With N-ch open drain
V
With an on-chip pull-up resistor
V
Output voltage
VO
IOH
V
Output current, high
Per pin
µPD78910xA, 78911xA
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
Total for all pins
Per pin
–30
µPD78910xA(A),
–7
78911xA(A)
Total for all pins
Per pin
–22
Output current, low
IOL
µPD78910xA, 78911xA
30
Total for all pins
Per pin
160
µPD78910xA(A),
10
78911xA(A)
Total for all pins
120
Operating ambient temperature
Storage temperature
TA
–40 to +85
–65 to +150
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
Ceramic
Oscillation frequency (fX)Note 1
VDD = oscillation voltage
range
1.0
5.0
MHz
IC0 X1
X2
resonator
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage range
MIN.
4
ms
C1
C2
IC0 X1
X2
Crystal
Oscillation frequency (fX)Note 1
1.0
5.0
10
30
MHz
ms
resonator
Oscillation stabilization
timeNote 2
VDD = 4.5 to 5.5 V
C1
X1
C2
V
DD = 1.8 to 5.5 V
Note 1
)
External
clock
X1 input frequency (f
X
1.0
85
5.0
MHz
ns
X2
X1 input high-/low-level
width (tXH, tXL)
500
X1 input frequency (fX)Note 1
VDD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
X1
X2
X1 input high-/low-level
width (tXH, tXL)
500
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscillation wait time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS
.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
Recommended Oscillator Constant
Ceramic resonator (TA = −40 to +85°C)
(µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (Conventional-specification products)
Manufacturer
Part Number
Frequency
(MHz)
Recommended
Oscillation Voltage
Range (VDD)
Remark
Circuit Constant (pF)
C1
C2
MIN.
2.1
MAX.
5.5
Murata Mfg.
Co., Ltd.
CSBLA1M00J58-B0Note
CSBFB1M00J58-R1Note
CSTCC2M00G56-R0
CSTLS2M00G56-B0
CSTCR4M00G53-R0
CSTLS4M00GG53-B0
CSTCR4M19G53-R0
CSTLS4M19GG53-B0
CSTCR4M91G53-R0
CSTLS4M91GG53-B0
CSTCR5M00G53-R0
CSTLS5M00GG53-B0
1.0
2.0
100
100
Rd = 2.2 kΩ
–
–
1.8
On-chip capacitor
version
4.0
4.194
4.915
5.0
Note A limiting resistor (Rd = 2.2 kΩ) is required when the CSBLA1M00J58-B0 and CSBFB1M00J58-R1 (1.0
MHz) of Murata Mfg. Co., Ltd. are used as ceramic resonators (see the figure below). A limiting resistor is
not necessary when other recommended resonators are used.
X1
X2
CSBLA1M00J58-B0
CSBFB1M00J58-R1
Rd
C2
C1
Caution This oscillator constant is a reference value based on evaluation under a specific environment
by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the
actual application, apply to the resonator manufacturer for evaluation on the implementation
circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the
µPD78910xA, 78911xA, 78910xA(A), and 78911xA(A) so that the internal operating conditions are
within the specifications of the DC and AC characteristics.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
Output current, high
IOH
Per pin
µPD78910xA, 78911xA
Total for all pins
Per pin
–15
–1
µPD78910xA(A), 78911xA(A)
µPD78910xA, 78911xA
Total for all pins
Per pin
–11
10
Output current, low
Input voltage, high
IOL
Total for all pins
Per pin
80
µPD78910xA(A), 78911xA(A)
3
Total for all pins
60
VIH1
VIH2
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.8VDD
0.9VDD
VDD
VDD
V
P50 to P53 With N-ch open VDD = 2.7 to 5.5 V
12
V
drain
VDD = 1.8 to 5.5 V
12
V
With on-chip
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD
V
pull-up resistor
VDD
V
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
RESET, P20 to P25
VDD
V
VDD
V
X1, X2
VDD = 4.5 to 5.5 V VDD – 0.5
VDD = 1.8 to 5.5 V VDD – 0.1
VDD
V
VDD
V
Input voltage, low
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
0
0.3VDD
0.1VDD
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.4
V
0
V
P50 to P53
0
V
0
V
RESET, P20 to P25
X1, X2
0
V
0
V
0
V
0
0.1
V
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD – 0.5
V
VDD = 1.8 to 5.5 V, IOH = –100 µA
V
Pins other
than P50 to
P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
1.0
V
(µPD78910xA, 78911xA)
VDD = 4.5 to 5.5 V, IOL = 3 mA
V
(µPD78910xA(A), 78911xA(A))
VDD = 1.8 to 5.5 V, IOL = 400 µA
0.5
1.0
V
V
VOL2
P50 to P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
(µPD78910xA, 78911xA)
VDD = 4.5 to 5.5 V, IOL = 3 mA
1.0
0.4
V
V
(µPD78910xA(A), 78911xA(A))
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage current,
high
ILIH1
Pins other than X1, X2,
VI = VDD
µA
or P50 to P53
ILIH2
X1, X2
20
20
µA
µA
ILIH3
P50 to P53 (N-ch open
drain)
VI = 12 V
VI = 0 V
Input leakage current,
low
ILIL1
Pins other than X1, X2,
or P50 to P53
–3
µA
ILIL2
X1, X2
–20
µA
µA
ILIL3
P50 to P53 (N-ch open
drain)
–3Note 1
µA
µA
kΩ
kΩ
Output leakage
current, high
ILOH
ILOL
R1
VO = VDD
3
Output leakage
current, low
VO = 0 V
–3
Software pull-up
resistance
VI = 0 V, for pins other than P50 to P53 or P60 to
P63
50
10
100
30
200
60
Mask option pull-up
resistance
R2
VI = 0 V, P50 to P53
Note 2
Power supply
current
IDD1
5.0 MHz crystal
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%
1.8
0.45
0.25
0.8
3.2
0.9
0.45
1.6
0.6
0.3
10
mA
mA
mA
mA
mA
mA
µA
oscillation operating
mode (C1 = C2 = 22 pF)
Note 2
IDD2
5.0 MHz crystal
oscillation HALT mode
(C1 = C2 = 22 pF)
0.3
0.15
0.1
Note 2
IDD3
STOP mode
µA
VDD = 3.0 V ±10%
0.05
0.05
3.0
5.0
5.0
5.5
3.2
2.7
µA
VDD = 2.0 V ±10%
Note 3
IDD4
5.0 MHz crystal
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
mA
mA
oscillation A/D operating
mode (C1 = C2 = 22 pF)
1.65
1.25
mA
Notes 1. When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5
is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle time after a
read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operation (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
8
Unit
TCY
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
µs
(minimum instruction
execution time)
1.6
8
µs
TI80 input high-/low-
level width
tTIH,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
INTP0 to INTP2
0.1
1.8
0
µs
µs
tTIL
MHz
kHz
TI80 input frequency
fTI
4
0
275
Interrupt input high-
/low-level width
tINTH,
10
µs
µs
µs
tINTL
RESET low-level
width
tRSL
10
10
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY1
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
tKCY1/2 – 50
tKCY1/2 – 150
150
SCK20 high-/low-
level width
tKH1,
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
(to SCK20↑)
500
SI20 hold time
400
(from SCK20↑)
600
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
time from SCK20↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY2
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK20 high-/low-
level width
tKH2,
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
time from SCK20↓
0
1000
120
ns
ns
SO20 setup time
(for SS20↓ when
SS20 is used)
tKAS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
400
240
800
ns
ns
ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SS20 setup time
tSSK2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
100
150
400
ns
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V
600
ns
Note R and C are the load resistance and load capacitance of the SO output line.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
78125
19531
Unit
bps
bps
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
400
ns
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
1600
ns
Transfer rate
39063
9766
1
bps
bps
µs
ASCK20 rise/fall time
tR,
tF
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.8VDD
0.2VDD
Measurement points
0.2VDD
Clock Timing
1/f
X
t
XL
t
XH
V
IH4 (MIN.)
X1 input
V
IL4 (MAX.)
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
8-Bit A/D Converter Characteristics (µPD78910xA, 78910xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
Bits
%FSR
%FSR
µs
Overall errorNotes 1, 2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
±0.4
±0.8
±0.6
±1.2
100
100
AVDD
Conversion time
tCONV
VIAN
14
28
0
µs
Analog input
voltage
V
Notes 1. Excludes quantization error (±0.2%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (µPD78911xA, 78911xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1, 2
4.5 V ≤ VDD ≤ 5.5 V
±0.2
±0.4
±0.8
±0.4
±0.6
±1.2
100
%FSR
%FSR
%FSR
µs
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
Conversion time
tCONV
14
28
100
µs
Zero-scale errorNotes 1, 2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
Full-scale errorNotes 1, 2
Integral linearity
errorNote 1
ILE
LSB
LSB
Differential linearity
errorNote 1
DLE
VIAN
LSB
LSB
LSB
Analog input voltage
0
V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A)) (CONVENTIONAL-SPECIFICATION PRODUCTS)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
tWAIT
Release by RESET
Release by interrupt request
215/fX
s
s
stabilization wait
timeNote 1
Note 2
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark fX: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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CHAPTER 23 ELECTRICAL SPECIFICATIONS
(µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VI1
Conditions
Ratings
Unit
V
VDD = AVDD
–0.3 to +6.5
Input voltage
Pins other than P50 to P53
–0.3 to VDD + 0.3
V
VI2
P50 to P53
With N-ch open drain
–0.3 to +13
V
With an on-chip pull-up resistor
–0.3 to VDD + 0.3
V
Output voltage
VO
IOH
–0.3 to VDD + 0.3
V
Output current, high
Per pin
µPD78910xA(A1),
–4
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
°C
78911xA(A1)
Total for all pins
Per pin
–14
µPD78910xA(A2),
–2
78911xA(A2)
Total for all pins
Per pin
–6
Output current, low
IOL
µPD78910xA(A1),
5
78911xA(A1)
Total for all pins
Per pin
80
2
µPD78910xA(A2),
78911xA(A2)
Total for all pins
40
Operating ambient temperature
Storage temperature
TA
µPD78910xA(A1), 78911xA(A1)
µPD78910xA(A2), 78911xA(A2)
–40 to +110
–40 to +125
–65 to +150
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
System Clock Oscillator Characteristics
(VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78910xA(A1), 78911xA(A1)),
–40 to +125°C (µPD78910xA(A2), 78911xA(A2)) )
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
Ceramic
Oscillation frequency (fX)Note 1
VDD = oscillation voltage
range
1.0
5.0
MHz
IC0 X1
X2
resonator
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage range
MIN.
4
ms
C1
X1
C2
External
clock
X1 input frequency (fX)Note 1
1.0
85
5.0
MHz
ns
X2
X1 input high-/low-level
width (tXH, tXL)
500
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscillation wait time.
Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. Use a ceramic resonator that is guaranteed by the resonator manufacturer to operate under
the following conditions.
µPD78910xA(A1), 78911xA(A1): TA = 110°C
µPD78910xA(A2), 78911xA(A2): TA = 125°C
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
DC Characteristics (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78910xA(A1), 78911xA(A1)),
–40 to +125°C (µPD78910xA(A2), 78911xA(A2)) ) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
Output current, high
IOH
Per pin
µPD78910xA(A1),
mA
mA
mA
mA
mA
mA
mA
mA
V
78911xA(A1)
Total for all pins
Per pin
–7
µPD78910xA(A2),
–1
78911xA(A2)
Total for all pins
Per pin
–3
Output current, low
Input voltage, high
IOL
µPD78910xA(A1),
1.6
78911xA(A1)
Total for all pins
Per pin
40
µPD78910xA(A2),
1.6
78911xA(A2)
Total for all pins
20
VIH1
VIH2
Pins other than described below
0.7VDD
0.7VDD
0.7VDD
0.8VDD
VDD – 0.1
0
VDD
10
P50 to P53
With N-ch open drain
With on-chip pull-up resistor
V
VDD
VDD
VDD
0.3VDD
0.3VDD
0.2VDD
0.1
V
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
VOH1
VOH2
VOL1
RESET, P20 to P25
X1, X2
V
V
Input voltage, low
Pins other than described below
P50 to P53
V
0
V
RESET, P20 to P25
X1, X2
0
V
0
V
Output voltage, high
Output voltage, low
IOH = –1 mA
VDD – 2.0
VDD – 1.0
V
IOH = –100 µA
V
Pins other than
P50 to P53
IOL = 1.6 mA
IOL = 400 µA
IOL = 1.6 mA
2.0
1.0
1.0
10
V
V
VOL2
P50 to P53
V
Input leakage current,
high
ILIH1
Pins other than X1, X2, or P50
to P53
VI = VDD
µA
ILIH2
ILIH3
ILIL1
X1, X2
20
80
µA
µA
µA
P50 to P53 (N-ch open drain)
VI = 10 V
VI = 0 V
Input leakage current,
low
Pins other than X1, X2, or P50
to P53
–10
ILIL2
ILIL3
ILOH
X1, X2
–20
–10Note
10
µA
µA
µA
P50 to P53 (N-ch open drain)
VO = VDD
Output leakage
current, high
µA
Output leakage
current, low
ILOL
VO = 0 V
–10
Note When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in
input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle time after a read
instruction has been executed to port 5.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
DC Characteristics (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78910xA(A1), 78911xA(A1)),
–40 to +125°C (µPD78910xA(A2), 78911xA(A2)) ) (2/2)
Parameter
Symbol
Conditions
MIN.
50
TYP.
100
MAX.
300
Unit
Software pull-up
resistance
R1
VI = 0 V, for pins other than P50 to P53 or P60 to
P63
kΩ
Mask option pull-up
resistance
R2
VI = 0 V, P50 to P53
10
30
1.8
0.8
100
8.0
5.0
kΩ
mA
mA
Note 1
Power supply
current
IDD1
5.0 MHz crystal oscillation operating mode
(C1 = C2 = 22 pF)Note 3
Note 1
IDD2
5.0 MHz crystal oscillation HALT mode
(C1 = C2 = 22 pF)Note 3
Note 1
µA
IDD3
STOP mode
0.1
3.0
1000
10
Note 2
IDD4
5.0 MHz crystal oscillation A/D operating mode
(C1 = C2 = 22 pF)Note 3
mA
Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
3. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
AC Characteristics
(1) Basic operation (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78910xA(A1), 78911xA(A1)),
–40 to +125°C (µPD78910xA(A2), 78911xA(A2)) )
Parameter
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
8
Unit
Cycle time
TCY
µs
(minimum instruction
execution time)
TI80 input high-/low-
level width
tTIH,
0.1
µs
tTIL
MHz
TI80 input frequency
fTI
0
4
Interrupt input high-
/low-level width
tINTH,
INTP0 to INTP2
10
µs
tINTL
RESET low-level
width
tRSL
10
10
µs
µs
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
(2) Serial interface (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78910xA(A1), 78911xA(A1)),
–40 to +125°C (µPD78910xA(A2), 78911xA(A2)) )
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
MIN.
800
TYP.
MAX.
Unit
ns
SCK20 cycle time
tKCY1
SCK20 high-/low-
level width
tKH1,
tKCY1/2 – 50
ns
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
150
400
0
ns
ns
ns
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ, C = 100 pFNote
250
time from SCK20↓
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
SCK20 cycle time
tKCY2
SCK20 high-/low-
level width
tKH2,
ns
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
tKAS2
100
400
0
ns
ns
ns
ns
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ, C = 100 pFNote
300
120
time from SCK20↓
SO20 setup time
(to SS20↓ when
SS20 is used)
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
240
ns
SS20 setup time
tSSK2
100
400
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
bps
78125
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
Transfer rate
39063
1
bps
ASCK20 rise/fall time
tR,
tF
µs
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
V
IH4 (MIN.)
X1 input
V
IL4 (MAX.)
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
8-Bit A/D Converter Characteristics (µPD78910xA(A1), 78910xA(A2) only)
(AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = –40 to +110°C (µPD78910xA(A1)),
–40 to +125°C (µPD78910xA(A2)) )
Parameter
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
Bits
%FSR
µs
Resolution
Overall errorNotes 1, 2
Conversion time
±0.4
±1.0
28
tCONV
VIAN
14
0
Analog input
voltage
AVDD
V
Notes 1. Excludes quantization error (±0.2%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (µPD78911xA(A1), 78911xA(A2) only)
(AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = –40 to +110°C (µPD78911xA(A1)),
–40 to +125°C (µPD78911xA(A2)) )
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1, 2
±0.4
±0.6
28
%FSR
µs
Conversion time
tCONV
14
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
±0.6
±0.6
±4.5
%FSR
%FSR
LSB
Integral linearity
errorNote 1
ILE
Differential linearity
errorNote 1
DLE
VIAN
±2.0
LSB
V
Analog input voltage
0
AVDD
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = –40 to +110°C (µPD78910xA(A1), 78911xA(A1)), –40 to +125°C (µPD78910xA(A2), 78911xA(A2)) )
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
tWAIT
Release by RESET
Release by interrupt request
215/fX
s
s
stabilization wait
timeNote 1
Note 2
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark fX: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Conditions
Ratings
–0.3 to +6.5
–0.3 to +10.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–10
Unit
V
Supply voltage
VDD, AVDD
VDD = AVDD
VPP
VI1
VI2
VO
IOH
Note
V
Input voltage
Pins other than P50 to P53
V
P50 to P53
With N-ch open drain
V
Output voltage
V
Output current, high
Per pin
µPD78F9116B
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
°C
Total for all pins
Per pin
–30
µPD78F9116B(A)
µPD78F9116B
–7
Total for all pins
Per pin
–22
Output current, low
IOL
30
Total for all pins
Per pin
160
µPD78F9116B(A)
10
Total for all pins
120
Operating ambient temperature
Storage temperature
TA
In normal operation mode
–40 to +85
10 to 40
–40 to +125
During flash memory programming
Tstg
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
a
b
VPP
1.8 V
0 V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
294
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CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
Ceramic
Oscillation frequency (fX)Note 1
VDD = 4.5 to 5.5 V
VDD = 3.0 to 5.5 V
VDD = 1.8 to 5.5 V
1.0
1.0
1.0
10.0
6.0
5.0
4
MHz
MHz
MHz
ms
V
PP X1
X2
resonator
C1
C2
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage range
MIN.
Crystal
Oscillation frequency (fX)Note 1
VDD = 4.5 to 5.5 V
VDD = 3.0 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 3.0 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 3.0 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
1.0
1.0
1.0
10.0
6.0
5.0
10
MHz
MHz
MHz
ms
V
PP X1
C1
X2
resonator
C2
Oscillation stabilization
timeNote 2
30
External
clock
X1 input frequency (fX)Note 1
1.0
1.0
1.0
45
10.0
6.0
5.0
500
500
500
5.0
MHz
MHz
MHz
ns
X2
X1
X1 input high-/low-level
width (tXH, tXL)
75
ns
85
ns
X1 input frequency (fX)Note 1
1.0
MHz
X1
X2
X1 input high-/low-level
width (tXH, tXL)
85
500
ns
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscillation wait time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
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CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
Recommended Oscillator Constant
Ceramic resonator (TA = −40 to +85°C) (µPD78F9116B, 78F9116B(A))
Manufacturer
Part Number
Frequency
(MHz)
Recommended
Oscillation Voltage
Range (VDD)
Remark
Circuit Constant (pF)
C1
100
–
C2
100
–
MIN.
2.0
MAX.
5.5
Murata Mfg.
Co., Ltd.
CSBLA1M00J58-B0Note
CSTCC2M00G56-R0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
CSTCR5M00G53-R0
CSTLS5M00G53-B0
CSTCR6M00G53-R0
CSTLS6M00G53-B0
CSTCE8M38G52-R0
CSTLS8M38G53-B0
CSTCE10M0G52-R0
CSTLS10M0G53-B0
CSTCR4M00G53U-R0
CSTLS4M00G53093-B0
CSTCR5M00G53U-R0
CSTLS5M00G53U-B0
CSTCR6M00G53093-R0
CSTLS6M00G53U-B0
CSTLS8M38G53193-B0
CSTLS10M0G53U-B0
1.0
2.0
4.0
Rd = 2.2 kΩ
On-chip capacitor
version
(Standard
products)
5.0
6.0
2.1
2.2
2.0
2.2
2.1
2.4
1.8
8.388
10.0
4.0
Murata Mfg.
Co., Ltd.
–
–
5.5
On-chip capacitor
version
(Low-voltage
drive type)
5.0
6.0
1.9
2.0
8.0
10.0
Note A limiting resistor (Rd = 2.2 kΩ) is required when the CSBLA1M00J58-B0 (1.0 MHz) of Murata Mfg. Co.,
Ltd. is used as the ceramic resonator (see the figure below). A limiting resistor is not necessary when other
recommended resonators are used.
X1
X2
Rd
C2
CSBLA1M00J58-B0
C1
Caution This oscillator constant is a reference value based on evaluation under a specific environment
by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the
actual application, apply to the resonator manufacturer for evaluation on the implementation
circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the
µPD78F9116B and 78F9116B(A) so that the internal operating conditions are within the
specifications of the DC and AC characteristics.
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CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
Output current, high
IOH
Per pin
µPD78F9116B
Total for all pins
Per pin
–15
–1
µPD78F9116B(A)
µPD78F9116B
Total for all pins
Per pin
–11
10
Output current, low
Input voltage, high
IOL
Total for all pins
Per pin
80
µPD78F9116B(A)
3
Total for all pins
60
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.8VDD
0.9VDD
VDD – 0.5
VDD – 0.1
0
VDD
VDD
12
V
P50 to P53 N-ch open drain VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
V
12
V
RESET, P20 to P25
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD
VDD
VDD
VDD
0.3VDD
0.1VDD
0.3VDD
0.1VDD
V
V
X1, X2
V
V
Input voltage, low
Pins other than described
below
V
0
V
P50 to P53 N-ch open drain VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
V
0
V
VIL3
RESET, P20 to P25
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
0
0.2VDD
0.1VDD
0.4
V
V
V
V
V
V
V
0
VIL4
X1, X2
0
0
0.1
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD – 0.5
VDD = 1.8 to 5.5 V, IOH = –100 µA
Pins other
than P50 to
P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
1.0
(µPD78F9116B)
VDD = 4.5 to 5.5 V, IOL = 3 mA
V
(µPD78F9116B(A))
VDD = 1.8 to 5.5 V, IOL = 400 µA
0.5
1.0
V
V
VOL2
P50 to P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
(µPD78F9116B)
VDD = 4.5 to 5.5 V, IOL = 3 mA
1.0
0.4
V
V
(µPD78F9116B(A))
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Symbol
Conditions
Pins other than X1, X2, or VI = VDD
P50 to P53
MIN.
TYP.
MAX.
3
Unit
Input leakage current,
high
ILIH1
µA
ILIH2
ILIH3
ILIL1
X1, X2
20
20
–3
µA
µA
µA
P50 to P53 (N-ch open drain) VI = 12 V
Input leakage current,
low
Pins other than X1, X2, or
P50 to P53
VI = 0 V
ILIL2
X1, X2
–20
–3Note 1
3
µA
µA
µA
ILIL3
P50 to P53 (N-ch open drain)
VO = VDD
Output leakage current, ILOH
high
Output leakage current, ILOL
low
VO = 0 V
–3
µA
Software pull-up resistance R1
VI = 0 V, for pins other than P50 to P53 or P60 to P63
10.0 MHz crystal oscillation
operating mode
50
100
200
kΩ
Note 2
V
V
DD = 5.0 V
DD = 5.0 V
±
±
10%Note 4
10%Note 4
Power supply current
10.0
20.0
mA
IDD1
6.0 MHz crystal oscillation
operating mode
6.0
12.0
mA
V
V
V
V
DD = 5.0 V
DD = 3.0 V
DD = 2.0 V
DD = 5.0 V
±
±
±
±
10%Note 4
10%Note 5
10%Note 5
10%Note 4
5.0 MHz crystal oscillation
operating mode
(C1 = C2 = 22 pF)
4.0
1.0
0.8
1.2
10.0
2.5
2.0
6.0
mA
mA
mA
mA
Note 2
IDD2
10.0 MHz crystal oscillation
HALT mode
10%Note 4
6.0 MHz crystal oscillation
HALT mode
0.9
2.8
mA
V
DD = 5.0 V
±
10%Note 4
10%Note 5
10%Note 5
5.0 MHz crystal oscillation
HALT mode
(C1 = C2 = 22 pF)
0.6
0.3
2.5
2.0
1.5
30
mA
mA
mA
V
V
V
DD = 5.0 V
DD = 3.0 V
DD = 2.0 V
±
±
±
0.2
Note 2
IDD3
STOP mode
0.1
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±10%
µA
µA
µA
mA
0.05
0.05
11.0
10
10
Note 3
IDD4
10%Note 4
10.0 MHz crystal oscillation
A/D operating mode
22.5
V
DD = 5.0 V
±
6.0 MHz crystal oscillation
A/D operating mode
7.0
14.5
mA
V
DD = 5.0 V
±
10%Note 4
5.0 MHz crystal oscillation
A/D operating mode
(C1 = C2 = 22 pF)
5.0
2.0
1.8
12.5
5.0
mA
mA
mA
V
V
V
DD = 5.0 V
DD = 3.0 V
DD = 2.0 V
±
±
±
10%Note 4
10%Note 5
10%Note 5
4.5
Notes 1. When port 5 is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operation (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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User’s Manual U14643EJ2V0UD
CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
fX
Conditions
MIN.
1.0
TYP.
MAX.
10.0
6.0
Unit
MHz
MHz
MHz
MHz
mA
Operating frequency
VDD = 4.5 to 5.5 V
VDD = 3.0 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
1.0
1.0
5.0
1.0
1.25
21
Write current
(VDD pin)Note
IDDW
IPPW
IDDE
IPPE
When VPP supply voltage = VPP1
(@ 5.0 MHz operation)
Write current
(VPP pin)Note
When VPP supply voltage = VPP1
22.5
21
mA
mA
mA
Erase current
(VDD pin)Note
When VPP supply voltage = VPP1
(@ 5.0 MHz operation)
Erase current
(VPP pin)Note
When VPP supply voltage = VPP1
115
Unit erase time
Total erase time
Rewrite count
ter
0.2
0.2
20
0.2
20
s
tera
s
Times
V
Erase/write are regarded as 1 cycle
In normal operation
20
0
20
VPP supply voltage
VPP0
0.2VDD
10.3
VPP1
During flash memory programming
9.7
10.0
V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
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CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.2
TYP.
MAX.
8
Unit
TCY
VDD = 4.5 to 5.5 V
VDD = 3.0 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
µs
(minimum instruction
execution time)
0.33
0.4
8
8
8
µs
µs
µs
1.6
TI80 input high-/low-
level width
tTIH,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
INTP0 to INTP2
0.1
1.8
0
µs
µs
tTIL
MHz
kHz
TI80 input frequency
fTI
4
0
275
Interrupt input high-
/low-level width
tINTH,
10
µs
µs
µs
tINTL
RESET low-level
width
tRSL
10
10
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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User’s Manual U14643EJ2V0UD
CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY1
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
tKCY1/2 – 50
tKCY1/2 – 150
150
SCK20 high-/low-
level width
tKH1,
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
(to SCK20↑)
500
SI20 hold time
400
(from SCK20↑)
600
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
time from SCK20↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY2
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK20 high-/low-
level width
tKH2,
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
time from SCK20↓
0
1000
120
ns
ns
SO20 setup time
(for SS20↓ when
SS20 is used)
tKAS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
400
240
800
ns
ns
ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SS20 setup time
tSSK2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
100
150
400
ns
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V
600
ns
Note R and C are the load resistance and load capacitance of the SO output line.
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User’s Manual U14643EJ2V0UD
CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
78125
19531
Unit
bps
bps
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
400
ns
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
1600
ns
Transfer rate
39063
9766
1
bps
bps
µs
ASCK20 rise/fall time
tR,
tF
302
User’s Manual U14643EJ2V0UD
CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
V
IH4 (MIN.)
X1 input
V
IL4 (MAX.)
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
303
User’s Manual U14643EJ2V0UD
CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
304
User’s Manual U14643EJ2V0UD
CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
10-Bit A/D Converter Characteristics (TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1, 2
Conversion time
4.5 V ≤ VDD ≤ 5.5 V
±0.2
±0.4
±0.8
±0.4
±0.6
±1.2
100
%FSR
%FSR
%FSR
µs
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
tCONV
12
14
28
100
µs
100
µs
Zero-scale errorNotes 1, 2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
Full-scale errorNotes 1, 2
Integral linearity
errorNote 1
ILE
LSB
LSB
Differential linearity
errorNote 1
DLE
VIAN
LSB
LSB
LSB
Analog input voltage
0
V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
305
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CHAPTER 24 ELECTRICAL SPECIFICATIONS (µPD78F9116B, 78F9116B(A))
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
tWAIT
Release by RESET
Release by interrupt request
215/fX
s
s
stabilization wait
timeNote 1
Note 2
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark fX: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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User’s Manual U14643EJ2V0UD
CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VPP
Conditions
Ratings
–0.3 to +6.5
–0.3 to +10.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–4
Unit
V
VDD = AVDD
Note
V
Input voltage
VI1
Pins other than P50 to P53
V
VI2
P50 to P53
With N-ch open drain
V
Output voltage
VO
V
Output current, high
IOH
Per pin
mA
mA
mA
mA
°C
°C
°C
Total for all pins
–14
Output current, low
IOL
TA
Per pin
5
Total for all pins
80
Operating ambient temperature
Storage temperature
In normal operation mode
During flash memory programming
–40 to +105
10 to 40
Tstg
–40 to +125
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (4.5 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (4.5 V) of the operating
voltage range of VDD (see b in the figure below).
4.5 V
V
DD
0 V
a
b
VPP
4.5 V
0 V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
307
User’s Manual U14643EJ2V0UD
CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
System Clock Oscillator Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
Ceramic
Oscillation frequency (fX)Note 1
VDD = oscillation voltage
range
1.0
5.0
MHz
V
PP X1
X2
resonator
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage range
MIN.
4
ms
C1
C2
External
clock
X1 input frequency (fX)Note 1
1.0
85
5.0
MHz
ns
X1
X2
X1 input high-/low-level
width (tXH, tXL)
500
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscillation wait time.
Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. Use a ceramic resonator that is guaranteed by the resonator manufacturer to operate at TA =
105°C.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
308
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
DC Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
Output current, high
IOH
Per pin
mA
mA
mA
mA
V
Total for all pins
Per pin
–7
Output current, low
Input voltage, high
IOL
1.6
Total for all pins
40
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
VOH1
VOH2
VOL1
Pins other than described below
0.7VDD
0.7VDD
0.8VDD
VDD – 0.1
0
VDD
P50 to P53
With N-ch open drain
10
V
RESET, P20 to P25
X1, X2
VDD
V
VDD
V
Input voltage, low
Pins other than described below
P50 to P53
0.3VDD
0.3VDD
0.2VDD
0.1
V
0
V
RESET, P20 to P25
X1, X2
0
V
0
V
Output voltage, high
Output voltage, low
IOH = –1 mA
VDD – 2.0
VDD – 1.0
V
IOH = –100 µA
V
Pins other than
P50 to P53
IOL = 1.6 mA
IOL = 400 µA
IOL = 1.6 mA
2.0
1.0
1.0
10
V
V
VOL2
P50 to P53
V
Input leakage current,
high
ILIH1
Pins other than X1, X2, or P50
to P53
VI = VDD
µA
ILIH2
ILIH3
ILIL1
X1, X2
20
80
µA
µA
µA
P50 to P53 (N-ch open drain)
VI = 10 V
VI = 0 V
Input leakage current,
low
Pins other than X1, X2, or P50
to P53
–10
ILIL2
ILIL3
ILOH
X1, X2
–20
–10Note
10
µA
µA
µA
P50 to P53 (N-ch open drain)
VO = VDD
Output leakage
current, high
µA
Output leakage
current, low
ILOL
VO = 0 V
–10
Note When port 5 is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle time
after a read instruction has been executed to port 5.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
DC Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V) (2/2)
Parameter
Symbol
Conditions
MIN.
50
TYP.
100
MAX.
300
Unit
Software pull-up
resistance
R1
VI = 0 V, for pins other than P50 to P53 or P60 to
P63
kΩ
Note 1
Power supply
current
IDD1
5.0 MHz crystal oscillation operating mode
(C1 = C2 = 22 pF)Note 3
7.5
3.0
20.0
5.5
mA
mA
Note 1
IDD2
5.0 MHz crystal oscillation HALT mode
(C1 = C2 = 22 pF)Note 3
Note 1
µA
IDD3
STOP mode
1
1000
22.3
Note 2
IDD4
5.0 MHz crystal oscillation A/D operating mode
(C1 = C2 = 22 pF)Note 3
8.7
mA
Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
3. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 4.5 to 5.5 V)
Parameter
Symbol
IDDW
Conditions
MIN.
TYP.
MAX.
21
Unit
mA
Write current
(VDD pin)Note
When VPP supply voltage = VPP1
(@ 5.0 MHz operation)
Write current
(VPP pin)Note
IPPW
IDDE
IPPE
When VPP supply voltage = VPP1
22.5
21
mA
mA
mA
Erase current
(VDD pin)Note
When VPP supply voltage = VPP1
(@ 5.0 MHz operation)
Erase current
(VPP pin)Note
When VPP supply voltage = VPP1
115
Unit erase time
Total erase time
Rewrite count
ter
0.2
0.2
20
0.2
20
s
tera
s
Times
V
Erase/write are regarded as 1 cycle
In normal operation
20
0
20
VPP supply voltage VPP0
VPP1
0.2VDD
10.3
During flash memory programming
9.7
10.0
V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
310
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
AC Characteristics
(1) Basic operation (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
8
Unit
TCY
µs
(minimum instruction
execution time)
TI80 input high-/low-
level width
tTIH,
0.1
µs
tTIL
MHz
TI80 input frequency
fTI
0
4
Interrupt input high-
/low-level width
tINTH,
INTP0 to INTP2
10
µs
tINTL
RESET low-level
width
tRSL
10
10
µs
µs
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
(2) Serial interface (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
MIN.
800
TYP.
MAX.
Unit
ns
SCK20 cycle time
tKCY1
SCK20 high-/low-
level width
tKH1,
tKCY1/2 – 50
ns
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
150
400
0
ns
ns
ns
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ, C = 100 pFNote
250
time from SCK20↓
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
SCK20 cycle time
tKCY2
SCK20 high-/low-
level width
tKH2,
ns
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
tKAS2
100
400
0
ns
ns
ns
ns
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ, C = 100 pFNote
300
120
time from SCK20↓
SO20 setup time
(to SS20↓ when
SS20 is used)
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
240
ns
SS20 setup time
tSSK2
100
400
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
bps
78125
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
Transfer rate
39063
1
bps
ASCK20 rise/fall time
tR,
tF
µs
313
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
V
IH4 (MIN.)
X1 input
V
IL4 (MAX.)
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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User’s Manual U14643EJ2V0UD
CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
10-Bit A/D Converter Characteristics (TA = –40 to +105°C, AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1,2
±0.4
±0.6
28
%FSR
µs
Conversion time
tCONV
14
Zero-scale errorNotes 1,2
Full-scale errorNotes 1,2
±0.6
±0.6
±4.5
%FSR
%FSR
LSB
Integral linearity
errorNote 1
ILE
Differential linearity
errorNote 1
DLE
VIAN
±2.0
LSB
V
Analog input voltage
0
AVDD
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (µPD78F9116B(A1))
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +105°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
tWAIT
Release by RESET
Release by interrupt request
215/fX
s
s
stabilization wait
timeNote 1
Note 2
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark fX: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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User’s Manual U14643EJ2V0UD
CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VPP
Conditions
Ratings
–0.3 to +6.5
–0.3 to +10.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–10
Unit
V
VDD = AVDD
Note
V
Input voltage
VI1
Pins other than P50 to P53
V
VI2
P50 to P53
With N-ch open drain
V
Output voltage
VO
V
Output current, high
IOH
Per pin
mA
mA
mA
mA
°C
°C
°C
Total for all pins
–30
Output current, low
IOL
TA
Per pin
30
Total for all pins
160
Operating ambient temperature
Storage temperature
In normal operation mode
During flash memory programming
–40 to +85
10 to 40
Tstg
–40 to +125
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
a
b
VPP
1.8 V
0 V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
318
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
Ceramic
Oscillation frequency (fX)Note 1
VDD = oscillation voltage
range
1.0
5.0
MHz
V
PP X1
X2
resonator
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage range
MIN.
4
ms
C1
C2
V
PP X1
C1
X2
Crystal
Oscillation frequency (fX)Note 1
1.0
5.0
10
30
MHz
ms
resonator
Oscillation stabilization
timeNote 2
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
C2
External
clock
X1 input frequency (fX)Note 1
1.0
85
5.0
MHz
ns
X2
X1
X1 input high-/low-level
width (tXH, tXL)
500
X1 input frequency (fX)Note 1
VDD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
X1
X2
X1 input high-/low-level
width (tXH, tXL)
500
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use a resonator that
stabilizes oscillation during the oscillation wait time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
319
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
mA
mA
mA
mA
V
Output current, high
IOH
Per pin
Total for all pins
Per pin
–15
10
Output current, low
Input voltage, high
IOL
Total for all pins
80
VIH1
VIH2
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.7VDD
0.9VDD
0.7VDD
VDD
VDD
12
V
P50 to P53 N-ch open drain VDD = 2.7 to 5.5 V
V
VDD = 1.8 to 5.5 V, 0.9VDD
12
V
TA = 25 to 85°C
VIH3
VIH4
VIL1
VIL2
RESET, P20 to P25
X1, X2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.8VDD
0.9VDD
VDD
VDD
V
V
V
V
V
V
V
V
VDD = 4.5 to 5.5 V VDD – 0.5
VDD = 1.8 to 5.5 V VDD – 0.1
VDD
VDD
Input voltage, low
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
0
0
0
0.3VDD
0.1VDD
0.3VDD
0.1VDD
P50 to P53 N-ch open drain VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V,
TA = 25 to 85°C
VIL3
RESET, P20 to P25
X1, X2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
0
0.2VDD
0.1VDD
0.4
V
V
V
V
V
V
V
0
VIL4
0
0
0.1
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD – 0.5
VDD = 1.8 to 5.5 V, IOH = –100 µA
Pins other
than P50 to
P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
VDD = 1.8 to 5.5 V, IOL = 400 µA
VDD = 4.5 to 5.5 V, IOL = 10 mA
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
0.5
1.0
0.4
V
V
V
VOL2
P50 to P53
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage current,
high
ILIH1
Pins other than X1, X2,
VI = VDD
µA
or P50 to P53
ILIH2
X1, X2
20
20
µA
µA
ILIH3
P50 to P53 (N-ch open
drain)
VI = 12 V
VI = 0 V
Input leakage current,
low
ILIL1
Pins other than X1, X2,
or P50 to P53
–3
µA
ILIL2
X1, X2
–20
µA
µA
ILIL3
P50 to P53 (N-ch open
drain)
–3Note 1
µA
µA
kΩ
Output leakage
current, high
ILOH
ILOL
R1
VO = VDD
3
Output leakage
current, low
VO = 0 V
–3
Software pull-up
resistance
VI = 0 V, for pins other than P50 to P53 or P60 to
P63
50
100
200
Note 2
Power supply
current
IDD1
5.0 MHz crystal
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%
5.0
1.9
15.0
4.9
3.0
5.0
2.0
1.5
30
mA
mA
mA
mA
mA
mA
µA
oscillation operating
mode (C1 = C2 = 22 pF)
1.5
Note 2
IDD2
5.0 MHz crystal
2.5
oscillation HALT mode
(C1 = C2 = 22 pF)
1.0
0.75
0.1
Note 2
IDD3
STOP mode
µA
VDD = 3.0 V ±10%
0.05
0.05
6.2
10
µA
VDD = 2.0 V ±10%
10
Note 3
IDD4
5.0 MHz crystal
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
17.3
7.2
5.0
mA
mA
mA
oscillation A/D operating
mode (C1 = C2 = 22 pF)
3.1
2.5
Notes 1. When port 5 is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operation (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
IDDW
Conditions
MIN.
TYP.
MAX.
18
Unit
mA
Write current
(VDD pin)Note
When VPP supply voltage = VPP1
(@ 5.0 MHz operation)
Write current
(VPP pin)Note
IPPW
IDDE
IPPE
When VPP supply voltage = VPP1
22.5
18
mA
mA
mA
Erase current
(VDD pin)Note
When VPP supply voltage = VPP1
(@ 5.0 MHz operation)
Erase current
(VPP pin)Note
When VPP supply voltage = VPP1
115
Unit erase time
Total erase time
Rewrite count
ter
0.5
1
1
20
s
tera
s
Times
V
Erase/write are regarded as 1 cycle
In normal operation
20
0
20
20
VPP supply voltage VPP0
VPP1
0.2VDD
10.3
During flash memory programming
9.7
10.0
V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
8
Unit
TCY
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
µs
(minimum instruction
execution time)
1.6
8
µs
TI80 input high-/low-
level width
tTIH,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
INTP0 to INTP2
0.1
1.8
0
µs
µs
tTIL
MHz
kHz
TI80 input frequency
fTI
4
0
275
Interrupt input high-
/low-level width
tINTH,
10
µs
µs
µs
tINTL
RESET low-level
width
tRSL
10
10
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY1
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
tKCY1/2 – 50
tKCY1/2 – 150
150
SCK20 high-/low-
level width
tKH1,
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
(to SCK20↑)
500
SI20 hold time
400
(from SCK20↑)
600
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
time from SCK20↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY2
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK20 high-/low-
level width
tKH2,
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
time from SCK20↓
0
1000
120
ns
ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
400
240
800
ns
ns
ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SS20 setup time
tSSK2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
100
150
400
ns
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V
600
ns
Note R and C are the load resistance and load capacitance of the SO output line.
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
78125
19531
Unit
bps
bps
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
400
ns
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
1600
ns
Transfer rate
39063
9766
1
bps
bps
µs
ASCK20 rise/fall time
tR,
tF
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
AC Timing Measurement Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/f
X
t
XL
t
XH
V
IH4 (MIN.)
X1 input
V
IL4 (MAX.)
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
10-Bit A/D Converter Characteristics (TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1, 2
4.5 V ≤ VDD ≤ 5.5 V
±0.2
±0.4
±0.8
±0.4
±0.6
±1.2
100
%FSR
%FSR
%FSR
µs
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
Conversion time
tCONV
14
28
100
µs
Zero-scale errorNotes 1, 2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
Full-scale errorNotes 1, 2
Integral linearity
errorNote 1
ILE
LSB
LSB
Differential linearity
errorNote 1
DLE
VIAN
LSB
LSB
LSB
Analog input voltage
0
V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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CHAPTER 26 ELECTRICAL SPECIFICATIONS (µPD78F9116A)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
tWAIT
Release by RESET
Release by interrupt request
215/fX
s
s
stabilization wait
timeNote 1
Note 2
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
2. Selection of 212/fX, 215/fX, or 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register.
Remark fX: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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User’s Manual U14643EJ2V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VI1
Conditions
Ratings
–0.3 to +6.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–10
Unit
V
VDD = AVDD
Input voltage
Pins other than P50 to P53
V
VI2
P50 to P53
With N-ch open drain
V
With an on-chip pull-up resistor
V
Output voltage
VO
IOH
V
Output current, high
Per pin
µPD78912xA, 78913xA
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
Total for all pins
Per pin
–30
µPD78912xA(A),
–7
78913xA(A)
Total for all pins
Per pin
–22
Output current, low
IOL
µPD78912xA, 78913xA
30
Total for all pins
Per pin
160
µPD78912xA(A),
10
78913xA(A)
Total for all pins
120
Operating ambient temperature
Storage temperature
TA
–40 to +85
–65 to +150
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
CL1
RC
Oscillation frequency (fCC)Note
2.0
4.0
MHz
CL2
oscillator
External
clock
CL1 input frequency (fCC)Note
1.0
85
5.0
MHz
ns
CL2
CL1
CL1 input high-/low-level
width (tXH, tXL)
500
CL1 input frequency (fCC)Note
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
CL2
CL1
CL1 input high-/low-level
width (tXH, tXL)
500
OPEN
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
RC Oscillator Frequency Characteristics (TA = –40 to +85°C)
Parameter
Symbol
fCC1
Conditions
MIN.
1.5
TYP.
2.0
2.0
2.0
3.0
3.0
3.0
4.0
4.0
4.0
MAX.
2.5
2.5
2.5
3.5
3.5
3.5
4.7
4.7
4.7
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Oscillator frequency
R = 11.0 kΩ, C = 22 pF VDD = 2.7 to 5.5 V
Target: 2 MHz
fCC2
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
0.5
fCC3
0.5
fCC4
R = 6.8 kΩ, C = 22 pF
2.5
Target: 3 MHz
fCC5
0.75
0.75
3.5
fCC6
fCC7
R = 4.7 kΩ, C = 22 pF
Target: 4 MHz
fCC8
1.0
fCC9
1.0
Remark So that the TYP. spec. is satisfied between 2.0 to 4.0 MHz, set one of the above nine patterns for R and
C.
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
Output current, high
IOH
Per pin
µPD78912xA, 78913xA
Total for all pins
Per pin
–15
–1
µPD78912xA(A), 78913xA(A)
µPD78912xA, 78913xA
Total for all pins
Per pin
–11
10
Output current, low
Input voltage, high
IOL
Total for all pins
Per pin
80
µPD78912xA(A), 78913xA(A)
3
Total for all pins
60
VIH1
VIH2
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.8VDD
0.9VDD
VDD
VDD
V
P50 to P53 With N-ch open VDD = 2.7 to 5.5 V
12
V
drain
VDD = 1.8 to 5.5 V
12
V
With on-chip
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD
V
pull-up resistor
VDD
V
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
RESET, P20 to P25
VDD
V
VDD
V
CL1, CL2
VDD = 4.5 to 5.5 V VDD – 0.5
VDD = 1.8 to 5.5 V VDD – 0.1
VDD
V
VDD
V
Input voltage, low
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
0
0.3VDD
0.1VDD
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.4
V
0
V
P50 to P53
0
V
0
V
RESET, P20 to P25
CL1, CL2
0
V
0
V
0
V
0
0.1
V
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD – 0.5
V
VDD = 1.8 to 5.5 V, IOH = –100 µA
V
Pins other
than P50 to
P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
1.0
V
(µPD78912xA, 78913xA)
VDD = 4.5 to 5.5 V, IOL = 3 mA
V
(µPD78912xA(A), 78913xA(A))
VDD = 1.8 to 5.5 V, IOL = 400 µA
0.5
1.0
V
V
VOL2
P50 to P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
(µPD78912xA, 78913xA)
VDD = 4.5 to 5.5 V, IOL = 3 mA
1.0
0.4
V
V
(µPD78912xA(A), 78913xA(A))
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage current,
high
ILIH1
Pins other than CL1,
VI = VDD
µA
CL2, or P50 to P53
ILIH2
CL1, CL2
20
20
µA
µA
ILIH3
P50 to P53 (N-ch open
drain)
VI = 12 V
VI = 0 V
Input leakage current,
low
ILIL1
Pins other than CL1,
CL2, or P50 to P53
–3
µA
ILIL2
CL1, CL2
–20
µA
µA
ILIL3
P50 to P53 (N-ch open
drain)
–3Note 1
µA
µA
kΩ
kΩ
Output leakage
current, high
ILOH
ILOL
R1
VO = VDD
3
Output leakage
current, low
VO = 0 V
–3
Software pull-up
resistor
VI = 0 V, for pins other than P50 to P53
VI = 0 V, P50 to P53
50
10
100
30
200
60
Mask option pull-up
resistor
R2
Note 2
Power supply
current
IDD1
4.0 MHz RC oscillation
operating mode
VDD = 5.0 V ±10%Note 4
1.8
0.45
0.25
0.8
3.2
0.9
0.45
1.6
0.6
0.3
10
mA
mA
mA
mA
mA
mA
µA
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%
(R = 4.7 kΩ, C = 22 pF)
Note 2
IDD2
4.0 MHz RC oscillation
HALT mode
0.3
(R = 4.7 kΩ, C = 22 pF)
0.15
0.1
Note 2
IDD3
STOP mode
µA
VDD = 3.0 V ±10%
0.05
0.05
3.0
5.0
5.0
5.5
3.2
2.7
µA
VDD = 2.0 V ±10%
Note 3
IDD4
4.0 MHz RC oscillation
A/D operating mode
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
mA
mA
1.65
1.25
(R = 4.7 kΩ, C = 22 pF)
mA
Notes 1. When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5
is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle time after a
read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operation (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
16
Unit
TCY
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
µs
(minimum instruction
execution time)
1.6
16
µs
TI80 input high-/low-
level width
tTIH,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
INTP0 to INTP2
0.1
1.8
0
µs
µs
tTIL
MHz
kHz
TI80 input frequency
fTI
4
0
275
Interrupt input high-
/low-level width
tINTH,
10
µs
µs
µs
tINTL
RESET low-level
width
tRSL
10
10
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY1
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
tKCY1/2 – 50
tKCY1/2 – 150
150
SCK20 high-/low-
level width
tKH1,
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
(to SCK20↑)
500
SI20 hold time
400
(from SCK20↑)
600
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
time from SCK20↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY2
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK20 high-/low-
level width
tKH2,
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
time from SCK20↓
0
1000
120
ns
ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
400
240
800
ns
ns
ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SS20 setup time
tSSK2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
100
150
400
ns
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V
600
ns
Note R and C are the load resistance and load capacitance of the SO output line.
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
78125
19531
Unit
bps
bps
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
400
ns
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
1600
ns
Transfer rate
39063
9766
1
bps
bps
µs
ASCK20 rise/fall time
tR,
tF
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/fCC
t
XL
t
XH
V
IH4 (MIN.)
IL4 (MAX.)
CL1 input
V
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
8-Bit A/D Converter Characteristics (µPD78912xA, 78912xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
Bits
%FSR
%FSR
µs
Overall errorNotes 1, 2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
±0.4
±0.8
±0.6
±1.2
100
100
AVDD
Conversion time
tCONV
VIAN
14
28
0
µs
Analog input
voltage
V
Notes 1. Excludes quantization error (±0.2%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (µPD78913xA, 78913xA(A))
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1, 2
Conversion time
4.5 V ≤ VDD ≤ 5.5 V
±0.2
±0.4
±0.8
±0.4
±0.6
±1.2
100
%FSR
%FSR
%FSR
µs
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
tCONV
14
14
28
100
µs
100
µs
Zero-scale errorNotes 1, 2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
Full-scale errorNotes 1, 2
Integral linearity
errorNote 1
ILE
LSB
LSB
Differential linearity
errorNote 1
DLE
VIAN
LSB
LSB
LSB
Analog input voltage
0
V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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CHAPTER 27 ELECTRICAL SPECIFICATIONS (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A))
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
stabilization wait
timeNote
tWAIT
Release by RESET
Release by interrupt request
27/fCC
27/fCC
s
s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark fCC: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
V
DDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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CHAPTER 28 ELECTRICAL SPECIFICATIONS
(µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VI1
Conditions
Ratings
Unit
V
VDD = AVDD
–0.3 to +6.5
Input voltage
Pins other than P50 to P53
–0.3 to VDD + 0.3
V
VI2
P50 to P53
With N-ch open drain
–0.3 to +13
V
With an on-chip pull-up resistor
–0.3 to VDD + 0.3
V
Output voltage
VO
IOH
–0.3 to VDD + 0.3
V
Output current, high
Per pin
µPD78912xA(A1),
–4
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
°C
78913xA(A1)
Total for all pins
Per pin
–14
µPD78912xA(A2),
–2
78913xA(A2)
Total for all pins
Per pin
–6
Output current, low
IOL
µPD78912xA(A1),
5
78913xA(A1)
Total for all pins
Per pin
80
2
µPD78912xA(A2),
78913xA(A2)
Total for all pins
40
Operating ambient temperature
Storage temperature
TA
µPD78912xA(A1), 78913xA(A1)
µPD78912xA(A2), 78913xA(A2)
–40 to +110
–40 to +125
–65 to +150
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
System Clock Oscillator Characteristics
(VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78912xA(A1), 78913xA(A1)),
–40 to +125°C (µPD78912xA(A2), 78913xA(A2)) )
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
CL1
CL2
RC
Oscillation frequency (fCC)Note
2.0
4.0
MHz
oscillator
External
clock
CL1 input frequency (fCC)Note
1.0
85
5.0
MHz
ns
CL1
CL2
CL1 input high-/low-level
width (tXH, tXL)
500
OPEN
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. Construct the oscillator with R and C devices that are guaranteed to operate under the
following temperature conditions.
µPD78912xA(A1), 78913xA(A1): TA = 110°C
µPD78912xA(A2), 78913xA(A2): TA = 125°C
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CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
DC Characteristics (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78912xA(A1), 78913xA(A1)),
–40 to +125°C (µPD78912xA(A2), 78913xA(A2)) ) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
Output current, high
IOH
Per pin
µPD78912xA(A1),
mA
mA
mA
mA
mA
mA
mA
mA
V
78913xA(A1)
Total for all pins
Per pin
–7
µPD78912xA(A2),
–1
78913xA(A2)
Total for all pins
Per pin
–3
Output current, low
Input voltage, high
IOL
µPD78912xA(A1),
1.6
78913xA(A1)
Total for all pins
Per pin
40
µPD78912xA(A2),
1.6
78913xA(A2)
Total for all pins
20
VIH1
VIH2
Pins other than described below
0.7VDD
0.7VDD
0.7VDD
0.8VDD
VDD – 0.1
0
VDD
10
P50 to P53
With N-ch open drain
With on-chip pull-up resistor
V
VDD
VDD
VDD
0.3VDD
0.3VDD
0.2VDD
0.1
V
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
VOH1
VOH2
VOL1
RESET, P20 to P25
CL1, CL2
V
V
Input voltage, low
Pins other than described below
P50 to P53
V
0
V
RESET, P20 to P25
CL1, CL2
0
V
0
V
Output voltage, high
Output voltage, low
IOH = –1 mA
VDD – 2.0
VDD – 1.0
V
IOH = –100 µA
V
Pins other than
P50 to P53
IOL = 1.6 mA
IOL = 400 µA
IOL = 1.6 mA
2.0
1.0
1.0
10
V
V
VOL2
P50 to P53
V
Input leakage current,
high
ILIH1
Pins other than CL1, CL2, or
P50 to P53
VI = VDD
µA
ILIH2
ILIH3
ILIL1
CL1, CL2
20
80
µA
µA
µA
P50 to P53 (N-ch open drain)
VI = 10 V
VI = 0 V
Input leakage current,
low
Pins other than CL1, CL2, or
P50 to P53
–10
ILIL2
ILIL3
ILOH
CL1, CL2
–20
–10Note
10
µA
µA
µA
P50 to P53 (N-ch open drain)
VO = VDD
Output leakage
current, high
µA
Output leakage
current, low
ILOL
VO = 0 V
–10
Note When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5 is in
input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle time after a read
instruction has been executed to port 5.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
DC Characteristics (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78912xA(A1), 78913xA(A1)),
–40 to +125°C (µPD78912xA(A2), 78913xA(A2)) ) (2/2)
Parameter
Symbol
Conditions
MIN.
50
TYP.
100
MAX.
300
Unit
Software pull-up
resistance
R1
VI = 0 V, for pins other than P50 to P53 or P60 to
P63
kΩ
Mask option pull-up
resistance
R2
VI = 0 V, P50 to P53
10
30
1.8
0.8
100
8.0
5.0
kΩ
mA
mA
Note 1
Power supply
current
IDD1
4.0 MHz crystal oscillation operating mode
(R = 4.7 kΩ, C = 22 pF)Note 3
Note 1
IDD2
4.0 MHz crystal oscillation HALT mode
(R = 4.7 kΩ, C = 22 pF)Note 3
Note 1
µA
IDD3
STOP mode
0.1
3.0
1000
10
Note 2
IDD4
4.0 MHz crystal oscillation A/D operating mode
(R = 4.7 kΩ, C = 22 pF)Note 3
mA
Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
3. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
AC Characteristics
(1) Basic operation (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78912xA(A1), 78913xA(A1)),
–40 to +125°C (µPD78912xA(A2), 78913xA(A2)) )
Parameter
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
8
Unit
Cycle time
TCY
µs
(minimum instruction
execution time)
TI80 input high-/low-
level width
tTIH,
0.1
µs
tTIL
MHz
TI80 input frequency
fTI
0
4
Interrupt input high-
/low-level width
tINTH,
INTP0 to INTP2
10
µs
tINTL
RESET low-level
width
tRSL
10
10
µs
µs
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
(2) Serial interface (VDD = 4.5 to 5.5 V, TA = –40 to +110°C (µPD78912xA(A1), 78913xA(A1)),
–40 to +125°C (µPD78912xA(A2), 78913xA(A2)) )
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
MIN.
800
TYP.
MAX.
Unit
ns
SCK20 cycle time
tKCY1
SCK20 high-/low-
level width
tKH1,
tKCY1/2 – 50
ns
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
150
400
0
ns
ns
ns
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ, C = 100 pFNote
250
time from SCK20↓
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
SCK20 cycle time
tKCY2
SCK20 high-/low-
level width
tKH2,
ns
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
tKAS2
100
400
0
ns
ns
ns
ns
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ, C = 100 pFNote
300
120
time from SCK20↓
SO20 setup time
(to SS20↓ when
SS20 is used)
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
240
ns
SS20 setup time
tSSK2
100
400
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
bps
78125
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CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
Transfer rate
39063
1
bps
ASCK20 rise/fall time
tR,
tF
µs
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CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/fCC
t
XL
t
XH
V
IH4 (MIN.)
CL1 input
V
IL4 (MAX.)
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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User’s Manual U14643EJ2V0UD
CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
8-Bit A/D Converter Characteristics (µPD78912xA(A1), 78912xA(A2) only)
(AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = –40 to +110°C (µPD78912xA(A1)),
–40 to +125°C (µPD78912xA(A2)) )
Parameter
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
Bits
%FSR
µs
Resolution
Overall errorNotes 1, 2
Conversion time
±0.4
±1.0
28
tCONV
VIAN
14
0
Analog input
voltage
AVDD
V
Notes 1. Excludes quantization error (±0.2%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
10-Bit A/D Converter Characteristics (µPD78913xA(A1), 78913xA(A2) only)
(AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V, TA = –40 to +110°C (µPD78913xA(A1)),
–40 to +125°C (µPD78913xA(A2)) )
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1, 2
±0.4
±0.6
28
%FSR
µs
Conversion time
tCONV
14
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
±0.6
±0.6
±4.5
%FSR
%FSR
LSB
Integral linearity
errorNote 1
ILE
Differential linearity
errorNote 1
DLE
VIAN
±2.0
LSB
V
Analog input voltage
0
AVDD
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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User’s Manual U14643EJ2V0UD
CHAPTER 28 ELECTRICAL SPECIFICATIONS (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = –40 to +110°C (µPD78912xA(A1), 78913xA(A1)), –40 to +125°C (µPD78912xA(A2), 78913xA(A2)) )
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
stabilization wait
timeNote
tWAIT
Release by RESET
Release by interrupt request
27/fCC
27/fCC
s
s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark fcc: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Conditions
Ratings
–0.3 to +6.5
–0.3 to +10.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–10
Unit
V
Supply voltage
VDD, AVDD
VDD = AVDD
VPP
VI1
VI2
VO
IOH
Note
V
Input voltage
Pins other than P50 to P53
V
P50 to P53
With N-ch open drain
V
Output voltage
V
Output current, high
Per pin
µPD78F9136B
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
°C
Total for all pins
Per pin
–30
µPD78F9136B(A)
µPD78F9136B
–7
Total for all pins
Per pin
–22
Output current, low
IOL
30
Total for all pins
Per pin
160
µPD78F9136B(A)
10
Total for all pins
120
Operating ambient temperature
Storage temperature
TA
In normal operation mode
–40 to +85
10 to 40
–40 to +125
During flash memory programming
Tstg
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
a
b
VPP
1.8 V
0 V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
352
User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
CL1
RC
Oscillation frequency (fCC)Note
2.0
4.0
MHz
CL2
oscillator
External
clock
CL1 input frequency (fCC)Note
1.0
85
5.0
MHz
ns
CL2
CL1
CL1 input high-/low-level
width (tXH, tXL)
500
CL1 input frequency (fCC)Note
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
CL2
CL1
CL1 input high-/low-level
width (tXH, tXL)
500
OPEN
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
RC Oscillator Frequency Characteristics (TA = –40 to +85°C)
Parameter
Symbol
fCC1
Conditions
MIN.
1.5
TYP.
2.0
2.0
2.0
3.0
3.0
3.0
4.0
4.0
4.0
MAX.
2.5
2.5
2.5
3.5
3.5
3.5
4.7
4.7
4.7
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Oscillator frequency
R = 11.0 kΩ, C = 22 pF VDD = 2.7 to 5.5 V
Target: 2 MHz
fCC2
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
0.5
fCC3
0.5
fCC4
R = 6.8 kΩ, C = 22 pF
2.5
Target: 3 MHz
fCC5
0.75
0.75
3.5
fCC6
fCC7
R = 4.7 kΩ, C = 22 pF
Target: 4 MHz
fCC8
1.0
fCC9
1.0
Remark So that the TYP. spec. is satisfied between 2.0 to 4.0 MHz, set one of the above nine patterns for R and
C.
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CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
Output current, high
IOH
Per pin
µPD78F9136B
Total for all pins
Per pin
–15
–1
µPD78F9136B(A)
µPD78F9136B
Total for all pins
Per pin
–11
10
Output current, low
Input voltage, high
IOL
Total for all pins
Per pin
80
µPD78F9136B(A)
3
Total for all pins
60
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.7VDD
0.9VDD
0.7VDD
0.9VDD
0.8VDD
0.9VDD
VDD
VDD
V
P50 to P53 With N-ch open VDD = 2.7 to 5.5 V
12
V
drain
VDD = 1.8 to 5.5 V
12
V
RESET, P20 to P25
CL1, CL2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD
V
VDD
V
VDD = 4.5 to 5.5 V VDD – 0.5
VDD = 1.8 to 5.5 V VDD – 0.1
VDD
V
VDD
V
Input voltage, low
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
0
0.3VDD
0.1VDD
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.4
V
0
V
P50 to P53
0
V
0
V
RESET, P20 to P25
CL1, CL2
0
V
0
V
0
V
0
0.1
V
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD – 0.5
V
VDD = 1.8 to 5.5 V, IOH = –100 µA
V
Pins other
than P50 to
P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
1.0
V
(µPD78F9136B)
VDD = 4.5 to 5.5 V, IOL = 3 mA
V
(µPD78F9136B(A))
VDD = 1.8 to 5.5 V, IOL = 400 µA
0.5
1.0
V
V
VOL2
P50 to P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
(µPD78F9136B)
VDD = 4.5 to 5.5 V, IOL = 3 mA
1.0
0.4
V
V
(µPD78F9136B(A))
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
354
User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage current,
high
ILIH1
Pins other than CL1,
VI = VDD
µA
CL2, or P50 to P53
ILIH2
CL1, CL2
20
20
µA
µA
ILIH3
P50 to P53 (N-ch open
drain)
VI = 12 V
VI = 0 V
Input leakage current,
low
ILIL1
Pins other than CL1,
CL2, or P50 to P53
–3
µA
ILIL2
CL1, CL2
–20
µA
µA
ILIL3
P50 to P53 (N-ch open
drain)
–3Note 1
µA
µA
kΩ
Output leakage
current, high
ILOH
ILOL
R1
VO = VDD
3
Output leakage
current, low
VO = 0 V
–3
Software pull-up
resistance
VI = 0 V, for pins other than P50 to P53
50
100
200
Note 2
Power supply
current
IDD1
4.0 MHz RC oscillation
operating mode
VDD = 5.0 V ±10%Note 4
6.5
3.9
18.0
7.9
5.0
5.0
2.0
1.5
30
mA
mA
mA
mA
mA
mA
µA
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%
(R = 4.7 kΩ, C = 22 pF)
3.0
Note 2
IDD2
4.0 MHz RC oscillation
HALT mode
2.5
1.0
(R = 4.7 kΩ, C = 22 pF)
0.75
0.1
Note 2
IDD3
STOP mode
µA
VDD = 3.0 V ±10%
0.05
0.05
7.7
10
µA
VDD = 2.0 V ±10%
10
Note 3
IDD4
4.0 MHz RC oscillation
A/D operating mode
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
20.3
10.2
7.0
mA
mA
mA
5.1
(R = 4.7 kΩ, C = 22 pF)
4.0
Notes 1. When port 5 is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operation (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
355
User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V, RC Oscillation Mode)
Parameter
Symbol
IDDW
Conditions
MIN.
TYP.
MAX.
21
Unit
mA
Write current
(VDD pin)Note
When VPP supply voltage = VPP1
Write current
(VPP pin)Note
IPPW
IDDE
IPPE
When VPP supply voltage = VPP1
When VPP supply voltage = VPP1
When VPP supply voltage = VPP1
22.5
21
mA
mA
mA
Erase current
(VDD pin)Note
Erase current
(VPP pin)Note
115
Unit erase time
Total erase time
Rewrite count
ter
0.2
0.2
20
0.2
20
s
tera
s
Times
V
Erase/write are regarded as 1 cycle
In normal operation
20
0
20
VPP supply voltage VPP0
VPP1
0.2VDD
10.3
During flash memory programming
9.7
10.0
V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
356
User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
16
Unit
TCY
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
µs
(minimum instruction
execution time)
1.6
16
µs
TI80 input high-/low-
level width
tTIH,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
INTP0 to INTP2
0.1
1.8
0
µs
µs
tTIL
MHz
kHz
TI80 input frequency
fTI
4
0
275
Interrupt input high-
/low-level width
tINTH,
10
µs
µs
µs
tINTL
RESET low-level
width
tRSL
10
10
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY1
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
tKCY1/2 – 50
tKCY1/2 – 150
150
SCK20 high-/low-
level width
tKH1,
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
(to SCK20↑)
500
SI20 hold time
400
(from SCK20↑)
600
SO20 output delay
R = 1 k Ω,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
time from SCK20↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY2
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK20 high-/low-
level width
tKH2,
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
time from SCK20↓
0
1000
120
ns
ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
400
240
800
ns
ns
ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SS20 setup time
tSSK2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
100
150
400
ns
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V
600
ns
Note R and C are the load resistance and load capacitance of the SO output line.
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User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
78125
19531
Unit
bps
bps
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
400
ns
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
1600
ns
Transfer rate
39063
9766
1
bps
bps
µs
ASCK20 rise/fall time
tR,
tF
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User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/fCC
t
XL
t
XH
V
IH4 (MIN.)
CL1 input
V
IL4 (MAX.)
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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User’s Manual U14643EJ2V0UD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
10-Bit A/D Converter Characteristics (TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1, 2
Conversion time
4.5 V ≤ VDD ≤ 5.5 V
±0.2
±0.4
±0.8
±0.4
±0.6
±1.2
100
%FSR
%FSR
%FSR
µs
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
tCONV
14
14
28
100
µs
100
µs
Zero-scale errorNotes 1, 2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
Full-scale errorNotes 1, 2
Integral linearity
errorNote 1
ILE
LSB
LSB
Differential linearity
errorNote 1
DLE
VIAN
LSB
LSB
LSB
Analog input voltage
0
V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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CHAPTER 29 ELECTRICAL SPECIFICATIONS (µPD78F9136B, 78F9136B(A))
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
stabilization wait
timeNote
tWAIT
Release by RESET
Release by interrupt request
27/fCC
27/fCC
s
s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark fCC: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VPP
Conditions
Ratings
–0.3 to +6.5
–0.3 to +10.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–4
Unit
V
VDD = AVDD
Note
V
Input voltage
VI1
Pins other than P50 to P53
V
VI2
P50 to P53
With N-ch open drain
V
Output voltage
VO
V
Output current, high
IOH
Per pin
mA
mA
mA
mA
°C
°C
°C
Total for all pins
–14
Output current, low
IOL
TA
Per pin
5
Total for all pins
80
Operating ambient temperature
Storage temperature
In normal operation mode
During flash memory programming
–40 to +105
10 to 40
Tstg
–40 to +125
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (4.5 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (4.5 V) of the operating
voltage range of VDD (see b in the figure below).
4.5 V
V
DD
0 V
a
b
VPP
4.5 V
0 V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
364
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
System Clock Oscillator Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
CL1
RC
Oscillation frequency (fCC)Note
2.0
4.0
MHz
CL2
oscillator
External
clock
CL1 input frequency (fCC)Note
1.0
85
5.0
MHz
ns
CL1
CL2
CL1 input high-/low-level
width (tXH, tXL)
500
OPEN
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. Construct the oscillator with R and C devices that are guaranteed to operate at TA = 105°C.
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
DC Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
Output current, high
IOH
Per pin
mA
mA
mA
mA
V
Total for all pins
Per pin
–7
Output current, low
Input voltage, high
IOL
1.6
Total for all pins
40
VIH1
VIH2
VIH3
VIH4
VIL1
VIL2
VIL3
VIL4
VOH1
VOH2
VOL1
Pins other than described below
0.7VDD
0.7VDD
0.8VDD
VDD – 0.1
0
VDD
P50 to P53
With N-ch open drain
10
V
RESET, P20 to P25
CL1, CL2
VDD
V
VDD
V
Input voltage, low
Pins other than described below
P50 to P53
0.3VDD
0.3VDD
0.2VDD
0.1
V
0
V
RESET, P20 to P25
CL1, CL2
0
V
0
V
Output voltage, high
Output voltage, low
IOH = –1 mA
VDD – 2.0
VDD – 1.0
V
IOH = –100 µA
V
Pins other than
P50 to P53
IOL = 1.6 mA
IOL = 400 µA
IOL = 1.6 mA
2.0
1.0
1.0
10
V
V
VOL2
P50 to P53
V
Input leakage current,
high
ILIH1
Pins other than CL1, CL2, or
P50 to P53
VI = VDD
µA
ILIH2
ILIH3
ILIL1
CL1, CL2
20
80
µA
µA
µA
P50 to P53 (N-ch open drain)
VI = 10 V
VI = 0 V
Input leakage current,
low
Pins other than CL1, CL2, or
P50 to P53
–10
ILIL2
ILIL3
ILOH
CL1, CL2
–20
–10Note
10
µA
µA
µA
P50 to P53 (N-ch open drain)
VO = VDD
Output leakage
current, high
µA
Output leakage
current, low
ILOL
VO = 0 V
–10
Note When port 5 is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle time
after a read instruction has been executed to port 5.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
DC Characteristics (TA = –40 to +105°C, VDD = 4.5 to 5.5 V) (2/2)
Parameter
Symbol
Conditions
MIN.
50
TYP.
100
MAX.
300
Unit
Software pull-up
resistance
R1
VI = 0 V, for pins other than P50 to P53 or P60 to
P63
kΩ
Note 1
Power supply
current
IDD1
4.0 MHz RC oscillation operating mode
7.5
3.0
20.0
5.5
mA
mA
(R = 4.7 kΩ, C = 22 pF)Note 3
Note 1
IDD2
4.0 MHz RC oscillation HALT mode
(R = 4.7 kΩ, C = 22 pF)Note 3
Note 1
µA
IDD3
STOP mode
1
1000
22.3
Note 2
IDD4
4.0 MHz RC oscillation A/D operating mode
(R = 4.7 kΩ, C = 22 pF)Note 3
8.7
mA
Notes 1. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
3. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Flash Memory Write/Erase Characteristics
(TA = 10 to 40°C, VDD = 4.5 to 5.5 V, RC Oscillation Operating Mode)
Parameter
Symbol
IDDW
Conditions
MIN.
TYP.
MAX.
21
Unit
mA
Write current
(VDD pin)Note
When VPP supply voltage = VPP1
Write current
(VPP pin)Note
IPPW
When VPP supply voltage = VPP1
22.5
mA
Erase current
(VDD pin)Note
IDDE
When VPP supply voltage = VPP1
When VPP supply voltage = VPP1
21
mA
mA
Erase current
(VPP pin)Note
IPPE
115
Unit erase time
Total erase time
Rewrite count
ter
0.2
0.2
20
0.2
20
s
tera
s
Times
V
Erase/write are regarded as 1 cycle
In normal operation
20
0
20
VPP supply voltage VPP0
VPP1
0.2VDD
10.3
During flash memory programming
9.7
10.0
V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
AC Characteristics
(1) Basic operation (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
8
Unit
TCY
µs
(minimum instruction
execution time)
TI80 input high-/low-
level width
tTIH,
0.1
µs
tTIL
MHz
TI80 input frequency
fTI
0
4
Interrupt input high-
/low-level width
tINTH,
INTP0 to INTP2
10
µs
tINTL
RESET low-level
width
tRSL
10
10
µs
µs
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
(2) Serial interface (TA = –40 to +105°C, VDD = 4.5 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
MIN.
800
TYP.
MAX.
Unit
ns
SCK20 cycle time
tKCY1
SCK20 high-/low-
level width
tKH1,
tKCY1/2 – 50
ns
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
150
400
0
ns
ns
ns
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ, C = 100 pFNote
250
time from SCK20↓
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
SCK20 cycle time
tKCY2
SCK20 high-/low-
level width
tKH2,
ns
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
tKAS2
100
400
0
ns
ns
ns
ns
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ, C = 100 pFNote
300
120
time from SCK20↓
SO20 setup time
(to SS20↓ when
SS20 is used)
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
240
ns
SS20 setup time
tSSK2
100
400
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
bps
78125
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
Transfer rate
39063
1
bps
ASCK20 rise/fall time
tR,
tF
µs
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/fCC
t
XL
t
XH
V
IH4 (MIN.)
IL4 (MAX.)
CL1 input
V
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
10-Bit A/D Converter Characteristics (TA = –40 to +105°C, AVDD = VDD = 4.5 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1,2
±0.4
±0.6
28
%FSR
µs
Conversion time
tCONV
14
Zero-scale errorNotes 1,2
Full-scale errorNotes 1,2
±0.6
±0.6
±4.5
%FSR
%FSR
LSB
Integral linearity
errorNote 1
ILE
Differential linearity
errorNote 1
DLE
VIAN
±2.0
LSB
V
Analog input voltage
0
AVDD
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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CHAPTER 30 ELECTRICAL SPECIFICATIONS (µPD78F9136B(A1))
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +105°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
stabilization wait
timeNote
tWAIT
Release by RESET
Release by interrupt request
27/fCC
27/fCC
s
s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark fcc: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
V
DDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
VPP
Conditions
Ratings
–0.3 to +6.5
–0.3 to +10.5
–0.3 to VDD + 0.3
–0.3 to +13
–0.3 to VDD + 0.3
–10
Unit
V
VDD = AVDD
Note
V
Input voltage
VI1
Pins other than P50 to P53
V
VI2
P50 to P53
With N-ch open drain
V
Output voltage
VO
V
Output current, high
IOH
Per pin
mA
mA
mA
mA
°C
°C
°C
Total for all pins
–30
Output current, low
IOL
TA
Per pin
30
Total for all pins
160
Operating ambient temperature
Storage temperature
In normal operation mode
During flash memory programming
–40 to +85
10 to 40
Tstg
–40 to +125
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
a
b
VPP
1.8 V
0 V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
375
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CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Resonator
Parameter
Conditions
MIN. TYP. MAX. Unit
Circuit
Oscillation frequency (fCC)Note 1
VDD = oscillation voltage
range
2.0
4.0
MHz
CL1
CL2
RC
oscillator
External
clock
CL1 input frequency (fCC)Note 1
1.0
85
5.0
MHz
ns
CL2
CL1
CL1 input high-/low-level
width (tXH, tXL)
500
CL1 input frequency (fCC)Note 1 VDD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
CL1
CL2
CL1 input high-/low-level
width (tXH, tXL)
500
OPEN
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
RC Oscillator Frequency Characteristics (TA = –40 to +85°C)
Parameter
Symbol
fCC1
Conditions
R = 11.0 kΩ, C = 22 pF
MIN.
1.5
TYP. MAX.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Oscillator frequency
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 3.6 V
VDD = 1.8 to 5.5 V
2.0
2.0
2.0
3.0
3.0
3.0
4.0
4.0
4.0
2.5
2.5
2.5
3.5
3.5
3.5
4.7
4.7
4.7
Target: 2 MHz
fCC2
0.5
fCC3
0.5
fCC4
R = 6.8 kΩ, C = 22 pF
2.5
Target: 3 MHz
fCC5
0.75
0.75
3.5
fCC6
fCC7
R = 4.7 kΩ, C = 22 pF
Target: 4 MHz
fCC8
1.0
fCC9
1.0
Remark So that the TYP. Spec is satisfied between 2.0 to 4.0 MHz, set one of the above nine patterns for R and
C.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–1
Unit
mA
mA
mA
mA
V
Output current, high
IOH
Per pin
Total for all pins
Per pin
–15
10
Output current, low
Input voltage, high
IOL
Total for all pins
80
VIH1
VIH2
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.7VDD
0.9VDD
0.7VDD
0.9VDD
VDD
VDD
12
V
P50 to P53 With N-ch open VDD = 2.7 to 5.5 V
V
drain
VDD = 1.8 to 5.5 V
12
V
TA = 25 to 85°C
VIH3
VIH4
VIL1
RESET, P20 to P25
CL1, CL2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.8VDD
0.9VDD
VDD
VDD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD = 4.5 to 5.5 V VDD – 0.5
VDD = 1.8 to 5.5 V VDD – 0.1
VDD
VDD
Input voltage, low
Pins other than described
below
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
0
0.3VDD
0.1VDD
0.3VDD
0.2VDD
0.1VDD
0.4
0
VIL2
VIL3
P50 to P53
0
RESET, P20 to P25
0
0
VIL4
CL1, CL2
0
0
0.1
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD – 0.5
VDD = 1.8 to 5.5 V, IOH = –100 µA
Pins other
than P50 to
P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
VDD = 1.8 to 5.5 V, IOL = 400 µA
VDD = 4.5 to 5.5 V, IOL = 10 mA
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
0.5
1.0
0.4
V
V
V
VOL2
P50 to P53
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage current,
high
ILIH1
Pins other than CL1,
VI = VDD
µA
CL2, or P50 to P53
ILIH2
CL1, CL2
20
20
µA
µA
ILIH3
P50 to P53 (N-ch open
drain)
VI = 12 V
VI = 0 V
Input leakage current,
low
ILIL1
Pins other than CL1,
CL2, or P50 to P53
–3
µA
ILIL2
CL1, CL2
–20
µA
µA
ILIL3
P50 to P53 (N-ch open
drain)
–3Note 1
µA
µA
kΩ
Output leakage
current, high
ILOH
ILOL
R1
VO = VDD
3
Output leakage
current, low
VO = 0 V
–3
Software pull-up
resistance
VI = 0 V, for pins other than P50 to P53
50
100
200
Note 2
Power supply
current
IDD1
4.0 MHz RC oscillation
operating mode
VDD = 5.0 V ±10%Note 4
5.0
1.9
15.0
4.9
3.0
5.0
2.0
1.5
30
mA
mA
mA
mA
mA
mA
µA
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
VDD = 5.0 V ±10%
(R = 4.7 kΩ, C = 22 pF)
1.5
Note 2
IDD2
4.0 MHz RC oscillation
HALT mode (R = 4.7
kΩ, C = 22 pF)
2.5
1.0
0.75
0.1
Note 2
IDD3
STOP mode
µA
VDD = 3.0 V ±10%
0.05
0.05
6.2
10
µA
VDD = 2.0 V ±10%
10
Note 3
IDD4
4.0 MHz RC oscillation
A/D operating mode
VDD = 5.0 V ±10%Note 4
VDD = 3.0 V ±10%Note 5
VDD = 2.0 V ±10%Note 5
17.3
7.2
5.0
mA
mA
mA
3.1
(R = 4.7 kΩ, C = 22 pF)
2.5
Notes 1. When port 5 is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through on-chip pull-up resistors) is not
included.
4. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
5. Low-speed mode operation (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V, RC Oscillation Operating Mode)
Parameter
Symbol
IDDW
Conditions
MIN.
TYP.
MAX.
18
Unit
mA
Write current
(VDD pin)Note
When VPP supply voltage = VPP1
Write current
(VPP pin)Note
IPPW
IDDE
IPPE
When VPP supply voltage = VPP1
When VPP supply voltage = VPP1
When VPP supply voltage = VPP1
22.5
18
mA
mA
mA
Erase current
(VDD pin)Note
Erase current
(VPP pin)Note
115
Unit erase time
Total erase time
Rewrite count
ter
0.5
1
1
20
s
tera
s
Times
V
Erase/write are regarded as 1 cycle
In normal operation
20
0
20
20
VPP supply voltage VPP0
VPP1
0.2VDD
10.3
During flash memory programming
9.7
10.0
V
Note The current flowing to the ports (including the current flowing through on-chip pull-up resistors) and AVDD
current are not included.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
16
Unit
TCY
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
µs
(minimum instruction
execution time)
1.6
16
µs
TI80 input high-/low-
level width
tTIH,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
INTP0 to INTP2
0.1
1.8
0
µs
µs
tTIL
MHz
kHz
TI80 input frequency
fTI
4
0
275
Interrupt input high-
/low-level width
tINTH,
10
µs
µs
µs
tINTL
RESET low-level
width
tRSL
10
10
CPT20 input high-
/low-level width
tCPH,
tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
(2) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...internal clock output)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY1
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
tKCY1/2 – 50
tKCY1/2 – 150
150
SCK20 high-/low-
level width
tKH1,
tKL1
SI20 setup time
tSIK1
tKSI1
tKSO1
(to SCK20↑)
500
SI20 hold time
400
(from SCK20↑)
600
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
time from SCK20↓
0
1000
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK20 cycle time
tKCY2
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SCK20 high-/low-
level width
tKH2,
tKL2
SI20 setup time
tSIK2
tKSI2
tKSO2
(to SCK20↑)
SI20 hold time
(from SCK20↑)
SO20 output delay
R = 1 kΩ,
C = 100 pFNote
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
time from SCK20↓
0
1000
120
ns
ns
SO20 setup time
(to SS20↓ when
SS20 is used)
tKAS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
400
240
800
ns
ns
ns
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SS20 setup time
tSSK2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
100
150
400
ns
ns
ns
(to SCK20 first edge)
SS20 hold time
(from SCK20 last
edge)
tKSS2
VDD = 1.8 to 5.5 V
600
ns
Note R and C are the load resistance and load capacitance of the SO output line.
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CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
(iii) UART mode (dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
78125
19531
Unit
bps
bps
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(iv) UART mode (external clock input)
Parameter
Symbol
Conditions
VDD = 2.7 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK20 cycle time
tKCY3
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
3200
400
ns
ASCK20 high-/low-
level width
tKH3,
ns
tKL3
1600
ns
Transfer rate
39063
9766
1
bps
bps
µs
ASCK20 rise/fall time
tR,
tF
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User’s Manual U14643EJ2V0UD
CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
AC Timing Measurement Points (Excluding CL1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement points
Clock Timing
1/fCC
t
XL
t
XH
V
IH4 (MIN.)
IL4 (MAX.)
CL1 input
V
TI Timing
1/fTI
t
TIL
t
TIH
TI80
Capture Input Timing
t
CPH
t
CPL
CPT20
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
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User’s Manual U14643EJ2V0UD
CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
t
KAS2
t
KDS2
SO20
SS20
Output data
t
SSK2
t
KSS2
SCK20
(CKP20 = 0)
SCK20
(CKP20 = 1)
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
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User’s Manual U14643EJ2V0UD
CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
10-Bit A/D Converter Characteristics
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
Bits
Overall errorNotes 1,2
4.5 V ≤ VDD ≤ 5.5 V
±0.2
±0.4
±0.8
±0.4
±0.6
±1.2
100
%FSR
%FSR
%FSR
µs
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
Conversion time
tCONV
14
28
100
µs
Zero-scale errorNotes 1,2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
Full-scale errorNotes 1,2
Integral linearity
errorNote 1
ILE
LSB
LSB
Differential linearity
errorNote 1
DLE
VIAN
LSB
LSB
LSB
Analog input voltage
0
V
Notes 1. Excludes quantization error (±0.05%FSR).
2. This value is indicated as a ratio to the full-scale value (%FSR).
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CHAPTER 31 ELECTRICAL SPECIFICATIONS (µPD78F9136A)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention
supply voltage
VDDDR
Release signal
set time
tSREL
0
µs
Oscillation
stabilization wait
timeNote
tWAIT
Release by RESET
Release by interrupt request
27/fCC
27/fCC
s
s
Note The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark fCC: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
V
DDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
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CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES)
(µPD78910xA, 78911xA, 78910xA(A), 78911xA(A))
IDD vs VDD (System clock: 5.0 MHz crystal resonator)
(TA = 25˚C)
10
5.0
PCC = 00H
PCC = 02H
1.0
0.5
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
0.1
0.05
0.01
X2
X1
0.005
Crystal resonator
5.0 MHz
22 pF
22 pF
0.001
7
5
6
8
3
4
0
1
2
Power supply voltage VDD (V)
387
User’s Manual U14643EJ2V0UD
CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES) (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A))
IDD vs VDD (System clock: 4.0 MHz crystal resonator)
(TA = 25˚C)
10
5.0
PCC = 00H
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
1.0
0.5
0.1
0.05
0.01
X2
X1
0.005
Crystal resonator
4.0 MHz
22 pF
22 pF
0.001
7
5
6
8
3
4
0
1
2
Power supply voltage VDD (V)
388
User’s Manual U14643EJ2V0UD
CHAPTER 32 CHARACTERISTICS CURVES (REFERENCE VALUES) (µPD78910xA, 78911xA, 78910xA(A), 78911xA(A))
IDD vs VDD (System clock: 2.0 MHz crystal resonator)
(TA = 25˚C)
10
5.0
1.0
0.5
PCC = 00H
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
0.1
0.05
0.01
X2
X1
0.005
Crystal resonator
2.0 MHz
47 pF
47 pF
0.001
7
5
6
8
3
4
0
1
2
Power supply voltage VDD (V)
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User’s Manual U14643EJ2V0UD
CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES)
(µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
IDD vs VDD (System clock: 5.0 MHz ceramic resonator)
(TA = 25˚C)
10
5.0
PCC = 00H
PCC = 02H
1.0
0.5
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
0.1
0.05
0.01
X2
X1
0.005
Ceramic resonator
5.0 MHz
22 pF
22 pF
0.001
7
5
6
8
3
4
0
1
2
Power supply voltage VDD (V)
390
User’s Manual U14643EJ2V0UD
CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
IDD vs VDD (System clock: 4.0 MHz ceramic resonator)
(TA = 25˚C)
10
5.0
PCC = 00H
1.0
0.5
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
0.1
0.05
0.01
X2
X1
0.005
Ceramic resonator
4.0 MHz
22 pF
22 pF
0.001
7
5
6
8
3
4
0
1
2
Power supply voltage VDD (V)
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User’s Manual U14643EJ2V0UD
CHAPTER 33 CHARACTERISTICS CURVES (REFERENCE VALUES) (µPD78910xA(A1), 78911xA(A1), 78910xA(A2), 78911xA(A2))
IDD vs VDD (System clock: 2.0 MHz ceramic resonator)
(TA = 25˚C)
10
5.0
1.0
0.5
PCC = 00H
PCC = 02H
PCC = 00H (HALT mode)
PCC = 02H (HALT mode)
0.1
0.05
0.01
X2
X1
0.005
Ceramic resonator
2.0 MHz
47 pF
47 pF
0.001
7
5
6
8
3
4
0
1
2
Power supply voltage VDD (V)
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User’s Manual U14643EJ2V0UD
CHAPTER 34 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS
(REFERENCE VALUES) (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136A)
fCC vs VDD (RC oscillation, R = 11 kΩ, C= 22 pF)
(T
A
= –40˚C
)
2.6
2.4
CL1
CL2
11 kΩ
22 pF
2.2
2.0
1.8
Sample A
Sample B
Sample C
1.6
1.4
2
3
4
5
6
Supply voltage VDD [V]
(T
A
= 25˚C
)
2.6
2.4
CL1
CL2
11 kΩ
22 pF
2.2
2.0
1.8
Sample A
Sample B
Sample C
1.6
1.4
2
3
4
5
6
)
Supply voltage VDD [V]
(TA = 85˚C
2.6
2.4
CL1
CL2
11 kΩ
22 pF
2.2
2.0
1.8
Sample A
Sample B
Sample C
1.6
1.4
2
3
4
5
6
Supply voltage VDD [V]
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User’s Manual U14643EJ2V0UD
CHAPTER 34 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (µPD78912xA, 78913xA, 78912xA(A), 78913xA(A), 78F9136(A)
fCC vs VDD (RC oscillation, R = 4.7 kΩ, C= 22 pF)
(TA = –40˚C)
4.6
4.4
CL1
CL2
4.7 kΩ
22 pF
4.2
4.0
3.8
Sample A
Sample B
Sample C
3.6
3.4
2
3
4
5
6
Supply voltage VDD [V]
(TA = 25˚C)
4.6
4.4
CL1
CL2
4.7 kΩ
22 pF
4.2
4.0
3.8
Sample A
Sample B
Sample C
3.6
3.4
2
3
4
5
6
Supply voltage VDD [V]
(TA = 85˚C
)
4.6
4.4
CL1
CL2
4.7 kΩ
22 pF
4.2
4.0
3.8
Sample A
Sample B
Sample C
3.6
3.4
2
3
4
5
6
Supply voltage VDD [V]
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User’s Manual U14643EJ2V0UD
CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS
(REFERENCE VALUES) (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
fCC vs VDD (RC oscillation, R = 11 kΩ, C= 22 pF)
(T
A
= –40˚C
)
2.6
2.4
CL1
CL2
11 kΩ
22 pF
2.2
2.0
1.8
Sample A
Sample B
Sample C
1.6
1.4
2
3
4
5
6
Supply voltage VDD [V]
(TA = 25˚C)
2.6
CL1
CL2
11 kΩ
2.4
22 pF
2.2
2.0
1.8
Sample A
Sample B
Sample C
1.6
1.4
2
3
4
5
6
)
Supply voltage VDD [V]
(TA = 85˚C
2.6
2.4
CL1
CL2
11 kΩ
22 pF
2.2
2.0
1.8
Sample A
Sample B
Sample C
1.6
1.4
2
3
4
5
6
Supply voltage VDD [V]
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User’s Manual U14643EJ2V0UD
CHAPTER 35 EXAMPLE OF RC OSCILLATOR FREQUENCY CHARACTERISTICS (REFERENCE VALUES) (µPD78912xA(A1), 78913xA(A1), 78912xA(A2), 78913xA(A2))
fCC vs VDD (RC oscillation, R = 4.7 kΩ, C= 22 pF)
(TA = –40˚C)
4.6
4.4
CL1
CL2
4.7 kΩ
22 pF
4.2
4.0
3.8
Sample A
Sample B
Sample C
3.6
3.4
2
3
4
5
6
Supply voltage VDD [V]
(TA = 25˚C)
4.6
CL1
CL2
4.7 kΩ
4.4
22 pF
4.2
4.0
3.8
Sample A
Sample B
Sample C
3.6
3.4
2
3
4
5
6
Supply voltage VDD [V]
(TA = 85˚C)
4.6
CL1
CL2
4.7 kΩ
4.4
22 pF
4.2
4.0
3.8
Sample A
Sample B
Sample C
3.6
3.4
2
3
4
5
6
Supply voltage VDD [V]
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CHAPTER 36 PACKAGE DRAWING
30-PIN PLASTIC SSOP (7.62 mm (300))
30
16
detail of lead end
F
G
T
P
L
1
15
U
E
A
H
I
J
S
B
C
N
S
M
D
M
K
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
9.85±0.15
0.45 MAX.
0.65 (T.P.)
+0.08
0.24
D
−0.07
E
F
G
H
I
0.1±0.05
1.3±0.1
1.2
8.1±0.2
6.1±0.2
1.0±0.2
0.17±0.03
0.5
J
K
L
M
N
0.13
0.10
+5°
3°
P
−3°
T
0.25
U
0.6±0.15
S30MC-65-5A4-2
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CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS
The µPD789104A, 789114A, 789124A, and 789134A Subseries should be soldered and mounted under the
following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 37-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD789101AMC-×××-5A4, µPD789102AMC-×××-5A4, µPD789104AMC-×××-5A4
µPD789111AMC-×××-5A4, µPD789112AMC-×××-5A4, µPD789114AMC-×××-5A4
µPD789121AMC-×××-5A4, µPD789122AMC-×××-5A4, µPD789124AMC-×××-5A4
µPD789131AMC-×××-5A4, µPD789132AMC-×××-5A4, µPD789134AMC-×××-5A4
µPD789101AMC(A)-×××-5A4, µPD789102AMC(A)-×××-5A4, µPD789104AMC(A)-×××-5A4
µPD789111AMC(A)-×××-5A4, µPD789112AMC(A)-×××-5A4, µPD789114AMC(A)-×××-5A4
µPD789121AMC(A)-×××-5A4, µPD789122AMC(A)-×××-5A4, µPD789124AMC(A)-×××-5A4
µPD789131AMC(A)-×××-5A4, µPD789132AMC(A)-×××-5A4, µPD789134AMC(A)-×××-5A4
µPD789101AMC(A1)-×××-5A4, µPD789102AMC(A1)-×××-5A4, µPD789104AMC(A1)-×××-5A4
µPD789111AMC(A1)-×××-5A4, µPD789112AMC(A1)-×××-5A4, µPD789114AMC(A1)-×××-5A4
µPD789121AMC(A1)-×××-5A4, µPD789122AMC(A1)-×××-5A4, µPD789124AMC(A1)-×××-5A4
µPD789131AMC(A1)-×××-5A4, µPD789132AMC(A1)-×××-5A4, µPD789134AMC(A1)-×××-5A4
µPD789101AMC(A2)-×××-5A4, µPD789102AMC(A2)-×××-5A4, µPD789104AMC(A2)-×××-5A4
µPD789111AMC(A2)-×××-5A4, µPD789112AMC(A2)-×××-5A4, µPD789114AMC(A2)-×××-5A4
µPD789121AMC(A2)-×××-5A4, µPD789122AMC(A2)-×××-5A4, µPD789124AMC(A2)-×××-5A4
µPD789131AMC(A2)-×××-5A4, µPD789132AMC(A2)-×××-5A4, µPD789134AMC(A2)-×××-5A4
Soldering Method
Infrared reflow
VPS
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Three times or less
IR35-00-3
VP15-00-3
WS60-00-1
–
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times or less
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
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CHAPTER 37 RECOMMENDED SOLDERING CONDITIONS
Table 37-1. Surface Mounting Type Soldering Conditions (2/2)
(2) µPD78F9116BMC-5A4, µPD78F9136BMC-5A4,
µPD78F9116BMC(A)-5A4, µPD78F9136BMC(A)-5A4,
µPD78F9116BMC(A1)-5A4, µPD78F9136BMC(A1)-5A4
Soldering Method
Infrared reflow
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote
IR35-107-2
VP15-107-2
WS60-107-1
(after that, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote
(after that, prebake at 125°C for 10 hours)
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max.,
Count: Once
Preheating temperature: 120°C max. (package surface temperature), Exposure
limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(3) µPD78F9116AMC-5A4, µPD78F9136AMC-5A4
Soldering Method
Infrared reflow
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Three times or less, Exposure limit: 7 daysNote
IR35-107-3
VP15-107-3
WS60-107-1
–
(after that, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times or less, Exposure limit: 7 daysNote
(after that, prebake at 125°C for 10 hours)
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once
Preheating temperature: 120°C max.(package surface temperature), Exposure
limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
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APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the
µPD789104A/114A/124A/134A Subseries.
Figure A-1 shows the development tool configuration.
• Support of the PC98-NX Series
Unless otherwise specified, the µPD789104A/114A/124A/134A Subseries supported by IBM PC/ATTM and
compatibles can be used for the PC98-NX Series. When using the PC98-NX Series, refer to the descriptions of
IBM PC/AT and compatibles.
• Windows
Unless otherwise specified, “Windows” indicates the following OSs.
• Windows 3.1
• Windows 95
• Windows 98
• Windows 2000
• Windows NTTM Ver. 4.0
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tools
Software package
·
Software package
Language processing software
Debugging software
·
·
·
·
Assembler package
C compiler package
Device file
·
·
Integrated debugger
System simulator
C library source fileNote 1
Control software
·
Project manager
(Windows version only)Note 2
Host machine
(PC or EWS)
Interface adapter
Power supply unit
Flash memory writing tools
Flash programmer
In-circuit emulator
Emulation board
Flash memory
writing adapter
Flash memory
Emulation probe
Conversion socket or
conversion adapter
Target system
Notes 1. The C library source file is not included in the software package.
2. The project manager is included in the assembler package and is available only for Windows.
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APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0S
Various software tools for 78K/0S development are integrated in one package.
The following tools are included.
Software package
RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, various device files
Part number: µS××××SP78K0S
Remark ×××× in the part number differs depending on the operating system to be used.
µS×××× SP78K0S
××××
Host Machine
OS
Supply Medium
CD-ROM
AB17
BB17
PC-9800 series,
IBM PC/AT and compatibles
Japanese Windows
English Windows
A.2 Language Processing Software
RA78K0S
Program that converts program written in mnemonic into object codes that can be executed by a
microcontroller.
Assembler package
In addition, automatic functions to generate a symbol table and optimize branch instructions are also
provided.
Used in combination with a device file (DF789136) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows environment
by using the Project Manager of Windows (included in the package).
Part number: µS××××RA78K0S
CC78K0S
Program that converts program written in C language into object codes that can be executed by a
microcontroller.
C compiler package
Used in combination with an assembler package (RA78K0S) and device file (DF789136) (both sold
separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows environment
by using the Project Manager of Windows (included in the assembler package).
Part number: µS××××CC78K0S
DF789136Note 1
Device file
File containing the information inherent to the device.
Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold
separately).
Part number: µS××××DF789136
CC78K0S-LNote 2
Source file of functions constituting the object library included in the C compiler package.
Necessary for changing the object library included in the C compiler package according to the
customer’s specifications.
C library source file
Since this is the source file, its working environment does not depend on any particular operating
system.
Part number: µS××××CC78K0S-L
Notes 1. DF789136 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and
SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
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APPENDIX A DEVELOPMENT TOOLS
Remark ×××× in the part number differs depending on the host machine and operating system to be used.
µS××××RA78K0S
µS××××CC78K0S
××××
AB13
Host Machine
PC-9800 series,
OS
Supply Medium
3.5” 2HD FD
Japanese Windows
English Windows
Japanese Windows
English Windows
HP-UXTM (Rel.10.10)
IBM PC/AT and compatibles
BB13
AB17
BB17
3P17
3K17
CD-ROM
HP9000 series 700TM
SPARCstationTM
SunOSTM (Rel.4.1.1),
SolarisTM (Rel.2.5.1)
µS××××DF789136
µS××××CC78K0S-L
××××
AB13
BB13
3P16
3K13
3K15
Host Machine
OS
Supply Medium
PC-9800 series,
Japanese Windows
English Windows
HP-UX (Rel.10.10)
3.5” 2HD FD
IBM PC/AT and compatibles
HP9000 series 700
SPARCstation
DAT
SunOS (Rel.4.1.1),
Solaris (Rel.2.5.1)
3.5” 2HD FD
1/4” CGMT
A.3 Control Software
Project Manager
Control software provided for efficient user program development in the Windows
environment. The Project Manager allows a series of tasks required for user program
development to be performed, including starting the editor, building, and starting the
debugger.
<Caution>
The Project Manager is included in the assembler package (RA78K0S).
It cannot be used in an environment other than Windows.
A.4 Flash Memory Writing Tools
Flashpro III
Flash programmer dedicated to microcontrollers incorporating flash memory.
(part number: FL-PR3, PG-FP3)
Flashpro IV
(part number: FL-PR4, PG-FP4)
Flash programmer
FA-30MC
Flash memory writing adapter. Used connected to Flashpro III.
30-pin plastic SSOP (MC-5A4 type)
Flash memory writing adapter
Remark FL-PR3, FL-PR4, and FA-30MC are products of Naito Densei Machida Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191)
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APPENDIX A DEVELOPMENT TOOLS
A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator for debugging the hardware and software of an application system using the
78K/0S Series. Used with an integrated debugger (ID78K0S-NS). Used in combination with
an AC adapter, emulation probe, and interface adapter for connecting the host machine.
In-circuit emulator
IE-78K0S-NS-A
In-circuit emulator with enhanced functions of the IE-78K0S-NS. The debug function is further
enhanced by adding a coverage function and enhancing the tracer and timer functions.
In-circuit emulator
IE-70000-MC-PS-B
AC adapter
Adapter for supplying power from a 100 to 240 VAC outlet.
IE-70000-98-IF-C
Interface adapter
Adapter required when using a PC-9800 series (except notebook type) as the host machine (C
bus supported).
IE-70000-CD-IF-A
PC card interface
PC card and interface cable required when using a notebook type PC as the host machine
(PCMICA socket supported).
IE-70000-PC-IF-C
Interface adapter
Adapter required when using an IBM PC/AT or compatible as the host machine (ISA bus
supported).
IE-70000-PCI-IF-A
Interface adapter
Adapter required when using a personal computer incorporating a PCI bus as the host
machine.
IE-789136-NS-EM1
Emulation board
Emulation board for emulating the peripheral hardware inherent to the device.
Used in combination with an in-circuit emulator.
NP-30MC
Probe for connecting the in-circuit emulator and target system.
Used in combination with the NSPACK30BK and YSPACK30BK.
Emulation probe
NSPACK30BK
Conversion adapter used to connect a target system board designed to allow mounting a 30-
pin plastic SSOP (MC-5A4 type) and the NP-30MC.
YSPACK30BK
Conversion adapter
Remarks 1. The NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191)
2. The NSPACK30BK and YSPACK30BK are products of TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
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APPENDIX A DEVELOPMENT TOOLS
A.6 Debugging Tools (Software)
ID78K0S-NS
This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the
78K/0S Series. The ID78K0S-NS is Windows-based software.
Integrated debugger
It has improved C-compatible debugging functions and can display the results of tracing with the
source program using an integrating window function that associates the source program,
disassemble display, and memory display with the trace result.
Used in combination with a device file (DF789136) (sold separately).
Part number: µS××××ID78K0S-NS
SM78K0S
This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.
It can be used to debug the target system at C source level or assembler level while simulating
the operation of the target system on the host machine.
System simulator
Using SM78K0S, the logic and performance of the application can be verified independently of
hardware development. Therefore, the development efficiency can be enhanced and the
software quality can be improved.
Used in combination with a device file (DF789136) (sold separately).
Part number: µS××××SM78K0S
DF789136Note
Device file
File containing the information inherent to the device.
Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold
separately).
Part number: µS××××DF789136
Note DF789136 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Remark ×××× in the part number differs depending on the operating system to be used and the supply medium.
µS××××ID78K0S-NS
µS××××SM78K0S
××××
AB13
Host Machine
OS
Supply Medium
3.5” 2HD FD
PC-9800 series,
IBM PC/AT and compatibles
Japanese Windows
English Windows
Japanese Windows
English Windows
BB13
AB17
BB17
CD-ROM
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
The following show the conditions when connecting the emulation probe to the conversion adapter. Follow the
configuration below and consider the shape of parts to be mounted on the target system when designing a system.
Figure B-1. Distance Between In-Circuit Emulator and Conversion Adapter
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Target system
Emulation board
IE-789136-NS-EM1
Board on end of NP-30MC
150 mm
CN2
Emulation probe
NP-30MC
Conversion adapter:
YSPACK30BK,
NSPACK30BK
Remarks 1. The NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd.
2. The YSPACK30BK and NSPACK30BK are products of TOKYO ELETECH CORPORATION.
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Figure B-2. Connection Condition of Target System
Emulation board
IE-789136-NS-EM1
Emulation probe
NP-30MC
Board on end of NP-30MC
Guide pin
YQGUIDE
13 mm
Conversion adapter
YSPACK30BK,
NSPACK30BK
5 mm
15 mm
31 mm
20 mm
37 mm
Target system
Remarks 1. The NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd.
2. The YSPACK30BK, NSPACK30BK, and YQGUIDE are products of TOKYO ELETECH
CORPORATION.
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APPENDIX C REGISTER INDEX
C.1 Register Name Index (Alphabetical Order)
[A]
A/D conversion result register 0 (ADCR0)...........................................................................................................143, 155
A/D converter mode register 0 (ADM0) ...............................................................................................................144, 156
Analog input channel specification register 0 (ADS0) .........................................................................................145, 157
Asynchronous serial interface mode register 20 (ASIM20) .................................................................172, 178, 181, 193
Asynchronous serial interface status register 20 (ASIS20) .................................................................................174, 182
[B]
Baud rate generator control register 20 (BRGC20).....................................................................................175, 183, 194
[E]
8-bit compare register 80 (CR80)............................................................................................................................... 125
8-bit timer counter 80 (TM80)..................................................................................................................................... 125
8-bit timer mode control register 80 (TMC80)............................................................................................................. 126
External interrupt mode register 0 (INTM0)................................................................................................................ 212
[I]
Interrupt mask flag register 0 (MK0)............................................................................................................................211
Interrupt mask flag register 1 (MK1)............................................................................................................................211
Interrupt request flag register 0 (IF0).......................................................................................................................... 210
Interrupt request flag register 1 (IF1).......................................................................................................................... 210
[M]
Multiplication data register A0 (MRA0)....................................................................................................................... 202
Multiplication data register B0 (MRB0)....................................................................................................................... 202
Multiplier control register 0 (MULC0).......................................................................................................................... 204
[O]
Oscillation stabilization time select register (OSTS)................................................................................................... 222
[P]
Port 0 (P0).................................................................................................................................................................... 82
Port 1 (P1).................................................................................................................................................................... 83
Port 2 (P2).................................................................................................................................................................... 84
Port 5 (P5).................................................................................................................................................................... 88
Port 6 (P6).................................................................................................................................................................... 89
Port mode register 0 (PM0).......................................................................................................................................... 90
Port mode register 1 (PM1).......................................................................................................................................... 90
Port mode register 2 (PM2)...........................................................................................................................90, 115, 127
Port mode register 5 (PM5).......................................................................................................................................... 90
Processor clock control register (PCC) .................................................................................................................96, 103
Pull-up resistor option register 0 (PU0) ........................................................................................................................ 91
Pull-up resistor option register B2 (PUB2).................................................................................................................... 92
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APPENDIX C REGISTER INDEX
[R]
Receive buffer register 20 (RXB20) ............................................................................................................................169
Receive shift register 20 (RXS20)...............................................................................................................................169
[S]
Serial operating mode register 20 (CSIM20).......................................................................................170, 178, 180, 192
16-bit capture register 20 (TCP20)..............................................................................................................................112
16-bit compare register 20 (CR20)..............................................................................................................................112
16-bit multiplication result storage register 0 (MUL0)..................................................................................................202
16-bit timer counter 20 (TM20)....................................................................................................................................112
16-bit timer mode control register 20 (TMC20) ...........................................................................................................113
[T]
Timer clock select register 2 (TCL2) ...........................................................................................................................138
Transmit shift register 20 (TXS20)...............................................................................................................................169
[W]
Watchdog timer mode register (WDTM)......................................................................................................................139
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APPENDIX C REGISTER INDEX
C.2 Register Symbol Index (Alphabetical Order)
[A]
ADCR0: A/D conversion result register 0 .........................................................................................................143, 155
ADM0:
ADS0:
A/D converter mode register 0............................................................................................................144, 156
Analog input channel specification register 0 .....................................................................................145, 157
ASIM20: Asynchronous serial interface mode register 20.................................................................172, 178, 181, 193
ASIS20: Asynchronous serial interface status register 20................................................................................174, 182
[B]
BRGC20: Baud rate generator control register 20......................................................................................175, 183, 194
[C]
CR20:
CR80:
16-bit compare register 20 .........................................................................................................................112
8-bit compare register 80 .......................................................................................................................... 125
CSIM20: Serial operating mode register 20 ......................................................................................170, 178, 180, 192
[I]
IF0:
IF1:
Interrupt request flag register 0 ................................................................................................................. 210
Interrupt request flag register 1 ................................................................................................................. 210
INTM0: External interrupt mode register 0............................................................................................................. 212
[M]
MK0:
Interrupt mask flag register 0......................................................................................................................211
Interrupt mask flag register 1......................................................................................................................211
Multiplication data register A0 ................................................................................................................... 202
Multiplication data register B0 ................................................................................................................... 202
16-bit multiplication result storage register 0 ............................................................................................. 202
MK1:
MRA0:
MRB0:
MUL0:
MULC0: Multiplier control register 0 ........................................................................................................................ 204
[O]
OSTS:
Oscillation stabilization time select register............................................................................................... 222
[P]
P0:
Port 0........................................................................................................................................................... 82
Port 1........................................................................................................................................................... 83
Port 2........................................................................................................................................................... 84
Port 5........................................................................................................................................................... 88
Port 6........................................................................................................................................................... 89
Processor clock control register ...........................................................................................................96, 103
Port mode register 0.................................................................................................................................... 90
Port mode register 1.................................................................................................................................... 90
Port mode register 2.....................................................................................................................90, 115, 127
Port mode register 5.................................................................................................................................... 90
Pull-up resistor option register 0.................................................................................................................. 91
Pull-up resistor option register B2 ............................................................................................................... 92
P1:
P2:
P5:
P6:
PCC:
PM0:
PM1:
PM2:
PM5:
PU0:
PUB2:
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APPENDIX C REGISTER INDEX
[R]
RXB20: Receive buffer register 20 ..........................................................................................................................169
RXS20: Receive shift register 20.............................................................................................................................169
[T]
TCL2:
Timer clock select register 2 ......................................................................................................................138
TCP20: 16-bit capture register 20 ...........................................................................................................................112
TM20:
TM80:
16-bit timer counter 20 ...............................................................................................................................112
8-bit timer counter 80 .................................................................................................................................125
TMC20: 16-bit timer mode control register 20..........................................................................................................113
TMC80: 8-bit timer mode control register 80 ...........................................................................................................126
TXS20: Transmit shift register 20............................................................................................................................169
[W]
WDTM: Watchdog timer mode register ...................................................................................................................139
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APPENDIX D REVISION HISTORY
The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of
each edition in which the revision was applied.
(1/2)
Edition
2nd
Major Revision from Previous Edition
Applied to:
• Addition of µPD789101A(A1), 789102A(A1), 789104A(A1), 789111A(A1), 789112A(A1), Throughout
789114A(A1), 789121A(A1), 789122A(A1), 789124A(A1), 789131A(A1), 789132A(A1),
789134A(A1), 789101A(A2), 789102A(A2), 789104A(A2), 789111A(A2), 789112A(A2),
789114A(A2), 789121A(A2), 789122A(A2), 789124A(A2), 789131A(A2), 789132A(A2),
789134A(A2), 78F9116B, 78F9136B, 78F9116B(A), 78F9136B(A), 78F9116B(A1),
78F9136B(A1)
• Addition of description related to expanded-specification products
• Addition of 1.1 Expanded-Specification Products and Conventional-Specification
CHAPTER 1 GENERAL
Products
(µPD789104A, 789114A
• Addition of 1.10 Differences Between Standard Quality Grade Products and (A),
SUBSERIES)
(A1), (A2) Products
Addition of 2.9 Differences Between Standard Quality Grade Products and (A), (A1), CHAPTER 2 GENERAL
(A2) Products
(µPD789124A, 789134A
SUBSERIES)
• Modification of description in 8.4.1 Operation as timer interrupt
• Modification of Figure 8-5 Timing of Timer Interrupt Operation
• Modification of description in 8.4.2 Operation as timer output
• Modification of description in Figure 8-7 Timer Output Timing
• Addition of 8.5 Notes on Using 16-Bit Timer 20
CHAPTER 8 16-BIT TIMER
20
Addition of description to 9.5 Notes on Using 8-Bit Timer/Event Counter 80
CHAPTER 9 8-BIT
TIMER/EVENT COUNTER
80
Addition of 11.5 (8) Input impedance of ANI0 to ANI3 pins
CHAPTER 11 8-BIT A/D
CONVERTER
(µPD789104A, 789124A
SUBSERIES)
• Modification of description in 12.2 (2) A/D conversion result register 0 (ADCR0)
• Addition of 12.5 (8) Input impedance of ANI0 to ANI3 pins
CHAPTER 12 10-BIT A/D
CONVERTER
(µPD789114A, 789134A
SUBSERIES)
• Modification of Figure 13-1 Block Diagram of Serial Interface 20
CHAPTER 13 SERIAL
• Addition of 13.3 (4) (c) Generation of serial clock from system clock in 3-wire serial INTERFACE 20
I/O mode
• Addition of 13.4.2 (2) (f) Reading receive data
Addition of Caution 3 in Figure 15-2 Format of Interrupt Request Flag Register
CHAPTER 15 INTERRUPT
FUNCTIONS
Revision of chapter
CHAPTER 18
µPD78F9116A, 78F9116B,
78F9136A, 78F9136B
412
User’s Manual U14643EJ2V0UD
APPENDIX D REVISION HISTORY
(2/2)
Edition
2nd
Major Revision from Previous Edition
Applied to:
Addition of chapters
CHAPTER 21 to CHAPTER
31 ELECTRICAL
SPECIFICATIONS
CHAPTER 32, CHAPTER 33
CHARACTERISTICS
CURVES (REFERENCE
VALUES)
CHAPTER 34, CHAPTER 35
EXAMPLE OF RC
OSCILLATOR FREQUENCY
CHARACTERISTICS
(REFERENCE VALUES)
CHAPTER 36 PACKAGE
DRAWING
CHAPTER 37
RECOMMENDED
SOLDERING CONDITIONS
Revision of appendix
Addition of appendices
APPENDIX A
DEVELOPMENT TOOLS
APPENDIX B NOTES ON
TARGET SYSTEM DESIGN
APPENDIX D REVISION
HISTORY
Deletion of APPENDIX B EMBEDDED SOFTWARE
−
413
User’s Manual U14643EJ2V0UD
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