UPD78F9201GR(T2)-AND-A [NEC]
Microcontroller, 8-Bit, FLASH, 10MHz, CMOS, PDSO8, 5.72 MM, LEAD FREE, PLASTIC, SOP-8;型号: | UPD78F9201GR(T2)-AND-A |
厂家: | NEC |
描述: | Microcontroller, 8-Bit, FLASH, 10MHz, CMOS, PDSO8, 5.72 MM, LEAD FREE, PLASTIC, SOP-8 微控制器 光电二极管 |
文件: | 总301页 (文件大小:2101K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary User’s Manual
78K0S/KU1+, 78K0S/KY1+
8-Bit Single-Chip Microcontrollers
µPD78F9200
µPD78F9201
µPD78F9202
µPD78F9210
µPD78F9211
µPD78F9212
Document No. U16994EJ2V0UD00 (2nd edition)
Date Published February 2005 NS CP(K)
©
2004
Printed in Japan
[MEMO]
2
Preliminary User’s Manual U16994EJ2V0UD
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
3
Preliminary User’s Manual U16994EJ2V0UD
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, inc.
•
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
• Not all products and/or types are available in every country. Please check with an NEC Electronics sales
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No part of this document may be copied or reproduced in any form or by any means without the prior written consent
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•
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Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M5D 02. 11-1
4
Preliminary User’s Manual U16994EJ2V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
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•
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Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
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Tel: 2886-9318
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Tel: 408-588-6000
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800-366-9782
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J04.1
5
Preliminary User’s Manual U16994EJ2V0UD
INTRODUCTION
Target Readers
This manual is intended for user engineers who wish to understand the functions of
the 78K0S/KU1+ and 78K0S/KY1+ in order to design and develop its application
systems and programs.
The target devices are the following subseries products.
• 78K0S/KU1+: µPD78F9200, 78F9201, 78F9202
• 78K0S/KY1+: µPD78F9210, 78F9211, 78F9212
Purpose
This manual is intended to give users on understanding of the functions described in
the Organization below.
Organization
Two manuals are available for 78K0S/KU1+ and 78K0S/KY1+: this manual and the
Instruction Manual (common to the 78K/0S Series).
78K/0S Series
78K0S/KU1+, 78K0S/KY1+
Instructions
User’s Manual
User’s Manual
• Pin functions
• CPU function
• Internal block functions
• Interrupts
• Instruction set
• Instruction description
• Other internal peripheral functions
• Electrical specifications (target)
How to Use This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
◊ To understand the overall functions of the 78K0S/KU1+ and 78K0S/KY1+
→ Read this manual in the order of the CONTENTS. The mark
revised points.
shows major
◊ How to read register formats
→ For a bit number enclosed in angle brackets (<>), the bit name is defined as a
reserved word in the RA78K0S, and is defined as an sfr variable using the
#pragma sfr directive in the CC78K0S.
◊ To learn the detailed functions of a register whose register name is known
→ See APPENDIX B REGISTER INDEX.
◊ To learn the details of the instruction functions of the 78K/0S Series
→ Refer to 78K/0S Series Instructions User’s Manual (U11047E) separately
available.
◊ To learn the electrical specifications (target) of the 78K0S/KU1+ and 78K0S/KY1+
→ See CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES).
6
Preliminary User’s Manual U16994EJ2V0UD
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note:
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
This manual
U11047E
78K0S/KU1+, 78K0S/KY1+ User’s Manual
78K/0S Series Instructions User’s Manual
Documents Related to Development Software Tools (User’s Manuals)
Document Name
Document No.
U16656E
U14877E
U11623E
U16654E
U14872E
U16584E
U17287E
U16934E
RA78K0S Assembler Package
CC78K0S C Compiler
Operation
Language
Structured Assembly Language
Operation
Language
ID78K0S-NS Ver. 2.52 Integrated Debugger
ID78K0S-QB Ver. 2.81 Integrated Debugger
PM plus Ver.5.20
Operation
Operation
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name
IE-78K0S-NS In-Circuit Emulator
Document No.
U13549E
IE-78K0S-NS-A In-Circuit Emulator
U15207E
QB-78K0SKX1MINI In-Circuit Emulator
U17272E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
7
Preliminary User’s Manual U16994EJ2V0UD
Documents Related to Flash Memory Writing
Document Name
Document No.
U15260E
PG-FP4 Flash Memory Programmer User’s Manual
PG-FPL2 Flash Memory Programmer User’s Manual
U17307E
Other Related Documents
Document Name
Document No.
X13769X
Note
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Quality Grades on NEC Semiconductor Devices
C11531E
C10983E
C11892E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
8
Preliminary User’s Manual U16994EJ2V0UD
CONTENTS
CHAPTER 1 OVERVIEW.........................................................................................................................14
1.1 Features ......................................................................................................................................14
1.2 Application Fields......................................................................................................................14
1.3 Ordering Information.................................................................................................................15
1.4 Pin Configuration (Top View) ...................................................................................................17
1.5 78K0S/Kx1+ Product Lineup.....................................................................................................19
1.6 Block Diagram............................................................................................................................20
1.7 Functional Outline .....................................................................................................................21
CHAPTER 2 PIN FUNCTIONS...............................................................................................................22
2.1 Pin Function List........................................................................................................................22
2.2 Pin Functions .............................................................................................................................24
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
P20 to P23 (Port 2)...................................................................................................................... 24
P32 and P34 (Port 3)................................................................................................................... 25
P40 to P47 (Port 4)...................................................................................................................... 25
RESET ........................................................................................................................................ 25
X1 and X2 ................................................................................................................................... 25
VDD .............................................................................................................................................. 25
VSS............................................................................................................................................... 25
2.3 Pin I/O Circuits and Connection of Unused Pins ...................................................................26
CHAPTER 3 CPU ARCHITECTURE......................................................................................................28
3.1 Memory Space............................................................................................................................28
3.1.1
3.1.2
3.1.3
3.1.4
Internal program memory space.................................................................................................. 31
Internal data memory space........................................................................................................ 32
Special function register (SFR) area ........................................................................................... 32
Data memory addressing ............................................................................................................ 32
3.2 Processor Registers..................................................................................................................35
3.2.1
3.2.2
3.2.3
Control registers.......................................................................................................................... 35
General-purpose registers........................................................................................................... 38
Special function registers (SFRs)................................................................................................ 39
3.3 Instruction Address Addressing..............................................................................................42
3.3.1
3.3.2
3.3.3
3.3.4
Relative addressing..................................................................................................................... 42
Immediate addressing................................................................................................................. 43
Table indirect addressing ............................................................................................................ 43
Register addressing .................................................................................................................... 44
3.4 Operand Address Addressing..................................................................................................45
3.4.1
3.4.2
3.4.3
3.4.4
Direct addressing ........................................................................................................................ 45
Short direct addressing ............................................................................................................... 46
Special function register (SFR) addressing ................................................................................. 47
Register addressing .................................................................................................................... 48
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Preliminary User’s Manual U16994EJ2V0UD
3.4.5
3.4.6
3.4.7
Register indirect addressing ........................................................................................................49
Based addressing........................................................................................................................50
Stack addressing.........................................................................................................................50
CHAPTER 4 PORT FUNCTIONS...........................................................................................................51
4.1 Functions of Ports .....................................................................................................................51
4.2 Port Configuration .....................................................................................................................52
4.2.1
4.2.2
4.2.3
Port 2...........................................................................................................................................52
Port 3...........................................................................................................................................55
Port 4 (78K0S/KY1+ only) ...........................................................................................................56
4.3 Registers Controlling Port Functions......................................................................................57
4.4 Operation of Port Function .......................................................................................................62
4.4.1
4.4.2
4.4.3
Writing to I/O port ........................................................................................................................62
Reading from I/O port..................................................................................................................62
Operations on I/O port.................................................................................................................62
CHAPTER 5 CLOCK GENERATORS...................................................................................................63
5.1 Functions of Clock Generators ................................................................................................63
5.1.1
5.1.2
System clock oscillators...............................................................................................................63
Clock oscillator for interval time generation .................................................................................63
5.2 Configuration of Clock Generators..........................................................................................64
5.3 Registers Controlling Clock Generators .................................................................................66
5.4 System Clock Oscillators..........................................................................................................69
5.4.1
5.4.2
5.4.3
5.4.4
High-speed Ring-OSC oscillator..................................................................................................69
Crystal/ceramic oscillator.............................................................................................................69
External clock input circuit ...........................................................................................................71
Prescaler .....................................................................................................................................71
5.5 Operation of CPU Clock Generator..........................................................................................72
5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware.............................78
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00.............................................................................80
6.1 Functions of 16-Bit Timer/Event Counter 00...........................................................................80
6.2 Configuration of 16-Bit Timer/Event Counter 00 ....................................................................81
6.3 Registers to Control 16-Bit Timer/Event Counter 00..............................................................85
6.4 Operation of 16-Bit Timer/Event Counter 00 ...........................................................................91
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Interval timer operation................................................................................................................91
External event counter operation.................................................................................................93
Pulse width measurement operations..........................................................................................96
Square-wave output operation...................................................................................................104
PPG output operations ..............................................................................................................106
One-shot pulse output operation ...............................................................................................109
6.5 Cautions Related to 16-Bit Timer/Event Counter 00.............................................................114
CHAPTER 7 8-BIT TIMER H1 .............................................................................................................120
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Preliminary User’s Manual U16994EJ2V0UD
7.1 Functions of 8-Bit Timer H1....................................................................................................120
7.2 Configuration of 8-Bit Timer H1 .............................................................................................120
7.3 Registers Controlling 8-Bit Timer H1.....................................................................................123
7.4 Operation of 8-Bit Timer H1....................................................................................................125
7.4.1
7.4.2
Operation as interval timer/square-wave output........................................................................ 125
Operation as PWM output mode ............................................................................................... 129
CHAPTER 8 WATCHDOG TIMER.......................................................................................................135
8.1 Functions of Watchdog Timer................................................................................................135
8.2 Configuration of Watchdog Timer..........................................................................................137
8.3 Registers Controlling Watchdog Timer.................................................................................138
8.4 Operation of Watchdog Timer ................................................................................................140
8.4.1
8.4.2
8.4.3
8.4.4
Watchdog timer operation when “low-speed Ring-OSC cannot be stopped” is selected by
option byte................................................................................................................................. 140
Watchdog timer operation when “low-speed Ring-OSC can be stopped by software” is
selected by option byte.............................................................................................................. 142
Watchdog timer operation in STOP mode (when “low-speed Ring-OSC can be
stopped by software” is selected by option byte)....................................................................... 144
Watchdog timer operation in HALT mode (when “low-speed Ring-OSC can be
stopped by software” is selected by option byte)....................................................................... 145
CHAPTER 9 A/D CONVERTER...........................................................................................................146
9.1 Functions of A/D Converter....................................................................................................146
9.2 Configuration of A/D Converter..............................................................................................148
9.3 Registers Used by A/D Converter ..........................................................................................150
9.4 A/D Converter Operations.......................................................................................................155
9.4.1
9.4.2
9.4.3
Basic operations of A/D converter............................................................................................. 155
Input voltage and conversion results......................................................................................... 157
A/D converter operation mode................................................................................................... 158
9.5 How to Read A/D Converter Characteristics Table..............................................................160
9.6 Cautions for A/D Converter ....................................................................................................162
CHAPTER 10 INTERRUPT FUNCTIONS............................................................................................165
10.1 Interrupt Function Types.........................................................................................................165
10.2 Interrupt Sources and Configuration.....................................................................................165
10.3 Interrupt Function Control Registers.....................................................................................166
10.4 Interrupt Servicing Operation.................................................................................................169
10.4.1
10.4.2
10.4.3
Maskable interrupt request acknowledgment operation ............................................................ 169
Multiple interrupt servicing......................................................................................................... 171
Interrupt request pending .......................................................................................................... 172
CHAPTER 11 STANDBY FUNCTION..................................................................................................173
11.1 Standby Function and Configuration ....................................................................................173
11.1.1
Standby function........................................................................................................................ 173
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Preliminary User’s Manual U16994EJ2V0UD
11.1.2
Registers used during standby ..................................................................................................175
11.2 Standby Function Operation...................................................................................................176
11.2.1
11.2.2
HALT mode ...............................................................................................................................176
STOP mode...............................................................................................................................179
CHAPTER 12 RESET FUNCTION .......................................................................................................183
12.1 Register for Confirming Reset Source...................................................................................190
CHAPTER 13 POWER-ON-CLEAR CIRCUIT .....................................................................................191
13.1 Functions of Power-on-Clear Circuit .....................................................................................191
13.2 Configuration of Power-on-Clear Circuit...............................................................................192
13.3 Operation of Power-on-Clear Circuit......................................................................................192
13.4 Cautions for Power-on-Clear Circuit......................................................................................193
CHAPTER 14 LOW-VOLTAGE DETECTOR .......................................................................................195
14.1 Functions of Low-Voltage Detector .......................................................................................195
14.2 Configuration of Low-Voltage Detector.................................................................................195
14.3 Registers Controlling Low-Voltage Detector ........................................................................196
14.4 Operation of Low-Voltage Detector........................................................................................198
14.5 Cautions for Low-Voltage Detector........................................................................................201
CHAPTER 15 OPTION BYTE................................................................................................................204
CHAPTER 16 FLASH MEMORY..........................................................................................................207
16.1 Features ....................................................................................................................................207
16.2 Memory Configuration.............................................................................................................208
16.3 Functional Outline....................................................................................................................208
16.4 Writing with Flash Programmer..............................................................................................209
16.5 Programming Environment.....................................................................................................210
16.6 Processing of Pins on Board..................................................................................................213
16.6.1
16.6.2
16.6.3
16.6.4
X1 and X2 pins ..........................................................................................................................213
RESET pin.................................................................................................................................214
Port pins ....................................................................................................................................215
Power supply.............................................................................................................................215
16.7 On-board and Off-board Flash Memory Programming.........................................................215
16.7.1
16.7.2
16.7.3
16.7.4
Controlling flash memory...........................................................................................................215
Flash memory programming mode............................................................................................216
Communication commands .......................................................................................................216
Security settings ........................................................................................................................217
16.8 Flash Memory Programming by Self Writing ........................................................................218
16.8.1
16.8.2
16.8.3
16.8.4
Outline of self programming.......................................................................................................218
Cautions on self programming function .....................................................................................220
Registers used for self programming function ...........................................................................221
Example of shifting normal mode to self programming mode....................................................228
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Preliminary User’s Manual U16994EJ2V0UD
16.8.5
16.8.6
16.8.7
16.8.8
16.8.9
Example of shifting self programming mode to normal mode.................................................... 231
Example of block erase operation in self programming mode................................................... 234
Example of block blank check operation in self programming mode ......................................... 237
Example of byte write operation in self programming mode...................................................... 240
Example of internal verify operation in self programming mode................................................ 243
16.8.10 Examples of operation when command execution time should be minimized in self
programming mode .................................................................................................................. 246
16.8.11 Examples of operation when interrupt-disabled time should be minimized in self
programming mode ................................................................................................................... 253
CHAPTER 17 INSTRUCTION SET OVERVIEW.................................................................................264
17.1 Operation ..................................................................................................................................264
17.1.1
17.1.2
17.1.3
Operand identifiers and description methods ............................................................................ 264
Description of “Operation” column............................................................................................. 265
Description of “Flag” column...................................................................................................... 265
17.2 Operation List...........................................................................................................................266
17.3 Instructions Listed by Addressing Type...............................................................................271
CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES).............................................274
CHAPTER 19 PACKAGE DRAWING ..................................................................................................286
19.1 Package drawing of the 78K0S/KU1+ ....................................................................................286
19.2 Package drawing of the 78K0S/KY1+ ....................................................................................287
APPENDIX A DEVELOPMENT TOOLS ..............................................................................................288
A.1 Software Package ....................................................................................................................291
A.2 Language Processing Software .............................................................................................291
A.3 Control Software......................................................................................................................292
A.4 Flash Memory Writing Tools...................................................................................................292
A.5 Debugging Tools (Hardware)..................................................................................................293
A.5.1
A.5.2
When using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A........................................ 293
When using in-circuit emulator QB-78K0SKX1MINI............................................................. 293
A.6 Debugging Tools (Software)...................................................................................................294
APPENDIX B REGISTER INDEX.........................................................................................................296
B.1 Register Index (Register Name) .............................................................................................296
B.2 Register Index (Symbol)..........................................................................................................298
APPENDIX C REVISION HISTORY......................................................................................................300
C.1 Major Revisions in This Edition .............................................................................................300
13
Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 1 OVERVIEW
1.1 Features
O Minimum instruction execution time selectable from high speed (0.2 µs) and low speed (3.2 µs) (with CPU clock
of 10 MHz)
O General-purpose registers: 8 bits × 8 registers
O ROM and RAM capacities
Item
Program Memory (Flash Memory)
Memory (Internal High-Speed RAM)
Part number
µPD78F9200, 78F9210
µPD78F9201, 78F9211
µPD78F9202, 78F9212
1 KB
2 KB
4 KB
128 bytes
O On-chip power-on clear (POC) circuit and low voltage detector (LVI)
O On-chip watchdog timer (operable on internal low-speed Ring-OSC clock)
O I/O ports
• µPD78F9200, 78F9201, 78F9202: 6
• µPD78F9210, 78F9211, 78F9212: 14
O Timer: 3 channels
• 16-bit timer/event counter: 1 channel
• 8-bit timer:
1 channel
1 channel
• Watchdog timer:
O 10-bit resolution A/D converter: 4 channels
O Supply voltage: VDD = 2.0 to 5.5 VNote
O Operating temperature range: TA = −40 to +85°C
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on
clear (POC) circuit is 2.1 V 0.1 V.
1.2 Application Fields
O Automotive electronics
• System control of body instrumentation system (such as power windows and keyless entry reception)
• Sub-microcontroller of control system
O Household appliances
• Electric toothbrushes
• Electric shavers
O Toys
O Industrial equipment
• Sensor and switch control
• Power tools
14
Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 1 OVERVIEW
1.3 Ordering Information
(1) 78K0S/KU1+
Part Number
Package
Quality Grade
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
µ PD78F9200GR(T)-AND
µ PD78F9200GR(T2)-AND
µ PD78F9200GR(S)-AND
µ PD78F9200GR(T)-AND-A
µ PD78F9200GR(T2)-AND-A
µ PD78F9200GR(S)-AND-A
µ PD78F9201GR(T)-AND
µ PD78F9201GR(T2)-AND
µ PD78F9201GR(S)-AND
µ PD78F9201GR(T)-AND-A
µ PD78F9201GR(T2)-AND-A
µ PD78F9201GR(S)-AND-A
µ PD78F9202GR(T)-AND
µ PD78F9202GR(T2)-AND
µ PD78F9202GR(S)-AND
µ PD78F9202GR(T)-AND-A
µ PD78F9202GR(T2)-AND-A
µ PD78F9202GR(S)-AND-A
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
8-pin plastic SOP (5.75mm (225))
Remark The µPD78F9200GR(xx)-AND-A, 78F9201GR(xx)-AND-A, and 78F9202GR(xx)-AND-A are lead-free
products.
xx : T, T2, S
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The 78K0S/KU1+ standard grade products are further classified as follows.
(T), (T2): General management
(S):
Management based on individual contract
15
Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 1 OVERVIEW
(2) 78K0S/KY1+
Part Number
Package
Quality Grade
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
µ PD78F9210GR(T)-JJG
µ PD78F9210GR(T2)-JJG
µ PD78F9210GR(S)-JJG
µ PD78F9210GR(R)-JJG
µ PD78F9210GR(T)-JJG-A
µ PD78F9210GR(T2)-JJG-A
µ PD78F9210GR(S)-JJG-A
µ PD78F9210GR(R)-JJG-A
µ PD78F9211GR(T)-JJG
µ PD78F9211GR(T2)-JJG
µ PD78F9211GR(S)-JJG
µ PD78F9211GR(R)-JJG
µ PD78F9211GR(T)-JJG-A
µ PD78F9211GR(T2)-JJG-A
µ PD78F9211GR(S)-JJG-A
µ PD78F9211GR(R)-JJG-A
µ PD78F9212GR(T)-JJG
µ PD78F9212GR(T2)-JJG
µ PD78F9212GR(S)-JJG
µ PD78F9212GR(R)-JJG
µ PD78F9212GR(T)-JJG-A
µ PD78F9212GR(T2)-JJG-A
µ PD78F9212GR(S)-JJG-A
µ PD78F9212GR(R)-JJG-A
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
16-pin plastic SSOP (5.72 mm (225))
Remark The µPD78F9210GR(xx)-JJG-A, 78F9211GR(xx)-JJG-A, and 78F9212GR(xx)-JJG-A are lead-free
products.
xx : T, T2, S, R
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The 78K0S/KY1+ standard grade products are further classified as follows.
(T), (T2): General management
(S):
(R):
Management based on individual contract
Management for automotive accessories
16
Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 1 OVERVIEW
1.4 Pin Configuration (Top View)
(1) 78K0S/KU1+
8-pin plastic SOP (5.72mm (225))
Note1
Note2
SS
V
DD
1
2
3
4
V
8
7
6
5
P22/ANI0/TI000/TOH1
P21/ANI1/TI010/TO00/INTP0
P32/INTP1
P23/X1/ANI3
P22/X2/ANI2
P34/RESET
Notes 1. In the 78K0S/KU1+, VDD functions alternately as the A/D converter reference voltage input. When using
the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
2. In the 78K0S/KU1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
ANI0 to ANI3:
INTP0, INTP1:
P20 to P23:
P30, P34:
Analog input
External interrupt input
Port 2
TI000, TI010:
TO00, TOH1:
VDD:
Timer input
Timer output
Power supply
Port 3
VSS:
Ground
RESET:
Reset
X1, X2:
Crystal oscillator (X1 input clock)
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 1 OVERVIEW
(2) 78K0S/KY1+
16-pin plastic SSOP (5.72 mm (225))
P22/ANI0/TI000/TOH1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P21/ANI1/TI010/TO00/INTP0
P41
P42
P40
P43
Note1
SS
V
P32/INTP1
P34/RESET
P44
Note2
DD
V
P47
P46
P45
P23/X1/ANI3
P22/X2/ANI2
Notes 1. In the 78K0S/KY1+, VDD functions alternately as the A/D converter reference voltage input. When using
the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
2. In the 78K0S/KY1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
ANI0 to ANI3:
INTP0, INTP1:
P20 to P23:
P30, P34:
Analog input
External interrupt input
Port 2
TI000, TI010:
TO00, TOH1:
VDD:
Timer input
Timer output
Power supply
Port 3
VSS:
Ground
P40 to P47:
RESET:
Port 4
X1, X2:
Crystal oscillator (X1 input clock)
Reset
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 1 OVERVIEW
1.5 78K0S/Kx1+ Product Lineup
The following table shows the product lineup of the 78K0S/Kx1+.
Part Number
78K0S/KU1+
78K0S/KY1+
78K0S/KA1+
20 pins
78K0S/KB1+
Item
Number of pins
8 pins
16 pins
1 KB, 2 KB, 4 KB
128 bytes
30 pins
4 KB, 8 KB
256 bytes
Internal
memory
Flash memory
RAM
1 KB, 2 KB, 4 KB
128 bytes
2 KB
128 bytes
4 KB
256
bytes
VDD = 2.0 to 5.5 VNote
Supply voltage
Minimum instruction
execution time
0.20 µs (10 MHz, VDD = 4.0 to 5.5 V)
0.33 µs (6 MHz, VDD = 3.0 to 5.5 V)
0.40 µs (5 MHz, VDD = 2.7 to 5.5 V)
1.0 µs (2 MHz, VDD = 2.0 to 5.5 V)
Internal high-speed Ring-OSC oscillation (8 MHz (TYP.))
Crystal/ceramic oscillation (1 to 10 MHz)
System clock
(oscillation frequency)
External clock input oscillation (1 to 10 MHz)
Clock for TMH1 and WDT
(oscillation frequency)
Internal low-speed Ring-OSC oscillation (240 kHz (TYP.))
Port
CMOS I/O
CMOS input
CMOS output
16-bit (TM0)
8-bit (TMH)
8-bit (TM8)
WDT
5
1
−
13
1
15
1
22
1
−
1
1
Timer
1 ch
1 ch
−
−
1 ch
1 ch
Serial interface
A/D converter
LIN-Bus-supporting UART: 1 ch
10 bits: 4 ch (2.7 to 5.5V)
Multiplier (8 bits × 8 bits)
Interrupts External
Internal
−
Provided
2
5
4
9
Reset
RESET pin
POC
Provided
2.1 V 0.1 V
LVI
Provided (selectable by software)
Provided
WDT
Operating temperature range
−40 to +85°C
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on- clear
(POC) circuit is 2.1 V 0.1 V.
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 1 OVERVIEW
1.6 Block Diagram
TO00/TI010/P21
TI000/P20
4
PORT 2
PORT 3
P20-P23
16-bit TIMER/
EVENT COUNTER 00
P32
P34
TOH1/P20
78K0S
FLASH
CPU
8-bit TIMER H1
MEMORY
CORE
PORT 4Note1
P40-P47Note1
8
LOW-SPEED
Ring-OSC
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
ANI0/P20-
4
A/D CONVERTER
ANI3/P23
INTERNAL
HIGH-SPEED
RAM
RESET CONTROL
INTP0/P21
INTP1/P32
INTERRUPT
CONTROL
RESET/P34
X1/P23
SYSTEM
CONTROL
X2/P22
HIGH-SPEED
Ring-OSC
Note3
DDNote2 VSS
V
Notes 1. 78K0S/KY1+ only. When using the 78K0S/KU1+, set port mode register 4 (PM4) to 00H when initially
setting the program.
2. In the 78K0S/KU1+ and 78K0S/KY1+, VDD functions alternately as the A/D converter reference voltage
input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
3. In the 78K0S/KU1+ and 78K0S/KY1+, VSS functions alternately as the ground potential of the A/D
converter. Be sure to connect VSS to a stabilized GND (= 0 V).
20
Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 1 OVERVIEW
1.7 Functional Outline
Item
78K0S/KU1+
78K0S/KY1+
µPD78F9210: 1 KB
Internal
memory
Flash memory
µPD78F9200: 1 KB
µPD78F9201: 2 KB
µPD78F9202: 4 KB
128 bytes
µPD78F9211: 2 KB
µPD78F9212: 4 KB
High-speed RAM
Memory space
64 KB
X1 input clock (oscillation frequency)
Crystal/ceramic/external clock input:
10 MHz (VDD = 2.0 to 5.5 V)
Ring-OSC High speed (oscillation
Internal Ring oscillation: 8 MHz (TYP.)
Internal Ring oscillation: 240 kHz (TYP.)
8 bits × 8 registers
clock
frequency)
Low speed (for TMH1
and WDT)
General-purpose registers
Minimum instruction execution time
Instruction set
0.2 µs/0.4 µs/0.8 µs/1.6 µs/3.2 µs (X1 input clock: fX = 10 MHz)
• 16-bit operation
• Bit manipulation (set, reset, test), etc.
I/O port
Timer
Total:
6 pins
5 pins
1 pin
Total:
14 pins
13 pins
1 pin
CMOS I/O:
CMOS input:
CMOS I/O:
CMOS input:
• 16-bit timer/event counter: 1 channel
• 8-bit timer (timer H1):
• Watchdog timer:
1 channel
1 channel
Timer output
A/D converter
2 pins (PWM: 1 pin)
10-bit resolution × 4 channels
Vectored
External
Internal
2
interrupt sources
5
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on clear
• Internal reset by low-voltage detector
VDD = 2.0 to 5.5 VNote
Supply voltage
Operating temperature range
Package
TA = −40 to +85°C
8-pin plastic SOP (5.72mm (225))
16-pin plastic SSOP(5.72 mm(225))
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on- clear
(POC) circuit is 2.1 V 0.1 V.
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
(1) Port pins
Pin Name
I/O
Function
After Reset Alternate-Function
Pin
P20
I/O
Port 2.
Input
ANI0/TI000/TOH1
4-bit I/O port.
P21
ANI1/TI010/
TO00/INTP0
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected by setting
software.
P22
P23
P32
X2/ANI2
X1/ANI3
INTP1
I/O
Port 3
Can be set to input or output mode in
1-bit units.
Input
An on-chip pull-up resistor can be
connected by setting software.
P34
Input
I/O
Input only
Input
Input
RESET
P40 to P47Note
Port 4.
−
8-bit I/O port.
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected by setting
software.
Note The P40 to P47 pins are provided only in the 78K0S/KY1+. When using the 78K0S/KU1+, set port mode
register 4 (PM4) to 00H when initially setting the program.
Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset.
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin Name
I/O
Function
After Reset
Input
Alternate-
Function Pin
INTP0
Input
External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
P21/ANI1/TI010/
TO00
INTP1
TI000
P32
Input
External count clock input to 16-bit timer/event counter 00.
Capture trigger input to capture registers (CR000 and CR010) of
16-bit timer/event counter 00
Input
P20/ANI0/TOH1
TI010
TO00
Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
P21/ANI1/TO00/
INTP0
Output
16-bit timer/event counter 00 output
Input
P21/ANI1/TI010/
INTP0
TOH1
ANI0
ANI1
Output
Input
8-bit timer H1 output
Input
Input
P20/ANI0/TI000
P20/TI000/TOH1
Analog input of A/D converter
P21/TI010/TO00/
INTP0
ANI2
ANI3
RESET
X1
P22/X2
P23/X1
P34
Input
Input
System reset input
Input
Connection of crystal/ceramic oscillator for system clock
oscillation.
−
P23/ANI3
External clock input
X2
−
Connection of crystal/ceramic oscillator for system clock
oscillation.
−
P22/ANI2
VDD
VSS
−
−
Positive power supply
Ground potential
−
−
−
−
Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset.
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.2 Pin Functions
2.2.1 P20 to P23 (Port 2)
P20 to P23 constitute a 4-bit I/O port. In addition to the function as I/O port pins, these pins also have a function to
input an analog signal to the A/D converter, input/output a timer signal, and input an external interrupt request signal.
P22 and P23 are also function as the X1 and X2 pins, respectively.
These pins can be set to the following operation modes in 1-bit units.
(1) Port mode
P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using
port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pull-
up resistor option register 2 (PU2).
(2) Control mode
P20 to P23 function to input an analog signal to the A/D converter, input/output a timer signal, and input an
external interrupt request signal.
(a) ANI0 to ANI3
These are the analog input pins of the A/D converter. When using these pins as analog input pins, refer
to 9.6 Cautions for A/D converter (5) ANI0/P20 to ANI3/P23.
(b) TI000
This pin inputs an external count clock to 16-bit timer/event counter 00, or a capture trigger signal to the
capture registers (CR000 and CR010) of 16-bit timer/event counter 00.
(c) TI010
This pin inputs a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00.
(d) TO00
This pin outputs a signal from 16-bit timer/event counter 00.
(e) TOH1
This pin outputs a signal from 8-bit timer H1.
(f) INTP0
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset.
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.2.2 P32 and P34 (Port 3)
P32 is a 1-bit I/O port. In addition to the function as an I/O port pin, this pin also has a function to input an external
interrupt request signal.
P34 is a 1-bit input-only port. This pin is also used as a RESET pin.
P32 can be set to the following operation modes in 1-bit units.
(1) Port mode
P32 functions as a 1-bit I/O port. This pin can be set to the input or output mode by using port mode register 3
(PM3). In addition, an on-chip pull-up resistor can be connected to the port by using pull-up resistor option
register 3 (PU3).
P34 functions as a 1-bit input-only port.
(2) Control mode
P32 functions as an external interrupt request input pin (INTP1) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified. .
2.2.3 P40 to P47 (Port 4)Note
P40 to P47 constitute a 8-bit I/O port. Each bit of this port can be set to the input or output mode by using port
mode register 4 (PM4). In addition, an on-chip pull-up resistor can be connected to the port by using pull-up resistor
option register 4 (PU4).
Note The P40 to P47 pins are provided only in the 78K0S/KY1+. When using the 78K0S/KU1+, set port mode
register 4 (PM4) to 00H when initially setting the program.
2.2.4 RESET
This pin inputs an active-low system reset signal.
2.2.5 X1 and X2
These pins connect an oscillator to oscillate the X1 input clock.
Supply an external clock to X1.
Caution P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset.
2.2.6 VDD
This is the positive power supply pin.
In the 78K0S/KU1+ and 78K0S/KY1+, VDD functions alternately as the A/D converter reference voltage input.
When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
2.2.7 VSS
This is the ground pin.
In the 78K0S/KU1+ and 78K0S/KY1+, VSS functions alternately as the ground potential of the A/D converter. Be
sure to connect VSS to a stabilized GND (= 0 V).
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Connection of Unused Pins
Table 2-1 shows I/O circuit type of each pin and the connections of unused pins.
For the configuration of the I/O circuit of each type, refer to Figure 2-1.
Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins
Pin Name
P20/ANI0/TI000/TOH1
P21/ANI1/TI010/TO00/
INTP0
I/O Circuit Type
11
I/O
Recommended Connection of Unused Pin
I/O
Input: Individually connect to VDD or VSS via resistor.
Output: Leave open.
P22/ANI2/X2
36
Input: Individually connect to VSS via resistor.
Output: Leave open.
P23/ANI3/X1
P32/INTP1
8-A
Input: Individually connect to VDD or VSS via resistor.
Output: Leave open.
P34/RESET
2
Input
I/O
Connect to VDD via resistor.
P40 to P47Note
8-A
Input: Individually connect to VDD or VSS via resistor.
Output: Leave open.
Note The P40 to P47 pins are provided only in the 78K0S/KY1+. When using the 78K0S/KU1+, set port mode
register 4 (PM4) to 00H when initially setting the program.
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits
Type 36
Type 2
feedback
cut-off
IN
P-ch
Schmitt-triggered input with hysteresis characteristics
OSC
enable
X1,
X2,
IN/OUT
IN/OUT
VDD
Type 8-A
pullup
enable
V
DD
P-ch
V
DD
Pull up
enable
P-ch
data
P-ch
VDD
output
N-ch
disable
Data
P-ch
Comparator
P-ch
N-ch
IN/OUT
+
-
Output
disable
N-ch
V
SS
V
DD
(Threshold voltage)
VDD
pullup
enable
P-ch
VDD
Type 11
data
V
DD
P-ch
Pull up
enable
P-ch
output
disable
N-ch
V
DD
Data
Comparator
P-ch
P-ch
N-ch
+
IN/OUT
-
V
SS
Output
disable
N-ch
V
DD
(Threshold voltage)
Comparator
P-ch
N-ch
+
-
V
SS
V
DD
(Threshold voltage)
Input
enable
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The 78K0S/KU1+ and 78K0S/KY1+ can access up to 64 KB of memory space. Figures 3-1 to 3-3 show the
memory maps.
Figure 3-1. Memory Map (µPD78F9200, 78F9210)
F F F F H
Special function registers
(SFR)
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Use prohibited
Data memory
space
0 3 F F H
0 4 0 0 H
0 3 F F H
Program area
0 0 8 2 H
0 0 8 1 H
0 0 8 0 H
0 0 7 F H
Protect byte area
Option byte area
Program memory
space
Flash memory
1024 × 8 bits
CALLT table area
0 0 4 0 H
0 0 3 F H
Program area
0 0 1 4 H
0 0 1 3 H
Vector table area
0 0 0 0 H
0 0 0 0 H
Remark The option byte and protect byte are 1 byte each.
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Preliminary User’s Manual U16994EJ2V0UD
CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (µPD78F9201, 78F9211)
F F F F H
Special function registers
(SFR)
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Use prohibited
Data memory
space
0 7 F F H
0 8 0 0 H
0 7 F F H
Program area
0 0 8 2 H
0 0 8 1 H
0 0 8 0 H
0 0 7 F H
Protect byte area
Option byte area
Flash memory
2,048 × 8 bits
Program memory
space
CALLT table area
0 0 4 0 H
0 0 3 F H
Program area
0 0 1 4 H
0 0 1 3 H
Vector table area
0 0 0 0 H
0 0 0 0 H
Remark The option byte and protect byte are 1 byte each.
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Figure 3-3. Memory Map (µPD78F9202, 78F9212)
F F F F H
Special function registers
(SFR)
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F D 7 F H
Use prohibited
Data memory
space
0 F F F H
1 0 0 0 H
0 F F F H
Program area
0 0 8 2 H
0 0 8 1 H
0 0 8 0 H
0 0 7 F H
Protect byte area
Option byte area
Flash memory
4,096 × 8 bits
Program memory
space
CALLT table area
0 0 4 0 H
0 0 3 F H
Program area
0 0 1 4 H
0 0 1 3 H
Vector table area
0 0 0 0 H
0 0 0 0 H
Remark The option byte and protect byte are 1 byte each.
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CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The 78K0S/KU1+ and 78K0S/KY1+ provide the following internal ROMs (or flash memory) containing the following
capacities.
Table 3-1. Internal ROM Capacity
Part Number
Internal ROM
Structure
Flash memory
Capacity
1,024 × 8 bits
µPD78F9200, 78F9210
µPD78F9201, 78F9211
µPD78F9202, 78F9212
2,048 × 8 bits
4,096 × 8 bits
The following areas are allocated to the internal program memory space.
(1) Vector table area
The 20-byte area of addresses 0000H to 0013H is reserved as a vector table area. This area stores program
start addresses to be used when branching by RESET input or interrupt request generation. Of a
16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd
address.
Table 3-2. Vector Table
Vector Table Address
0000H
Interrupt Request
Reset input
Vector Table Address
000CH
Interrupt Request
INTTMH1
0006H
0008H
000AH
INTLVI
INTP0
INTP1
000EH
0010H
0012H
INTTM000
INTTM010
INTAD
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
(3) Option byte area
The option byte area is the 1-byte area of address 0080H. For details, refer to CHAPTER 15 OPTION
BYTE.
(4) Protect byte area
The protect byte area is the 1-byte area of address 0081H. For details, refer to CHAPTER 16 FLASH
MEMORY.
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3.1.2 Internal data memory space
128-byte internal high-speed RAM is provided in the 78K0S/KU1+ and 78K0S/KY1+.
The internal high-speed RAM can also be used as a stack memory.
3.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see
Table 3-3).
3.1.4 Data memory addressing
The 78K0S/KU1+ and 78K0S/KY1+ are provided with a wide range of addressing modes to make memory
manipulation as efficient as possible. The area (FE80H to FEFFH) which contains a data memory and the special
function register (SFR) area can be accessed using a unique addressing mode in accordance with each function.
Figures 3-4 to 3-6 illustrate the data memory addressing.
Figure 3-4. Data Memory Addressing (µPD78F9200, 78F9210)
F F F F H
Special function registers (SFR)
SFR addressing
256 × 8 bits
F F 2 0 H
F E 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Direct addressing
Register indirect addressing
Based addressing
Use prohibted
0 4 0 0 H
0 3 F F H
Flash memory
1,024 × 8 bits
0 0 0 0 H
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Figure 3-5. Data Memory Addressing (µPD78F9201, 78F9211)
F F F F H
Special function registers (SFR)
SFR addressing
256 × 8 bits
F F 2 0 H
F E 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Direct addressing
Register indirect addressing
Based addressing
Use prohibted
0 8 0 0 H
0 7 F F H
Flash memory
2,048 × 8 bits
0 0 0 0 H
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Figure 3-6. Data Memory Addressing (µPD78F9202, 78F9212)
F F F F H
Special function registers (SFR)
SFR addressing
256 × 8 bits
F F 2 0 H
F E 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
128 × 8 bits
F E 8 0 H
F E 7 F H
Direct addressing
Register indirect addressing
Based addressing
Use prohibted
1 0 0 0 H
0 F F F H
Flash memory
4,096 × 8 bits
0 0 0 0 H
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3.2 Processor Registers
The 78K0S/KU1+ and 78K0S/KY1+ provide the following on-chip processor registers.
3.2.1 Control registers
The control registers have special functions to control the program sequence statuses and stack memory. The
control registers include a program counter, a program status word, and a stack pointer.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to
be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-7. Program Counter Configuration
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 3-8. Program Status Word Configuration
7
0
IE
Z
0
AC
0
0
1
CY
PSW
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(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt
are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
(d) Carry flag (CY)
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
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(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 3-9. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.
Caution Since reset input makes SP contents undefined, be sure to initialize the SP before using the
stack memory.
Figure 3-10. Data to Be Saved to Stack Memory
Interrupt
PUSH rp
instruction
CALL, CALLT
instructions
_
_
_
_
SP
SP
SP
SP
SP
3
3
2
1
_
_
_
_
_
_
SP
SP
SP
SP
2
2
1
SP
SP
SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Lower half
register pairs
PC7 to PC0
Upper half
register pairs
PC15 to PC8
SP
SP
SP
Figure 3-11. Data to Be Restored from Stack Memory
POP rp
RET instruction
RETI instruction
instruction
Lower half
register pairs
SP
SP
PC7 to PC0
SP
PC7 to PC0
PC15 to PC8
PSW
Upper half
register pairs
PC15 to PC8
SP + 1
SP + 2
SP + 1
SP + 2
SP + 1
SP + 2
SP + 3
SP
SP
SP
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3.2.2 General-purpose registers
A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).
In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register
(AX, BC, DE, and HL).
Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Figure 3-12. General-Purpose Register Configuration
(a) Absolute names
16-bit processing
RP3
8-bit processing
R7
R6
R5
R4
RP2
RP1
RP0
R3
R2
R1
R0
15
0
7
0
(b) Function names
16-bit processing
HL
8-bit processing
H
L
D
E
DE
BC
AX
B
C
A
X
15
0
7
0
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3.2.3 Special function registers (SFRs)
Unlike the general-purpose registers, each special function register has a special function.
The special function registers are allocated to the 256-byte area FF00H to FFFFH.
The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and
bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register
type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying
an address, describe an even address.
Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:
• Symbol
Indicates the addresses of the implemented special function registers. It is defined as a reserved word in the
RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. Therefore, these
symbols can be used as instruction operands if an assembler or integrated debugger is used.
• R/W
Indicates whether the special function register can be read or written.
R/W: Read/write
R: Read only
W: Write only
• Number of bits manipulated simultaneously
Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.
• After reset
Indicates the status of the special function register when a reset is input.
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Table 3-3. Special Function Registers (1/2)
Address
Special Function Register (SFR) Name
Symbol
R/W
Number of Bits Manipulated
Simultaneously
After Reset
00H
1 Bit
8 Bits
16 Bits
FF02H
FF03H
FF04H
FF0EH
FF0FH
FF12H
FF13H
FF14H
FF15H
FF16H
FF17H
FF18H
FF19H
FF1AH
FF22H
FF23H
FF24H
FF32H
FF33H
FF34H
FF48H
FF49H
FF50H
FF51H
FF54H
FF58H
FF60H
FF61H
FF62H
FF63H
FF70H
FF80H
FF81H
FF84H
Port register 2
P2
R/W
Note 2
√
√
√
−
−
−
√
√
√
√
√
−
−
−
−
−
−
Port register 3
P3
Port register 4
P4
8-bit timer H compare register 01
8-bit timer H compare register 11
16-bit timer counter 00
CMP01
CMP11
TM00
R/W
R
Note 3
√
0000H
Note 3
16-bit timer capture/compare register 000
16-bit timer capture/compare register 010
10-bit A/D conversion result register
CR000
CR010
ADCR
R/W
−
−
−
−
−
−
√
0000H
Note 3
√
0000H
Note 3
√
R
Undefined
8-bit A/D conversion result register
Port mode register 2
ADCRH
PM2
−
√
√
√
√
√
√
−
−
√
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R/W
FFH
00H
Port mode register 3
Port mode register 4Note 1
PM3
PM4Note 1
Pull-up resistance option register 2
Pull-up resistance option register 3
Pull-up resistance option register 4
Watchdog timer mode register
Watchdog timer enable register
Low voltage detect register
PU2
PU3
PU4
WDTM
WDTE
LVIM
67H
9AH
00HNote 4
Low voltage detection level select register
Reset control flag register
LVIS
RESF
LSRCM
TMC00
PRM00
CRC00
TOC00
TMHMD1
R
00HNote 5
00H
Low-speed Ring-OSC mode register
16-bit timer mode control register 00
Prescaler mode register 00
R/W
Capture/compare control register 00
16-bit timer output control register 00
8-bit timer H mode register 1
A/D converter mode register
ADM
ADS
Analog input channel specify register
Port mode control register 2
PMC2
Notes 1. When using the 78K0S/KU1+, set port mode register 4 (PM4) to 00H when initially setting the program.
2. Only P34 is an input-only port.
3. A 16-bit access is possible only by the short direction addressing.
4. Retained only after a reset by LVI.
5. Varies depending on the reset cause.
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Table 3-3. Special Function Registers (2/2)
Address
Special Function Register (SFR) Name
Symbol
R/W
Number of Bits Manipulated
Simultaneously
After Reset
1 Bit
−
8 Bits
16 Bits
FFA0H
FFA1H
FFA2H
FFA3H
FFA4H
FFA5H
FFA6H
FFA7H
FFA8H
FFE0H
FFE4H
FFECH
FFF3H
FFF4H
Flash Protect Command register
Flash Status register
PFCMD
PFS
W
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Undefined
00H
R/W
√
Flash Programming Mode Control register
Flash Programming Command register
Flash Address Pointer L
FLPMC
FLCMD
FLAPL
FLAPH
FLAPHC
FLAPLC
FLW
√
Undefined
00H
√
√
Undefined
Flash Address Pointer H
√
Flash Address Pointer H Compare register
Flash Address Pointer L Compare register
Flash Write buffer register
√
00H
√
−
Interrupt request flag register 0
Interrupt mask flag register 0
IF0
√
MK0
√
FFH
00H
02H
External interrupt mode register 0
Preprocessor clock control register
Oscillation stabilization time selection register
INTM0
PPCC
OSTS
−
√
−
Undefined
Note
FFFBH
Processor clock control register
PCC
√
√
−
02H
Note The oscillation stabilization time that elapses after release of reset is selected by the option byte. For details,
refer to CHAPTER 15 OPTION BYTE.
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3.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination address
information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S
Series Instructions User’s Manual (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start
address of the following instruction is transferred to the program counter (PC) to branch. The displacement
value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes the sign bit. In other words,
the range of branch in relative addressing is between –128 and +127 of the start address of the following
instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
0
0
...
PC is the start address of
the next instruction of
a BR instruction.
PC
+
8
7
6
α
S
jdisp8
15
0
PC
When S = 0, α indicates that all bits are “0”.
When S = 1, α indicates that all bits are “1”.
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) to branch.
This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.
CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low addr.
High addr.
15
8 7
0
PC
3.3.3 Table indirect addressing
[Function]
The table contents (branch destination address) of the particular location to be addressed by the immediate data
of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be
used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH.
[Illustration]
7
0
6
1
5
1
0
0
Instruction code
Effective address
ta4–0
15
0
8
0
7
0
6
1
5
1
0
0
0
0
0
0
0
0
7
Memory (Table)
Low addr.
0
High addr.
Effective address + 1
15
8
7
0
PC
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3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) to branch.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
8
7
7
0
0
rp
A
X
15
PC
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3.4 Operand Address Addressing
The following methods (addressing) are available to specify the register and memory to undergo manipulation
during instruction execution.
3.4.1 Direct addressing
[Function]
The memory indicated by immediate data in an instruction word is directly addressed.
[Operand format]
Identifier
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
OP Code
00H
FEH
[Illustration]
7
0
OP code
addr16 (low)
addr16 (high)
Memory
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3.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word.
The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal high-
speed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to
FF1FH.
The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this
area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped,
and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to
1FH, bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier
saddr
Description
Label or FE20H to FF1FH immediate data
saddrp
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
OP code
90H (saddr-offset)
50H (immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
15
1
8
0
Effective
address
1
1
1
1
1
1
α
α
When 8-bit immediate data is 20H to FFH, = 0.
α
When 8-bit immediate data is 00H to 1FH, = 1.
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3.4.3 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction
word.
This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to
FF1FH are accessed with short direct addressing.
[Operand format]
Identifier
sfr
Description
Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code
1
0
1
0
1
1
0
0
0
0
1
0
1
0
1
0
[Illustration]
7
0
OP code
sfr-offset
SFR
15
1
8 7
0
Effective
address
1
1
1
1
1
1
1
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3.4.4 Register addressing
[Function]
A general-purpose register is accessed as an operand.
The general-purpose register to be accessed is specified with the register specify code and functional name in
the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
AX, BC, DE, HL
rp
‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
Register specify code
INCW DE; When selecting the DE register pair for rp
Instruction code
1
0
0
0
1
0
0
0
Register specify code
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3.4.5 Register indirect addressing
[Function]
The memory is addressed with the contents of the register pair specified as an operand. The register pair to be
accessed is specified with the register pair specify code in the instruction code. This addressing can be carried
out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code
0
0
1
0
1
0
1
1
[Illustration]
15
8
7
7
0
0
DE
D
E
Memory address specified
by register pair DE
The contents of addressed
memory are transferred
7
0
A
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CHAPTER 3 CPU ARCHITECTURE
3.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
3.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions
are executed or the register is saved/restored upon interrupt request generation.
Stack addressing can be used to access the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Instruction code
1
0
1
0
1
0
1
0
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CHAPTER 4 PORT FUNCTIONS
4.1 Functions of Ports
The 78K0S/KU1+ and 78K0S/KY1+ have the ports shown in Figure 4-1, which can be used for various control
operations. Table 4-1 shows the functions of each port.
In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to
CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Functions
P40Note
P20
P23
Port 2
Port 3
Port 4Note
P32
P34
P47Note
Note The P40 to P47 pins are provided only in the 78K0S/KY1+. When using the 78K0S/KU1+, set port mode
register 4 (PM4) to 00H when initially setting the program.
Table 4-1. Port Functions
Pin Name
I/O
Function
After Reset
Input
Alternate-
Function Pin
P20
I/O
Port 2.
ANI0/TI000/TOH1
4-bit I/O port.
P21
ANI1/TI010/TO00/
INTP0
Can be set to input or output mode in 1-bit units.
On-chip pull-up resistor can be connected by setting software.
P22
P23
P32
X2/ANI2
X1/ANI3
INTP1
I/O
Port 3
Can be set to input or output mode in 1- Input
bit units.
On-chip pull-up resistor can be
connected by setting software.
P34
Input
I/O
Input only
Input
Input
RESET
P40 to P47Note
Port 4.
−
8-bit I/O port.
Can be set to input or output mode in 1-bit units.
On-chip pull-up resistor can be connected setting software.
Note The P40 to P47 pins are provided only in the 78K0S/KY1+. When using the 78K0S/KU1+, set port mode
register 4 (PM4) to 00H when initially setting the program.
Caution The P22/X2/ANI2 and P23/X1/ANI3 pins are pulled down during reset.
Remarks 1. P22 and P23 can be allocated when the high-speed Ring-OSC is selected as the system clock.
2. P22 can be allocated when an external clock input is selected as the system clock.
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CHAPTER 4 PORT FUNCTIONS
4.2 Port Configuration
Ports consist of the following hardware units.
Table 4-2. Configuration of Ports
Item
Configuration
Control registers
Port mode registers (PM2 to PM4)
Port registers (P3, P4)
Port mode control register 2 (PMC2)
Pull-up resistor option registers (PU2 to PU4)
Ports
78K0S/KU1+
Total: 6 (CMOS I/O: 5, CMOS input: 1)
78K0S/KY1+
Total: 14 (CMOS I/O: 13, CMOS input: 1)
Pull-up resistor
78K0S/KU1+
Total: 5
78K0S/KY1+
Total: 13
4.2.1 Port 2
Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using
port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be
connected in 1-bit units by using pull-up resistor option register 2 (PU2).
This port can also be used for A/D converter analog input, timer I/O, and external interrupt request input.
The P22 and P23 pins are also used as the X2 and X1 pins of the system clock oscillator. The functions of the P22
and P23 pins differ, therefore, depending on the selected system clock oscillator. The following three system clock
oscillators can be used.
(1) High-speed Ring-OSC circuit
The P22 and P23 pins can be used as I/O port pins or analog input pins to the A/D converter.
(2) Crystal/ceramic oscillator
The P22 and P23 pins cannot be used as I/O port pins or analog input pins to the A/D converter because they are
used as the X2 and X1 pins.
(3) External clock input
The P22 pin can be used as an I/O port pin or an analog input pin to the A/D converter.
The P23 pin is used as the X1 pin to input an external clock, and therefore it cannot be used as an I/O port pin or
an analog input pin to the A/D converter.
The system clock oscillation is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE.
Reset input sets port 2 to the input mode.
Figure 4-2 and 4-3 show the block diagrams of port 2.
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CHAPTER 4 PORT FUNCTIONS
Figure 4-2. Block Diagram of P20 and P21
VDD
WRPU
PU2
PU20, PU21
P-ch
PMC2
PMC20, PMC21
Alternate
function
RD
WRPORT
WRPM
Output latch
(P20, P21)
P20/ANI0/TI000/TOH1,
P21/ANI1/TI010/TO00/INTP0
PM2
PM20, PM21
Alternate
function
A/D converter
PU2:
PM2:
Pull-up resistor option register 2
Port mode register 2
PMC2: Port mode control register 2
RD: Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-3. Block Diagram of P22
VDD
WRPU
PU2
PU22
P-ch
PMC2
PMC22
RD
WRPORT
WRPM
Output latch
(P22)
P22/ANI2/X2
PM2
PM22
A/D converter
Figure 4-4. Block Diagram of P23
VDD
WRPU
PU2
PU23
P-ch
PMC2
PMC23
RD
WRPORT
WRPM
Output latch
(P23)
P23/ANI3/X1
PM2
PM23
A/D converter
PU2:
PM2:
Pull-up resistor option register 2
Port mode register 2
PMC2: Port mode control register 2
RD: Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.2 Port 3
The P32 pin is a 1-bit I/O port with an output latch. This pin can be set to the input or output mode by using port
mode register 3 (PM3). When this pin is used as an input port, an on-chip pull-up resistor can be connected in 1-bit
units by using pull-up resistor option register 3 (PU3). This pin can also be used for external interrupt request input.
The P34 pin is a 1-bit input-only port and can also be used for the RESET input.
Reset input sets port 3 to the input mode.
Figures 4-5 and 4-6 show the block diagrams of port 3.
Figure 4-5. Block Diagram of P32
V
DD
WRPU
PU3
PU32
P-ch
Alternate
function
RD
WRPORT
Output latch
(P32)
P32/INTP1
WRPM
PM3
PM32
PU3:
PM3:
RD:
Pull-up resistor option register 3
Port mode register 3
Read signal
WR××: Write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-6. Block Diagram of P34
RD
P34/RESET
Reset
Option
byte
RD:
Read signal
Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the
function to input an external reset signal to the RESET pin cannot be used. The function of the
port is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE.
If a low level is input to the RESET pin before the option byte is referenced again after reset is
released by the POC circuit, the 78K0S/KU1+ and 78K0S/KY1+ are reset and are held in the reset
state until a high level is input to the RESET pin.
4.2.3 Port 4 (78K0S/KY1+ only)
Port 4 is a 8-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using
port mode register 4 (PM4). When the P40 to P47 pinsNote are used as an input port, an on-chip pull-up resistor can
be connected in 1-bit units by using pull-up resistor option register 4 (PU4).
Reset input sets port 4 to the input mode.
Figures 4-6 shows the block diagram of port 4.
Note The P40 to P47 pins are provided only in the 78K0S/KY1+. When using the 78K0S/KU1+, set port mode
register 4 (PM4) to 00H when initially setting the program.
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CHAPTER 4 PORT FUNCTIONS
Figure 4-7. Block Diagram of P40 and P47 (78K0S/KY1+ only)
V
DD
WRPU
PU4
PU40-PU47
P-ch
RD
WRPORT
Output latch
(P40-P47)
P40-P47
WRPM
PM4
PM40-PM47
PU4:
Pull-up resistor option register 4
PM4:
RD:
Port mode register 4
Read signal
WR××: Write signal
4.3 Registers Controlling Port Functions
The ports are controlled by the following four types of registers.
• Port mode registers (PM2 to PM4)
• Port registers (P2 to P4)
• Port mode control register 2 (PMC2)
• Pull-up resistor option registers (PU2 to PU4)
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CHAPTER 4 PORT FUNCTIONS
(1) Port mode registers (PM2 to PM4Note
)
These registers are used to set the corresponding port to the input or output mode in 1-bit units.
Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets these registers to FFH.
When a port pin is used as an alternate-function pin, set its port mode register and output latch as shown in
Table 4-3.
Note When using the 78K0S/KU1+, set port mode register 4 (PM4) to 00H when initially setting the program.
Caution Because P21 and P32 are also used as external interrupt pins, the corresponding interrupt
request flag is set if each of these pins is set to the output mode and its output level is
changed. To use the port pin in the output mode, therefore, set the corresponding interrupt
mask flag to 1 in advance.
Figure 4-8. Format of Port Mode Register
Address: FF22H, After reset: FFH, R/W
Symbol
PM2
7
1
6
1
5
1
4
1
3
2
1
0
PM23
PM22
PM21
PM20
Address: FF23H, After reset: FFH, R/W
Symbol
PM3
7
1
6
1
5
1
4
1
3
1
2
1
1
0
1
PM32
Address: FF24H, After reset: FFH, R/W
Symbol
PM4Note
7
6
5
4
3
2
1
0
PM47Note
PM46Note
PM45Note
PM44Note
PM43Note
PM42Note
PM41Note
PM40Note
PMmn
Selection of I/O mode of Pmn pin (m = 2 to 4; n = 0 to 7)
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
Note When using the 78K0S/KU1+, set port mode register 4 (PM4) to 00H when initially setting the program.
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CHAPTER 4 PORT FUNCTIONS
(2) Port registers (P2 to P4)
These registers are used to write data to be output from the corresponding port pin to an external device
connected to the chip.
When a port register is read, the pin level is read in the input mode, and the value of the output latch of the
port is read in the output mode.
P20 to P23, P32, and P40 to P47 are set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input sets these registers to 00H.
Figure 4-9. Format of Port Register
Address: FF02H, After reset: 00H (Output latch) R/W
Symbol
P2
7
0
6
0
5
0
4
0
3
2
1
0
P23
P22
P21
P20
Address: FF03H, After reset: 00HNote (Output latch) R/WNote
Symbol
P3
7
0
6
0
5
0
4
3
0
2
1
0
0
0
P34
P32
Address: FF04H, After reset: 00H (Output latch) R/W
Symbol
P4
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
Pmn
m = 2 to 4; n = 0 to 7
Controls of output data (in output mode)
Output 0
Output 1
Input data read (in input mode)
Input low level
Input high level
0
1
Note Because P34 is read-only, its reset value is undefined.
(3) Port mode control register 2 (PMC2)
This register specifies the port/alternate function (except the A/D converter function) mode or the A/D
converter mode.
Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units.
PMC2 is set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input sets PMC2 to 00H.
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CHAPTER 4 PORT FUNCTIONS
Figure 4-10. Format of Port Mode Control Register 2
Address: FF84H, After reset: R/W
Symbol
PMC2
7
0
6
0
5
0
4
0
3
2
1
0
PMC23
PMC22
PMC21
PMC20
PMC2n
Specification of operation mode (n = 0 to 3)
0
1
Port/alternate-function (except the A/D converter function) mode
A/D converter mode
Table 4-3. Setting of Port Mode Register, Port Register (Output Latch), and Port Mode Control Register
When Alternate Function Is Used
Pin Name
Alternate-Function Pin
Name
PM××
P××
PMC2n
(n = 0 to 3)
I/O
P20
P21
ANI0
Input
Input
1
1
0
1
1
0
1
1
1
1
×
×
0
×
×
0
×
×
×
×
1
0
0
1
0
0
0
1
1
−
TI000
TOH1
ANI1
Output
Input
Input
Output
Input
Input
Input
Input
TI010
TO00
INTP0
ANI2
P22
P23
P32
ANI3
INTP1
Remark ×:
don’t care
PM××: Port mode register, P××: Port register (output latch of port)
PMC2×: Port mode control register
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CHAPTER 4 PORT FUNCTIONS
(4) Pull-up resistor option registers (PU2 to PU4)
These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P32, and
P40 to P47. By setting PU2 to PU4, an on-chip pull-up resistor can be connected to the port pin corresponding
to the bit of PU2 to PU4.
PU2 to PU4 are set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input set these registers to 00H.
Figure 4-11. Format of Pull-up Resistor Option Register
Address: FF32H, After reset: 00H R/W
Symbol
PU2
7
0
6
0
5
0
4
0
3
2
1
0
PU23
PU22
PU21
PU20
Address: FF33H, After reset: 00H R/W
Symbol
PU3
7
0
6
0
5
0
4
0
3
0
2
1
0
0
0
PU32
Address: FF34H, After reset: 00H R/W
Symbol
PU4
7
6
5
4
3
2
1
0
PU47
PU46
PU45
PU44
PU43
PU42
PU41
PU40
PUmn
Selection of connection of on-chip pull-up resistor of Pmn (m = 2 to 4; n = 0 to 7)
0
1
Does not connect on-chip pull-up resistor
Connects on-chip pull-up resistor
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CHAPTER 4 PORT FUNCTIONS
4.4 Operation of Port Function
The operation of a port differs, as follows, depending on the setting of the I/O mode.
Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit
units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not
subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and
outputs.
4.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch by a transfer instruction. In addition, the contents of the output latch are
output from the pin. Once data is written to the output latch, it is retained until new data is written to the output
latch.
Reset input cleans the data in the output latch.
(2) In input mode
A value can be written to the output latch by a transfer instruction. Because the output buffer is off, however, the
pin status remains unchanged.
Once data is written to the output latch, it is retained until new data is written to the output latch.
4.4.2 Reading from I/O port
(1) In output mode
The contents of the output latch can be read by a transfer instruction. The contents of the output latch remain
unchanged.
(2) In input mode
The pin status can be read by a transfer instruction. The contents of the output latch remain unchanged.
4.4.3 Operations on I/O port
(1) In output mode
An operation is performed on the contents of the output latch and the result is written to the output latch. The
contents of the output latch are output from the pin.
Once data is written to the output latch, it is retained until new data is written to the output latch.
Reset input clears the data in the output latch.
(2) In input mode
The pin level is read and an operation is performed on its contents. The operation result is written to the output
latch. However, the pin status remains unchanged because the output buffer is off.
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CHAPTER 5 CLOCK GENERATORS
5.1 Functions of Clock Generators
The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and
peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the
watchdog timer and 8-bit timer H1 (TMH1).
5.1.1 System clock oscillators
The following three types of system clock oscillators are used.
• High-speed Ring-OSC oscillator
This circuit internally oscillates a clock of 8 MHz (TYP.). Its oscillation can be stopped by execution of the STOP
instruction.
If the high-speed Ring-OSC oscillator is selected to supply the system clock, the X1 and X2 pins can be used as
I/O port pins.
• Crystal/ceramic oscillator
This circuit oscillates a clock with a crystal/ceramic oscillator connected across the X1 and X2 pins. It can
oscillate a clock of 1 MHz to 10 MHz. Oscillation of this circuit can be stopped by execution of the STOP
instruction.
• External clock input circuit
This circuit supplies a clock from an external IC to the X1 pin. A clock of 1 MHz to 10 MHz can be supplied.
Internal clock supply can be stopped by execution of the STOP instruction.
If the external clock input is selected as the system clock, the X2 pin can be used as an I/O port pin.
The system clock source is selected by using the option byte. For details, refer to CHAPTER 15 OPTION BYTE.
When using the X1 and X2 pins as I/O port pins, refer to CHAPTER 4 PORT FUNCTIONS for details.
5.1.2 Clock oscillator for interval time generation
The following circuit is used as a clock oscillator for interval time generation.
• Low-speed Ring-OSC oscillator
This circuit oscillates a clock of 240 kHz (TYP.). Its oscillation can be stopped by using the low-speed Ring-OSC
mode register (LSRCM) when it is specified by the option byte that its oscillation can be stopped by software.
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CHAPTER 5 CLOCK GENERATORS
5.2 Configuration of Clock Generators
The clock generators consist of the following hardware.
Table 5-1. Configuration of Clock Generators
Item
Configuration
Control registers
Processor clock control register (PCC)
Preprocessor clock control register (PPCC)
Low-speed Ring-OSC mode register (LSRCM)
Oscillation stabilization time select register (OSTS)
Oscillators
Crystal/ceramic oscillator
High-speed Ring-OSC oscillator
External clock input circuit
Low-speed Ring-OSC oscillator
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CHAPTER 5 CLOCK GENERATORS
Figure 5-1. Block Diagram of Clock Generators
Internal bus
Oscillation stabilization
Preprocessor clock
Processor clock
time select register (OSTS)
control register (PPCC)
control register (PCC)
OSTS1 OSTS0
PPCC1 PPCC0
PCC1
System clock oscillation
stabilization time counter
Controller
CPU clock
(fCPU
)
STOP
Watchdog timer
System clock
oscillatorNote
X1/P23/ANI3
X2/P22/ANI2
Crystal/ceramic
oscillation
Prescaler
f
X
f
2
X
fX
22
External clock
input
High-speed
Ring-OSC
oscillation
f
XP
22
f
XP
Prescaler
Clock to peripheral
hardware (fXP
)
Low-speed
Ring-OSC
oscillator
f
RL
8-bit timer H1,
watchdog timer
Option byte
1: Cannot be stopped.
0: Can be stopped.
LSRSTOP
Low-speed Ring-OSC
mode register (LSRCM)
Internal bus
Note Select the high-speed Ring-OSC oscillator, crystal/ceramic oscillator, or external clock input as the system
clock source by using the option byte.
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5.3 Registers Controlling Clock Generators
The clock generators are controlled by the following four registers.
• Processor clock control register (PCC)
• Preprocessor clock control register (PPCC)
• Low-speed Ring-OSC mode register (LSRCM)
• Oscillation stabilization time select register (OSTS)
(1) Processor clock control register (PCC) and preprocessor clock control register (PPCC)
These registers are used to specify the division ratio of the system clock.
PCC and PPCC are set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input sets PCC and PPCC to 02H.
Figure 5-2. Format of Processor Clock Control Register (PCC)
Address: FFFBH, After reset: 02H, R/W
Symbol
PCC
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
PCC1
Figure 5-3. Format of Preprocessor Clock Control Register (PPCC)
Address: FFF3H, After reset: 02H, R/W
Symbol
PPCC
7
0
6
0
5
0
4
0
3
0
2
0
1
0
PPCC1
PPCC0
PPCC1
PPCC0
PCC1
Selection of CPU clock (fCPU)
0
0
0
1
0
1
0
0
0
1
0
1
1
fX
1
fX/2 Note 1
fX/22
0
Note 2
0
fX/22
Note 1
1
fX/23
Note 2
0
fX/24
Other than above
Setting prohibited
Notes 1. If PPCC = 01H, the clock (fXP) supplied to the peripheral hardware is fX/2.
2. If PPCC = 02H, the clock (fXP) supplied to the peripheral hardware is fX/22.
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The fastest instruction of the 78K0S/KU1+ and 78K0S/KY1+ is executed in two CPU clocks. Therefore, the
relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2.
Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU) Note
Minimum Instruction Execution Time: 2/fCPU
High-speed Ring-OSC clock
(at 8.0 MHz (TYP.))
Crystal/ceramic oscillation clock
or external clock input (at 10.0 MHz)
fX
0.25 µs
0.5 µs
1.0 µs
2.0 µs
4.0 µs
0.2 µs
fX/2
fX/22
fX/23
fX/24
0.4 µs
0.8 µs
1.6 µs
3.2 µs
Note The CPU clock (high-speed Ring-OSC clock, crystal/ceramic oscillation clock, or external clock input) is
selected by the option byte.
(2) Low-speed Ring-OSC mode register (LSRCM)
This register is used to select the operation mode of the low-speed Ring-OSC oscillator (240 kHz (TYP.)).
This register is valid when it is specified by the option byte that the low-speed Ring-OSC oscillator can be
stopped by software. If it is specified by the option byte that the low-speed Ring-OSC oscillator cannot be
stopped by software, setting of this register is invalid, and the low-speed Ring-OSC oscillator continues
oscillating. In addition, the source clock of WDT is fixed to the low-speed Ring-OSC oscillator. For details, refer
to CHAPTER 8 WATCHDOG TIMER.
LSRCM can be set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input sets LSRCM to 00H.
Figure 5-4. Format of Low-Speed Ring-OSC Mode Register (LSRCM)
Address: FF58H, After reset: 00H, R/W
Symbol
LSRCM
7
0
6
0
5
0
4
0
3
0
2
0
1
0
<0>
LSRSTOP
LSRSTOP
Oscillation/stop of low-speed Ring-OSC
0
1
Low-speed Ring-OSC oscillates
Low-speed Ring-OSC stops
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(3) Oscillation stabilization time select register (OSTS)
This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP
mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected
as the system clock and after the STOP mode is released. If the high-speed Ring-OSC oscillator or external
clock input is selected as the system clock source, no wait time elapses.
The system clock oscillator and the oscillation stabilization time that elapses after power application or release of
reset are selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE.
OSTS is set by using an 8-bit memory manipulation instruction.
Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFF4H, After reset: Undefined, R/W
Symbol
OSTS
7
0
6
0
5
0
4
0
3
0
2
0
1
0
OSTS1
OSTS0
OSTS1
OSTS0
Selection of oscillation stabilization time
0
0
1
1
0
1
0
1
210/fX (102.4 µs)
212/fX (409.6 µs)
215/fX (3.27 ms)
217/fX (13.1 ms)
Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as
follows.
Expected oscillation stabilization time of resonator
stabilization time set by OSTS
≤
Oscillation
2. The wait time after the STOP mode is released does not include the time from the
release of the STOP mode to the start of clock oscillation (“a” in the next figure),
regardless of whether STOP mode was released by reset input or interrupt
generation.
STOP mode is released
Voltage
waveform
of X1 pin
a
3. The oscillation stabilization time that elapses on power application or after release
of reset is selected by the option byte. For details, refer to CHAPTER 15 OPTION
BYTE.
Remarks 1. ( ): fX = 10 MHz
2. Determine the oscillation stabilization time of the resonator by checking the
characteristics of the resonator to be used.
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5.4 System Clock Oscillators
The following three types of system clock oscillators are available.
• High-speed Ring-OSC oscillator: Internally oscillates a clock of 8 MHz (TYP.).
• Crystal/ceramic oscillator:
• External clock input circuit:
Oscillates a clock of 1 MHz to 10 MHz.
Supplies a clock of 1 MHz to 10 MHz to the X1 pin.
5.4.1 High-speed Ring-OSC oscillator
The 78K0S/KU1+ and 78K0S/KY1+ include a high-speed Ring-OSC oscillator (8 MHz (TYP.)).
If the high-speed Ring-OSC is selected by the option byte as the clock source, the X1 and X2 pins can be used as
I/O port pins.
For details of the option byte, refer to CHAPTER 15 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4
PORT FUNCTIONS.
5.4.2 Crystal/ceramic oscillator
The crystal/ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2
pins.
If the crystal/ceramic oscillator is selected by the option byte as the system clock source, the X1 and X2 pins are
used as crystal or ceramic resonator connection pins.
For details of the option byte, refer to CHAPTER 15 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4
PORT FUNCTIONS.
Figure 5-6 shows the external circuit of the crystal/ceramic oscillator.
Figure 5-6. External Circuit of Crystal/Ceramic Oscillator
V
SS
X1
X2
Crystal resonator
or ceramic resonator
Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken
lines in Figure 5-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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Figure 5-7 shows examples of incorrect resonator connection.
Figure 5-7. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring of connected circuit (b) Crossed signal lines
PORT
X2
VSS
X1
X2
VSS
X1
(d) Current flowing through ground line of oscillator
(Potential at points A, B, and C fluctuates.)
(c) Wiring near high fluctuating current
VDD
PORT
X2
VSS
X1
X2
X1
VSS
A
B
C
High current
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Figure 5-7. Examples of Incorrect Resonator Connection (2/2)
(e) Signals are fetched
VSS
X1
X2
5.4.3 External clock input circuit
This circuit supplies a clock from an external IC to the X1 pin.
If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O
port pin.
For details of the option byte, refer to CHAPTER 15 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4
PORT FUNCTIONS.
5.4.4 Prescaler
The prescaler divides the clock (fX) output by the system clock oscillator to generate a clock (fXP) to be supplied to
the peripheral hardware. It also divides the clock to peripheral hardware (fXP) to generate a clock to be supplied to the
CPU.
Remark The clock output by the oscillator selected by the option byte (high-speed Ring-OSC oscillator,
crystal/ceramic oscillator, or external clock input circuit) is divided. For details of the option byte, refer to
CHAPTER 15 OPTION BYTE.
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5.5 Operation of CPU Clock Generator
A clock (fCPU) is supplied to the CPU from the system clock (fX) oscillated by one of the following three types of
oscillators.
• High-speed Ring-OSC oscillator: Internally oscillates a clock of 8 MHz (TYP.).
• Crystal/ceramic oscillator:
• External clock input circuit:
Oscillates a clock of 1 MHz to 10 MHz.
Supplies a clock of 1 MHz to 10 MHz to X1 pin.
The system clock oscillator is selected by the option byte. For details of the option byte, refer to CHAPTER 15
OPTION BYTE.
(1) High-speed Ring-OSC oscillator
When the high-speed Ring-OSC oscillator is selected by the option byte, the following is possible.
• Shortening of start time
If the high-speed Ring-OSC oscillator is selected as the oscillator, the CPU can be started without having to
wait for the oscillation stabilization time of the system clock. Therefore, the start time can be shortened.
• Improvement of expandability
If the high-speed Ring-OSC oscillator is selected as the oscillator, the X1 and X2 pins can be used as I/O port
pins. For details, refer to CHAPTER 4 PORT FUNCTIONS.
Figures 5-8 and 5-9 show the timing chart and status transition diagram of the default start by the high-speed
Ring-OSC oscillator.
Remark When the high-speed Ring-OSC oscillator is used, the clock accuracy is 5%.
Figure 5-8. Timing Chart of Default Start by High-Speed Ring-OSC Oscillator
(a)
VDD
RESET
H
Internal reset
(b)
System clock
CPU clock
High-speed Ring-OSC clock
PCC = 02H, PPCC = 02H
Option byte is read.
System clock is selected.
(Operation stopsNote
)
Note Operation stop time is 277 µs (MIN.), 544 µs (TYP.), and 1.075 ms (MAX.).
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(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the high-speed Ring-OSC clock
operates as the system clock.
Figure 5-9. Status Transition of Default Start by High-Speed Ring-OSC
Power
application
VDD > 2.1 V 0.1 V
Reset by
power-on clear
Reset signal
High-speed Ring-OSC
selected by option byte
Start with PCC = 02H,
PPCC = 02H
Clock division ratio
variable during
CPU operation
Interrupt
Interrupt
HALT
instruction
STOP
instruction
HALT
STOP
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
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(2) Crystal/ceramic oscillator
If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 1 MHz to 10 MHz can be selected
and the accuracy of processing is improved because the frequency deviation is small, as compared with high-
speed Ring-OSC oscillation (8 MHz (TYP.)).
Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic
oscillator.
Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator
(a)
VDD
RESET
H
Internal reset
(b)
System clock
CPU clock
(c)
Crystal/ceramic
oscillator clock
PCC = 02H, PPCC = 02H
Option byte is read.
Clock oscillation
stabilization
timeNote 2
System clock is selected.
(Operation stopsNote 1
)
Notes 1. Operation stop time is 276 µs (MIN.), 544 µs (TYP.), and 1.074 ms (MAX.).
2. The clock oscillation stabilization time for default start is selected by the option byte. For details, refer to
CHAPTER 15 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode is
released is selected by the oscillation stabilization time select register (OSTS).
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) After high-speed Ring-OSC clock is generated, the option byte is referenced and the system clock is
selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock.
(c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock
oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
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Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation
Power
application
V
DD > 2.1 V 0.1 V
Reset by
power-on clear
Reset signal
Crystal/ceramic
oscillation selected
by option byte
Start with PCC = 02H,
PPCC = 02H
Wait for clock
oscillation stabilization
Clock division ratio
variable during
CPU operation
Interrupt
Interrupt
HALT
instruction
STOP
instruction
HALT
STOP
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
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(3) External clock input circuit
If external clock input is selected by the option byte, the following is possible.
• High-speed operation
The accuracy of processing is improved as compared with high-speed Ring-OSC oscillation (8 MHz (TYP.))
because an oscillation frequency of 1 MHz to 10 MHz can be selected and an external clock with a small
frequency deviation can be supplied.
• Improvement of expandability
If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For
details, refer to CHAPTER 4 PORT FUNCTIONS.
Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input.
Figure 5-12. Timing of Default Start by External Clock Input
(a)
VDD
RESET
H
Internal reset
(b)
System clock
CPU clock
External clock input
PCC = 02H, PPCC = 02H
Option byte is read.
System clock is selected.
(Operation stopsNote
)
Note Operation stop time is 277 µs (MIN.), 544 µs (TYP.), and 1.075 ms (MAX.).
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
system clock.
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Figure 5-13. Status Transition of Default Start by External Clock Input
Power
application
VDD > 2.1 V 0.1 V
Reset by
power-on clear
Reset signal
External clock input
selected by option byte
Start with PCC = 02H,
PPCC = 02H
Clock division ratio
variable during
CPU operation
Interrupt
Interrupt
HALT
instruction
STOP
instruction
HALT
STOP
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
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5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware
The following two types of clocks are supplied to the peripheral hardware.
• Clock to peripheral hardware (fXP)
• Low-speed Ring-OSC clock (fRL)
(1) Clock to peripheral hardware
The clock to the peripheral hardware is supplied by dividing the system clock (fX). The division ratio is selected
by the pre-processor clock control register (PPCC).
Three types of frequencies are selectable: “fX”, “fX/2”, and “fX/22”. Table 5-3 lists the clocks supplied to the
peripheral hardware.
Table 5-3. Clocks to Peripheral Hardware
PPCC1
PPCC0
Selection of clock to peripheral hardware (fXP)
0
0
1
1
0
1
0
1
fX
fX/2
fX/22
Setting prohibited
(2) Low-speed Ring-OSC clock
The low-speed Ring-OSC oscillator of the clock oscillator for interval time generation is always started after
release of reset, and oscillates at 240 kHz (TYP.).
It can be specified by the option byte whether the low-speed Ring-OSC oscillator can or cannot be stopped by
software. If it is specified that the low-speed Ring-OSC oscillator can be stopped by software, oscillation can be
started or stopped by using the low-speed Ring-OSC mode register (LSRCM). If it is specified that it cannot be
stopped by software, the clock source of WDT is fixed to the low-speed Ring-OSC clock (fRL).
The low-speed Ring-OSC oscillator is independent of the CPU clock. If it is used as the source clock of WDT,
therefore, a hang-up can be detected even if the CPU clock is stopped. If the low-speed Ring-OSC oscillator is
used as a count clock source of 8-bit timer H1, 8-bit timer H1 can operate even in the standby status.
Table 5-4 shows the operation status of the low-speed Ring-OSC oscillator when it is selected as the source
clock of WDT and the count clock of 8-bit timer H1. Figure 5-14 shows the status transition of the low-speed
Ring-OSC oscillator.
Table 5-4. Operation Status of Low-Speed Ring-OSC Oscillator
Option Byte Setting
CPU Status
WDT Status
Stopped
TMH1 Status
Stopped
Can be stopped by
LSRSTOP = 1
LSRSTOP = 0
LSRSTOP = 1
LSRSTOP = 0
Operation mode
software
Operates
Stopped
Stopped
Operates
Operates
Stopped
Operates
Standby
Cannot be stopped
Operation mode
Standby
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Figure 5-14. Status Transition of Low-Speed Ring-OSC Oscillator
Power
application
VDD > 2.1 V 0.1 V
Reset by
power-on clear
Reset signal
Select by option byte
if low-speed Ring-OSC
can be stopped or not
Can be stopped
Cannot be stopped
Clock source of
WDT is selected
by softwareNote
Clock source of
WDT is fixed to fRL
Low-speed Ring-OSC
oscillator cannot be stopped
Low-speed Ring-OSC
oscillator can be stopped
LSRSTOP = 1
LSRSTOP = 0
Low-speed Ring-OSC
oscillator stops
Note The clock source of the watchdog timer (WDT) is selected from fX or fRL, or it may be stopped. For details,
refer to CHAPTER 8 WATCHDOG TIMER.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.1 Functions of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 has the following functions.
(1) Interval timer
16-bit timer/event counter 00 generates interrupt requests at the preset time interval.
• Number of counts: 2 to 65536
(2) External event counter
16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of a signal input
externally.
• Valid level pulse width: 16/fXP or more
(3) Pulse width measurement
16-bit timer/event counter 00 can measure the pulse width of an externally input signal.
• Valid level pulse width: 2/fXP or more
(4) Square-wave output
16-bit timer/event counter 00 can output a square wave with any selected frequency.
• Cycle: (2 × 2 to 65536 × 2) × count clock cycle
(5) PPG output
16-bit timer/event counter 00 can output a square wave that have arbitrary cycle and pulse width.
• 1 < Pulse width < Cycle ≤ (FFFF + 1) H
(6) One-shot pulse output
16-bit timer/event counter 00 can output a one-shot pulse for which output pulse width can be set to any
desired value.
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6.2 Configuration of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 consists of the following hardware.
Table 6-1. Configuration of 16-Bit Timer/Event Counter 00
Item
Timer counter
Register
Configuration
16-bit timer counter 00 (TM00)
16-bit timer capture/compare registers 000, 010 (CR000, CR010)
Timer input
Timer output
Control registers
TI000, TI010
TO00, output controller
16-bit timer mode control register 00 (TMC00)
Capture/compare control register 00 (CRC00)
16-bit timer output control register 00 (TOC00)
Prescaler mode register 00 (PRM00)
Port mode register 2 (PM2)
Port register 2 (P2)
Port mode control register 2 (PMC2)
Figures 6-1 shows a block diagram of these counters.
Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00
Internal bus
Capture/compare control
register 00 (CRC00)
CRC002CRC001 CRC000
to CR010
INTTM000
16-bit timer capture/compare
register 000 (CR000)
Noise
elimi-
nator
TI010/TO00/ANI1/
INTP0/P21
Match
fXP
fXP/22
fXP/28
16-bit timer counter 00
(TM00)
Clear
Output
TO00/TI010/ANI1/
INTP0/P21
controller
Match
Noise
elimi-
nator
2
fX
Output latch
(P21)
PM21
Noise
elimi-
nator
16-bit timer capture/compare
register 010 (CR010)
TI000/ANI0/
TOH1/P20
INTTM010
CRC002
PRM001
TMC003 TMC002 TMC001OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
PRM000
16-bit timer output
control register 00
(TOC00)
16-bit timer mode
control register 00
(TMC00)
Prescaler mode
register 00 (PRM00)
Internal bus
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(1) 16-bit timer counter 00 (TM00)
TM00 is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read
during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00)
Address: FF12H, FF13H After reset: 0000H
R
Symbol
FF13H
FF12H
TM00
The count value is reset to 0000H in the following cases.
<1> At reset input
<2> If TMC003 and TMC002 are cleared
<3> If the valid edge of TI000 is input in the clear & start mode entered by inputting the valid edge of TI000
<4> If TM00 and CR000 match in the clear & start mode entered on a match between TM00 and CR000
<5> If OSPT00 is set to 1 in the one-shot pulse output mode
Cautions 1. Even if TM00 is read, the value is not captured by CR010.
2. The count clock does not stop while TM00 is being read.
(2) 16-bit timer capture/compare register 000 (CR000)
CR000 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control
register 00 (CRC00).
CR000 is set by 16-bit memory manipulation instruction.
A reset clears CR000 to 0000H.
Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000)
Address: FF14H, FF15H After reset: 0000H R/W
Symbol
FF15H
FF14H
CR000
•
•
When CR000 is used as a compare register
The value set in CR000 is constantly compared with the 16-bit timer/counter 00 (TM00) count value, and an
interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the
interval time then TM00 is set to interval timer operation.
When CR000 is used as a capture register
It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the
TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 6-
2).
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Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
CR000 Capture Trigger
TI000 Pin Valid Edge
ES010
ES000
Falling edge
Rising edge
Falling edge
0
0
1
1
0
1
Rising edge
No capture operation
Both rising and falling edges
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
CR000 Capture Trigger
TI010 Pin Valid Edge
ES110
ES100
Falling edge
Falling edge
Rising edge
0
0
1
0
1
1
Rising edge
Both rising and falling edges
Both rising and falling edges
Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited.
2. ES010, ES000:
Bits 5 and 4 of prescaler mode register 00 (PRM00)
Bits 7 and 6 of prescaler mode register 00 (PRM00)
ES110, ES100:
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
Cautions 1. Set CR000 to other than 0000H in the clear & start mode entered on match between TM00
and CR000. This means a 1-pulse count operation cannot be performed when this
register is used as an external event counter. However, in the free-running mode and in
the clear & start mode using the valid edge of TI000, if CR000 is set to 0000H, an interrupt
request (INTTM000) is generated when CR000 changes from 0000H to 0001H following
overflow (FFFFH).
2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR000 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR000 is changed.
3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR000 set in compare mode even if a
capture trigger is input.
5. When P21 is used as the input pin for the valid edge of TI010, it cannot be used as a timer
output (TO00). Moreover, when P21 is used as TO00, it cannot be used as the input pin
for the valid edge of TI010.
6. If the register read period and the input of the capture trigger conflict when CR000 is
used as a capture register, the read data is undefined (the capture data itself is a normal
value). Also, if the count stop of the timer and the input of the capture trigger conflict,
the capture trigger is undefined.
7. Changing the CR000 setting may cause a malfunction. To change the setting, refer to 6.5
Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register
during timer operation.
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(3) 16-bit timer capture/compare register 010 (CR010)
CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether
it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control
register 00 (CRC00).
CR010 is set by 16-bit memory manipulation instruction.
Reset input clears CR010 to 0000H.
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
Address: FF16H, FF17H After reset: 0000H R/W
Symbol
FF17H
FF16H
CR010
•
•
When CR010 is used as a compare register
The value set in CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an
interrupt request (INTTM010) is generated if they match.
When CR010 is used as a capture register
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by
means of prescaler mode register 00 (PRM00) (refer to Table 6-3).
Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)
CR010 Capture Trigger
TI000 Pin Valid Edge
ES010
ES000
Falling edge
Falling edge
Rising edge
0
0
1
0
1
1
Rising edge
Both rising and falling edges
Both rising and falling edges
Remarks 1. Setting ES010, ES000 = 1, 0 is prohibited.
2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
CRC002: Bit 2 of capture/compare control register 00 (CRC00)
Cautions 1. In the free-running mode and in the clear & start mode using the valid edge of the TI000
pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010
changes from 0000H to 0001H following overflow (FFFFH).
2. If the new value of CR010 is less than the value of 16-bit timer counter 00 (TM00), TM00
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR010 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR010 is changed.
3. The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR010 set in compare mode even if a
capture trigger is input.
5. If the register read period and the input of the capture trigger conflict when CR000 is
used as a capture register, the capture trigger input takes precedence and the read data
is undefined. Also, if the timer count stop and the input of the capture trigger conflict,
the capture data is undefined.
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Cautions 6. Changing the CR010 setting during TM00 operation may cause a malfunction. To change
the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing
compare register during timer operation.
6.3 Registers to Control 16-Bit Timer/Event Counter 00
The following seven types of registers are used to control 16-bit timer/event counter 00.
• 16-bit timer mode control register 00 (TMC00)
• Capture/compare control register 00 (CRC00)
• 16-bit timer output control register 00 (TOC00)
• Prescaler mode register 00 (PRM00)
• Port mode register 2 (PM2)
• Port register 2 (P2)
• Port mode control register 2 (PMC2)
(1) 16-bit timer mode control register 00 (TMC00)
This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output
timing, and detects an overflow.
TMC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets the value of TMC00 to 00H.
Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003
(operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and
TMC003 to 0, 0 to stop the operation.
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Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address: FF60H After reset: 00H R/W
Symbol
TMC00
7
0
6
0
5
0
4
0
3
2
1
<0>
TMC003TMC002TMC001 OVF00
TMC003 TMC002 TMC001
Operating mode and clear
mode selection
TO00 inversion timing selection
No change
Interrupt request generation
Not generated
0
0
0
0
0
1
0
1
0
Operation stop
(TM00 cleared to 0)
Free-running mode
Match between TM00 and
CR000 or match between
TM00 and CR010
< When operating as compare
register >
Generated on match between
TM00 and CR000, or match
between TM00 and CR010
0
1
1
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
< When operating as capture
register >
1
1
1
0
0
1
0
1
0
Clear & start occurs on valid
edge of TI000 pin
−
Generated on TI000 pin and
TI010 pin valid edge
Clear & start occurs on match
between TM00 and CR000
Match between TM00 and
CR000 or match between
TM00 and CR010
1
1
1
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
OVF00
Overflow detection of 16-bit timer counter 00 (TM00)
0
1
Overflow not detected
Overflow detected
Cautions 1. The timer operation must be stopped before writing to bits other than the OVF00 flag.
2. Regardless of the CPU’s operation mode, when the timer stops, the signals input to pins
TI000/TI010 are not acknowledged.
3. Except when TI000 pin valid edge is selected as the count clock, stop the timer operation before
setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the
system clock starts.
4. Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 (PRM00) after
stopping the timer operation.
5. If the clear & start mode entered on a match between TM00 and CR000, clear & start mode at the
valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000 is
FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1.
6. Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes
0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is
disabled.
7. The capture operation is performed at the fall of the count clock. An interrupt request input
(INTTM0n0), however, occurs at the rise of the next count clock.
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Remark
TM00:
16-bit timer counter 00
CR000:
CR010:
16-bit timer capture/compare register 000
16-bit timer capture/compare register 010
(2) Capture/compare control register 00 (CRC00)
This register controls the operation of the 16-bit capture/compare registers (CR000, CR010).
CRC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets the value of CRC00 to 00H.
Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)
Address: FF62H After reset: 00H R/W
Symbol
CRC00
7
0
6
0
5
0
4
0
3
0
2
1
0
CRC002
CRC001
CRC000
CRC002
CR010 operating mode selection
0
1
Operate as compare register
Operate as capture register
CRC001
CR000 capture trigger selection
0
1
Capture on valid edge of TI010 pin
Capture on valid edge of TI000 pin by reverse phaseNote
CRC000
CR000 operating mode selection
0
1
Operate as compare register
Operate as capture register
Note If both the rising and falling edges have been selected as the valid edges of the TI000 pin, capture is
not performed.
Cautions 1. The timer operation must be stopped before setting CRC00.
2. When the clear & start mode entered on a match between TM00 and CR000 is selected by
16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a
capture register.
3. To ensure the reliability of the capture operation, the capture trigger requires a pulse
longer than two cycles of the count clock selected by prescaler mode register 00
(PRM00) (refer to Figure 6-17).
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(3) 16-bit timer output control register 00 (TOC00)
This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F
set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot
pulse output operation enable/disable, and output trigger of one-shot pulse by software.
TOC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets the value of TOC00 to 00H.
Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FF63H After reset: 00H R/W
Symbol
TOC00
7
0
<6>
<5>
4
<3>
<2>
1
<0>
OSPT00
OSPE00
TOC004
LVS00
LVR00
TOC001
TOE00
OSPT00
One-shot pulse output trigger control via software
0
1
No one-shot pulse output trigger
One-shot pulse output trigger
OSPE00
One-shot pulse output operation control
0
1
Successive pulse output mode
One-shot pulse output modeNote
TOC004
Timer output F/F control using match of CR010 and TM00
0
1
Disables inversion operation
Enables inversion operation
LVS00
LVR00
Timer output F/F status setting
0
0
1
1
0
1
0
1
No change
Timer output F/F reset (0)
Timer output F/F set (1)
Setting prohibited
TOC001
Timer output F/F control using match of CR000 and TM00
0
1
Disables inversion operation
Enables inversion operation
TOE00
Timer output control
0
1
Disables output (output fixed to level 0)
Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match
between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur.
Cautions 1. Timer operation must be stopped before setting other than OSPT00.
2. If LVS00 and LVR00 are read, 0 is read.
3. OSPT00 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the count clock selected by prescaler mode register
00 (PRM00) is required to write to OSPT00 successively.
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Cautions 6. When the TOE00 is 0, set the TOE00, LVS00, and LVR00 at the same time with the 8-bit
memory manipulation instruction. When the TOE00 is 1, the LVS00 and LVR00 can be set
with the 1-bit memory manipulation instruction.
(4) Prescaler mode register 00 (PRM00)
This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid
edges.
PRM00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets the value of PRM00 to 00H.
Figure 6-8. Format of Prescaler Mode Register 00 (PRM00)
Address: FF61H After reset: 00H R/W
Symbol
PRM00
7
6
5
4
3
0
2
0
1
0
ES110
ES100
ES010
ES000
PRM001
PRM000
ES110
ES100
TI010 pin valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES010
ES000
TI000 pin valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
PRM001
PRM000
Count clock selection
0
0
1
1
0
1
0
1
fXP (10 MHz)
fXP/22 (2.5 MHz)
fXP/28 (39.06 kHz)
TI000 pin valid edgeNote
Remarks 1. fXP: Oscillation frequency of clock supplied to peripheral hardware
2. ( ): fXP = 10 MHz
Note The external clock requires a pulse longer than two cycles of the internal count clock (fXP).
Cautions 1. Always set data to PRM00 after stopping the timer operation.
2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start
mode and the capture trigger at the valid edge of the TI000 pin.
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Cautions 3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the
operation of the 16-bit timer counter 00 (TM00) is enabled
→ If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is
then enabled after a low level is input to the TI0n0 pin
→ If the falling edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is
enabled.
<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is
then enabled after a high level is input to the TI0n0 pin
→ If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
4. The sampling clock used to eliminate noise differs when a TI000 valid edge is used as the
count clock and when it is used as a capture trigger. In the former case, the count clock
is fXP, and in the latter case the count clock is selected by prescaler mode register 00
(PRM00). The capture operation is not performed until the valid edge is sampled and the
valid level is detected twice, thus eliminating noise with a short pulse width.
5. When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer
output (TO00). When using P21 as the timer output pin (TO00), it cannot be used as the
input pin (TI010) of the valid edge.
Remark n = 0, 1
(5) Port mode register 2 (PM2) and port mode control register 2 (PMC2)
When using the P21/TO00/TI010/ANI1/INTP0 pin for timer output, clear PM21, the output latch of P21, and
PMC21 to 0.
When using the P20/TI000/TOH1/ANI0 and P21/TO00/TI010/ANI1/INTP0 pins as a timer input, set PM20 and
PM21 to 1, and clear PMC20 and PMC21 to 0.
At this time, the output latches of P20 and P21 can be either 0 or 1.
PM2 and PMC2 are set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets the value of PM2 to FFH, and clears the value of PMC2 to 00H.
Figure 6-9. Format of Port Mode Register 2 (PM2)
Address: FF22H After reset: FFH R/W
Symbol
PM2
7
1
6
1
5
1
4
1
3
2
1
0
PM23
PM22
PM21
PM20
PM2n
P2n pin I/O mode selection (n = 0 to 3)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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Figure 6-10. Format of Port Mode Control Register 2 (PMC2)
Address: FF84H After reset: 00H R/W
Symbol
PMC2
7
0
6
0
5
0
4
0
3
2
1
0
PMC23
PMC22
PMC21
PMC20
PMC2n
Specification of operation mode (n = 0 to 3)
0
1
Port/Alternate-function (except A/D converter) mode
A/D converter mode
6.4 Operation of 16-Bit Timer/Event Counter 00
6.4.1 Interval timer operation
Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown
in Figure 6-11 allows operation as an interval timer.
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see Figure 6-11 for the set value).
<2> Set any value to the CR000 register.
<3> Set the count clock by using the PRM00 register.
<4> Set the TMC00 register to start the operation (see Figure 6-11 for the set value).
Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remark For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
Interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 000
(CR000) beforehand as the interval.
When the count value of 16-bit timer counter 00 (TM00) matches the value set to CR000, counting continues with
the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.
The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM000, PRM001) of
prescaler mode register 00 (PRM00).
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Figure 6-11. Control Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
1
1
0/1
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002 CRC001 CRC000
CRC00
0/1
0/1
0
CR000 used as compare register
(c) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00 0/1 0/1 0/1 0/1
3
0
2
0
PRM001 PRM000
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the
description of the respective control registers for details.
Figure 6-12. Interval Timer Configuration Diagram
16-bit timer capture/compare
register 000 (CR000)
INTTM000
fXP
f
f
XP/22
XP/28
Note
16-bit timer counter 00
(TM00)
OVF00
Noise
eliminator
TI000/ANI0/
TOH1/P20
Clear
circuit
f
XP
Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.
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Figure 6-13. Timing of Interval Timer Operation
t
Count clock
TM00 count value
0000H
0001H
N
0000H 0001H
N
0000H 0001H
N
N
Timer operation enabled
N
Clear
Clear
N
N
CR000
INTTM000
Interrupt acknowledged
Interrupt acknowledged
Remark Interval time = (N + 1) × t
N = 0001H to FFFFH (settable range)
When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare
register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting,
overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N)
before the change, it is necessary to restart the timer after changing CR000.
Figure 6-14. Timing After Change of Compare Register During Timer Count Operation (N → M: N > M )
Count clock
N
M
CR000
X – 1
X
FFFFH
0000H
0001H
0002H
TM00 count value
Remark N > X > M
6.4.2 External event counter operation
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see Figure 6-15 for the set value).
<2> Set the count clock by using the PRM00 register.
<3> Set any value to the CR000 register (0000H cannot be set).
<4> Set the TMC00 register to start the operation (see Figure 6-15 for the set value).
Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control
register 2 (PMC2).
2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
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The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit
timer counter 00 (TM00).
TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input.
When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is
cleared to 0 and the interrupt request signal (INTTM000) is generated.
Input a value other than 0000H to CR000. (A count operation with a pulse cannot be carried out.)
The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES000 and ES010) of
prescaler mode register 00 (PRM00).
Because an operation is carried out only when the valid edge of the TI000 pin is detected twice after sampling with
the internal clock (fXP), noise with a short pulse width can be removed.
Figure 6-15. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
1
1
0/1
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002 CRC001 CRC000
CRC00
0/1
0/1
0
CR000 used as compare register
(c) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00 0/1 0/1
3
0
2
0
PRM001 PRM000
0
1
1
1
Selects external clock.
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.
See the description of the respective control registers for details.
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Figure 6-16. External Event Counter Configuration Diagram
Internal bus
16-bit timer capture/compare
register 000 (CR000)
Match
Clear
INTTM000
OVF00Note
f
XP
16-bit timer counter 00 (TM00)
Noise eliminator
Valid edge of TI000
Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.
Figure 6-17. External Event Counter Operation Timing (with Rising Edge Specified)
(1) INTTM000 generation timing immediately after operation starts
Counting is started after a valid edge is detected twice.
Count starts
TI000 pin input
TM00 count value
CR000
2
3
1
0000H 0001H 0002H 0003H
N
N
|2
N
|1
N
0000H 0001H 0002H
INTTM000
(2) INTTM000 generation timing after INTTM000 has been generated twice
TI000 pin input
TM00 count value
CR000
N
0000H 0001H 0002H 0003H 0004H
N
N
|1
N
0000H 0001H 0002H 0003H
INTTM000
Caution When reading the external event counter count value, TM00 should be read.
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6.4.3 Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer
counter 00 (TM00).
There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate
the necessary pulse width. Clear the overflow flag after checking it.
The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by
prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating
noise with a short pulse width.
Figure 6-18. CR010 Capture Operation with Rising Edge Specified
Count clock
TM00
N − 3
N − 2
N − 1
N
N + 1
TI000
Rising edge detection
N
CR010
INTTM010
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see Figures 6-19, 6-22, 6-24, and 6-26 for the set value).
<2> Set the count clock by using the PRM00 register.
<3> Set the TMC00 register to start the operation (see Figures 6-19, 6-22, 6-24, and 6-26 for the set value).
Caution To use two capture registers, set the TI000 and TI010 pins.
Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 2 (PM2) and port mode
control register 2 (PMC2).
2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 10 INTERRUPT
FUNCTIONS.
(1) Pulse width measurement with free-running counter and one capture register
When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler
mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer
capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set.
Specify both the rising and falling edges by using bits 4 and 5 (ES000 and ES010) of PRM00.
Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed
when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width.
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Figure 6-19. Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register (When TI000 and CR010 Are Used)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002 CRC001 CRC000
CRC00
1
0/1
0
CR000 used as compare register
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101 ES100 ES010 ES000
PRM00 0/1 0/1
3
0
2
0
PRM001 PRM000
1
1
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
Figure 6-20. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
fXP
16-bit timer/counter 00
(TM00)
f
f
XP/22
OVF00
XP/28
16-bit timer capture/compare
register 010 (CR010)
TI000/ANI0/
TOH1/P20
INTTM010
Internal bus
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Figure 6-21. Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified)
t
Count clock
0000H 0001H
D0 D0 + 1
D1 D1 + 1
FFFFH 0000H
D2
D3
TM00 count value
TI000 pin input
CR010 capture value
INTTM010
D0
D1
D2
D3
Note
OVF00
(D1 − D0) × t
(10000H − D1 + D2) × t
(D3 − D2) × t
Note OVF00 must be cleared by software.
(2) Measurement of two pulse widths with free-running counter
When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously
measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin.
When the edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00 (PRM00) is input
to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an
interrupt request signal (INTTM010) is set.
Also, when the edge specified by bits 6 and 7 (ES100 and ES110) of PRM00 is input to the TI010 pin, the
value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal
(INTTM000) is set.
Specify both the rising and falling edges as the edges of the TI000 and TI010 pins, by using bits 4 and 5
(ES000 and ES010) and bits 6 and 7 (ES100 and ES110) of PRM00.
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a
capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus
eliminating noise with a short pulse width.
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Figure 6-22. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002 CRC001 CRC000
CRC00
1
0
1
CR000 used as capture register
Captures valid edge of TI010 pin to CR000.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
3
0
2
0
PRM001 PRM000
PRM00
1
1
1
1
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Specifies both edges for pulse width detection.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified)
t
Count clock
0000H 0001H
D0 D0 + 1
D1 D1 + 1
FFFFH 0000H
D2 D2 + 1 D2 + 2
D3
TM00 count value
TI000 pin input
CR010 capture value
INTTM010
D0
D1
D2
TI010 pin input
CR000 capture value
INTTM000
D1
D2 + 1
Note
OVF00
(D1 − D0) × t
(10000H − D1 + D2) × t
(D3 − D2) × t
(10000H − D1 + (D2 + 1)) × t
Note OVF00 must be cleared by software.
(3) Pulse width measurement with free-running counter and two capture registers
When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse
width of the signal input to the TI000 pin.
When the rising or falling edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00
(PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010
(CR010) and an interrupt request signal (INTTM010) is set.
Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken
into 16-bit timer capture/compare register 000 (CR000).
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a
capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating
noise with a short pulse width.
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Figure 6-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002 CRC001 CRC000
CRC00
1
1
1
CR000 used as capture register
Captures to CR000 at inverse edge
to valid edge of TI000Note
.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00 0/1 0/1
3
0
2
0
PRM001 PRM000
0
1
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Note If the valid edge of TI000 is specified to be both the rising and falling edges, 16-bit timer capture/compare
register 000 (CR000) cannot perform the capture operation. When the CRC001 bit value is 1, the TM00
count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected, but the
input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at
that timing.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-25. Timing of Pulse Width Measurement Operation by Free-Running Counter
and Two Capture Registers (with Rising Edge Specified)
t
Count clock
TM00 count value
TI000 pin input
0000H 0001H
D0 D0 + 1
D1 D1 + 1
FFFFH 0000H
D2 D2 + 1
D3
CR010 capture value
CR000 capture value
INTTM010
D0
D2
D1
D3
Note
OVF00
(D1 − D0) × t
(10000H − D1 + D2) × t
(D3 − D2) × t
Note OVF00 must be cleared by software.
(4) Pulse width measurement by means of restart
When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer/counter 00 (TM00) is
taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to
the TI000 pin is measured by clearing TM00 and restarting the count.
The edge specification can be selected from two types, rising or falling edges, by bits 4 and 5 (ES000 and
ES010) of prescaler mode register 00 (PRM00)
Sampling is performed at the interval selected by prescaler mode register 00 (PRM00) and a capture operation
is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short
pulse width.
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Figure 6-26. Control Register Settings for Pulse Width Measurement by Means of Restart
(with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
1
0
0/1
0
Clears and starts at valid edge of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002 CRC001 CRC000
CRC00
1
1
1
CR000 used as capture register
Captures to CR000 at inverse edge to valid edge of
Note
TI000
.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00 0/1 0/1
3
0
2
0
PRM001 PRM000
0
1
0/1
0/1
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Note If the valid edge of TI000 is specified to be both the rising and falling edges, 16-bit timer capture/compare
register 000 (CR000) cannot perform the capture operation.
Figure 6-27. Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified)
t
Count clock
0000H 0001H
D0 0000H 0001H D1
D2 0000H 0001H
TM00 count value
TI000 pin input
CR010 capture value
D0
D2
D1
CR000 capture value
INTTM010
D1 × t
D2 × t
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6.4.4 Square-wave output operation
Setting
The basic operation setting procedure is as follows.
<1> Set the count clock by using the PRM00 register.
<2> Set the CRC00 register (see Figure 6-28 for the set value).
<3> Set the TOC00 register (see Figure 6-28 for the set value).
<4> Set any value to the CR000 register (0000H cannot be set).
<5> Set the TMC00 register to start the operation (see Figure 6-28 for the set value).
Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control
register 2 (PMC2).
2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
A square wave with any selected frequency can be output at intervals determined by the count value preset to 16-
bit timer capture/compare register 000 (CR000).
The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 + 1 by setting
bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave
with any selected frequency to be output.
Figure 6-28. Control Register Settings in Square-Wave Output Mode (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
1
1
0
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002 CRC001 CRC000
CRC00
0/1
0/1
0
CR000 used as compare register
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Figure 6-28. Control Register Settings in Square-Wave Output Mode (2/2)
(c) 16-bit timer output control register 00 (TOC00)
7
0
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
TOC00
0
0
0
0/1
0/1
1
1
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting “11” is prohibited).
Does not invert output on match between TM00 and CR010.
Disables one-shot pulse output.
(d) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00 0/1 0/1 0/1 0/1
3
0
2
0
PRM001 PRM000
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the
description of the respective control registers for details.
Figure 6-29. Square-Wave Output Operation Timing
Count clock
TM00 count value
CR000
0000H 0001H 0002H
N − 1
N
0000H 0001H 0002H
N − 1
N
0000H
N
INTTM000
TO00 pin output
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6.4.5 PPG output operations
Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown
in Figure 6-30 allows operation as PPG (Programmable Pulse Generator) output.
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see Figure 6-30 for the set value).
<2> Set any value to the CR000 register as the cycle.
<3> Set any value to the CR010 register as the duty factor.
<4> Set the TOC00 register (see Figure 6-30 for the set value).
<5> Set the count clock by using the PRM00 register.
<6> Set the TMC00 register to start the operation (see Figure 6-30 for the set value).
Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2) and port mode control
register 2 (PMC2).
2. For how to enable the INTTM000 interrupt, see CHAPTER 10 INTERRUPT FUNCTIONS.
3. n = 0 or 1
In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle
that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer
capture/compare register 000 (CR000), respectively.
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Figure 6-30. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
1
1
0
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002 CRC001 CRC000
CRC00
0
×
0
CR000 used as compare register
CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
TOC00
0
0
0
1
0/1
0/1
1
1
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting "11" is prohibited).
Inverts output on match between TM00 and CR010.
Disables one-shot pulse output.
(d) Prescaler mode register 00 (PRM00)
ES110 ES100 ES010 ES000
PRM00 0/1 0/1 0/1 0/1
3
0
2
PRM001 PRM000
0
0/1
0/1
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Cautions 1. Values in the following range should be set in CR000 and CR010:
0000H < CR010 < CR000 ≤ FFFFH
2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of
(CR010 setting value + 1)/(CR000 setting value + 1).
Remark ×: Don’t care
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Figure 6-31. Configuration Diagram of PPG Output
16-bit timer capture/compare
register 000 (CR000)
f
XP
f
f
XP/22
XP/28
Clear
circuit
16-bit timer counter 00
(TM00)
Noise
eliminator
TI000/ANI0/
TOH1/P20
TO00/TI010/ANI1/
INTP0/P21
f
XP
16-bit timer capture/compare
register 010 (CR010)
Figure 6-32. PPG Output Operation Timing
t
Count clock
TM00 count value
0000H 0001H
M − 1
M
0000H 0001H
N
N − 1
N
Clear
Clear
CR000 capture value
CR010 capture value
TO00
N
M
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
Remark 0000H < M < N ≤ FFFFH
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6.4.6 One-shot pulse output operation
16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external
trigger (TI000 pin input).
Setting
The basic operation setting procedure is as follows.
<1> Set the count clock by using the PRM00 register.
<2> Set the CRC00 register (see Figures 6-33 and 6-35 for the set value).
<3> Set the TOC00 register (see Figures 6-33 and 6-35 for the set value).
<4> Set any value to the CR000 and CR010 registers (0000H cannot be set).
<5> Set the TMC00 register to start the operation (see Figures 6-33 and 6-35 for the set value).
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 2 (PM2).
2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 10
INTERRUPT FUNCTIONS.
(1) One-shot pulse output with software trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in
Figure 6-33, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.
By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes
active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that,
the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000
(CR000)Note
.
Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00
register, the TMC003 and TMC002 bits of the TMC00 register must be cleared to 00.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 register. Do not set N to M.
Cautions 1. Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the
one-shot pulse again, wait until the current one-shot pulse output is completed.
2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software
trigger, do not change the level of the TI000 pin or its alternate-function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even
at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a
pulse at an undesired timing.
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Figure 6-33. Control Register Settings for One-Shot Pulse Output with Software Trigger
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
0
1
0
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
6
5
0
4
0
3
0
CRC002 CRC001 CRC000
0/1
CRC00
0
0
0
0
CR000 as compare register
CR010 as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
0
OSPT00 OSPE00 TOC004 LVS00
LVR00 TOC001 TOE00
0/1
TOC00
0
1
1
0/1
1
1
Enables TO00 output.
Inverts output upon match
between TM00 and CR000.
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010.
Sets one-shot pulse output mode.
Set to 1 for output.
(d) Prescaler mode register 00 (PRM00)
ES110
0/1
ES100
0/1
ES010
0/1
ES000
0/1
3
0
2
0
PRM001 PRM010
0/1 0/1
PRM00
Selects count clock.
Setting invalid
(setting “10” is prohibited.)
Setting invalid
(setting “10” is prohibited.)
Caution Do not set 0000H to the CR000 and CR010 registers.
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Figure 6-34. Timing of One-Shot Pulse Output Operation with Software Trigger
Set TMC00 to 04H
(TM00 count starts)
Count clock
TM00 count
CR010 set value
CR000 set value
0000H 0001H
N
N + 1 0000H
N − 1
N
N
M − 1
M
M + 1 M + 2
N
N
N
M
M
M
M
OSPT00
INTTM010
INTTM000
TO00 pin output
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop
mode) is set to the TMC003 and TMC002 bits.
Remark N < M
(2) One-shot pulse output with external trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in
Figure 6-35, and by using the valid edge of the TI000 pin as an external trigger.
The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES010) of prescaler mode register 00
(PRM00). The rising, falling, or both the rising and falling edges can be specified.
When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the
output becomes active at the count value set in advance to 16-bit timer capture/compare register 010
(CR010). After that, the output becomes inactive at the count value set in advance to 16-bit timer
capture/compare register 000 (CR000)Note
.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 register. Do not set N to M.
Caution Do not input the external trigger again while the one-shot pulse is output.
To output the one-shot pulse again, wait until the current one-shot pulse output is
completed.
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Figure 6-35. Control Register Settings for One-Shot Pulse Output with External Trigger
(with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003 TMC002 TMC001 OVF00
TMC00
1
0
0
0
Clears and starts at
valid edge of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
7
6
5
0
4
0
3
0
CRC002 CRC001 CRC000
0/1
CRC00
0
0
0
0
CR000 used as compare register
CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
0
OSPT00 OSPE00 TOC004 LVS00
LVR00 TOC001 TOE00
0/1
TOC00
0
1
1
0/1
1
1
Enables TO00 output.
Inverts output upon match
between TM00 and CR000.
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010.
Sets one-shot pulse output mode.
(d) Prescaler mode register 00 (PRM00)
ES110
0/1
ES100
0/1
ES010
0
ES000
1
3
0
2
0
PRM001 PRM000
0/1 0/1
PRM00
Selects count clock
(setting “11” is prohibited).
Specifies the rising edge
for pulse width detection.
Setting invalid
(setting “10” is prohibited.)
Caution Do not set 0000H to the CR000 and CR010 registers.
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Figure 6-36. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
When TMC00 is set to 08H
(TM00 count starts)
t
Count clock
TM00 count value
CR010 set value
CR000 set value
0000H 0001H
0000H
N
N
N + 1 N + 2
M − 2 M − 1
M
M + 1 M + 2
N
N
N
M
M
M
M
TI000 pin input
INTTM010
INTTM000
TO00 pin output
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is
set to the TMC002 and TMC003 bits.
Remark N < M
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6.5 Cautions Related to 16-Bit Timer/Event Counter 00
(1) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Figure 6-37. Start Timing of 16-Bit Timer Counter 00 (TM00)
Count clock
0000H
0001H
0002H
0003H
0004H
TM00 count value
Timer start
(2) 16-bit timer counter 00 (TM00) operation
<1> 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop
mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the
operation.
<2> Even if TM00 is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010).
<3> During TM00 is read, the count clock is stopped.
<4> Regardless of the CPU’s operation mode, when the timer stops, the signals input to pins TI000/TI010
are not acknowledged.
(3) Setting of 16-bit timer capture/compare registers 000, 010 (CR000, CR010)
<1> Set 16-bit timer capture/compare register 000 (CR000) to other than 0000H in the clear & start mode
entered on match between TM00 and CR000. This means a 1-pulse count operation cannot be
performed when this register is used as an external event counter.
<2> When the clear & start mode entered on a match between TM00 and CR000 is selected, CR000 should
not be specified as a capture register.
<3> In the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR0n0 is
set to 0000H, an interrupt request (INTTM0n0) is generated when CR0n0 changes from 0000H to
0001H following overflow (FFFFH).
<4> If the new value of CR0n0 is less than the value of TM00, TM00 continues counting, overflows, and then
starts counting from 0 again. If the new value of CR0n0 is less than the old value, therefore, the timer
must be reset to be restarted after the value of CR0n0 is changed.
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(4) Capture register data retention
The values of 16-bit timer capture/compare registers 0n0 (CR0n0) after 16-bit timer/event counter 00 has
stopped are not guaranteed.
Remark n = 0, 1
(5) Setting of 16-bit timer mode control register 00 (TMC00)
The timer operation must be stopped before writing to bits other than the OVF flag.
(6) Setting of capture/compare control register 00 (CRC00)
The timer operation must be stopped before setting CRC00.
(7) Setting of 16-bit timer output control register 00 (TOC00)
<1> Timer operation must be stopped before setting other than OSPT00.
<2> If LVS00 and LVR00 are read, 0 is read.
<3> OSPT00 is automatically cleared after data is set, so 0 is read.
<4> Do not set OSPT00 to 1 other than in one-shot pulse output mode.
<5> A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00)
is required to write to OSPT00 successively.
(8) Setting of prescaler mode register 00 (PRM00)
Always set data to PRM00 after stopping the timer operation.
(9) Valid edge setting
Set the valid edge of the TI000 pin with bits 4 and 5 (ES000 and ES010) of prescaler mode register 00
(PRM00) after stopping the timer operation.
(10) One-shot pulse output
One-shot pulse output normally operates only in the free-running mode or in the clear & start mode at the valid
edge of the TI000 pin. Because an overflow does not occur in the clear & start mode on a match between
TM00 and CR000, one-shot pulse output is not possible.
(11) One-shot pulse output by software
<1> Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the one-shot
pulse again, wait until the current one-shot pulse output is completed.
<2> When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not
change the level of the TI000 pin or its alternate function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even at the level
of the TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing.
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<3> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.
(12) One-shot pulse output with external trigger
<1> Do not input the external trigger again while the one-shot pulse is output.
To output the one-shot pulse again, wait until the current one-shot pulse output is completed.
<2> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.
(13) Operation of OVF00 flag
<1> The OVF00 flag is also set to 1 in the following case.
Either of the clear & start mode entered on a match between TM00 and CR000, clear & start at the valid
edge of the TI000 pin, or free-running mode is selected.
↓
CR000 is set to FFFFH.
↓
When TM00 is counted up from FFFFH to 0000H.
Figure 6-38. Operation Timing of OVF00 Flag
Count clock
CR000
TM00
FFFFH
FFFEH
FFFFH
0000H
0001H
OVF00
INTTM000
<2> Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H)
after the occurrence of a TM00 overflow, the OVF00 flag is reset newly and clear is disabled.
(14) Conflicting operations
If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture
register, the capture trigger input takes precedence and the read data is undefined. Also, if the count stop of
the timer and the input of the capture trigger conflict, the captured data is undefined.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-39. Capture Register Data Retention Timing
Count clock
TM00 count value
Edge input
N
N + 1
N + 2
M
M + 1
M + 2
INTTM010
Capture read signal
CR010 capture value
X
N + 2
M + 1
Capture
Capture, but
read value is
not guaranteed
(15) Capture operation
<1> If the TI000 pin is specified as the valid edge of the count clock, a capture operation by the capture
register specified as the trigger for the TI000 pin is not possible.
<2> If both the rising and falling edges are selected as the valid edges of the TI000 pin, capture is not
performed.
<3> When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a
valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external
interrupt source because INTTM000 is generated at that timing.
<4> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two
cycles of the count clock selected by prescaler mode register 00 (PRM00).
<5> The capture operation is performed at the fall of the count clock. A interrupt request input (INTTM0n0),
however, occurs at the rise of the next count clock.
<6> To use two capture registers, set the TI000 and TI010 pins.
Remark n = 0, 1
(16) Compare operation
The capture operation may not be performed for CR0n0 set in compare mode even if a capture trigger is input.
Remark n = 0, 1
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(17) Changing compare register during timer operation
<1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare register, when changing
CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer
capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the
timing of the match, so the operation is not guaranteed in such cases. To change CR0n0 during timer
counting, follow the procedure below using an INTTM000 interrupt.
<Changing cycle (CR000)>
1. Disable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 0).
2. Disable the INTTM000 interrupt (TMMK000 = 1).
3. Rewrite CR000.
4. Wait for 1 cycle of the TM00 count clock.
5. Enable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 1).
6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0).
7. Enable the INTTM000 interrupt (TMMK000 = 0).
<Changing duty (CR010)>
1. Disable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 0).
2. Disable the INTTM000 interrupt (TMMK000 = 1).
3. Rewrite CR010.
4. Wait for 1 cycle of the TM00 count clock.
5. Enable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 1).
6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0).
7. Enable the INTTM000 interrupt (TMMK000 = 0).
While interrupts and timer output inversion are disabled (1 to 4 above), timer counting is continued. If
the value to be set in CR0n0 is small, the value of TM00 may exceed CR0n0. Therefore, set the value,
considering the time lapse of the timer clock and CPU after an INTTM000 interrupt has been generated.
Remark n = 0 or 1
<2> If CR010 is changed during timer counting without performing processing <1> above, the value in
CR010 may be rewritten twice or more, causing an inversion of the output level of the TO00 pin at each
rewrite.
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(18) Edge detection
<1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
(a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit
timer counter 00 (TM00) is enabled
→ If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
(b) If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled
after a low level is input to the TI0n0 pin
→ If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,
a falling edge is detected immediately after the TM00 operation is enabled.
(c) When the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then
enabled after a high level is input to the TI0n0 pin
→ If the rising edge or both rising and falling edges are specified as the valid edge, of the TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
Remark n = 0, 1
<2> The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and
when it is used as a capture trigger. In the former case, the count clock is fXP, and in the latter case the
count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise with a short
pulse width.
(19) External event counter
When reading the external event counter count value, TM00 should be read.
(20) PPG output
<1> Values in the following range should be set in CR000 and CR010:
0000H < CR010 < CR000 ≤ FFFFH (setting CR000 to 0000H is prohibited)
<2> The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010
setting value + 1)/(CR000 setting value + 1).
(21) STOP mode or system clock stop mode setting
Except when TI000 pin valid edge is selected as the count clock, stop the timer operation before setting STOP
mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts.
(22) P21/TI010/TO00 pin
When using P21 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00).
When using P21 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge.
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CHAPTER 7 8-BIT TIMER H1
7.1 Functions of 8-Bit Timer H1
8-bit timer H1 has the following functions.
•
•
•
Interval timer
PWM output mode
Square-wave output
7.2 Configuration of 8-Bit Timer H1
8-bit timer H1 consists of the following hardware.
Table 7-1. Configuration of 8-Bit Timer H1
Item
Timer register
Registers
Configuration
8-bit timer counter H1
8-bit timer H compare register 01 (CMP01)
8-bit timer H compare register 11 (CMP11)
Timer output
TOH1
Control registers
8-bit timer H mode register 1 (TMHMD1)
Port mode register 2 (PM2)
Port register 2 (P2)
Port mode control register 2 (PMC2)
Figure 7-1 shows a block diagram.
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Figure 7-1. Block Diagram of 8-Bit Timer H1
Internal bus
8-bit timer H mode register 1
(TMHMD1)
8-bit timer H
compare register
11 (CMP11)
8-bit timer H
compare register
01 (CMP01)
TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
3
2
Decoder
TOH1/TI000/
ANI1/P20
Selector
Output latch
(P20)
F/F
R
Match
Level
inversion
PM20
Interrupt
generator
Output
controller
fXP
f
f
f
XP/22
XP/24
XP/26
8-bit timer
counter H1
f
XP/212
Clear
f
RL/27
PWM mode signal
1
0
Timer H enable signal
INTTMH1
CHAPTER 7 8-BIT TIMER H1
(1) 8-bit timer H compare register 01 (CMP01)
This register can be read or written by an 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
Figure 7-2. Format of 8-Bit Timer H Compare Register 01 (CMP01)
Address: FF0EH After reset: 00H R/W
Symbol
CMP01
7
5
3
2
1
0
6
4
Caution CMP01 cannot be rewritten during timer count operation.
(2) 8-bit timer H compare register 11 (CMP11)
This register can be read or written by an 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
Figure 7-3. Format of 8-Bit Timer H Compare Register 11 (CMP11)
Address: FF0FH After reset: 00H R/W
Symbol
CMP11
7
5
3
2
1
0
6
4
CMP11 can be rewritten during timer count operation.
If the CMP11 value is rewritten during timer operation, transferring is performed at the timing at which the count
value and CMP11 value match. If the transfer timing and writing from CPU to CMP11 conflict, transfer is not
performed.
Caution In the PWM output mode, be sure to set CMP11 when starting the timer count operation (TMHE1
= 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting
the same value to CMP11).
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7.3 Registers Controlling 8-Bit Timer H1
The following four registers are used to control 8-Bit Timer H1.
• 8-bit timer H mode register 1 (TMHMD1)
• Port mode register 2 (PM2)
• Port register 2 (P2)
• Port mode control register 2 (PMC2)
(1) 8-bit timer H mode register 1 (TMHMD1)
This register controls the mode of timer H.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
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Figure 7-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
Address: FF70H After reset: 00H R/W
<7>
5
3
2
<1>
<0>
6
4
Symbol
TMHMD1
TMHE1 CKS12
CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
TMHE1
Timer operation enable
0
1
Stop timer count operation (counter is cleared to 0)
Enable timer count operation (count operation started by inputting clock)
CKS12
CKS11
CKS10
Count clock (fCNT) selection
(10 MHz)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
f
f
f
f
f
f
XP
XP/22 (2.5 MHz)
XP/24 (625 kHz)
XP/26 (156.25 kHz)
XP/212 (2.44 kHz)
RL/27 (1.88 kHz (TYP.))
Other than above
Setting prohibited
TMMD11 TMMD10
Timer operation mode
0
1
0
0
Interval timer mode
PWM output mode
Other than above Setting prohibited
TOLEV1
Timer output level control (in default mode)
0
1
Low level
High level
TOEN1
Timer output control
0
1
Disable output
Enable output
Cautions 1. When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited.
2. In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when
starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped
(TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register).
Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware
2. fRL: Low-speed Ring-OSC clock oscillation frequency
3. Figures in parentheses apply to operation at fXP = 10 MHz, fRL = 240 kHz (TYP.).
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(2) Port mode register 2 (PM2) and port mode control register 2 (PMC2)
When using the P20/TOH1/TI000/ANI0 pin for timer output, clear PM20, the output latch of P20, and PMC20 to 0.
PM2 and PMC2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets PM2 to FFH, and clears PMC2 to 00H.
Figure 7-5. Format of Port Mode Register 2 (PM2)
Address: FF22H After reset: FFH R/W
Symbol
PM2
7
1
6
1
5
1
4
1
3
2
1
0
PM23
PM22
PM21
PM20
PM2n
P2n pin I/O mode selection (n = 0 to 3)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
Figure 7-6. Format of Port Mode Control Register 2 (PMC2)
Address: FF84H After reset: 00H R/W
Symbol
PMC2
7
0
6
0
5
0
4
0
3
2
1
0
PMC23
PMC22
PMC21
PMC20
PMC2n
Specification of operation mode (n = 0 to 3)
0
1
Port/Alternate-function (except A/D converter) mode
A/D converter mode
7.4 Operation of 8-Bit Timer H1
7.4.1 Operation as interval timer/square-wave output
When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is
generated and 8-bit timer counter H1 is cleared to 00H.
Compare register 11 (CMP11) is not used in interval timer mode. Since a match of 8-bit timer counter H1 and the
CMP11 register is not detected even if the CMP11 register is set, timer output is not affected.
By setting bit 0 (TOEN1) of timer H mode register 1 (TMHMD1) to 1, a square wave of any frequency (duty = 50%)
is output from TOH1.
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(1) Usage
Generates the INTTMH1 signal repeatedly at the same interval.
<1> Set each register.
Figure 7-7. Register Setting During Interval Timer/Square-Wave Output Operation
(i) Setting timer H mode register 1 (TMHMD1)
TMHE1
0
CKS12 CKS11
0/1 0/1
CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
0/1 0/1 0/1
TMHMD1
0
0
Timer output setting
Timer output level inversion setting
Interval timer mode setting
Count clock (fCNT) selection
Count operation stopped
(ii) CMP01 register setting
Compare value (N)
•
<2> Count operation starts when TMHE1 = 1.
<3> When the values of 8-bit timer counter H1 and the CMP01 register match, the INTTMH1 signal is generated
and 8-bit timer counter H1 is cleared to 00H.
Interval time = (N +1)/fCNT
<4> Subsequently, the INTTMH1 signal is generated at the same interval. To stop the count operation, clear
TMHE1 to 0.
(2) Timing chart
The timing of the interval timer/square-wave output operation is shown below.
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Figure 7-8. Timing of Interval Timer/Square-Wave Output Operation (1/2)
(a) Basic operation
Count clock
Count start
00H
01H
N
N
00H
Clear
01H
N
00H 01H 00H
Clear
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
Interval time
<1>
<2>
Level inversion,
<3>
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter H1 clear
match interrupt occurrence,
8-bit timer counter H1 clear
<1> The count operation is enabled by setting the TMHE1 bit to 1. The count clock starts counting no more than
1 clock after the operation is enabled.
<2> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1
is cleared, the TOH1 output level is inverted, and the INTTMH1 signal is output.
<3> The INTTMH1 signal and TOH1 output become inactive by clearing the TMHE1 bit to 0 during timer H1
operation. If these are inactive from the first, the level is retained.
Remark N = 01H to FEH
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Figure 7-8. Timing of Interval Timer/Square-Wave Output Operation (2/2)
(b) Operation when CMP01 = FFH
Count clock
Count start
00H
00H
01H
FEH
FFH
00H
FEH
FFH
8-bit timer counter H1
Clear
Clear
FFH
CMP01
TMHE1
INTTMH1
TOH1
Interval time
(c) Operation when CMP01 = 00H
Count clock
Count start
00H
00H
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
Interval time
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CHAPTER 7 8-BIT TIMER H1
7.4.2 Operation as PWM output mode
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register
during timer operation is prohibited.
8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register
during timer operation is possible.
The operation in PWM output mode is as follows.
TOH1 output becomes active and 8-bit timer counter H1 is cleared to 0 when 8-bit timer counter H1 and the
CMP01 register match after the timer count is started. TOH1 output becomes inactive when 8-bit timer counter H1
and the CMP11 register match.
(1) Usage
In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.
<1> Set each register.
Figure 7-9. Register Setting in PWM Output Mode
(i) Setting timer H mode register 1 (TMHMD1)
TMHE1
0
CKS12 CKS11
0/1 0/1
CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
0/1 0/1
TMHMD1
1
0
1
Timer output enabled
Timer output level inversion setting
PWM output mode selection
Count clock (fCNT) selection
Count operation stopped
(ii) Setting CMP01 register
• Compare value (N): Cycle setting
(iii) Setting CMP11 register
• Compare value (M): Duty setting
Remark 00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH
<2> The count operation starts when TMHE1 = 1.
<3> The CMP01 register is the compare register that is to be compared first after count operation is enabled.
When the values of 8-bit timer counter H1 and the CMP01 register match, 8-bit timer counter H1 is cleared,
an interrupt request signal (INTTMH1) is generated, and TOH1 output becomes active. At the same time,
the compare register to be compared with 8-bit timer counter H1 is changed from the CMP01 register to the
CMP11 register.
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<4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the
compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the
CMP01 register. At this time, 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not
generated.
<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained.
<6> To stop the count operation, set TMHE1 = 0.
If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock
frequency is fCNT, the PWM pulse output cycle and duty are as follows.
PWM pulse output cycle = (N+1)/fCNT
Duty = Active width : Total width of PWM = (M + 1) : (N + 1)
Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKS12 to CKS10
bits of the TMHMD1 register) are required to transfer the CMP11 register value after
rewriting the register.
2. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after
the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the
same value to the CMP11 register).
(2) Timing chart
The operation timing in PWM output mode is shown below.
Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are
within the following range.
00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH
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CHAPTER 7 8-BIT TIMER H1
Figure 7-10. Operation Timing in PWM Output Mode (1/4)
(a) Basic operation
Count clock
00H 01H
A5H 00H 01H 02H
A5H 00H 01H 02H
A5H 00H
8-bit timer counter H1
A5H
01H
CMP01
CMP11
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
<4>
<2>
<3>
<1>
TOH1
(TOLEV1 = 1)
<1> The count operation is enabled by setting the TMHE1 bit to 1. Start 8-bit timer counter H1 by masking one
count clock to count up. At this time, TOH1 output remains inactive (when TOLEV1 = 0).
<2> When the values of 8-bit timer counter H1 and the CMP01 register match, the TOH1 output level is inverted,
the value of 8-bit timer counter H1 is cleared, and the INTTMH1 signal is output.
<3> When the values of 8-bit timer counter H1 and the CMP11 register match, the level of the TOH1 output is
returned. At this time, the 8-bit timer counter value is not cleared and the INTTMH1 signal is not output.
<4> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive.
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Figure 7-10. Operation Timing in PWM Output Mode (2/4)
(b) Operation when CMP01 = FFH, CMP11 = 00H
Count clock
8-bit timer counter H1
00H 01H
FFH 00H 01H 02H
FFH 00H 01H 02H
FFH 00H
FFH
00H
CMP01
CMP11
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
(c) Operation when CMP01 = FFH, CMP11 = FEH
Count clock
00H 01H
FEH FFH 00H 01H
FEH FFH 00H 01H
FEH FFH 00H
8-bit timer counter H1
FFH
FEH
CMP01
CMP11
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
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CHAPTER 7 8-BIT TIMER H1
Figure 7-10. Operation Timing in PWM Output Mode (3/4)
(d) Operation when CMP01 = 01H, CMP11 = 00H
Count clock
00H 01H 00H 01H 00H
00H 01H 00H 01H
8-bit timer counter H1
CMP01
01H
00H
CMP11
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
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CHAPTER 7 8-BIT TIMER H1
Figure 7-10. Operation Timing in PWM Output Mode (4/4)
(e) Operation by changing CMP11 (CMP11 = 01H → 03H, CMP01 = A5H)
Count clock
8-bit timer counter H1
00H 01H 02H
A5H 00H 01H 02H 03H
A5H 00H 01H 02H 03H
A5H 00H
A5H
03H
CMP01
CMP11
01H
01H (03H)
<2>'
<2>
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
<3>
<4>
<6>
<1>
<5>
<1> The count operation is enabled by setting TMHE1 = 1. Start 8-bit timer counter H1 by masking one count
clock to count up. At this time, the TOH1 output remains inactive (when TOLEV1 = 0).
<2> The CMP11 register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
<3> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1
is cleared, the TOH1 output becomes active, and the INTTMH1 signal is output.
<4> If the CMP11 register value is changed, the value is latched and not transferred to the register. When the
values of 8-bit timer counter H1 and the CMP11 register before the change match, the value is transferred to
the CMP11 register and the CMP11 register value is changed (<2>’).
However, three count clocks or more are required from when the CMP11 register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
<5> When the values of 8-bit timer counter H1 and the CMP11 register after the change match, the TOH1 output
becomes inactive. 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated.
<6> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive.
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CHAPTER 8 WATCHDOG TIMER
8.1 Functions of Watchdog Timer
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, see CHAPTER 12 RESET FUNCTION.
Table 8-1. Loop Detection Time of Watchdog Timer
Loop Detection Time
During Low-Speed Ring-OSC Clock Operation
211/fRL (4.27 ms)
During System Clock Operation
213/fX (819.2 µs)
212/fRL (8.53 ms)
214/fX (1.64 ms)
215/fX (3.28 ms)
216/fX (6.55 ms)
217/fX (13.11 ms)
218/fX (26.21 ms)
219/fX (52.43 ms)
220/fX (104.86 ms)
213/fRL (17.07 ms)
214/fRL (34.13 ms)
215/fRL (68.27 ms)
216/fRL (136.53 ms)
217/fRL (273.07 ms)
218/fRL (546.13 ms)
Remarks 1. fRL: Low-speed Ring-OSC clock oscillation frequency
2. fX: System clock oscillation frequency
3. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz.
The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the on-chip
low-speed Ring-OSC oscillator as shown in Table 8-2.
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Table 8-2. Option Byte Setting and Watchdog Timer Operation Mode
Option Byte Setting
Low-Speed Ring-OSC Cannot Be Stopped
Low-Speed Ring-OSC Can Be Stopped by Software
Note 1
Watchdog timer clock
source
Fixed to fRL
.
• Selectable by software (fX, fRL or stopped)
• When reset is released: fRL
Operation after reset
Operation starts with the maximum interval (218/fRL). Operation starts with the maximum interval
(218/fRL).
Operation mode
selection
The interval can be changed only once.
The clock selection/interval can be changed only
once.
Features
The watchdog timer cannot be stopped.
The watchdog timer can be stoppedNote 2
.
Notes 1. As long as power is being supplied, low-speed Ring-OSC oscillation cannot be stopped (except in the reset
period).
2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock
source of the watchdog timer.
<1> If the clock source is fX, clock supply to the watchdog timer is stopped under the following conditions.
• When fX is stopped
• In HALT/STOP mode
• During oscillation stabilization time
<2> If the clock source is fRL, clock supply to the watchdog timer is stopped under the following conditions.
• If the CPU clock is fX and if fRL is stopped by software before execution of the STOP instruction
• In HALT/STOP mode
Remarks 1. fRL: Low-speed Ring-OSC clock oscillation frequency
2. fX: System clock oscillation frequency
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8.2 Configuration of Watchdog Timer
The watchdog timer consists of the following hardware.
Table 8-3. Configuration of Watchdog Timer
Item
Configuration
Control registers
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Figure 8-1. Block Diagram of Watchdog Timer
211/fRL to
218/fRL
Clock
input
controller
f
RL/22
Output
controller
16-bit
counter
Internal reset signal
Selector
f
/24
X
or
213/f
220/f
X
X
to
2
3
Clear
Option byte
(to set “low-speed
Ring-OSC cannot be
stopped” or “low-speed
Ring-OSC can be
0
1
1
WDCS4 WDCS3 WDCS2 WDCS1 WDCS0
Watchdog timer enable
register (WDTE)
Watchdog timer mode
register (WDTM)
stopped by software”)
Internal bus
Remarks 1. fRL: Low-speed Ring-OSC clock oscillation frequency
2. fX: System clock oscillation frequency
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8.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers.
•
•
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
Reset input sets this register to 67H.
Figure 8-2. Format of Watchdog Timer Mode Register (WDTM)
Address: FF48H After reset: 67H R/W
7
0
6
1
5
1
4
3
2
1
0
Symbol
WDTM
WDCS4
WDCS3
WDCS2
WDCS1
WDCS0
WDCS4Note 1 WDCS3Note 1
Operation clock selection
0
0
1
0
1
×
Low-speed Ring-OSC clock (fRL)
System Clock (fX)
Watchdog timer operation stopped
WDCS2Note 2 WDCS1Note 2 WDCS0Note 2
Overflow time setting
During low-speed Ring-OSC During system clock operation
clock operation
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
211/fRL (4.27 ms)
212/fRL (8.53 ms)
213/fRL (17.07 ms)
214/fRL (34.13 ms)
215/fRL (68.27 ms)
216/fRL (136.53 ms)
217/fRL (273.07 ms)
218/fRL (546.13 ms)
213/fX (819.2 µs)
214/fX (1.64 ms)
215/fX (3.28 ms)
216/fX (6.55 ms)
217/fX (13.11 ms)
218/fX (26.21 ms)
219/fX (52.43 ms)
220/fX (104.86 ms)
Notes 1. If “low-speed Ring-OSC cannot be stopped” is specified by the option byte, this cannot be set.
The low-speed Ring-OSC clock will be selected no matter what value is written.
2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “low-speed Ring-OSC cannot be
stopped” is selected by the option byte, other values are ignored).
2. After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated.
3. WDTM cannot be set by a 1-bit memory manipulation instruction.
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Cautions 4. When using the flash memory self programming by self writing, set the overflow time
for the watchdog timer so that enough everflow time is secured (Example 1-byte
writing: 200 µs MIN., 1-block deletion: 10 ms MIN.).
Remarks 1. fRL: Low-speed Ring-OSC clock oscillation frequency
2. fX: System clock oscillation frequency
3. ×: Don’t care
4. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz.
(2) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset input sets this register to 9AH.
Figure 8-3. Format of Watchdog Timer Enable Register (WDTE)
Address: FF49H After reset: 9AH R/W
7
6
5
4
3
2
1
0
Symbol
WDTE
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
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8.4 Operation of Watchdog Timer
8.4.1 Watchdog timer operation when “low-speed Ring-OSC cannot be stopped” is selected by option byte
The operation clock of watchdog timer is fixed to low-speed Ring-OSC.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
•
•
•
Operation clock: Low-speed Ring-OSC clock
Cycle: 218/fRL (546.13 ms: At operation with fRL = 480 kHz (MAX.))
Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instructionNotes 1, 2
Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
.
•
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1. The operation clock (low-speed Ring-OSC clock) cannot be changed. If any value is written to bits 3
and 4 (WDCS3, WDCS4) of WDTM, it is ignored.
2. As soon as WDTM is written, the counter of the watchdog timer is cleared.
Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction
execution. For 8-bit timer H1 (TMH1), a division of the low-speed Ring-OSC clock can be
selected as the count source, so clear the watchdog timer using the interrupt request of TMH1
before the watchdog timer overflows after STOP instruction execution. If this processing is not
performed, an internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
A status transition diagram is shown below
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Figure 8-4. Status Transition Diagram When “Low-Speed Ring-OSC Cannot Be Stopped”
Is Selected by Option Byte
Reset
WDT clock: fRL
Overflow time: 546.13 ms (MAX.)
WDTE = “ACH”
Clear WDT counter.
WDT clock is fixed to fRL
.
Select overflow time (settable only once).
WDT clock: fRL
Overflow time: 4.27 ms to 546.13 ms (MAX.)
WDT count continues.
HALT instruction
STOP instruction
Interrupt
Interrupt
HALT
WDT count continues.
STOP
WDT count continues.
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8.4.2 Watchdog timer operation when “low-speed Ring-OSC can be stopped by software” is selected by
option byte
The operation clock of the watchdog timer can be selected as either the low-speed Ring-OSC clock or system
clock.
After reset is released, operation is started at the maximum cycle of the low-speed Ring-OSC clock (bits 2, 1, and 0
(WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
•
•
•
Operation clock: Low-speed Ring-OSC clock
Cycle: 218/fRL (546.13 ms: At operation with fRL = 480 kHz (MAX.))
Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instructionNotes 1, 2, 3
.
•
Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).
Low-speed Ring-OSC clock (fRL)
Syatem clock (fX)
Watchdog timer operation stopped
Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
•
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1. As soon as WDTM is written, the counter of the watchdog timer is cleared.
2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values.
3. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×, respectively, an internal
reset signal is not generated even if the following processing is performed.
•
•
•
WDTM is written a second time.
A 1-bit memory manipulation instruction is executed to WDTE.
A value other than ACH is written to WDTE.
Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0 but holds its value.
For the watchdog timer operation during STOP mode and HALT mode in each status, see 8.4.3 Watchdog timer
operation in STOP mode and 8.4.4 Watchdog timer operation in HALT mode.
A status transition diagram is shown below.
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Figure 8-5. Status Transition Diagram When “Low-Speed Ring-OSC Can Be Stopped by Software”
Is Selected by Option Byte
Reset
WDT clock: fRL
Overflow time: 546.13 ms (MAX.)
WDCS4 = 1
WDT clock = f
X
Select overflow time
(settable only once).
WDT clock = fRL
Select overflow time
(settable only once).
WDT operation stops.
WDTE = “ACH”
Clear WDT counter.
WDTE = “ACH”
Clear WDT counter.
WDTE = “ACH”
Clear WDT counter.
LSRSTOP = 1
LSRSTOP = 0
WDT clock: f
Overflow time: 213/f
WDT count continues.
X
WDT clock: fRL
Overflow time: 4.27 ms to 546.13 ms (MAX.)
WDT count continues.
to 220/f
X
WDT clock: fRL
WDT count stops.
X
HALT instruction
HALT
instruction
Interrupt
STOP
STOP
instruction
STOP
instruction
HALT
instruction
instruction
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
HALT
WDT count stops.
STOP
WDT count stops.
HALT
WDT count stops.
STOP
WDT count stops.
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8.4.3
Watchdog timer operation in STOP mode (when “low-speed Ring-OSC can be stopped by software” is
selected by option byte)
The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or
low-speed Ring-OSC clock is being used.
(1) When the watchdog timer operation clock is the system clock (fX) when the STOP instruction is executed
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
operation stops for 34 µs (TYP.) (after waiting for the oscillation stabilization time set by the oscillation stabilization
time select register (OSTS) after operation stops in the case of crystal/ceramic oscillation) and then counting is
started again using the operation clock before the operation was stopped. At this time, the counter is not cleared
to 0 but holds its value.
Figure 8-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware)
<1> CPU clock: Crystal/ceramic oscillation clock
Operation
Normal
operation
stoppedNote Oscillation stabilization time
Normal operation
STOP
CPU operation
f
CPU
Oscillation stabilization time
(set by OSTS register)
Oscillation stopped
Watchdog timer
Operating
Operation stopped
Operating
<2> CPU clock: High-speed Ring-OSC clock or external clock input
Normal
operation
Operation
stoppedNote
Normal operation
STOP
CPU operation
f
CPU
Oscillation stopped
Operation stopped
Watchdog timer
Operating
Operating
Note The operation stop time is 17 µs (MIN.), 34 µs (TYP.), and 67 µs (MAX.).
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(2) When the watchdog timer operation clock is the low-speed Ring-OSC clock (fRL) when the STOP
instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, operation stops for 34 µs (TYP.) and then counting is started again using the operation clock before the
operation was stopped. At this time, the counter is not cleared to 0 but holds its value.
Figure 8-7. Operation in STOP Mode (WDT Operation Clock: Low-Speed Ring-OSC Clock)
<1> CPU clock: Crystal/ceramic oscillation clock
Operation
Normal
operation
stoppedNote
STOP
Oscillation stabilization time
Normal operation
CPU operation
fCPU
Oscillation stabilization time
(set by OSTS register)
Oscillation stopped
fRL
Watchdog timer
Operating
Operation stopped
Operating
<2> CPU clock: High-speed Ring-OSC clock or external clock input
Operation
Normal
operation
stoppedNote
CPU operation
STOP
Normal operation
f
CPU
Oscillation stopped
f
RL
Watchdog timer
Operating
Operation stopped
Operating
Note The operation stop time is 17 µs (MIN.), 34 µs (TYP.), and 67 µs (MAX.).
8.4.4
Watchdog timer operation in HALT mode (when “low-speed Ring-OSC can be stopped by software” is
selected by option byte)
The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of
the watchdog timer is the system clock (fX) or low-speed Ring-OSC clock (fRL). After HALT mode is released, counting
is started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to
0 but holds its value.
Figure 8-8. Operation in HALT Mode
Normal operation
HALT
Normal operation
CPU operation
f
CPU
fX or fRL
Watchdog timer
Operating Operation stopped
Operating
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CHAPTER 9 A/D CONVERTER
9.1 Functions of A/D Converter
The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to
ANI3) with a resolution of 10 bits.
The A/D converter has the following function.
•
10-bit resolution A/D conversion
10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to
ANI3. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
Figure 9-1 shows the timing of sampling and A/D conversion, and Table 9-1 shows the sampling time and A/D
conversion time.
Figure 9-1. Timing of A/D Converter Sampling and A/D Conversion
ADCS ← 1 or ADS rewrite
ADCS
Sampling
timing
INTAD
Note Sampling
Sampling
time
time
Conversion time
Conversion time
Note 2 or 3 clocks are required from the ADCS rising to sampling start.
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Table 9-1. Sampling Time and A/D Conversion Time
FR2
FR1
FR0
Reference
Voltage
Sampling
TimeNote 2
Conversion
TimeNote 3
fXP = 8 MHz
fXP = 10 MHz
Sampling
TimeNote 2
1.5 µs
3.0 µs
Conversion
TimeNote 3
Sampling
TimeNote 2
1.2 µs
Conversion
TimeNote 3
RangeNote 1
0
0
0
0
0
1
VDD ≥ 4.5 V
12/fXP
24/fXP
36/fXP
48/fXP
4.5 µs
6.0 µs
3.6 µs
VDD ≥ 2.85 V
Setting prohibited Setting prohibited
(2.4 µs)
(4.8 µs)
0
0
1
1
0
1
VDD ≥ 2.7 V
VDD ≥ 2.7 V
48/fXP
88/fXP
72/fXP
Setting prohibited Setting prohibited Setting prohibited Setting prohibited
(6.0 µs)
11.0 µs
(9.0 µs)
14.0 µs
(4.8 µs)
(7.2 µs)
112/fXP
Setting prohibited Setting prohibited
(8.8 µs)
2.4 µs
4.8 µs
(11.2 µs)
7.2 µs
1
1
1
0
0
1
0
1
0
VDD ≥ 4.5 V
VDD ≥ 2.85 V
VDD ≥ 2.7 V
24/fXP
48/fXP
96/fXP
72/fXP
96/fXP
144/fXP
3.0 µs
6.0 µs
12.0 µs
9.0 µs
12.0 µs
18.0 µs
9.6 µs
Setting prohibited Setting prohibited
(9.6 µs)
17.6 µs
(14.4 µs)
22.4 µs
1
1
1
VDD ≥ 2.7 V
176/fXP
224/fXP
22.0 µs
28.0 µs
Notes 1. Be sure to set the FR2, FR1, and FR0 in accordance with the reference voltage range and satisfy Notes 2
and 3 below.
Example When VDD ≥ 2.7 V
• Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1.
• The sampling time is 11.0 µs or more and the A/D conversion time is 14.0 µs or more and less than
100 µs.
2. Set the sampling time as follows.
• VDD ≥ 4.5 V:
• VDD ≥ 4.0 V:
• VDD ≥ 2.85 V:
• VDD ≥ 2.7 V:
1.0 µs or more
2.4 µs or more
3.0 µs or more
11.0 µs or more
3. Set the A/D conversion time as follows.
• VDD ≥ 4.5 V:
• VDD ≥ 4.0 V:
• VDD ≥ 2.85 V:
• VDD ≥ 2.7 V:
3.0 µs or more and less than 100 µs
4.8 µs or more and less than 100 µs
6.0 µs or more and less than 100 µs
14.0 µs or more and less than 100 µs
Caution The above sampling time and conversion time do not include the clock frequency error. Select
the conversion time taking the clock frequency error into consideration.
Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware
2. The conversion time refers to the total of the sampling time and the time from successively
comparing with the sampling value until the conversion result is output.
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Figure 9-2 shows the block diagram of A/D converter.
Figure 9-2. Block Diagram of A/D Converter
ANI0/P20/TI000
TOH1
Sample & hold circuit
Voltage comparator
ANI1/P21/TI010/
TO00/INTP0
V
V
DD
SS
D/A converter
ANI2/X2/P22
ANI3/X1/P23
VSS
Successive
approximation
register (SAR)
INTAD
Controller
A/D conversion result register
(ADCR, ADCRH)
2
3
ADS1 ADS0
ADCS
FR2
FR1
FR0
ADCE
Analog input
A/D converter mode
register (ADM)
channel specification
register (ADS)
Internal bus
Cautions 1. In the 78K0S/KU1+ and 78K0S/KY1+, VSS functions alternately as the ground potential of the
A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V).
2. In the 78K0S/KU1+ and 78K0S/KY1+, VDD functions alternately as the A/D converter reference
voltage input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to
5.5 V).
9.2 Configuration of A/D Converter
The A/D converter consists of the following hardware.
Table 9-2. Registers of A/D Converter Used on Software
Item
Registers
Configuration
10-bit A/D conversion result register (ADCR)
8-bit A/D conversion result register (ADCRH)
A/D converter mode register (ADM)
Analog input channel specification register (ADS)
Port mode register 2 (PM2)
Port mode control register 2 (PMC2)
(1) ANI0 to ANI3 pins
These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into
digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification
register (ADS) can be used as input port pins.
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(2) Sample & hold circuit
The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D
conversion is started, and holds the sampled analog input voltage value during A/D conversion.
(3) D/A converter
The D/A converter is connected between VDD and VSS, and generates a voltage to be compared with the analog
input signal.
(4) Voltage comparator
The voltage comparator compares the sampled analog input voltage and the output voltage of the D/A converter.
(5) Successive approximation register (SAR)
This register compares the sampled analog voltage and the voltage of the D/A converter, and converts the result,
starting from the most significant bit (MSB).
When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D
conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).
(6) 10-bit A/D conversion result register (ADCR)
The result of A/D conversion is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the result of A/D conversion in its lower 10 bits (the higher
6 bits are fixed to 0).
(7) 8-bit A/D conversion result register (ADCRH)
The result of A/D conversion is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register holds the result of A/D conversion in its higher 8 bits.
(8) Controller
When A/D conversion has been completed, INTAD is generated.
(9) VDD pin
This is the positive power supply pin.
In the 78K0S/KU1+ and 78K0S/KY1+, VDD functions alternately as the A/D converter reference voltage input.
When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
(10) VSS pin
This is the ground potential pin.
In the 78K0S/KU1+ and 78K0S/KY1+, VSS functions alternately as the ground potential of the A/D converter. Be
sure to connect VSS to a stabilized GND (= 0 V).
(11) A/D converter mode register (ADM)
This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the
conversion operation.
(12) Analog input channel specification register (ADS)
This register is used to specify the port that inputs the analog voltage to be converted into a digital signal.
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(13) Port mode control register 2 (PMC2)
This register is used when the P20/ANI0/TI000/TOH1, P21/ANI1/TI010/TO00/INTP0, P22/ANI2, and P23/ANI3
pins are used as the analog input pins of the A/D converter.
9.3 Registers Used by A/D Converter
The A/D converter uses the following six registers.
•
•
•
•
•
•
A/D converter mode register (ADM)
Analog input channel specification register (ADS)
10-bit A/D conversion result register (ADCR)
8-bit A/D conversion result register (ADCRH)
Port mode register 2 (PM2)
Port mode control register 2 (PMC2)
(1) A/D converter mode register (ADM)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
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Figure 9-3. Format of A/D Converter Mode Register (ADM)
Address: FF80H After reset: 00H R/W
Symbol
ADM
<7>
6
0
5
4
3
2
0
1
0
<0>
ADCS
FR2
FR1
FR0
ADCE
ADCS
0
1Note 1
A/D conversion operation control
Stops conversion operation
Starts conversion operation
FR2
FR1
FR0
Reference Sampling Conversion
fXP = 8 MHz
fXP = 10 MHz
Voltage
TimeNote 3
TimeNote 4
Sampling Conversion Sampling Conversion
RangeNote 2
TimeNote 3
TimeNote 4
TimeNote 3
TimeNote 4
0
0
0
0
0
1
VDD ≥
4.5 V
12/fXP
24/fXP
36/fXP
48/fXP
1.5 µs
4.5 µs
1.2 µs
3.6 µs
VDD ≥
3.0 µs
6.0 µs
Setting
Setting
2.85 V
prohibited
(2.4 µs)
prohibited
(4.8 µs)
0
0
1
1
0
1
VDD ≥
2.7 V
48/fXP
88/fXP
72/fXP
Setting
prohibited
(6.0 µs)
Setting
prohibited
(9.0 µs)
Setting
prohibited
(4.8 µs)
Setting
prohibited
(7.2 µs)
VDD ≥
112/fXP
11.0 µs
14.0 µs
Setting
Setting
2.7 V
prohibited
(8.8 µs)
prohibited
(11.2 µs)
1
1
1
0
0
1
0
1
0
VDD ≥
4.5 V
24/fXP
48/fXP
96/fXP
72/fXP
96/fXP
144/fXP
3.0 µs
6.0 µs
12.0 µs
9.0 µs
2.4 µs
7.2 µs
VDD ≥
2.85 V
12.0 µs
18.0 µs
4.8 µs
9.6 µs
VDD ≥
Setting
Setting
2.7 V
prohibited
(9.6 µs)
prohibited
(14.4 µs)
1
1
1
VDD ≥
176/fXP
224/fXP
22.0 µs
28.0 µs
17.2 µs
22.4 µs
2.7 V
ADCE
0Note 1
1
Comparator operation controlNote 5
Stops operation of comparator
Enables operation of comparator
Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware
2. The conversion time refers to the total of the sampling time and the time from successively
comparing with the sampling value until the conversion result is output.
Notes 1. Even when the ADCE = 0 (comparator operation stopped), the A/D conversion operation starts if
the ADCS is set to 1. However, the data of the first conversion is out of the guaranteed-value
range, so ignore it.
2. Be sure to set the FR2, FR1, and FR0 in accordance with the reference voltage range and satisfy
Notes 3 and 4 below.
Example When VDD ≥ 2.7 V
• Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1.
• The sampling time is 11.0 µs or more and the A/D conversion time is 14.0 µs or
more and less than 100 µs.
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Notes 3. Set the sampling time as follows.
• VDD ≥ 4.5 V:
• VDD ≥ 4.0 V:
• VDD ≥ 2.85 V:
• VDD ≥ 2.7 V:
1.0 µs or more
2.4 µs or more
3.0 µs or more
11.0 µs or more
4. Set the A/D conversion time as follows.
• VDD ≥ 4.5 V:
• VDD ≥ 4.0 V:
• VDD ≥ 2.85 V:
• VDD ≥ 2.7 V:
3.0 µs or more and less than 100 µs
4.8 µs or more and less than 100 µs
6.0 µs or more and less than 100 µs
14.0 µs or more and less than 100 µs
5. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 µs from
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 µs or more
has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over
the first conversion result. If the ADCS is set to 1 without waiting for 1 µs or longer, ignore the
data of the first conversion.
Table 9-3. Settings of ADCS and ADCE
ADCS
ADCE
A/D Conversion Operation
Stop status (DC power consumption path does not exist)
Conversion waiting mode (only comparator consumes power)
Conversion mode
0
0
1
0
1
×
Figure 9-4. Timing Chart When Comparator Is Used
Comparator operating
ADCE
Comparator
ADCS
Conversion
operation
Conversion
waiting
Conversion
operation
Conversion stopped
Note
Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 µs or longer to stabilize the
internal circuit.
Cautions 1. The above sampling time and conversion time do not include the clock frequency error.
Select the conversion time taking the clock frequency error into consideration.
2. If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0)
and then A/D conversion is started, execute two NOP instructions or an instruction
equivalent to two machine cycles, and set ADCS to 1.
3. A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
4. Be sure to clear bits 6, 2, and 1 to 0.
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(2) Analog input channel specification register (ADS)
This register specifies the input port of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
Figure 9-5. Format of Analog Input Channel Specification Register (ADS)
Address: FF81H After reset: 00H R/W
Symbol
ADS
7
0
6
0
5
0
4
0
3
0
2
0
1
0
ADS1
ADS0
ADS1 ADS0
Analog input channel specification
0
0
1
1
0
1
0
1
ANI0
ANI1
ANI2
ANI3
Caution Be sure to clear bits 2 to 7 of ADS to 0.
(3) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The higher six bits are fixed to 0. Each
time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is
stored in ADCR in order starting from bit 1 of FF19H. FF19H indicates the higher 2 bits of the conversion result,
and FF18H indicates the lower 8 bits of the conversion result.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset input makes ADCR undefined.
Figure 9-6. Format of 10-Bit A/D Conversion Result Register (ADCR)
Address: FF18H, FF19H After reset: Undefined
FF19H
R
FF18H
Symbol
ADCR
0
0
0
0
0
0
Caution When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read the
conversion result following conversion completion before writing to ADM and ADS.
Using timing other than the above may cause an incorrect conversion result to be read.
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(4) 8-bit A/D conversion result register (ADCRH)
This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit
resolution result.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset input makes ADCRH undefined.
Figure 9-7. Format of 8-Bit A/D Conversion Result Register (ADCRH)
Address: FF1AH After reset: Undefined
R
Symbol
ADCRH
7
6
5
4
3
2
1
0
(5) Port mode register 2 (PM2) and port mode control register 2 (PMC2)
When using the when the P20/ANI0/TI000/TOH1, P21/ANI1/TI010/TO00/INTP0, P22/ANI2, and P23/ANI3 pins
for analog input, set PM20 to PM23 and PMC20 to PMC23 to 1. At this time, the output latches of P20 to P23
may be 0 or 1.
PM2 and PMC2 are set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets PM2 to FFH and clears PMC2 to 00H.
Figure 9-8. Format of Port Mode Register 2 (PM2)
Address: FF22H After reset: FFH R/W
Symbol
PM2
7
1
6
1
5
1
4
1
3
2
1
0
PM23
PM22
PM21
PM20
PM2n
Pmn pin I/O mode selection (n = 0 to 3)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
Figure 9-9. Format of Port Mode Control Register 2 (PMC2)
Address: FF84H After reset: 00H R/W
Symbol
PMC2
7
0
6
0
5
0
4
0
3
2
1
0
PMC23
PMC22
PMC21
PMC20
PMC2n
Operation mode specification (n = 0 to 3)
0
1
Port/Alternate-function (except A/D converter) mode
A/D converter mode
Caution If PMC20 to PMC23 are set to 1, the P20/ANI0/TI000/TOH1, P21/ANI1/TIO10/TO00/INTP0,
P22/ANI2, and P23/ANI3 pins cannot be used for any purpose other than the A/D converter
function.
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9.4 A/D Converter Operations
9.4.1 Basic operations of A/D converter
<1> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<2> Set ADCE to 1 and wait for 1 µs or longer.
<3> Execute two NOP instructions or an instruction equivalent to two machine cycles.
<4> Set ADCS to 1 and start the conversion operation.
(<5> to <11> are operations performed by hardware.)
<5> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<6> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
input analog voltage is held until the A/D conversion operation has ended.
<7> Bit 9 of the successive approximation register (SAR) is set. The D/A converter voltage tap is set to (1/2) VDD
by the tap selector.
<8> The voltage difference between the D/A converter voltage tap and analog input is compared by the voltage
comparator. If the analog input is greater than (1/2) AVDD, the MSB of SAR remains set to 1. If the analog
input is smaller than (1/2) VDD, the MSB is reset to 0.
<9> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The D/A
converter voltage tap is selected according to the preset value of bit 9, as described below.
•
•
Bit 9 = 1: (3/4) VDD
Bit 9 = 0: (1/4) VDD
The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.
•
•
Analog input voltage ≥ Voltage tap: Bit 8 = 1
Analog input voltage < Voltage tap: Bit 8 = 0
<10> Comparison is continued in this way up to bit 0 of SAR.
<11> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
<12> Repeat steps <5> to <11>, until ADCS is cleared to 0.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the
status of ADCE = 0, start from <2>.
Remark The following two types of A/D conversion result registers can be used.
<1> ADCR (16 bits): Stores a 10-bit A/D conversion value.
<2> ADCRH (8 bits): Stores an 8-bit A/D conversion value.
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Figure 9-10. Basic Operation of A/D Converter
Conversion time
Sampling time
Sampling
A/D converter
operation
A/D conversion
Conversion
result
Undefined
SAR
ADCR,
ADCRH
Conversion
result
INTAD
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM)
is reset (0) by software.
If a write operation is performed to ADM or the analog input channel specification register (ADS) during an A/D
conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again
from the beginning.
Reset input makes the A/D conversion result register (ADCR, ADCRH) undefined.
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9.4.2 Input voltage and conversion results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical
A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following
expression.
VAIN
SAR = INT (
× 1024 + 0.5)
VDD
ADCR = SAR × 64
or
VDD
VDD
(ADCR − 0.5) ×
≤ VAIN < (ADCR + 0.5) ×
1024
1024
where, INT( ): Function which returns integer part of value in parentheses
VAIN:
VDD:
Analog input voltage
VDD pin voltage
ADCR: 10-bit A/D conversion result register (ADCR) value
SAR: Successive approximation register
Figure 9-11 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 9-11. Relationship Between Analog Input Voltage and A/D Conversion Result
SAR
ADCR
1023
FFC0H
1022
FF80H
FF40H
00C0H
0080H
0040H
0000H
1021
A/D conversion result
(ADCR)
3
2
1
0
1
1
3
2
5
3
2043 1022 2045 1023 2047
2048 1024 2048 1024 2048
1
2048 1024 2048 1024 2048 1024
Input voltage/VDD
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9.4.3 A/D converter operation mode
The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to
ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed.
(1) A/D conversion operation
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the
voltage, which is applied to the analog input pin specified by the analog input channel specification register
(ADS), is started.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has
started and when one A/D conversion has been completed, the next A/D conversion operation is immediately
started. The A/D conversion operations are repeated until new data is written to ADS.
If ADM or ADS is written during A/D conversion, the A/D conversion operation under execution is stopped and
restarted from the beginning.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the
conversion result is undefined.
Figure 9-12. A/D Conversion Operation
Rewriting ADM
ADCS = 1
Rewriting ADS
ANIn
ADCS = 0
A/D conversion
ANIn
ANIn
ANIm
ANIm
Conversion is stopped
Conversion result is not retained
Stopped
ADCR,
ADCRH
ANIn
ANIn
ANIm
INTAD
Remarks 1. n = 0 to 3
2. m = 0 to 3
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The setting method is described below.
<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel
specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
<3> Execute two NOP instructions or an instruction equivalent to two machine cycles.
<4> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion.
<5> An interrupt request signal (INTAD) is generated.
<6> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Change the channel>
<7> Change the channel using bits 1 and 0 (ADS1, ADS0) of ADS to start A/D conversion.
<8> An interrupt request signal (INTAD) is generated.
<9> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Complete A/D conversion>
<10> Clear ADCS to 0.
<11> Clear ADCE to 0.
Cautions 1. Make sure the period of <1> to <4> is 1 µs or more.
2. It is no problem if the order of <1> and <2> is reversed.
3. <1> can be omitted. However, ignore the data resulting from the first conversion after
<4> in this case.
4. The period from <5> to <8> differs from the conversion time set using bits 5 to 3 (FR2 to
FR0) of ADM. The period from <7> to <8> is the conversion time set using FR2 to FR0.
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9.5 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input
voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the
full scale is expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of
these express the overall error.
Note that the quantization error is not included in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an
analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot
be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral
linearity error, and differential linearity error in the characteristics table.
Figure 9-13. Overall Error
Figure 9-14. Quantization Error
……
1
1
……
1
1
Ideal line
Overall
error
Quantization error
1/2LSB
1/2LSB
……
0
0
……
0
0
0
V
DD
0
V
DD
Analog input
Analog input
(4) Zero-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output
changes from 0……001 to 0……010.
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(5) Full-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It
expresses the maximum value of the difference between the actual measurement value and the ideal straight line
when the zero-scale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value
and the ideal value.
Figure 9-15. Zero-Scale Error
Figure 9-16. Full-Scale Error
111
Full-scale error
Ideal line
111
110
011
010
101
000
001
000
Ideal line
Zero-scale error
3
0
1
2
VDD
0
V
DD−3
V
DD−2
V
DD−1
V
DD
Analog input (LSB)
Analog input (LSB)
Figure 9-17. Integral Linearity Error
Figure 9-18. Differential Linearity Error
……
1
1
……
1
1
Ideal 1LSB width
Ideal line
Differential
linearity error
Integral linearity
error
……
0 0
……
0
0
VDD
VDD
0
0
Analog input
Analog input
(8) Conversion time
This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time
Conversion time
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9.6 Cautions for A/D Converter
(1) Operating current in STOP mode
The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by
clearing bit 7 (ADCS) of the A/D converter mode register (ADM) to 0.
(2) Input range of ANI0 to ANI3
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of VDD or higher and VSS or lower (even in
the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel
becomes undefined. In addition, the converted values of the other channels may also be affected.
(3) Conflicting operations
<1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by
instruction upon the end of conversion
ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR,
ADCRH.
<2> Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input
channel specification register (ADS) write upon the end of conversion
ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt
signal (INTAD) generated.
(4) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the VDD pin and ANI0 to ANI3 pins.
<1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply.
<2> Because the effect increases in proportion to the output impedance of the analog input source, it is
recommended that a capacitor be connected externally, as shown in Figure 9-19, to reduce noise.
<3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to their alternate functions during
conversion.
<4> The conversion accuracy can be improved by setting HALT mode immediately after the conversion starts.
Figure 9-19. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than VDD or
equal to or lower than VSS may enter, clamp with a diode with a
small V value (0.3 V or lower).
F
Reference
voltage
input
V
DD
ANI0 to ANI3
C = 0.01 to 0.1 µF
V
SS
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(5) ANI0/P20 to ANI3/P23
<1> The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23).
When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 while
conversion is in progress; otherwise the conversion resolution may be degraded.
<2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected
value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to
the pins adjacent to the pin undergoing A/D conversion.
(6) Input impedance of ANI0 to ANI3 pins
In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth
of the conversion time.
Since only the leakage current flows other than during sampling and the current for charging the capacitor also
flows during sampling, the input impedance fluctuates and has no meaning.
If the shortest conversion time of the reference voltage is used, to perform sufficient sampling, it is recommended
to make the output impedance of the analog input source 1 kΩ or lower, or attach a capacitor of around 0.01 µF
to 0.1 µF to the ANI0 to ANI3 pins (see Figure 9-19).
(7) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the
pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,
when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-
change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Figure 9-20. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
ADS rewrite
(start of ANIm conversion)
ADIF is set but ANIm conversion
has not ended.
A/D conversion
ANIn
ANIn
ANIm
ANIn
ANIm
ADCR,
ADCRH
ANIn
ANIm
ANIm
ADIF
Remarks 1. n = 0 to 3
2. m = 0 to 3
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(8) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the
ADCS bit is set to 1 within 1 µs after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit =
0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
(9) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR and ADCRH may become undefined. Read the conversion
result following conversion completion before writing to ADM and ADS. Using a timing other than the above may
cause an incorrect conversion result to be read.
(10) Internal equivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 9-21. Internal Equivalent Circuit of ANIn Pin
R
OUT
R
IN
ANIn
C
OUT
C
IN
LSI internal
Table 9-4. Resistance and Capacitance Values (Reference Values) of Equivalent Circuit
VDD
ROUT
1 kΩ
1 kΩ
RIN
COUT
8 pF
8 pF
CIN
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
3 kΩ
60 kΩ
15 pF
15 pF
Remarks 1. The resistance and capacitance values shown in Table 9-4 are not guaranteed
values.
2. n = 0 to 3
3. ROUT: Allowable signal source impedance
RIN: Analog input equivalent resistance
COUT: Internal pin capacitance
CIN: Analog Input equivalent capacitance
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CHAPTER 10 INTERRUPT FUNCTIONS
10.1 Interrupt Function Types
All interrupts are controlled as maskable interrupts.
•
Maskable interrupts
These interrupts undergo mask control. If two or more interrupt requests are simultaneously generated, each
interrupt has a predetermined priority as shown in Table 10-1.
A standby release signal is generated.
There are five internal sources and two external sources of maskable interrupts.
10.2 Interrupt Sources and Configuration
There are a total of seven interrupt sources, and up to four reset sources (see Table 10-1).
Table 10-1. Interrupt Sources
Interrupt Type
PriorityNote 1
Interrupt Source
Trigger
Internal/
External
Vector Table
Address
Basic
Configuration
TypeNote 2
Name
INTLVI
Maskable
1
2
3
4
Low-voltage detectionNote 3
Pin input edge detection
Internal
0006H
0008H
000AH
000CH
(A)
(B)
INTP0
External
INTP1
INTTMH1
Match between TMH1 and CMP01
(when compare register is specified)
Internal
(A)
5
INTTM000
INTTM010
Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection (when
capture register is specified)
000EH
6
Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection (when
capture register is specified)
0010H
7
INTAD
RESET
POC
End of A/D conversion
Reset input
0012H
0000H
Reset
−
−
−
Power-on-clear
LVI
Low-voltage detectionNote 4
WDT
WDT overflow
Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time. 1 is
the highest and 7 is the lowest.
2. Basic configuration types (A) and (B) correspond to (A) and (B) in Figure 10-1.
3. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 0 is selected.
4. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 1 is selected.
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Figure 10-1. Basic Configuration of Interrupt Function
(A) Internal maskable interrupt
Internal bus
IE
MK
Vector table
address generator
Interrupt request
IF
Standby release signal
(B) External maskable interrupt
Internal bus
External interrupt mode
register (INTM0)
MK
IE
Vector table
address generator
Edge
Interrupt
IF
detector
request
Standby
release signal
IF: Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
10.3 Interrupt Function Control Registers
The interrupt functions are controlled by the following four types of registers.
• Interrupt request flag register 0 (IF0)
• Interrupt mask flag register 0 (MK0)
• External interrupt mode register 0 (INTM0)
• Program status word (PSW)
Table 10-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags.
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Table 10-2. Interrupt Request Signals and Corresponding Flags
Interrupt Request Signal
Interrupt Request Flag
Interrupt Mask Flag
INTLVI
LVIIF
LVIMK
INTP0
PIF0
PMK0
INTP1
PIF1
PMK1
INTTMH1
INTTM000
INTTM010
INTAD
TMIFH1
TMIF000
TMIF010
ADIF
TMMKH1
TMMK000
TMMK010
ADMK
(1) Interrupt request flag register 0 (IF0)
An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the
instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is
acknowledged or when a reset signal is input.
IF0 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset input clears IF0 to 00H.
Figure 10-2. Format of Interrupt Request Flag Register 0 (IF0)
Address: FFE0H After reset: 00H R/W
Symbol
IF0
<7>
<6>
<5>
<4>
<3>
<2>
<1>
0
0
ADIF
TMIF010 TMIF000 TMIFH1
PIF1
PIF0
LVIIF
××IF×
Interrupt request flag
No interrupt request signal has been issued.
An interrupt request signal has been issued; an interrupt request status.
0
1
Caution Because P21 and P32 have an alternate function as external interrupt inputs, when the
output level is changed by specifying the output mode of the port function, an interrupt
request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the
output mode.
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(2) Interrupt mask flag register 0 (MK0)
The interrupt mask flag is used to enable and disable the corresponding maskable interrupts.
MK0 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset input sets MK0 to FFH.
Figure 10-3. Format of Interrupt Mask Flag Register 0 (MK0)
Address: FFE4H After reset: FFH R/W
Symbol
MK0
<7>
<6>
<5>
<4>
<3>
<2>
<1>
0
1
ADMK
TMMK010 TMMK000 TMMKH1
PMK1
PMK0
LVIMK
××MK×
Interrupt servicing control
0
1
Enables interrupt servicing.
Disables interrupt servicing.
Caution Because P21 and P32 have an alternate function as external interrupt inputs, when the
output level is changed by specifying the output mode of the port function, an interrupt
request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the
output mode.
(3) External interrupt mode register 0 (INTM0)
This register is used to set the valid edge of INTP0 and INTP1.
INTM0 is set with an 8-bit memory manipulation instruction.
Reset input clears INTM0 to 00H.
Figure 10-4. Format of External Interrupt Mode Register 0 (INTM0)
Address: FFECH After reset: 00H R/W
Symbol
INTM0
7
0
6
0
5
4
3
2
1
0
0
0
ES11
ES10
ES01
ES00
ES11
ES10
INTP1 valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES01
ES00
INTP0 valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Cautions 1. Be sure to clear bits 0, 1, 6, and 7 to 0.
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Cautions 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will
enable interrupts.
(4) Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the interrupt
requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.
PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and
dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically
saved to a stack, and the IE flag is reset to 0.
Reset input sets PSW to 02H.
Figure 10-5. Program Status Word (PSW) Configuration
Symbol
PSW
7
6
Z
5
0
4
3
0
2
0
1
1
0
After reset
02H
IE
AC
CY
Used in the execution of ordinary instructions
IE
0
Whether to enable/disable interrupt acknowledgment
Disabled
Enabled
1
10.4 Interrupt Servicing Operation
10.4.1 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt
enabled status (when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in
Table 10-3.
See Figures 10-7 and 10-8 for the interrupt request acknowledgment timing.
Table 10-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time
9 clocks
Maximum TimeNote
19 clocks
Note The wait time is maximum when an interrupt
request is generated immediately before BT and
BF instructions.
1
fCPU
Remark 1 clock:
(fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the interrupt request assigned the highest priority.
A pending interrupt is acknowledged when a status in which it can be acknowledged is set.
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Figure 10-6 shows the algorithm of interrupt request acknowledgment.
When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in
that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to
the PC, and execution branches.
To return from interrupt servicing, use the RETI instruction.
Figure 10-6. Interrupt Request Acknowledgment Processing Algorithm
Start
No
××IF = 1?
Yes (Interrupt request generated)
No
××MK = 0?
Yes
Interrupt request pending
Interrupt request pending
No
IE = 1?
Yes
Vectored interrupt
servicing
××IF:
Interrupt request flag
××MK: Interrupt mask flag
IE:
Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)
Figure 10-7. Interrupt Request Acknowledgment Timing (Example of MOV A, r)
8 clocks
Clock
Saving PSW and PC, jump
Interrupt servicing program
CPU
MOV A, r
to interrupt servicing
Interrupt
If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1,
the interrupt is acknowledged after the instruction under execution is complete. Figure 10-7 shows an example of the
interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is
executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment
processing is performed after the MOV A, r instruction is executed.
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Figure 10-8. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last
Clock During Instruction Execution)
8 clocks
Clock
Interrupt
Saving PSW and PC, jump
servicing
CPU
NOP
MOV A, r
to interrupt servicing
program
Interrupt
If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing
starts after the next instruction is executed.
Figure 10-8 shows an example of the interrupt request acknowledgment timing for an interrupt request flag that is
set at the second clock of NOP (2-clock instruction). In this case, the MOV A, r instruction after the NOP instruction is
executed, and then the interrupt acknowledgment processing is performed.
Caution Interrupt requests will be held pending while the interrupt request flag register 0 (IF0) or
interrupt mask flag register 0 (MK0) are being accessed.
10.4.2 Multiple interrupt servicing
Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced can be
performed using a priority order system. When two or more interrupts are generated at once, interrupt servicing is
performed according to the priority assigned to each interrupt request in advance (see Table 10-1).
Figure 10-9. Example of Multiple Interrupts
Example 1. Multiple interrupts are acknowledged
INTxx servicing
INTyy servicing
Main processing
IE = 0
IE = 0
EI
EI
INTxx
INTyy
RETI
RETI
During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated.
The EI instruction is issued before each interrupt request acknowledgment, and the interrupt request acknowledgment
enable state is set.
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Example 2. Multiple interrupts are not generated because interrupts are not enabled
INTxx servicing
INTyy servicing
Main processing
EI
IE = 0
INTyy is held pending
INTyy
RETI
INTxx
IE = 0
RETI
Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request
INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is held pending and
acknowledged after the INTxx servicing is performed.
IE = 0: Interrupt request acknowledgment disabled
10.4.3 Interrupt request pending
Some instructions may keep pending the acknowledgment of an instruction request until the completion of the
execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated
during the execution. The following shows such instructions (interrupt request pending instruction).
• Manipulation instruction for interrupt request flag register 0 (IF0)
• Manipulation instruction for interrupt mask flag register 0 (MK0)
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11.1 Standby Function and Configuration
11.1.1 Standby function
Table 11-1. Relationship Between Operation Clocks in Each Operation Status
Status
Low-Speed Ring-OSC Oscillator
System Clock
Clock Supplied to
Peripheral
Note 1
Note 2
Hardware
Operation Mode
LSRSTOP = 0
OscillatingNote 3
LSRSTOP = 1
Reset
STOP
HALT
Stopped
Oscillating
Stopped
Stopped
Stopped
Oscillating
Oscillating
Notes 1. When “Cannot be stopped” is selected for low-speed Ring-OSC by the option byte.
2. When it is selected that the low-speed Ring-OSC oscillator “can be stopped by software”, oscillation of
the low-speed Ring-OSC oscillator can be stopped by LSRSTOP.
3. If the operating clock of the watchdog timer is the low-speed Ring-OSC clock, the watchdog timer is
stopped.
Caution The LSRSTOP setting is valid only when “Can be stopped by software” is set for the low-speed
Ring-OSC oscillator by the option byte.
Remark LSRSTOP: Bit 0 of the low-speed Ring-OSC mode register (LSRCM)
The standby function is designed to reduce the operating current of the system. The following two modes are
available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped.
Oscillation of the system clock oscillator continues. If the low-speed Ring-OSC oscillator is operating before
the HALT mode is set, oscillation of the clock of the low-speed Ring-OSC oscillator continues (refer to Table
11-1. Oscillation of the low-speed Ring-OSC clock (whether it cannot be stopped or can be stopped by
software) is set by the option byte). In this mode, the operating current is not decreased as much as in the
STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request
generation and carrying out intermittent operations.
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(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops,
stopping the whole system, thereby considerably reducing the CPU operating current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, select the HALT mode if processing must be immediately started by an interrupt request when the
operation stop timeNote is generated after the STOP mode is released (because an additional wait time for
stabilizing oscillation elapses when crystal/ceramic oscillation is used).
Note
The operation stop time is 17 µs (MIN.), 34 µs (TYP.), and 67 µs (MAX.).
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
executing STOP instruction (except the peripheral hardware that operates on the low-speed
Ring-OSC clock).
2. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute
the HALT or STOP instruction.
3. If the low-speed Ring-OSC oscillator is operating before the STOP mode is set, oscillation of
the low-speed Ring-OSC clock cannot be stopped in the STOP mode (refer to Table 11-1).
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11.1.2 Registers used during standby
The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time
select register (OSTS).
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS.
(1) Oscillation stabilization time select register (OSTS)
This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the
STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is
selected as the system clock and after the STOP mode is released. If the high-speed Ring-OSC oscillator or
external clock input is selected as the system clock source, no wait time elapses.
The system clock oscillator and the oscillation stabilization time that elapses after power application or release
of reset are selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE.
OSTS is set by using the 8-bit memory manipulation instruction.
Figure 11-1. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFF4H, After reset: Undefined, R/W
Symbol
OSTS
7
0
6
0
5
0
4
0
3
0
2
0
1
0
OSTS1
OSTS0
OSTS1
OSTS0
Selection of oscillation stabilization time
0
0
1
1
0
1
0
1
210/fX (102.4 µs)
212/fX (409.6 µs)
215/fX (3.27 ms)
217/fX (13.1 ms)
Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time set
by OSTS
2. The wait time after the STOP mode is released does not include the time from the
release of the STOP mode to the start of clock oscillation (“a” in the figure below),
regardless of whether STOP mode was released by reset input or interrupt generation.
STOP mode is released
Voltage
waveform
of X1 pin
a
3. The oscillation stabilization time that elapses on power application or after release of
reset is selected by the option byte. For details, refer to CHAPTER 15 OPTION BYTE.
Remarks 1. ( ): fX = 10 MHz
2. Determine the oscillation stabilization time of the resonator by checking the characteristics of
the resonator to be used.
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11.2 Standby Function Operation
11.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operating statuses in the HALT mode are shown below.
Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby
mode is immediately cleared if set.
Table 11-2. Operating Statuses in HALT Mode
Setting of HALT Mode
Low-speed Ring-OSC
cannot be stoppedNote
Low-speed Ring-OSC can be stoppedNote
.
.
When Low-speed Ring-
OSC Oscillation
Continues
When Low-speed Ring-
OSC Oscillation Stops
Item
System clock
CPU
Clock supply to CPU is stopped.
Operation stops.
Port (latch)
Holds status before HALT mode was set.
Operable
16-bit timer/event counter 00
8-bit timer
H1
Sets count clock to fXP to fXP/212
Operable
Sets count clock to fRL/27
Operable
Operable
Operation stops.
Watchdog
timer
“System clock” selected as
operating clock
Setting disabled.
Operation stops.
“Low-speed Ring-OSC clock”
selected as operating clock
Operable
Operation stops.
(Operation continues)
Operable
A/D converter
Power-on-clear circuit
Low-voltage detector
External interrupt
Always operates.
Operable
Operable
Note “Low-speed Ring-OSC cannot be stopped” or “low-speed Ring-OSC can be stopped by software” can be
selected by the option byte (for the option byte, see CHAPTER 15 OPTION BYTE).
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(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt
acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is
disabled, the next address instruction is executed.
Figure 11-2. HALT Mode Release by Interrupt Request Generation
Interrupt
request
HALT
instruction
Wait
Wait
Standby
release signal
Operating mode
HALT mode
Operating mode
Status of CPU
Oscillation
System clock
oscillation
Remarks 1. The broken lines indicate the case when the interrupt request which has released the
standby mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is carried out: 11 to 13 clocks
• When vectored interrupt servicing is not carried out: 3 to 5 clocks
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(b) Release by reset input
When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 11-3. HALT Mode Release by Reset Input
(1) When CPU clock is high-speed Ring-OSC clock or external input clock
HALT
instruction
Reset signal
Operation
stopsNote
Reset
period
Operation
mode
CPU status
HALT mode
Oscillates
Operation mode
Oscillates
Oscillation stops
System clock
oscillation
Note Operation is stopped (277 µs (MIN.), 544 µs (TYP.), and 1.075 ms (MAX.)) because the option
byte is referenced.
(2) When CPU clock is crystal/ceramic oscillation clock
HALT
instruction
Reset signal
Oscillation
stabilization waits
Operation
stopsNote
Reset
period
Operation
mode
Operation
mode
CPU status
HALT mode
Oscillates
Oscillation stops
Oscillates
System clock
oscillation
Oscillation stabilization time
(210/f to 217/f
X
X)
Note Operation is stopped (276 µs (MIN.), 544 µs (TYP.), and 1.074 ms (MAX.)) because the option
byte is referenced.
Remark fX: System clock oscillation frequency
Table 11-3. Operation in Response to Interrupt Request in HALT Mode
Release Source
MK××
IE
0
Operation
Next address instruction execution
Interrupt servicing execution
HALT mode held
Maskable interrupt request
0
0
1
−
1
×
Reset input
×
Reset processing
×: don’t care
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11.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction.
Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby
mode is immediately cleared if set. Thus, in the STOP mode, the normal operation mode is
restored after the STOP instruction is executed and then the operation is stopped for the
duration of 34 µs (TYP.) (after an additional wait time for stabilizing oscillation set by the
oscillation stabilization time select register (OSTS) has elapsed when crystal/ceramic
oscillation is used).
The operating statuses in the STOP mode are shown below.
Table 11-4. Operating Statuses in STOP Mode
Setting of STOP Mode
Low-speed Ring-OSC
Low-speed Ring-OSC can be stoppedNote
.
cannot be stoppedNote
.
When Low-speed Ring-
OSC Oscillation
Continues
When Low-speed Ring-
OSC Oscillation Stops
Item
System clock
CPU
Oscillation stops.
Operation stops.
Port (latch)
Holds status before STOP mode was set.
Operation stops.
16-bit timer/event counter 00
8-bit timer
H1
Sets count clock to fXP to fXP/212
Operation stops.
Sets count clock to fRL/27
Operable
Operable
Operation stops.
Watchdog
timer
“System clock” selected as
operating clock
Setting disabled.
Operation stops.
“Low-speed Ring-OSC clock”
selected as operating clock
Operable
Operation stops.
(Operation continues)
Operation stops.
Always operates.
Operable
A/D converter
Power-on-clear circuit
Low-voltage detector
External interrupt
Operable
Note “Low-speed Ring-OSC cannot be stopped” or “low-speed Ring-OSC can be stopped by software” can be
selected by the option byte (for the option byte, see CHAPTER 15 OPTION BYTE).
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(2) STOP mode release
Figure 11-4. Operation Timing When STOP Mode Is Released
<1> If high-speed Ring-OSC clock or external input clock is selected as system clock to be supplied
STOP mode
is released.
STOP mode
System clock
oscillation
CPU clock
Operation
High-speedRing-OSC clock or external clock input
stopsNote
.
<2> If crystal/ceramic oscillation clock is selected as system clock to be supplied
STOP mode
is released.
STOP mode
System clock
oscillation
CPU clock
HALT status
(oscillation stabilization time set by OSTS)
Operation
stopsNote
Crystal/ceramic oscillation clock
.
Note The operation stop time is 17 µs (MIN.), 34 µs (TYP.), and 67 µs (MAX.).
The STOP mode can be released by the following two sources.
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(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is
carried out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Figure 11-5. STOP Mode Release by Interrupt Request Generation
(1) If CPU clock is high-speed Ring-OSC clock or external input clock
Interrupt
request
STOP
instruction
Standby release
signal
Operation
mode
Operation
stopsNote
STOP mode
Operation mode
Oscillation
.
CPU status
Oscillation stops.
Oscillation
System clock
oscillation
(2) If CPU clock is crystal/ceramic oscillation clock
Interrupt
request
STOP
instruction
Standby release
signal
Operation
Operation
mode
Waiting for stabilization
.
of oscillation
Operation
mode
stopsNote
CPU status
STOP mode
(HALT mode status)
Oscillation
Oscillation stops.
Oscillation
System clock
Oscillation stabilization time
(set by OSTS)
Note The operation stop time is 17 µs (MIN.), 34 µs (TYP.), and 67 µs (MAX.).
Remark The broken lines indicate the case when the interrupt request that has released the standby mode
is acknowledged.
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(b) Release by reset input
When the reset signal is input, STOP mode is released and a reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 11-6. STOP Mode Release by Reset Input
(1) If CPU clock is high-speed Ring-OSC clock or external input clock
STOP
instruction
Reset signal
Operation
stopsNote
Reset
period
Operation
mode
CPU status
STOP mode
.
Operation mode
Oscillation
System clock
oscillation
Oscillation
Oscillation stops.
Note Operation is stopped (277 µs (MIN.), 544 µs (TYP.), and 1.075 ms (MAX.)) because the option
byte is referenced.
(2) If CPU clock is crystal/ceramic oscillation clock
STOP
instruction
Reset signal
Reset
period
Oscillation
Operation
Operation
mode
Operation
mode
stopsNote
.
stabilization waits
CPU status
STOP mode
Oscillation
Oscillation stops.
Oscillation
System clock
oscillation
Oscillation stabilization time
(210/f to 217/f
X
X)
Note Operation is stopped (276 µs (MIN.), 544 µs (TYP.), and 1.074 ms (MAX.)) because the option
byte is referenced.
Remark fX: System clock oscillation frequency
Table 11-5. Operation in Response to Interrupt Request in STOP Mode
Release Source
MK××
IE
0
Operation
Next address instruction execution
Interrupt servicing execution
STOP mode held
Maskable interrupt request
0
0
1
−
1
×
Reset input
×
Reset processing
×: don’t care
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The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
at 0000H and 0001H when the reset signal is input.
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
circuit voltage detection, and each item of hardware is set to the status shown in Table 12-1. Each pin is high
impedance during reset input or during the oscillation stabilization time just after reset release.
When a high level is input to the RESET pin, the reset is released and program execution starts using the CPU
clock after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time
elapses if crystal/ceramic oscillation is selected). A reset generated by the watchdog timer source is automatically
released after the reset, and program execution starts using the CPU clock after referencing the option byte (after the
option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected).
(see Figures 12-2 to 12-4). Reset by POC and LVI circuit power supply detection is automatically released when VDD
> VPOC or VDD > VLVI after the reset, and program execution starts using the CPU clock after referencing the option
byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation
is selected) (see CHAPTER 13 POWER-ON-CLEAR CIRCUIT and CHAPTER 14 LOW-VOLTAGE DETECTOR).
Cautions 1. For an external reset, input a low level for 2 µs or more to the RESET pin.
2. During reset input, the system clock and low-speed Ring-OSC clock stop oscillating.
3. When the RESET pin is used as an input-only port pin (P34), the 78K0S/KU1+ and
78K0S/KY1+ are reset if a low level is input to the RESET pin after reset is released by the
POC circuit and before the option byte is referenced again. The reset status is retained until
a high level is input to the RESET pin.
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CHAPTER 12 RESET FUNCTION
Figure 12-1. Block Diagram of Reset Function
Internal bus
Reset control flag register (RESF)
WDTRF
Clear
LVIRF
Set
Set Clear
Reset signal of
watchdog timer
Reset signal to
LVIM/LVIS register
RESET
Reset signal of
power-on-clear circuit
Reset signal of
Reset signal
low-voltage detector
Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit.
Remarks 1. LVIM: Low-voltage detect register
2. LVIS: Low-voltage detection level select register
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Figure 12-2. Timing of Reset by RESET Input
<1> With high-speed Ring-OSC clock or external clock input
High-speed Ring-OSC clock or
external clock input
Normal operation
in progress
Reset period
(oscillation stops)
CPU clock
RESET
Normal operation (reset processing, CPU clock)
Operation stops because option byte is referencedNote
.
Internal reset signal
Port pin
Delay
Delay
Hi-Z
Note
The operation stop time is 277 µs (MIN.), 544 µs (TYP.), and 1.075 ms (MAX.).
<2> With crystal/ceramic oscillation clock
Crystal/ceramic
oscillation clock
Oscillation stabilization
Normal operation
(reset processing, CPU clock)
Normal operation
in progress
Reset period
(oscillation stops)
CPU clock
time (210/f
X
to 217/f
)
X
RESET
Operation stops because option byte is referencedNote
.
Internal reset signal
Delay
Delay
Hi-Z
Port pin
Note
The operation stop time is 276 µs (MIN.), 544 µs (TYP.), and 1.074 ms (MAX.).
Remark fX: System clock oscillation frequency
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Figure 12-3. Timing of Reset by Overflow of Watchdog Timer
<1> With high-speed Ring-OSC clock or external clock input
High-speed Ring-OSC clock or
external clock input
Normal operation
in progress
Reset period
(oscillation stops)
CPU clock
Normal operation (reset processing, CPU clock)
Watchdog timer
overflow
Operation stops because option byte is referencedNote
.
Internal reset signal
Port pin
Hi-Z
Note
The operation stop time is 277 µs (MIN.), 544 µs (TYP.), and 1.075 ms (MAX.).
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
<2> With crystal/ceramic oscillation clock
Crystal/ceramic
oscillation clock
Normal operation
(reset processing, CPU clock)
Oscillation stabilization
Normal operation
in progress
Reset period
(oscillation stops)
CPU clock
time (210/f
X
to 217/f
)
X
Watchdog timer
overflow
Operation stops because option byte is referencedNote
.
Internal reset signal
Port pin
Hi-Z
Note
The operation stop time is 276 µs (MIN.), 544 µs (TYP.), and 1.074 ms (MAX.).
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remark fX: System clock oscillation frequency
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CHAPTER 12 RESET FUNCTION
Figure 12-4. Reset Timing by RESET Input in STOP Mode
<1> With high-speed Ring-OSC clock or external clock input
STOP instruction is executed.
High-speed Ring-OSC clock or
external clock input
Normal operation
in progress
Stop status
(oscillation stops)
Reset period
(oscillation stops)
CPU clock
RESET
Normal operation (reset processing, CPU clock)
Operation stops because option byte is referencedNote
.
Internal reset signal
Port pin
Delay
Delay
Hi-Z
Note
The operation stop time is 277 µs (MIN.), 544 µs (TYP.), and 1.075 ms (MAX.).
<2> With crystal/ceramic oscillation clock
STOP instruction is executed.
Crystal/ceramic
oscillation clock
Oscillation stabilization
Normal operation
(reset processing, CPU clock)
Normal operation
in progress
Stop status
(oscillation stops)
Reset period
(oscillation stops)
CPU clock
time (210/f
X
to 217/f
)
X
RESET
Operation stops because option byte is referencedNote
.
Internal reset signal
Delay
Delay
Hi-Z
Port pin
Note
The operation stop time is 276 µs (MIN.), 544 µs (TYP.), and 1.074 ms (MAX.).
Remarks 1. For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 13
POWER-ON-CLEAR CIRCUIT and CHAPTER 14 LOW-VOLTAGE DETECTOR.
2. fX: System clock oscillation frequency
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Table 12-1. Hardware Statuses After Reset Acknowledgment (1/2)
Hardware
Status After Reset
Program counter (PC) Note 1
Contents of reset vector
table (0000H and
0001H) are set.
Stack pointer (SP)
Program status word (PSW)
RAM
Undefined
02H
Undefined Note 2
Undefined Note 2
00H
Data memory
General-purpose registers
Ports (P2 to P4) (output latches)
Port mode registers (PM2 to PM4 Note 3
)
FFH
Port mode control register (PMC2)
00H
Pull-up resistor option registers (PU2 to PU4)
Processor clock control register (PCC)
00H
02H
Preprocessor clock control register (PPCC)
Low-speed Ring-OSC mode register (LSRCM)
Oscillation stabilization time select register (OSTS)
02H
00H
Undefined
0000H
0000H
00H
16-bit timer 00
Timer counter 00 (TM00)
Capture/compare registers 000, 010 (CR000, CR010)
Mode control register 00 (TMC00)
Prescaler mode register 00 (PRM00)
00H
Capture/compare control register 00 (CRC00)
00H
Timer output control register 00 (TOC00)
Compare registers (CMP01, CMP11)
Mode register 1 (TMHMD1)
00H
8-bit timer H1
Watchdog timer
A/D converter
00H
00H
Mode register (WDTM)
67H
Enable register (WDTE)
9AH
Conversion result registers (ADCR, ADCRH)
Mode register (ADM)
Undefined
00H
Analog input channel specification register (ADS)
00H
Notes 1. Only the contents of PC are undefined while reset is being input and while the oscillation stabilization time
elapses. The statuses of the other hardware units remain unchanged.
2. The status after reset is held in the standby mode.
3. When using the 78K0S/KU1+, set port mode register 4 (PM4) to 00H when initially setting the program.
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Table 12-1. Hardware Statuses After Reset Acknowledgment (2/2)
Hardware
Status After Reset
00HNote
00HNote
Reset function
Reset control flag register (RESF)
Low-voltage detector
Low-voltage detection register (LVIM)
Low-voltage detection level select register (LVIS)
Request flag registers (IF0)
00HNote
Interrupt
00H
Mask flag registers (MK0)
FFH
External interrupt mode registers (INTM0)
Flash protect command register (PFCMD)
Flash status register (PFS)
00H
Flash memory
Undefined
00H
Flash programming mode control register (FLPMC)
Flash programming command register (FLCMD)
Flash address pointer L (FLAPL)
Undefined
00H
Undefined
Flash address pointer H (FLAPH)
Flash address pointer H compare register (FLAPHC)
Flash address pointer L compare register (FLAPLC)
Flash write buffer register (FLW)
00H
00H
00H
Note These values change as follows depending on the reset source.
Reset Source
RESET Input
Reset by POC
Cleared (00H)
Reset by WDT
Cleared (00H)
Reset by LVI
Register
RESF
LVIM
See Table 12-2.
Cleared (00H)
Held
LVIS
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CHAPTER 12 RESET FUNCTION
12.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0S/KU1+ and 78K0S/KY1+. The reset control flag register
(RESF) is used to store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Figure 12-5. Format of Reset Control Flag Register (RESF)
Address: FF54H After reset: 00HNote
R
Symbol
RESF
7
0
6
0
5
0
4
3
0
2
0
1
0
0
WDTRF
LVIRF
WDTRF
Internal reset request by watchdog timer (WDT)
0
1
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
LVIRF
Internal reset request by low-voltage detector (LVI)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
0
1
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 12-2.
Table 12-2. RESF Status When Reset Request Is Generated
Reset Source
RESET Input
Reset by POC
Reset by WDT
Reset by LVI
Flag
WDTRF
LVIRF
Cleared (0)
Cleared (0)
Set (1)
Held
Held
Set (1)
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CHAPTER 13 POWER-ON-CLEAR CIRCUIT
13.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the following functions.
•
•
Generates internal reset signal at power on.
Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V 0.1 V), and generates internal reset signal
when VDD < VPOC.
•
Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V 0.1 V), and releases internal reset signal
when VDD ≥ VPOC.
Cautions 1. If an internal reset signal is generated in the POC circuit, the reset control flag register
(RESF) is cleared to 00H.
2. Because the detection voltage (VPOC) of the POC circuit is in a range of 2.1 V 0.1 V, use a
voltage in the range of 2.2 to 5.5 V.
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT) or low-voltage-detection (LVI) circuit. RESF is not
cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI.
For details of RESF, see CHAPTER 12 RESET FUNCTION.
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13.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 13-1.
Figure 13-1. Block Diagram of Power-on-Clear Circuit
VDD
VDD
+
Internal reset signal
−
Reference
voltage
source
13.3 Operation of Power-on-Clear Circuit
In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC = 2.1 V 0.1 V) are compared,
and an internal reset signal is generated when VDD < VPOC, and an internal reset is released when VDD ≥ VPOC.
Figure 13-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit
Supply voltage (VDD
)
POC detection voltage
(VPOC = 2.1 V 0.1V)
Time
Internal reset signal
Remark
The internal reset signal is active-low.
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13.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection
voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 13-3. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Reset
Check reset
source Note 2
; The reset source (power-on clear, WDT, or LVI)
can be identified by the RESF register.
Power-on clear
; 8-bit timer H1 can operate on the low-speed Ring-OSC clock.
Timer starts
(set to 50 ms)
Source: fRL (480 kHz (MAX.))/27 × compare value 200 = 53 ms
(fRL: Low-speed Ring-OSC clock oscillation frequency)
Note 1
No
50 ms has passed?
(TMIFH1 = 1?)
; TMIFH1 = 1: Interrupt request is generated.
Yes
Initialization
processing
; Initialization of ports, etc.
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
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Figure 13-3. Example of Software Processing After Release of Reset (2/2)
• Checking reset cause
Check reset source
Yes
WDTRF of RESF
register = 1?
No
Reset processing by
watchdog timer
Yes
LVIRF of RESF
register = 1?
No
Reset processing by low-voltage
detector
Power-on clear/external
reset generated
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CHAPTER 14 LOW-VOLTAGE DETECTOR
14.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) has following functions.
•
Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or
internal reset signal when VDD < VLVI.
•
•
•
Detection levels (ten levels) of supply voltage can be changed by software.
Interrupt or reset function can be selected by software.
Operable in STOP mode.
When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if
reset occurs. For details of RESF, refer to CHAPTER 12 RESET FUNCTION.
14.2 Configuration of Low-Voltage Detector
The block diagram of the low-voltage detector is shown in Figure 14-1.
Figure 14-1. Block Diagram of Low-Voltage Detector
VDD
VDD
N-ch
Internal reset signal
+
−
INTLVI
Reference
voltage source
4
LVION LVIMD LVIF
LVIS3 LVIS2 LVIS1 LVIS0
Low-voltage detection
Low-voltage detect
register (LVIM)
level select register (LVIS)
Internal bus
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14.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
•
•
Low-voltage detect register (LVIM)
Low-voltage detection level select register (LVIS)
(1) Low-voltage detect register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00HNote 1
.
Figure 14-2. Format of Low-Voltage Detect Register (LVIM)
Address: FF50H After reset: 00HNote 1 R/WNote 2
<7>
6
0
5
0
4
0
3
0
2
0
<1>
<0>
Symbol
LVIM
LVION
LVIMD
LVIF
LVIONNote 3
Enabling low-voltage detection operation
0
1
Disable operation
Enable operation
LVIMD
Low-voltage detection operation mode selection
Generate interrupt signal when supply voltage (VDD) < detection voltage (VLVI)
0
1
Generate internal reset signal when supply voltage (VDD) < detection voltage (VLVI)
LVIFNote 4
Low-voltage detection flag
Supply voltage (VDD) ≥ detection voltage (VLVI), or when operation is disabled
Supply voltage (VDD) < detection voltage (VLVI)
0
1
Notes 1. The value of LVIM is not initialized after a reset by LVI.
2. Bit 0 is a read-only bit.
3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
confirmed at LVIF.
4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Cautions 1. To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. Be sure to set bits 2 to 6 to 0.
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(2) Low-voltage detection level select register (LVIS)
This register selects the low-voltage detection level.
This register can be set by an 8-bit memory manipulation instruction.
Reset input clears this register to 00HNote
.
Figure 14-3. Format of Low-Voltage Detection Level Select Register (LVIS)
Address: FF51H, After reset: 00HNote R/W
Symbol
LVIS
7
0
6
0
5
0
4
0
3
2
1
0
LVIS3
LVIS2
LVIS1
LVIS0
LVIS3
LVIS2
LVIS1
LVIS0
Detection level
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
VLVI0 (4.3 V 0.2 V)
VLVI1 (4.1 V 0.2 V)
VLVI2 (3.9 V 0.2 V)
VLVI3 (3.7 V 0.2 V)
VLVI4 (3.5 V 0.2 V)
VLVI5 (3.3 V 0.15 V)
VLVI6 (3.1 V 0.15 V)
VLVI7 (2.85 V 0.15 V)
VLVI8 (2.6 V 0.15 V)
VLVI9 (2.35 V 0.15 V)
Setting prohibited
Other than above
Note
The value of LVIS is not initialized after a reset by LVI.
Caution
Bits 4 to 7 must be set to 0.
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14.4 Operation of Low-Voltage Detector
The low-voltage detector can be used in the following two modes.
•
•
Used as reset
Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when
VDD < VLVI, and releases internal reset when VDD ≥ VLVI.
Used as interrupt
Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI)
when VDD < VLVI.
The operation is set as follows.
(1) When used as reset
•
When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select
register (LVIS).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to instigate a wait of at least 0.2 ms.
<5> Wait until “supply voltage (VDD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM is confirmed.
<6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection
voltage (VLVI)).
Figure 14-4 shows the timing of generating the internal reset signal of the low-voltage detector. Numbers <1>
to <6> in this figure correspond to <1> to <6> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <3>.
2. If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal reset
signal is not generated.
•
When stopping operation
Either of the following procedures must be executed.
•
When using 8-bit memory manipulation instruction: Write 00H to LVIM.
•
When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and LVION to 0 in that order.
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Figure 14-4. Timing of Low-Voltage Detector Internal Reset Signal Generation
Supply voltage (VDD
)
LVI detection voltage
(VLVI
)
POC detection voltage
(VPOC
)
Time
<2>
H
LVIMK flag
(set by software)
<1>Note 1
LVION flag
(set by software)
Not cleared
Not cleared
<3>
Clear
<4> Wait for 0.2 ms or longer
LVIF flag
Clear
Clear
<5>
Note 2
LVIMD flag
(set by software)
Not cleared
Not cleared
<6>
LVIRF flagNote 3
LVI reset signal
POC reset signal
Cleared by
software
Cleared by
software
Internal reset signal
Notes 1. The LVIMK flag is set to “1” by reset input.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 12
RESET FUNCTION.
Remark <1> to <6> in Figure 14-4 above correspond to <1> to <6> in the description of “when starting operation”
in 14.4 (1) When used as reset.
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(2) When used as interrupt
When starting operation
•
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select
register (LVIS).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to instigate a wait of at least 0.2 ms.
<5> Wait until “supply voltage (VDD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM is confirmed.
<6> Clear the interrupt request flag of LVI (LVIIF) to 0.
<7> Release the interrupt mask flag of LVI (LVIMK).
<8> Execute the EI instruction (when vector interrupts are used).
Figure 14-5 shows the timing of generating the interrupt signal of the low-voltage detector. Numbers <1> to
<7> in this figure correspond to <1> to <7> above.
•
When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Figure 14-5. Timing of Low-Voltage Detector Interrupt Signal Generation
Supply voltage (VDD
)
LVI detection voltage
(VLVI
)
POC detection voltage
(VPOC
)
Time
<2>
LVIMK flag
(set by software)
<1>Note 1
<7> Cleared by software
LVION flag
(set by software)
<3>
<4> Wait for 0.2 ms or longer
LVIF flag
INTLVI
<5>
Note 2
LVIIF flag
<6>
Cleared by software
Note 2
Internal reset signal
Notes 1. The LVIMK flag is set to “1” by reset input.
2. The LVIF and LVIIF flags may be set (1).
Remark <1> to <7> in Figure 14-5 above correspond to <1> to <7> in the description of “when starting operation”
in 14.4 (2) When used as interrupt.
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14.5 Cautions for Low-Voltage Detector
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage
(VLVI), the operation is as follows depending on how the low-voltage detector is used.
<1> When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily
set by taking action (1) below.
<2> When used as interrupt
Interrupt requests may be frequently generated. Take action (2) below.
In this system, take the following actions.
<Action>
(1) When used as reset
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports (see Figure 14-6).
(2) When used as interrupt
Perform the processingNote for low voltage detection. Check that “supply voltage (VDD) ≥ detection voltage (VLVI)”
in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM).
Clear bit 1 (LVIIF) of interrupt request flag register 0 (IF0) to 0 and enable interrupts (EI).
In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for
the supply voltage fluctuation period, check that “supply voltage (VDD) ≥ detection voltage (VLVI)” using the LVIF
flag, and then enable interrupts (EI).
Note For low voltage detection processing, the CPU clock speed is switched to slow speed and the A/D
converter is stopped, etc.
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Figure 14-6. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
Reset
Check
; The reset source (power-on clear, WDT, or LVI)
can be identified by the RESF register.
reset sourceNote 2
LVI
; 8-bit timer H1 can operate with the low-speed Ring-OSC clock.
Source: fRL (480 kHz (MAX.))/27 × compare value 200 = 53 ms
(fRL: low-speed Ring-OSC clock oscillation frequency)
Start timer
(set to 50 ms)
Note 1
No
50 ms has passed?
(TMIFH1 = 1?)
; TMIFH1 = 1: Interrupt request is generated.
Yes
Initialization
processing
; Initialization of ports
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
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Figure 14-6. Example of Software Processing After Release of Reset (2/2)
• Checking reset source
Check reset source
Yes
WDTRF of RESF
register = 1?
No
Reset processing by
watchdog timer
No
LVIRF of RESF
register = 1?
Yes
Power-on-clear/external
reset generated
Reset processing by
low-voltage detector
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CHAPTER 15 OPTION BYTE
The 78K0S/KU1+ and 78K0S/KY1+ have an area called an option byte at address 0080H of the flash memory.
When using the product, be sure to set the following functions by using the option byte.
1. Selection of system clock source
• High-speed Ring-OSC clock
• Crystal/ceramic oscillation clock
• External clock input
2. Low-speed Ring-OSC clock oscillation
• Cannot be stopped.
• Can be stopped by software.
3. Control of RESET pin
• Used as RESET pin
• RESET pin is used as an input port pin (P34).
4. Oscillation stabilization time on power application or after reset release
• 210/fX
• 212/fX
• 215/fX
• 217/fX
Figure 15-1. Positioning of Option Byte
03FFH/
07FFH/
0FFFH
Flash memory
(1024/2048/4096 × 8 bits)
0080H
Option byte
DEF
DEF
1
1
RMCE OSCSEL1 OSCSEL0 RINGOSC
OSTS1 OSTS0
0000H
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CHAPTER 15 OPTION BYTE
Figure 15-2. Format of Option Byte (1/2)
Address: 0080H
7
6
5
4
1
3
2
1
0
1
DEFOSTS1 DEFOSTS0
RMCE
OSCSEL1
OSCSEL0
RINGOSC
RINGOSC
Low-speed Ring-OSC clock oscillation
1
0
Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit)
Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit)
Cautions 1. If it is selected that low-speed Ring-OSC clock oscillation cannot be stopped, the count
clock to the watchdog timer (WDT) is fixed to low-speed Ring-OSC.
2. If it is selected that low-speed Ring-OSC can be stopped by software, supply of the count
clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of bit 0
(LSRSTOP) of the low-speed Ring-OSC mode register (LSRCM). Similarly, clock supply
is also stopped when a clock other than the low-speed Ring-OSC is selected as a count
clock to WDT. If low-speed Ring-OSC is selected as the count clock to 8-bit timer H1,
however, the count clock is supplied in the HALT/STOP mode while low-speed Ring-OSC
operates (LSRSTOP = 0).
OSCSEL1
OSCSEL0
Selection of system clock source
Crystal/ceramic oscillation clock
0
0
1
0
1
×
External clock input
High-speed Ring-OSC clock
Caution Because the X1 and X2 pins are also used as the P23/ANI3 and P22/ANI2 pins, the conditions
under which the X1 and X2 pins can be used differ depending on the selected system clock
source.
(1) High-speed Ring-OSC clock
P23/ANI3 and P22/ANI2 pins can be used as I/O port pins or analog input pins of A/D
converter.
(2) Crystal/ceramic oscillation clock
The X1 and X2 pins cannot be used as I/O port pins or analog input pins of A/D converter
because they are used as clock input pins.
(3) External clock input
Because the X1 pin is used as an external clock input pin, P23/ANI3 cannot be used as
an I/O port pin or an analog input pin of A/D converter.
Remark × : don’t care
RMCE
Control of RESET pin
1
0
RESET pin is used as is.
RESET pin is used as input port pin (P34).
Caution If a low level is input to the RESET pin after reset is released by the power-on clear function
and before the option byte is referenced again, the 78K0S/KU1+ and 78K0S/KY1+ are reset,
and the status is held until a high level is input to the RESET pin.
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Figure 15-2. Format of Option Byte (2/2)
DEFOSTS1
DEFOSTS0
Oscillation stabilization time on power application or after reset release
0
0
1
1
0
1
0
1
210/fx (102.4 µs)
212/fx (409.6 µs)
215/fx (3.27 ms)
217/fx (13.1 ms)
Caution The setting of this option is valid only when the crystal/ceramic oscillation clock is selected
as the system clock source. No wait time elapses if the high-speed Ring-OSC or external
clock input is selected as the system clock source.
Remarks 1. ( ): fX = 10 MHz
2. For the oscillation stabilization time of the resonator, refer to the characteristics of the resonator
to be used.
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CHAPTER 16 FLASH MEMORY
16.1 Features
The internal flash memory of the 78K0S/KU1+ and 78K0S/KY1+ has the following features.
{ Erase/write with a single power supply
{ Capacity: 1/2/4 KB
• Erase unit: 1 block (256 bytes)
• Write unit: 1 byte
{ Rewriting method
• Rewriting by communication with dedicated flash programmer (on-board/off-board programming)
• Rewriting flash memory by user program (self programming)
{ Flash memory write prohibit function supported (security function)
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16.2 Memory Configuration
The 1/2/4 KB internal flash memory area is divided into 4/8/16 blocks and can be programmed/erased in block
units. All the blocks can also be erased at once.
Figure 16-1. Flash Memory Mapping
µPD78F9202,78F9212
0FFFH
Block 15 (256 bytes)
Block 14 (256 bytes)
0F00H
0EFFH
0E00H
0DFFH
FFFFH
Block 13 (256 bytes)
Block 12 (256 bytes)
Block 11 (256 bytes)
Block 10 (256 bytes)
0D00H
0CFFH
Special function resister
(256 byte)
0C00H
0BFFH
FF00H
FEFFH
0B00H
0AFFH
Internal high-speed RAM
(128 byte)
0A00H
09FFH
FE80H
FE7FH
Block 9 (256 bytes)
Block 8 (256 bytes)
0900H
08FFH
µPD78F9201,78F9211
0800H
07FFH
Block 7 (256 bytes)
Block 6 (256 bytes)
Block 7 (256 bytes)
Block 6 (256 bytes)
Use prohibited
0700H
06FFH
0600H
05FFH
Block 5 (256 bytes)
Block 4 (256 bytes)
Block 3 (256 bytes)
Block 2 (256 bytes)
Block 5 (256 bytes)
Block 4 (256 bytes)
Block 3 (256 bytes)
Block 2 (256 bytes)
0500H
04FFH
µPD78F9200,78F9210
0400H
03FFH
Block 3 (256 bytes)
0300H
02FFH
Block 2 (256 bytes)
Block 1 (256 bytes)
Flash memory
(1/2/4 KB)
0200H
01FFH
Block 1 (256 bytes)
Block 1 (256 bytes)
0100H
00FFH
Block 0 (256 bytes)
1 KB
Block 0 (256 bytes)
2 KB
Block 0 (256 bytes)
4 KB
0000H
0000H
16.3 Functional Outline
The internal flash memory of the 78K0S/KU1+ and 78K0S/KY1+ can be rewritten by using the rewrite function of
the dedicated flash programmer, regardless of whether the 78K0S/KU1+ and 78K0S/KY1+ have already been
mounted on the target system or not (on-board/off-board programming).
The function for rewriting a program with the user program (self programming), which is ideal for an application
when it is assumed that the program is changed after production/shipment of the target system, is provided.
In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also
supported, so that the program cannot be changed by an unauthorized person.
Refer to 16.7.4 Security settings for details on the security function.
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Table 16-1. Rewrite Method
Rewrite Method
Functional Outline
Operation Mode
Flash memory
On-board programming
Flash memory can be rewritten after the device is mounted on the
target system, by using a dedicated flash programmer.
programming mode
Off-board programming
Self programming
Flash memory can be rewritten before the device is mounted on the
target system, by using a dedicated flash programmer and a dedicated
program adapter board (FA series).
Flash memory can be rewritten by executing a user program that has
been written to the flash memory in advance by means of on-board/off-
board programming.
Self programming mode
Remarks 1. The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
2. Refer to the following sections for details on the flash memory writing control function.
• 16.7 On-Board and Off-Board Flash Memory Programming
• 16.8 Flash Memory Programming by Self Writing
16.4 Writing with Flash Programmer
The following two types of dedicated flash programmers can be used for writing data to the internal flash memory
of the 78K0S/KU1+ and 78K0S/KY1+.
• FlashPro4 (PG-FP4, FL-PR4)
• PG-FPL2
Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer.
(1) On-board programming
The contents of the flash memory can be rewritten after the 78K0S/KU1+ and 78K0S/KY1+ have been mounted
on the target system. The connectors that connect the dedicated flash programmer and the test pad must be
mounted on the target system. The test pad is required only when writing data with the crystal/ceramic resonator
mounted (refer to Figure 16-7 for mounting of the test pad).
(2) Off-board programming
Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0S/KU1+
and 78K0S/KY1+ are mounted on the target system.
Remark The FL-PR4 and FA series are products of Naito Densei Machida Mfg. Co., Ltd.
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CHAPTER 16 FLASH MEMORY
16.5 Programming Environment
The environment required for writing a program to the flash memory is illustrated below.
Figure 16-2. Environment for Writing Program to Flash Memory
78K0S/KU1+
78K0S/KY1+
FlashPro4
Axxxx
RS-232-C
Bxxxxx
Cxxxxxx
(FSlTash Pro4)
A
TVE
PG-FP4
V
DD
SS
USB
V
RESET
DGCLKNote
DGDATANote
PG-FPL2
MODE
USB
Target 3V
Host machine
PG-FPL2
Power Status
Target
Dedicated flash programmer
Note DGCLK and DGDATA are single-wire bidirectional communication interfaces. They use UART as the
communication mode.
A host machine that controls the dedicated flash programmer is necessary. When using the PG-FP4 or FL-PR4,
data can be written with just the dedicated flash programmer after downloading the program from the host machine.
UART is used for manipulation such as writing and erasing when interfacing between the dedicated flash
programmer and the 78K0S/KU1+, 78K0S/KY1+. To write the flash memory off-board, a dedicated program adapter
(FA series) is necessary.
Download the latest programmer firmware, GUI, and parameter file from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html).
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Table 16-2. Wiring Between 78K0S/KU1+ and FlashPro4
FlashPro4 Connection Pin
Pin Function
78K0S/KU1+ Connection Pin
Pin Name Pin No.
X1/P23/ANI3
Pin Name
CLKNote
I/O
Output
Output
Input
Output
Output
–
Clock to 78K0S/KU1+
On-board mode signal
Receive signal
2
FLMD0Note
SI/RxDNote
SO/TxDNote
/RESET
VDD
X2/P22/ANI2
3
Receive signal/on-board mode signal
Reset signal
RESET/P34
VDD
4
1
8
VDD voltage generation/voltage monitor
Ground
GND
–
VSS
Note In the 78K0S/KU1+, the CLK and FLMD0 signals are connected to the X1 pin and the SI/RxD and SO/TxD
signals to the X2 signal; therefore, these signals need to be directly connected.
Figure 16-3. Communication with FlashPro4 (78K0S/KU1+)
FlashPro4
signal name
1
2
3
4
8
7
6
5
CLK
FLMD0
SI/RxD
SO/TxD
/RESET
V
DD
78K0S/KU1+
GND
Table 16-3. Wiring Between 78K0S/KU1+ and PG-FPL2
PG-FPL2 Connection Pin
Pin Function
78K0S/KU1+ Connection Pin
Pin Name
DGCLK
DGDATA
/RESET
VDD
I/O
Output
Pin Name
X1/P23/ANI3
X2/P22/ANI2
RESET/P34
VDD
Pin No.
Clock to 78K0S/KU1+
Transmit/receive signal, on-board mode signal
Reset signal
2
3
4
1
8
I/O
Output
I/O
VDD voltage generation
Ground
GND
–
VSS
Figure 16-4. Communication with PG-FPL2 (78K0S/KU1+)
PG-FPL2
signal name
1
2
3
4
8
7
6
5
DGCLK
DGDATA
/RESET
VDD
GND
78K0S/KU1+
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Table 16-4. Wiring Between 78K0S/KY1+ and FlashPro4
FlashPro4 Connection Pin
Pin Function
78K0S/KY1+ Connection Pin
Pin Name Pin No.
X1/P23/ANI3
Pin Name
CLKNote
I/O
Output
Output
Input
Output
Output
–
Clock to 78K0S/KY1+
On-board mode signal
Receive signal
8
FLMD0Note
SI/RxDNote
SO/TxDNote
/RESET
VDD
X2/P22/ANI2
9
Receive signal/on-board mode signal
Reset signal
RESET/P34
VDD
12
5
VDD voltage generation/voltage monitor
Ground
GND
–
VSS
4
Note In the 78K0S/KY1+, the CLK and FLMD0 signals are connected to the X1 pin and the SI/RxD and SO/TxD
signals to the X2 signal; therefore, these signals need to be directly connected.
Figure 16-5. Communication with FlashPro4 (78K0S/KY1+)
FlashPro4
signal name
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FLMD0
SI/RxD
SO/TxD
/RESET
VDD
78K0S/KY1+
GND
Table 16-5. Wiring Between 78K0S/KY1+ and PG-FPL2
PG-FPL2 Connection Pin
Pin Function
78K0S/KU1+ Connection Pin
Pin Name Pin No.
X1/P21
Pin Name
DGCLK
DGDATA
/RESET
VDD
I/O
Output
Clock to 78K0S/KY1+
Transmit/receive signal, on-board mode signal
Reset signal
8
9
I/O
X2/P22
RESET/P34
VDD
Output
I/O
12
5
VDD voltage generation
Ground
GND
–
VSS
4
Figure 16-6. Communication with PG-FPL2 (78K0S/KY1+)
PG-FPL2
signal name
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DGCLK
DGDATA
/RESET
VDD
GND
78K0S/KY1+
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16.6 Processing of Pins on Board
To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on
the target system. First provide a function that selects the normal operation mode or flash memory programming
mode on the board.
When the flash memory programming mode is set, all the pins not used for programming the flash memory are in
the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately
after reset, the pins must be processed as described below.
The state of the pins in the self programming mode is the same as that in the HALT mode.
16.6.1 X1 and X2 pins
The X1 and X2 pins are used as the serial interface of flash memory programming. Therefore, if the X1 and X2
pins are connected to an external device, a signal conflict occurs. To prevent the conflict of signals, isolate the
connection with the external device.
Perform the following processing (1) and (2) when on-board writing is performed with the resonator mounted, when
it is difficult to isolate the resonator, while a crystal or ceramic resonator is selected as the system clock.
(1) Mount the minimum-possible test pads between the device and the resonator, and connect the flash
programmer via the test pad. Keep the wiring as short as possible (refer to Figure 16-7 and Table 16-6).
(2) Set the oscillation frequency of the communication clock for writing using the GUI software of the dedicated
flash programmer. Research the series/parallel resonant and antiresonant frequencies of the resonator used,
and set the oscillation frequency so that it is outside the range of the resonant frequency 10% (refer to Figure
16-8 and Table 16-7).
Figure 16-7. Example of Mounting Test Pads
Test pad
VSS
X1
X2
Table 16-6. Clock to Be Used and Mounting of Test Pads
Clock to Be Used
High-speed Ring-OSC clock
Mounting of Test Pads
Not required
External clock
Crystal/ceramic oscillation
clock
Before resonator is mounted
After resonator is mounted
Required
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Figure 16-8. PG-FP4 GUI Software Setting Example
Set oscillation frequency
Click
(Standard tab in Device setup window)
(Main window)
Table 16-7. Oscillation Frequency and PG-FP4 GUI Software Setting Value Example
Oscillation Frequency
PG-FP4 GUI Software Setting Value Example
(Communication Frequency)
1 MHz ≤ fX < 4 MHz
8 MHz
4 MHz ≤ fX < 8 MHz
8 MHz ≤ fX < 9 MHz
9 MHz ≤ fX ≤ 10 MHz
9 MHz
10 MHz
8 MHz
Caution The above setting values are under development, so they may be changed in the
future.
16.6.2 RESET pin
If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset
signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the
reset signal generator.
If the reset signal is input from the user system while the flash memory programming mode is set, the flash
memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash
programmer.
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Figure 16-9. Signal Collision (RESET Pin)
78K0S/KU1+,
78K0S/KY1+
Dedicated flash programmer
Signal collision
connection signal
Reset signal generator
Output pin
RESET
In the flash memory programming mode, the signal output by the reset
signal generator collides with the signal output by the dedicated flash
programmer. Therefore, isolate the signal of the reset signal generator.
16.6.3 Port pins
When the flash memory programming mode is set, all the pins not used for flash memory programming enter the
same status as that immediately after reset. If external devices connected to the ports do not recognize the port
status immediately after reset, the port pin must be connected to VDD or VSS via a resistor.
The state of the pins in the self programming mode is the same as that in the HALT mode.
16.6.4 Power supply
Connect the VDD pin to VDD of the flash programmer, and the VSS pin to VSS of the flash programmer.
16.7 On-Board and Off-Board Flash Memory Programming
16.7.1 Controlling flash memory
The following figure illustrates the procedure to manipulate the flash memory.
Figure 16-10. Flash Memory Manipulation Procedure
Start
Flash memory programming
mode is set
Manipulate flash memory
No
End?
Yes
End
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16.7.2 Flash memory programming mode
To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0S/KU1+ and
78K0S/KY1+ in the flash memory programming mode. When the 78K0S/KU1+ and 78K0S/KY1+ are connected to
the flash programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in
the flash memory programming mode.
Change the mode by using a jumper when writing the flash memory on-board.
16.7.3 Communication commands
The 78K0S/KU1+ and 78K0S/KY1+ communicate with the dedicated flash programmer by using commands. The
signals sent from the flash programmer to the 78K0S/KU1+ and 78K0S/KY1+ are called commands, and the
commands sent from the 78K0S/KU1+ and 78K0S/KY1+ to the dedicated flash programmer are called response
commands.
Figure 16-11. Communication Commands
78K0S/KU1+
FlashPro4
Axxxx
Bxxxxx
Cxxxxxx
(FSlTash Pro4)
A
TVE
PG-FP4
Command
PG-FPL2
Response command
78K0S/KY1+
MODE
Target 3V
PG-FPL2
Power Status
Target
Dedicated flash programmer
The flash memory control commands of the 78K0S/KU1+ and 78K0S/KY1+ are listed in the table below. All these
commands are issued from the programmer, 78K0S/KU1+, and 78K0S/KY1+ perform processing corresponding to
the respective commands.
Table 16-8. Flash Memory Control Commands
Classification
Command Name
Batch erase (chip erase) command
Block erase command
Function
Erase
Write
Erases the contents of the entire memory
Erases the contents of the memory of the specified block
Write command
Writes to the specified address range and executes a verify
check of the contents.
Checksum
Checksum command
Reads the checksum of the specified address range and
compares with the written data.
Blank check
Security
Blank check command
Security set command
Confirms the erasure status of the entire memory.
Prohibits batch erase (chip erase) command, block erase
command, and write command to prevent operation by third
parties.
The 78K0S/KU1+ and 78K0S/KY1+ return a response command for the command issued by the dedicated flash
programmer. The response commands sent from the 78K0S/KU1+ and 78K0S/KY1+ are listed below.
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Table 16-6. Response Commands
Command Name
Function
ACK
NAK
Acknowledges command/data.
Acknowledges illegal command/data.
16.7.4 Security settings
The operations shown below can be prohibited using the security setting command.
Caution The security setting is valid when the programming mode is set next time. Therefore, when the
security setting command is executed, exit from the programming mode, then set the
programming mode again.
• Batch erase (chip erase)
Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is
prohibited. Once execution of the batch erase (chip erase) command is prohibited, all the prohibition settings can
no longer be cancelled.
Caution After the security setting of the batch erase is set, erasure cannot be performed for the device.
In addition, even if a write command is executed, data different from that which has already
been written to the flash memory cannot be written because the erase command is disabled.
• Block erase
Execution of the block erase command for a specific block in the flash memory is prohibited. This prohibition
setting can be cancelled using the batch erase (chip erase) command.
• Write
Execution of the write and block erase commands for entire blocks in the flash memory is prohibited. This
prohibition setting can be cancelled using the batch erase (chip erase) command.
The batch erase (chip erase), block erase, and write commands are enabled by the default setting when the flash
memory is shipped. The above security settings are possible only for on-board/off-board programming. Each security
setting can be used in combination.
Table 16-10 shows the relationship between the erase and write commands when the 78K0S/KU1+ and
78K0S/KY1+ security function is enabled.
Table 16-10. Relationship Between Commands When Security Function Is Enabled
Command Batch Erase (Chip
Erase) Command
Block Erase
Command
Write Command
Security
When batch erase (chip erase) security
operation is enabled
Disabled
Enabled
Disabled
EnabledNote
Enabled
When block erase security operation is
enabled
When write security operation is enabled
Disabled
Note Since the erase command is disabled, data different from that which has already been written to the
flash memory cannot be written.
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Table 16-11 shows the relationship between the security setting and the operation in each programming mode.
Table 16-11. Relationship Between Security Setting and Operation In Each Programming Mode
Programming Mode
Security Setting
On-Board/Off-Board Programming
Self Programming
Security Setting Security Operation
Impossible
InvalidNote 2
Security Setting
Possible
Security Operation
ValidNote 1
Batch erase (chip erase)
Block erase
Write
Notes 1. Execution of each command is prohibited by the security setting.
2. Execution of self programming command is possible regardless of the security setting.
16.8 Flash Memory Programming by Self Writing
The 78K0S/KU1+ and 78K0S/KY1+ support a self programming function that can be used to rewrite the flash
memory via a user program, making it possible to upgrade programs in the field.
Caution Self programming processing must be included in the program before performing self writing.
Remark To use the internal flash memory of the 78K0S/KU1+ and 78K0S/KY1+ as the external EEPROM for
storing data, refer to “78K0S/Kx1+ EEPROM Emulation AN” (release schedule is undefined).
16.8.1 Outline of self programming
To execute self programming, shift the mode from the normal operation of the user program (normal mode) to the
self programming mode. Write/erase processing for the flash memory, which has been set to the register in advance,
is performed by executing the HALT instruction during self programming mode. The HALT state is automatically
released when processing is completed.
To shift to the self programming mode, execute a specific sequence for a specific register. Refer to 16.8.4
Example of shifting normal mode to self programming for details.
Remark Data written by self programming can be referenced with the MOV instruction.
Table 16-12. Self Programming Mode
Mode
User Program Execution
Execution of Write/erase for Flash
Memory with HALT Instruction
Normal mode
Self programming mode
Enabled
−
EnabledNote
Enabled
Note Maskable interrupt servicing is disabled during self programming mode.
Figure 16-12 shows a block diagram for self programming, Figure 16-13 shows the self programming state
transition diagram, Table 16-13 lists the commands for controlling self programming.
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Figure 16-12. Block Diagram of Self Programming
Internal bus
Flash programming command
register (FLCMD)
Protect byte
Flash programming mode
control register (FLPMC)
Flash protect command
register (PFCMD)
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0
FLCMD2 FLCMD1 FLCMD0
Self programming mode
setting sequencer
Self programming mode setting register
5
3
HALT signal
Self programming command execution
Flash memory controller
Erase
circuit
Write
circuit
Verify
circuit
Increment
circuit
HALT release signal
Flash address
pointer H (FLAPH)
Flash memory
Match
Flash address
pointer L (FLAPL)
Unmatch
Match
Flash address pointer H
compare register
(FLAPHC)
Flash address pointer L
compare register
(FLAPLC)
Flash write buffer register
(FLW)
WEPERR VCERR FPRERR
Flash status register (PFS)
Internal bus
CHAPTER 16 FLASH MEMORY
Figure 16-13. Self Programming State Transition Diagram
User program
Operation setting
Normal mode
Specific sequence
Operation
setting
Register for
Self programming mode
self programming
Self programming command
execution by HALT instruction
Self programming
command completion/error
Flash memory
control block (hardware)
Operation reference
Self programming
command under execution
Flash memory
Table 16-13. Self Programming Controlling Commands
Command Name
Function
Time Taken from HALT Instruction Execution
to Command Execution End
Internal verify
This command is used to check if data has been
correctly written to the flash memory. After data has
Internal verify for 1 block (internal verify
command executed once): 6.8 ms
been written to the memory, specify the block number, Internal verify for 1 byte:
the start address, and the end address, then execute
this command.
27 µs
Block erasure
This command is used to erase a specified block.
Specify the block number before execution.
8.5 ms
Block blank check
This command is used to check if data in a specified
block has been erased. Specify the block number,
then execute this command.
480 µs
Byte write
This command is used to write 1-byte data to the
specified address in the flash memory. Specify the
write address and write data, then execute this
command.
150 µs
16.8.2 Cautions on self programming function
• If an interrupt occurs during self programming, the interrupt request flag is set (1), and interrupt servicing is
performed after the self programming mode is released. To avoid this operation, disable interrupt servicing (by
setting MK0 and MK1 to FFH, and executing the DI instruction) during self programming or before a mode is
shifted from the normal mode to the self programming mode with a specific sequence.
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• No instructions can be executed while a self programming command is being executed. Therefore, clear and
restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self
programming. Refer to Table 16-13 for the time taken for the execution of self programming.
• RAM is not used while a self programming command is being executed.
• If the supply voltage drops or the reset signal is input while the flash memory is being written or erased,
writing/erasing is not guaranteed.
• The value of the blank data set during block erasure is FFH.
• When the oscillator or the external clock is selected as the main clock, a wait time of 16 µs is required starting
from the setting of the self programming mode to the execution of the HALT instruction.
• The state of the pins in self programming mode is the same as that in HALT mode.
• Since the security function set via on-board/off-board programming is disabled in self programming mode, the
self programming command can be executed regardless of the security function setting. To disable write or erase
processing during self programming, set the protect byte.
• Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register
(FLAPHC) to 0 before executing the self programming command. If the value of these bits is 1 when executing
the self programming command.
16.8.3 Registers used for self-programming function
The following registers are used for the self-programming function.
• Flash programming mode control register (FLPMC)
• Flash protect command register (PFCMD)
• Flash status register (PFS)
• Flash programming command register (FLCMD)
• Flash address pointers H and L (FLAPH and FLAPL)
• Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and FLAPLC)
• Flash write buffer register (FLW)
The 78K0S/KU1+ and 78K0S/KY1+ have an area called a protect byte at address 0081H of the flash memory.
(1) Flash programming mode control register (FLPMC)
This register is used to set the operation mode when data is written to the flash memory in the self-
programming mode, and to read the set value of the protect byte.
Data can be written to FLPMC only in a specific sequence (refer to 16.8.3 (2) Flash protect command
register (PFCMD)) so that the application system does not stop by accident because of malfunction due to
noise or program hang-up.
This register is set with an 8-bit memory manipulation instruction.
Reset input makes the contents of this register undefined.
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Figure 16-14. Format of Flash Programming Mode Control Register (FLPMC)
Address: FFA2H
After reset: UndefinedNote 1
R/WNote 2
Symbol
FLPMC
7
6
5
4
3
2
1
0
0
0
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0
FLSPM
FLSPM
0
Selection of operation mode during self-programming mode
Normal mode
Flash memory instructions can be fetched from all addresses.
Self-programming mode
1
Before executing the HALT instruction, set the command, address offset, write
data, and set FLSPM to 1. After setting these items, execute the HALT
instruction; the flash memory mode is then shifted from the normal mode to the
flash memory programming mode.
The set value of the protect byte
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0
is read to these bits.
Notes 1. Bit 0 (FLSPM) is cleared to 0 when reset is released. The set value of the protect
byte is read to bits 2 to 6 (PRSELF0 to PRSELF4) after reset is released.
2. Bits 2 to 6 (PRSELF0 to PRSELF4) are read-only.
Cautions 1. Note the following when setting the self programming mode.
• If an interrupt occurs during self programming, the interrupt request flag
is set (1), and interrupt servicing is performed after the self programming
mode is released. To avoid this operation, disable interrupt servicing (by
setting MK0 to FFH, and executing the DI instruction) during self
programming or before a mode is shifted from the normal mode to the self
programming mode with a specific sequence.
• No instructions can be executed while a self programming command is
being executed. Therefore, clear and restart the watchdog timer counter in
advance so that the watchdog timer does not overflow during self
programming. Refer to Table 16-13 for the time taken for the execution of
self programming.
• If the supply voltage drops or the reset signal is input while the flash
memory is being written or erased, writing/erasing is not guaranteed.
2. When the oscillator or the external clock is selected as the main clock, a wait
time of 16 µs is required from setting FLSPM to 1 to execution of the HALT
instruction.
(2) Flash protect command register (PFCMD)
If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an
operation to write the flash programming mode control register (FLPMC) may have a serious effect on the
system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop
inadvertently.
Writing FLPMC is enabled only when a write operation is performed in the following specific sequence.
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<1> Write a specific value to PFCMD (PFCMD = A5H)
<2> Write the value to be set to FLPMC (writing in this step is invalid)
<3> Write the inverted value of the value to be set to FLPMC (writing in this step is invalid)
<4> Write the value to be set to FLPMC (writing in this step is valid)
This rewrites the value of the register, so that the register cannot be written illegally.
Occurrence of an illegal store operation can be checked by bit 0 (FPRERR) of the flash status register (PFS).
A5H must be written to PFCMD each time the value of FLPMC is changed.
PFCMD can be set by an 8-bit memory manipulation instruction.
Reset input makes PFCMD undefined.
Figure 16-15. Format of Flash Protect Command Register (PFCMD)
Address: FFA0H
After reset: Undefined
W
4
Symbol
PFCMD
7
6
5
3
2
1
0
REG7
REG6
REG5
REG4
REG3
REG2
REG1
REG0
Caution Disable interrupt servicing (by setting MK0 to FFH and executing the DI
instruction) while the specific sequence is under execution.
(3) Flash status register (PFS)
If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct
sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error
occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.
When FPRERR is 1, it can be cleared to 0 by writing 0 to it.
Errors that may occur during self-programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
VCERR or WEPRERR can be cleared by writing 0 to them.
All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly.
PFS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears PFS to 00H.
Figure 16-16. Format of Flash Status Register (PFS)
Address: FFA1H
After reset: 00H
6
R/W
Symbol
PFS
7
5
0
4
0
3
0
2
1
0
0
0
WEPRERR
VCERR
FPRERR
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1. Operating conditions of FPRERR flag
<Setting conditions>
• If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to
write a specific value (A5H) to PFCMD
• If the first store instruction operation after <1> is on a peripheral register other than FLPMC
• If the first store instruction operation after <2> is on a peripheral register other than FLPMC
• If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction
after <2>
• If the first store instruction operation after <3> is on a peripheral register other than FLPMC
• If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction
after <3>
Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command
register (PFCMD).
<Reset conditions>
• If 0 is written to the FPRERR flag
• If the reset signal is input
2. Operating conditions of VCERR flag
<Setting conditions>
• Erasure verification error
• Internal writing verification error
If VCERR is set, it means that the flash memory has not been erased or written correctly. Erase or write the
memory again in the specified procedure.
Remark The VCERR flag may also be set if an erase or write protect error occurs.
<Reset conditions>
• When 0 is written to the VCERR flag
• When the reset signal is input
3. Operating conditions of WEPRERR flag
<Setting conditions>
• If the area specified by the protect byte to be protected from erasing or writing is specified by the flash
address pointer H (FLAPH) and a command is executed to this area
<Reset conditions>
• When 0 is written to the WEPRERR flag
• When the reset signal is input
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(4) Flash programming command register (FLCMD)
This register is used to specify whether the flash memory is erased, written, or verified in the self-programming
mode.
This register is set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
Figure 16-17. Format of Flash Programming Command Register (FLCMD)
Address: FFA3H
After reset: 00H
6
R/W
Symbol
FLCMD
7
5
0
4
0
3
0
2
1
0
0
0
FLCMD2 FLCMD1 FLCMD0
FLCMD2 FLCMD1 FLCMD0 Command Name
Internal verify
Function
This command is used to check if
data has been correctly written to the
flash memory. After data has been
written to the memory, execute this
0
0
1
command by specifying
a block
number, start address, and end
address. If an error occurs, bit 1
(VCERR) or bit 2 (WEPRERR) of the
flash status register (PFS) is set to 1.
This command is used to erase
specified block. It is used both in the
Block erase
0
1
1
on-board
mode
and
self-
programming mode.
Block blank check This command is used to check if the
specified block has been erased.
1
1
0
0
0
1
Byte write
This command is used to write 1-byte
data to the specified address in the
flash memory.
Specify the write
address and write data, then execute
this command.
Other than aboveNote
Setting prohibited
Note If a value other than the above is set and the self programming mode is set, the self programming
mode is canceled immediately and no execution occurs. At this time, the flag of the PFS register is
not set.
(5) Flash address pointers H and L (FLAPH and FLAPL)
These registers are used to specify the start address of the flash memory when the memory is erased, written,
or verified in the self-programming mode.
FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of
FLAPHC and FLAPLC when the programming command is not executed. When the programming command
is executed, therefore, set the value again.
These registers are set with a 1-bit or 8-bit memory manipulation instruction.
Reset input makes these registers undefined.
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Figure 16-18. Format of Flash Address Pointer H/L (FLAPH/FLAPL)
Address: FFA4H, FFA5H
After reset: 00H
R/W
FLAPH (FFA5H)
FLAPL (FFA4H)
0
0
0
0
FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA
P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Caution Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self
programming command. If the value of these bits is 1 when executing the self
programming command.
(6) Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and
FLAPLC)
These registers are used to specify the address range in which the internal sequencer operates when the flash
memory is verified in the self-programming mode.
Set FLAPHC to the same value as that of FLAPH. Set the last address of the range in which verification is to
be executed to FLAPLC.
These registers are set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears these registers to 00H.
Figure 16-19. Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC)
Address: FFA6H, FFA7H
After reset: 00H
R/W
FLAPHC (FFA7H)
FLAPLC (FFA6H)
0
0
0
0
FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP
C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
Cautions 1. Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self
programming command. If the value of these bits is 1 when executing the self
programming command.
2. Set the number of the block subject to a block erase, write, verify, or blank check
(same value as FLAPH) to FLAPHC.
3. Clear FLAPLC to 00H when a block erase is performed, and set this register to FFH
when a blank check is performed.
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(7) Flash write buffer register (FLW)
This register is used to store the data to be written to the flash memory.
This register is set with an 8-bit memory manipulation instruction.
Reset input clears these registers to 00H.
Figure 16-20. Format of Flash Write Buffer Register (FLW)
Address: FFA8H
After reset: 00H
6
R/W
Symbol
FLW
7
5
4
3
2
1
0
FLW7
FLW6
FLW5
FLW4
FLW3
FLW2
FLW1
FLW0
(8) Protect byte
This protect byte is used to specify the area that is to be protected from writing or erasing. The specified area
is valid only in the self-programming mode. Because self-programming of the protected area is invalid, the data
written to the protected area is guaranteed.
Figure 16-21. Format of Protect Byte (1/2)
Address: 0081H
7
1
6
5
4
3
2
1
1
0
1
PRSELF4
PRSELF3
PRSELF2
PRSELF1
PRSELF0
• µ PD78F9200, 78F9210
PRSELF4
PRSELF3
PRSELF2
1
PRSELF1
1
PRSELF0
0
Status
0
1
Blocks 3 to 0 are protected.
Blocks 1 and 0 are protected.
0
1
1
1
1
1
1
1
1
Blocks 2 and 3 can be written or erased.
All blocks can be written or erased.
Setting prohibited
1
Other than above
• µ PD78F9201, 78F9211
PRSELF4
PRSELF3
PRSELF2
1
PRSELF1
0
PRSELF0
0
Status
0
1
Blocks 7 to 0 are protected.
Blocks 5 to 0 are protected.
0
0
1
1
1
1
1
0
1
1
0
Blocks 6 and 7 can be written or erased.
Blocks 3 to 0 are protected.
Blocks 4 to 7 can be written or erased.
Blocks 1 and 0 are protected.
Blocks 2 to 7 can be written or erased.
All blocks can be written or erased.
Setting prohibited
0
1
1
1
1
1
1
1
1
Other than above
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Figure 16-21. Format of Protect Byte (2/2)
• µ PD78F9202, 78F9212
PRSELF4
PRSELF3
PRSELF2
0
PRSELF1
0
PRSELF0
0
Status
0
1
Blocks 15 to 0 are protected.
Blocks 13 to 0 are protected.
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
Blocks 14 and 15 can be written or erased.
Blocks 11 to 0 are protected.
Blocks 12 to 15 can be written or erased.
Blocks 9 to 0 are protected.
Blocks 10 to 15 can be written or erased.
Blocks 7 to 0 are protected.
Blocks 8 to 15 can be written or erased.
Blocks 5 to 0 are protected.
Blocks 6 to 15 can be written or erased.
Blocks 3 to 0 are protected.
Blocks 4 to 15 can be written or erased.
Blocks 1 and 0 are protected.
0
1
1
1
1
1
1
1
Blocks 2 to 15 can be written or erased.
All blocks can be written or erased.
Setting prohibited
1
Other than above
16.8.4 Example of shifting normal mode to self programming mode
The operating mode must be shifted from normal mode to self programming mode before performing self
programming.
An example of shifting to self programming mode is explained below.
<1> Disable interrupts if the interrupt function is used (by setting the interrupt mask flag registers (MK0) to FFH
and executing the DI instruction).
<2> Clear the flash status register (PFS).
<3> Set self programming mode using a specific sequence.
• Write a specific value (A5H) to PFCMD.
• Write 01H to FLPMC (writing in this step is invalid).
• Write 0FEH (inverted value of 01H) to FLPMC (writing in this step is invalid).
• Write 01H to FLPMC (writing in this step is valid).
<4> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFS.
Abnormal → <2>, normal → <5>
<5> Mode shift is completed.
Caution Be sure to perform the series of operations described above using the user program at an
address where data is not erased nor written.
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Figure 16-22. Example of Shifting to Self Programming Mode
Shift to self programming mode
<1> Disable interrupts (by setting
MK0 to FFH and executing DI
; When interrupt function is used
instruction)
<2> Clear PFS
PFCMD = A5H
FLPMC = 01H (set value)
FLPMC = 0FEH (inverted set value)
FLPMC = 01H (set value)
; Set value is invalid
<3>
; Set value is valid
Abnormal
<4> Check execution result
(FPRERR flag)
Normal
<5> Termination
Caution Be sure to perform the series of operations described above using the user program at an
address where data is not erased nor written.
Remark <1> to <5> in Figure 16-22 correspond to <1> to <5> in 16.8.4 (previous page).
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An example of the program list that shifts the mode to self programming mode is shown below.
;----------------------------
;START
;----------------------------
MOV
MK0,#11111111B
; Masks all interrupts
DI
ModeOnLoop:
MOV
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#01H
FLPMC,#0FEH
FLPMC,#01H
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
; Sets self programming mode with FLPMC register
; control (sets value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOnLoop
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs.
;----------------------------
;END
;----------------------------
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16.8.5 Example of shifting self programming mode to normal mode
The operating mode must be returned from self programming mode to normal mode after performing self
programming.
An example of shifting to normal mode is explained below.
<1> Clear the flash status register (PFS).
<2> Set normal mode using a specific sequence.
• Write the specific value (A5H) to PFCMD.
• Write 00H to FLPMC (writing in this step is invalid)
• Write 0FFH (inverted value of 00H) to FLPMC (writing in this step is invalid)
• Write 00H to FLPMC (writing in this step is valid)
<3> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFS.
Abnormal → <1>, normal → <4>
<4> Enable interrupt servicing (by executing the EI instruction and changing MK0) to restore the original state.
<5> Mode shift is completed
Caution Be sure to perform the series of operations described above using the user program at an
address where data is not erased nor written.
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Figure 16-23. Example of Shifting to Normal Mode
Shift to normal mode
<1> Clear PFS
PFCMD = A5H
FLPMC = 00H (set value)
FLPMC = 0FFH (inverted set value)
FLPMC = 00H (set value)
; Set value is invalid
<2>
; Set value is valid
Abnormal
<3> Check execution result
(FPRERR flag)
Normal
<4> Enable interrupts
(by executing EI instruction
and changing MK0)
; When interrupt function is used
<5> Termination
Caution Be sure to perform the series of operations described above using the user program at an
address where data is not erased nor written.
Remark <1> to <5> in Figure 16-23 correspond to <1> to <5> in 16.8.5 (previous page).
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An example of a program list that shifts the mode to normal mode is shown below.
;----------------------------
;START
;----------------------------
ModeOffLoop:
MOV
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#00H
FLPMC,#0FFH
FLPMC,#00H
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
; Sets normal mode via FLPMC register control (sets value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOffLoop
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
MOV
EI
MK0,#INT_MK0
; Restores interrupt mask flag
;----------------------------
;END
;----------------------------
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16.8.6 Example of block erase operation in self programming mode
An example of the block erase operation in self programming mode is explained below.
<1> Set 03H (block erase) to the flash program command register (FLCMD).
<2> Set the block number to be erased, to flash address pointer H (FLAPH).
<3> Set flash address pointer L (FLAPL) to 00H.
<4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Set the flash address pointer L compare register (FLAPLC) to 00H.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note
.
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
Normal
→ <11>
<10> Block erase processing is abnormally terminated.
<11> Block erase processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
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Figure 16-24. Example of Block Erase Operation in Self Programming Mode
Block erasure
<1> Set erase command
(FLCMD = 03H)
<2> Set no. of block to be erased
to FLAPH
<3> Set FLAPL to 00H
<4> Set the same value as
that of FLAPH to FLAPHC
<5> Set FLAPLC to 00H
<6> Clear PFS
<7> Clear & restart WDT counter
(WDTE = ACH)Note
<8> Execute HALT instruction
<9> Check execution result
(VCERR and WEPRERR flags)
Abnormal
Normal
<11> Normal termination
<10> Abnormal termination
Note This setting is not required when the watchdog timer is not used.
Remark <1> to <11> in Figure 16-24 correspond to <1> to <11> in 16.8.6 (previous page).
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An example of a program list that performs a block erase in self programming mode is shown below.
;----------------------------
;START
;----------------------------
FlashBlockErase:
MOV
MOV
MOV
MOV
MOV
FLCMD,#03H
FLAPH,#07H
FLAPL,#00H
FLAPHC,#07H
FLAPLC,#00H
; Sets flash control command (block erase)
; Sets number of block to be erased (block 7 is specified here)
; Fixes FLAPL to “00H”
; Sets erase block compare number (same value as that of FLAPH)
; Fixes FLAPLC to “00H”
MOV
MOV
HALT
MOV
MOV
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
CmdStatus,A
; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
;----------------------------
;END
;----------------------------
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16.8.7 Example of block blank check operation in self programming mode
An example of the block blank check operation in self programming mode is explained below.
<1> Set 04H (block blank check) to the flash program command register (FLCMD).
<2> Set the number of block for which a blank check is performed, to flash address pointer H (FLAPH).
<3> Set flash address pointer L (FLAPL) to 00H.
<4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Set the flash address pointer L compare register (FLAPLC) to FFH.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note
.
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
Normal
→ <11>
<10> Block blank check is abnormally terminated.
<11> Block blank check is normally terminated.
Note This setting is not required when the watchdog timer is not used.
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Figure 16-25. Example of Block Blank Check Operation in Self Programming Mode
Block blank check
<1> Set block blank check
command (FLCMD = 04H)
<2> Set no. of block for
blank check to FLAPH
<3> Set FLAPL to 00H
<4> Set the same value as
that of FLAPH to FLAPHC
<5> Set FLAPLC to 00H
<6> Clear PFS
<7> Clear & restart WDT counter
(WDTE = ACH)Note
<8> Execute HALT instruction
Abnormal
<9> Check execution result
(VCERR and WEPRERR flags)
Normal
<10> Abnormal termination
<11> Normal termination
Note This setting is not required when the watchdog timer is not used.
Remark <1> to <11>in Figure 16-25 correspond to <1> to <11> in 16.8.7 (previous page).
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An example of a program list that performs a block blank check in self programming mode is shown below.
;----------------------------
;START
;----------------------------
FlashBlockBlankCheck:
MOV
MOV
FLCMD,#04H
FLAPH,#07H
; Sets flash control command (block blank check)
; Sets number of block for blank check (block 7 is specified
; here)
MOV
MOV
FLAPL,#00H
; Fixes FLAPL to “00H”
FLAPHC,#07H
; Sets blank check block compare number (same value as that of
; FLAPH)
MOV
FLAPLC,#0FFH
; Fixes FLAPLC to “FFH”
MOV
MOV
HALT
MOV
MOV
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
CmdStatus,A
; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
;----------------------------
;END
;----------------------------
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16.8.8 Example of byte write operation in self programming mode
An example of the byte write operation in self programming mode is explained below.
<1> Set 05H (byte write) to the flash program command register (FLCMD).
<2> Set the number of block to which data is to be written, to flash address pointer H (FLAPH).
<3> Set the address at which data is to be written, to flash address pointer L (FLAPL).
<4> Set the data to be written, to the flash write buffer register (FLW).
<5> Clear the flash status register (PFS).
<6> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note
.
<7> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<8> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <9>
Normal
→ <10>
<9> Byte write processing is abnormally terminated.
<10> Byte write processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
Caution If a write results in failure, erase the block once and write to it again.
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Figure 16-26. Example of Byte Write Operation in Self Programming Mode
Byte write
<1> Set byte write command
(FLCMD = 05H)
<2> Set no. of block to be
written, to FLAPH
<3> Set address at which data
is to be written, to FLAPL
<4> Set data to be written to FLW
<5> Clear PFS
<6> Clear & restart WDT counter
(WDTE = ACH)Note
<7> Execute HALT instruction
Abnormal
<8> Check execution result
(VCERR and WEPRERR flags)
Normal
<10> Normal termination
<9> Abnormal termination
Note This setting is not required when the watchdog timer is not used.
Remark <1> to <10> in Figure 16-26 correspond to <1> to <10> in 16.8.8 (previous page).
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An example of a program list that performs a byte write in self programming mode is shown below.
;----------------------------
;START
;----------------------------
FlashWrite:
MOV
MOV
FLCMD,#05H
FLAPH,#07H
; Sets flash control command (byte write)
; Sets address to which data is to be written, with
; FLAPH (block 7 is specified here)
MOV
MOV
FLAPL,#20H
FLW,#10H
; Sets address to which data is to be written, with
; FLAPL (address 20H is specified here)
; Sets data to be written (10H is specified here)
MOV
MOV
HALT
MOV
MOV
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
CmdStatus,A
; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
;----------------------------
;END
;----------------------------
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16.8.9 Example of internal verify operation in self programming mode
An example of the internal verify operation in self programming mode is explained below.
<1> Set 01H (internal verify) to the flash program command register (FLCMD).
<2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Sets the verify start address to flash address pointer L (FLAPL).
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Sets the verify end address to the flash address pointer L compare register (FLAPLC).
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note
.
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
Normal → <11>
<10> Internal verify processing is abnormally terminated.
<11> Internal verify processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
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Figure 16-27. Example of Internal Verify Operation in Self Programming Mode
Internal verify
<1> Set internal verify
command (FLCMD = 01H)
<2> Set no. of block for
internal verify, to FLAPH
<3> Set start address to FLAPL
<4> Set the same value as
that of FLAPH to FLAPHC
<5> Set end address to FLAPLC
<6> Clear PFS
<7> Clear & restart WDT counter
(WDTE = ACH)Note
<8> Execute HALT instruction
Abnormal
<9> Check execution result
(VCERR and WEPRERR flags)
Normal
<11> Normal termination
<10> Abnormal termination
Note This setting is not required when the watchdog timer is not used.
Remark <1> to <11> in Figure 16-27 correspond to <1> to <11> in 16.8.9 (previous page).
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An example of a program list that performs an internal verify in self programming mode is shown below.
;----------------------------
;START
;----------------------------
FlashVerify:
MOV
MOV
FLCMD,#01H
FLAPH,#07H
; Sets flash control command (internal verify)
; Sets verify start address with FLAPH (block 7 is specified
; here)
MOV
FLAPL,#00H
; Sets verify start address with FLAPL (Address 00H is
; specified here)
MOV
MOV
FLAPHC,#07H
FLAPLC,#20H
; Sets verify end address
MOV
MOV
HALT
MOV
MOV
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
CmdStatus,A
; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
;----------------------------
;END
;----------------------------
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16.8.10 Examples of operation when command execution time should be minimized in self programming
mode
Examples of operation when the command execution time should be minimized in self programming mode are
explained below.
(1) Erasure to blank check
<1> Mode is shifted from normal mode to self programming mode (<1> to <5> in 16.8.4)
<2> Execution of block erase → Error check (<1> to <11> in 16.8.6)
<3> Execution of block blank check → Error check (<1> to <11> in 16.8.7)
<4> Mode is shifted from self programming mode to normal mode (<1> to <5> in 16.8.5)
Figure 16-28. Example of Operation When Command Execution Time Should Be Minimized
(from Erasure to Blank Check)
Erasure to blank check
Figure 16-22
<1> to <5>
<1> Shift to self programming
mode
<2> Execute block erase
Figure 16-24
<1> to <11>
Abnormal
<2> Check execution result
(VCERR and WEPRERR flags)
Normal
<3> Execute block blank check
Figure 16-25
<1> to <11>
Abnormal
<3> Check execution result
(VCERR and WEPRERR flags)
Normal
Figure 16-23
<1> to <5>
<4> Shift to normal mode
Normal termination
Abnormal terminationNote
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <4> in Figure 16-28 correspond to <1> to <4> in 16.8.10 (1) above.
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An example of a program list when the command execution time (from erasure to black check) should be
minimized in self programming mode is shown below.
;---------------------------------------------------------------------
;START
;---------------------------------------------------------------------
MOV
DI
MK0,#11111111B
; Masks all interrupts
ModeOnLoop:
MOV
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#01H
FLPMC,#0FEH
FLPMC,#01H
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
; Sets self programming mode with FLPMC register control (sets
; value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOnLoop
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
FlashBlockErase:
MOV
MOV
FLCMD,#03H
FLAPH,#07H
; Sets flash control command (block erase)
; Sets number of block to be erased (block 7 is specified
; here)
MOV
MOV
FLAPL,#00H
; Fixes FLAPL to “00H”
FLAPHC,#07H
; Sets erase block compare number (same value as that of
; FLAPH)
MOV
FLAPLC,#00H
; Fixes FLAPLC to “00H”
MOV
MOV
HALT
MOV
CMP
BNZ
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
A,#00H
$StatusError
; Checks erase error
; Performs abnormal termination processing when an error
; occurs.
FlashBlockBlankCheck:
MOV
MOV
FLCMD,#04H
; Sets flash control command (block blank check)
; Sets number of block for blank check (block 7 is specified
; here)
FLAPH,#07H
FLAPL,#00H
MOV
; Fixes FLAPL to “00H”
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MOV
FLAPHC,#07H
; Sets blank check block compare number (same value as of
; FLAPH)
MOV
MOV
MOV
HALT
MOV
CMP
BNZ
FLAPLC,#0FFH
PFS,#00H
; Fixes FLAPLC to “FFH”
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
A,#00H
$StatusError
; Checks blank check error
; Performs abnormal termination processing when an error
; occurs.
ModeOffLoop:
MOV
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#00H
FLPMC,#0FFH
FLPMC,#00H
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
; Sets normal mode via FLPMC register control (sets value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOffLoop
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
MOV
EI
MK0,#INT_MK0
; Restores interrupt mask flag
BR
StatusNormal
;---------------------------------------------------------------------
;END (abnormal termination processing); Perform processing to shift to
normal mode in order to return to normal processing
;---------------------------------------------------------------------
StatusError:
;---------------------------------------------------------------------
;END (normal termination processing)
;---------------------------------------------------------------------
StatusNormal:
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(2) Write to internal verify
<1> Mode is shifted from normal mode to self programming mode (<1> to <5> in 16.8.4)
<2> Specification of source data for write
<3> Execution of byte write → Error check (<1> to <10> in 16.8.8)
<4> <3> is repeated until all data are written.
<5> Execution of internal verify → Error check (<1> to <11> in 16.8.9)
<6> Mode is shifted from self programming mode to normal mode (<1> to <5> in 16.8.5)
Figure 16-29. Example of Operation When Command Execution Time Should Be Minimized
(from Write to Internal Verify)
Write to internal verify
<1> Shift to self programming
mode
Figure 16-22
<1> to <5>
<2> Set source data for write
<3> Execute byte write command
Figure 16-26
<1> to <10>
<3> Check execution result
Abnormal
(VCERR and WEPRERR flags)
Normal
Yes
<4> All data written?
No
<5> Execute internal verify command
Figure 16-27
<1> to <11>
Abnormal
<5> Check execution result
(VCERR and WEPRERR flags)
Normal
Figure 16-23
<1> to <5>
<6> Shift to normal mode
Normal termination
Abnormal terminationNote
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <6> in Figure 16-29 correspond to <1> to <6> in 16.8.10 (2) above.
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An example of a program list when the command execution time (from write to internal verify) should be minimized
in self programming mode is shown below.
;---------------------------------------------------------------------
;START
;---------------------------------------------------------------------
MOV
DI
MK0,#11111111B
; Masks all interrupts
ModeOnLoop:
MOV
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#01H
FLPMC,#0FEH
FLPMC,#01H
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
; Sets self programming mode with FLPMC register control
; (sets value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOnLoop
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
FlashWrite:
MOVW
HL,#DataAdrTop
DE,#WriteAdr
; Sets address at which data to be written is located
; Sets address at which data is to be written
MOVW
FlashWriteLoop:
MOV
MOV
MOV
MOV
MOV
MOV
MOV
FLCMD,#05H
A,D
; Sets flash control command (byte write)
; Sets address at which data is to be written
; Sets address at which data is to be written
; Sets data to be written
FLAPH,A
A,E
FLAPL,A
A,[HL]
FLW,A
MOV
MOV
HALT
MOV
CMP
BNZ
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
A,#00H
$StatusError
; Checks write error
; Performs abnormal termination processing when an error
; occurs.
INCW
MOVW
CMPW
BNC
HL
; address at which data to be written is located + 1
AX,HL
AX,#DataAdrBtm
$FlashVerify
; Performs internal verify processing
; if write of all data is completed
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INCW
BR
DE
; Address at which data is to be written + 1
FlashWriteLoop
FlashVerify:
MOVW
HL,#WriteAdr
; Sets verify address
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
FLCMD,#01H
A,H
; Sets flash control command (internal verify)
; Sets verify start address
; Sets verify start address
; Sets verify end address
FLAPH,A
A,L
FLAPL,A
A,D
FLAPHC,A
A,E
FLAPLC,A
; Sets verify end address
MOV
MOV
HALT
MOV
CMP
BNZ
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
A,#00H
$StatusError
; Checks internal verify error
; Performs abnormal termination processing when an error
; occurs.
ModeOffLoop:
MOV
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#00H
FLPMC,#0FFH
FLPMC,#00H
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
; Sets normal mode via FLPMC register control (sets value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOffLoop
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
MOV
EI
MK0,#INT_MK0
; Restores interrupt mask flag
BR
StatusNormal
;---------------------------------------------------------------------
;END (abnormal termination processing); Perform processing to shift to
normal mode in order to return to normal processing
;---------------------------------------------------------------------
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StatusError:
;---------------------------------------------------------------------
;END (normal termination processing)
;---------------------------------------------------------------------
StatusNormal:
;---------------------------------------------------------------------
; Data to be written
;---------------------------------------------------------------------
DataAdrTop:
DB
DB
DB
DB
XXH
XXH
XXH
XXH
:
:
DB
XXH
DataAdrBtm:
;---------------------------------------------------------------------
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16.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode
Examples of operation when the interrupt-disabled time should be minimized in self programming mode are
explained below.
(1) Erasure to blank check
<1> Specification of block erase command (<1> to <5> in 16.8.6)
<2> Mode is shifted from normal mode to self programming mode (<1> to <5> in 16.8.4)
<3> Execution of block erase command → Error check (<6> to <11> in 16.8.6)
<4> Mode is shifted from self programming mode to normal mode (<1> to <5> in 16.8.5)
<5> Specification of block blank check command (<1> to <5> in 16.8.7)
<6> Mode is shifted from normal mode to self programming mode (<1> to <5> in 16.8.4)
<7> Execution of block blank check command → Error check (<6> to <11> in 16.8.7)
<8> Mode is shifted from self programming mode to normal mode (<1> to <5> in 16.8.5)
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Figure 16-30. Example of Operation When Interrupt-Disabled Time Should Be Minimized
(from Erasure to Blank Check)
Erasure to blank check
Figure 16-24
<1> to <5>
<1> Specify block erase command
<2> Shift to self programming
mode
Figure 16-22
<1> to <5>
<3> Execute block erase command
Figure 16-24
<6> to <11>
Abnormal
<3> Check execution result
(VCERR and WEPRERR flags)
Normal
Figure 16-23
<1> to <5>
<4> Shift to normal mode
<5> Specify block blank
check command
Figure 16-25
<1> to <5>
<6> Shift to self programming
mode
Figure 16-22
<1> to <5>
<7> Execute block blank
check command
Figure 16-25
<6> to <11>
<7> Check execution result
Abnormal
(VCERR and WEPRERR flags)
Normal
Figure 16-23
<1> to <5>
<8> Shift to normal mode
Normal termination
Abnormal terminationNote
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <8> in Figure 16-30 correspond to <1> to <8> in 16.8.11 (1) (previous page).
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An example of a program list when the interrupt-disabled time (from erasure to blank check) should be minimized
in self programming mode is shown below.
;---------------------------------------------------------------------
;START
;---------------------------------------------------------------------
FlashBlockErase:
; Sets erase command
MOV
MOV
MOV
MOV
MOV
FLCMD,#03H
FLAPH,#07H
FLAPL,#00H
FLAPHC,#07H
FLAPLC,#00H
; Sets flash control command (block erase)
; Sets number of block to be erased (block 7 is specified here)
; Fixes FLAPL to “00H”
; Sets erase block compare number (same value as that of FLAPH)
; Fixes FLAPLC to “00H”
CALL
!ModeOn
; Shift to self programming mode
; Execution of erase command
MOV
MOV
HALT
MOV
CMP
BNZ
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
A,#00H
$StatusError
; Checks erase error
; Performs abnormal termination processing when an error
; occurs.
CALL
!ModeOff
; Shift to normal mode
; Sets blank check command
MOV
MOV
MOV
MOV
FLCMD,#04H
FLAPH,#07H
FLAPL,#00H
FLAPHC,#07H
; Sets flash control command (block blank check)
; Sets block number for blank check (block 7 is specified here)
; Fixes FLAPL to “00H”
; Sets blank check block compare number (same value as that of
; FLAPH)
MOV
FLAPLC,#0FFH
!ModeOn
; Fixes FLAPLC to “FFH”
CALL
; Shift to self programming mode
; Execution of blank check command
MOV
MOV
HALT
MOV
CMP
BNZ
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
A,#00H
$StatusError
; Checks blank check error
; Performs abnormal termination processing when an error occurs
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CALL
BR
!ModeOff
; Shift to normal mode
StatusNormal
;---------------------------------------------------------------------
;END (abnormal termination processing); Perform processing to shift to
normal mode in order to return to normal processing
;---------------------------------------------------------------------
StatusError:
;---------------------------------------------------------------------
;END (normal termination processing)
;---------------------------------------------------------------------
StatusNormal:
;---------------------------------------------------------------------
;Processing to shift to self programming mode
;---------------------------------------------------------------------
ModeOn:
MOV
MK0,#11111111B
; Masks all interrupts
DI
ModeOnLoop:
MOV
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#01H
FLPMC,#0FEH
FLPMC,#01H
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
; Sets self programming mode via FLPMC register control (sets
; value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOnLoop
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
RET
;---------------------------------------------------------------------
; Processing to shift to normal mode
;---------------------------------------------------------------------
ModeOff:
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#00H
FLPMC,#0FFH
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
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MOV
FLPMC,#00H
; Sets normal mode via FLPMC register control (sets value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOff
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
MOV
EI
MK0,#INT_MK0
; Restores interrupt mask flag
RET
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(2) Write to internal verify
<1> Specification of source data for write
<2> Specification of byte write command (<1> to <4> in 16.8.8)
<3> Mode is shifted from normal mode to self programming mode (<1> to <5> in 16.8.4)
<4> Execution of byte write command → Error check (<5> to <10> in 16.8.8)
<5> Mode is shifted from self programming mode to normal mode (<1> to <5> in 16.8.5)
<6> <2> to <5> is repeated until all data are written.
<7> The internal verify command is specified (<1> to <5> in 16.8.9)
<8> Mode is shifted from normal mode to self programming mode (<1> to <5> in 16.8.4)
<9> Execution of internal verify command → Error check (<6> to <11> in 16.8.9)
<10> Mode is shifted from self programming mode to normal mode (<1> to <5> in 16.8.5)
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Figure 16-31. Example of Operation When Interrupt-Disabled Time Should Be Minimized
(from Write to Internal Verify)
Write to internal verify
<1> Set source data for write
Figure 16-26
<1> to <4>
<2> Specify byte write command
<3> Shift to self programming
mode
Figure 16-22
<1> to <5>
<4> Execute byte write command
Figure 16-26
<5> to <10>
Abnormal
<4> Check execution result
(VCERR and WEPRERR flags)
Normal
Figure 16-23
<1> to <5>
<5> Shift to normal mode
Yes
<6> All data written?
No
Figure 16-27
<1> to <5>
<7> Specify internal verify command
<8> Shift to self programming
mode
Figure 16-22
<1> to <5>
<9> Execute internal verify command
Figure 16-27
<6> to <10>
<9> Check execution result
Abnormal
(VCERR and WEPRERR flags)
Normal
Figure 16-23
<1> to <5>
<10> Shift to normal mode
Normal termination
Abnormal terminationNote
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <10> in Figure 16-31 correspond to <1> to <10> in 16.8.11 (2) (previous page).
Preliminary User’s Manual U16994EJ2V0UD
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CHAPTER 16 FLASH MEMORY
An example of a program list when the interrupt-disabled time (from write to internal verify) should be minimized in
self programming mode is shown below.
;---------------------------------------------------------------------
;START
;---------------------------------------------------------------------
; Sets write command
FlashWrite:
MOVW
MOVW
HL,#DataAdrTop ; Sets address at which data to be written is located
DE,#WriteAdr
; Sets address at which data is to be written
FlashWriteLoop:
MOV
MOV
MOV
MOV
MOV
MOV
MOV
FLCMD,#05H
A,D
; Sets flash control command (byte write)
; Sets address at which data is to be written
; Sets address at which data is to be written
; Sets data to be written
FLAPH,A
A,E
FLAPL,A
A,[HL]
FLW,A
CALL
!ModeOn
; Shift to self programming mode
; Execution of write command
MOV
MOV
HALT
MOV
CMP
BNZ
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
A,#00H
$StatusError
; Checks write error
; Performs abnormal termination processing when an error
; occurs.
CALL
MOV
EI
!ModeOff
; Shift to normal mode
MK0,#INT_MK0
; Restores interrupt mask flag
; Judgment of writing all data
INCW
MOVW
CMPW
BNC
HL
; Address at which data to be written is located + 1
AX,HL
AX,#DataAdrBtm ; Performs internal verify processing
$FlashVerify
; if write of all data is completed
INCW
BR
DE
; Address at which data is to be written + 1
FlashWriteLoop
; Setting internal verify command
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FlashVerify:
MOVW
HL,#WriteAdr
; Sets verify address
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
FLCMD,#01H
A,H
; Sets flash control command (internal verify)
; Sets verify start address
; Sets verify start address
; Sets verify end address
FLAPH,A
A,L
FLAPL,A
A,D
FLAPHC,A
A,E
FLAPLC,A
; Sets verify end address
CALL
!ModeOn
; Shift to self programming mode
; Execution of internal verify command
MOV
MOV
HALT
MOV
CMP
BNZ
PFS,#00H
; Clears flash status register
; Clears & restarts WDT
WDTE,#0ACH
; Self programming is started
A,PFS
A,#00H
$StatusError
; Checks internal verify error
; Performs abnormal termination processing when an error occurs
CALL
BR
!ModeOff
; Shift to normal mode
StatusNormal
;---------------------------------------------------------------------
;END (abnormal termination processing); Perform processing to shift to
normal mode in order to return to normal processing
;---------------------------------------------------------------------
StatusError:
;---------------------------------------------------------------------
;END (normal termination processing)
;---------------------------------------------------------------------
StatusNormal:
;---------------------------------------------------------------------
;Processing to shift to self programming mode
;---------------------------------------------------------------------
ModeOn:
MOV
MK0,#11111111B ; Masks all interrupts
DI
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ModeOnLoop:
MOV
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#01H
FLPMC,#0FEH
FLPMC,#01H
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
; Sets self programming mode via FLPMC register control (sets
; value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOnLoop
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
RET
;---------------------------------------------------------------------
; Processing to shift to normal mode
;---------------------------------------------------------------------
ModeOff:
MOV
MOV
MOV
MOV
MOV
PFS,#00H
PFCMD,#0A5H
FLPMC,#00H
FLPMC,#0FFH
FLPMC,#00H
; PFCMD register control
; FLPMC register control (sets value)
; FLPMC register control (inverts set value)
; Sets normal mode via FLPMC register control (sets value)
MOV
CMP
BNZ
A,PFS
A,#00H
$ModeOff
; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
MOV
EI
MK0,#INT_MK0
; Restores interrupt mask flag
RET
;---------------------------------------------------------------------
;Data to be written
;---------------------------------------------------------------------
DataAdrTop:
DB
DB
DB
DB
XXH
XXH
XXH
XXH
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CHAPTER 16 FLASH MEMORY
:
:
DB
XXH
DataAdrBtm:
;---------------------------------------------------------------------
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CHAPTER 17 INSTRUCTION SET OVERVIEW
This chapter lists the instruction set of the 78K0S/KU1+ and 78K0S/KY1+. For details of the operation and
machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual
(U11047E).
17.1 Operation
17.1.1 Operand identifiers and description methods
Operands are described in “Operand” column of each instruction in accordance with the description method of the
instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are
described as they are. Each symbol has the following meaning.
• #:
• !:
Immediate data specification
Absolute address specification
Relative address specification
• $:
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 17-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
rp
sfr
saddr
FE20H to FF1FH Immediate data or labels
saddrp
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark For symbols of special function registers, see Table 3-3 Special Function Registers.
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17.1.2 Description of “Operation” column
A:
A register; 8-bit accumulator
X:
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
PSW:
CY:
AC:
Z:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
Program status word
Carry flag
Auxiliary carry flag
Zero flag
IE:
( ):
×H, ×L:
∧:
Interrupt request enable flag
Memory contents indicated by address or register contents in parentheses
Higher 8 bits and lower 8 bits of 16-bit register
Logical product (AND)
∨:
Logical sum (OR)
∨:
Exclusive logical sum (exclusive OR)
Inverted data
:
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
17.1.3 Description of “Flag” column
(Blank): Unchanged
0:
1:
×:
R:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is stored
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CHAPTER 17 INSTRUCTION SET OVERVIEW
17.2 Operation List
Mnemonic
Operand
Bytes Clocks
Operation
Flag
Z
AC CY
MOV
r, #byte
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
r ← byte
saddr, #byte
sfr, #byte
A, r
(saddr) ← byte
sfr ← byte
A ← r
Note 1
Note 1
r, A
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
×
×
×
×
×
×
[DE], A
A, [HL]
[HL], A
(HL) ← A
A, [HL + byte]
[HL + byte], A
A, X
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
XCH
Note 2
A, r
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ sfr
A, [DE]
A ↔ (DE)
A ↔ (HL)
A, [HL]
A, [HL, byte]
A ↔ (HL + byte)
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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CHAPTER 17 INSTRUCTION SET OVERVIEW
Mnemonic
MOVW
Operand
Bytes Clocks
Operation
Flag
Z
AC CY
rp, #word
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
rp ← word
AX, saddrp
saddrp, AX
AX, rp
AX ← (saddrp)
(saddrp) ← AX
Note
Note
Note
AX ← rp
rp, AX
rp ← AX
XCHW
ADD
AX, rp
AX ↔ rp
A, #byte
saddr, #byte
A, r
A, CY ← A + byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
ADDC
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
SUB
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, [HL + byte]
A, CY ← A − (HL + byte)
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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Mnemonic
SUBC
Operand
Bytes Clocks
Operation
Flag
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A ← A ∧ byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
AND
saddr, #byte
A, r
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
A, saddr
A, !addr16
A, [HL]
A ← A ∧ (saddr)
A ← A ∧ (addr16)
A ← A ∧ (HL)
A, [HL + byte]
A, #byte
A ← A ∧ (HL + byte)
A ← A ∨ byte
OR
saddr, #byte
A, r
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A, [HL + byte]
A, #byte
A ← A ∨ (HL + byte)
A ← A ∨ byte
XOR
saddr, #byte
A, r
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A, [HL + byte]
A ← A ∨ (HL + byte)
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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Mnemonic
CMP
Operand
Bytes Clocks
Operation
Flag
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
A, #byte
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
10
6
6
4
6
10
2
2
2
A − byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
(saddr) − byte
A − r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
A − (saddr)
A − (addr16)
A − (HL)
A − (HL + byte)
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
ADDW
SUBW
CMPW
INC
r ← r + 1
saddr
r
(saddr) ← (saddr) + 1
r ← r − 1
DEC
saddr
rp
(saddr) ← (saddr) − 1
rp ← rp + 1
INCW
DECW
ROR
rp
rp ← rp − 1
A, 1
(CY, A7 ← A0, Am−1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
(saddr.bit) ← 1
sfr.bit ← 1
×
×
×
×
ROL
A, 1
RORC
ROLC
SET1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
A.bit ← 1
PSW.bit
[HL].bit
saddr.bit
sfr.bit
PSW.bit ← 1
×
×
×
×
×
×
(HL).bit ← 1
CLR1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit
A.bit ← 0
PSW.bit
[HL].bit
CY
PSW.bit ← 0
(HL).bit ← 0
SET1
CLR1
NOT1
CY ← 1
1
0
×
CY
CY ← 0
CY
CY ← CY
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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Mnemonic
Operand
Bytes Clocks
Operation
Flag
Z
AC CY
CALL
!addr16
[addr5]
3
1
6
8
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI
PCH ← (SP + 1), PCL ← (SP),
R
R
R
R
R
R
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
PUSH
POP
PSW
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
2
4
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW ← (SP), SP ← SP + 1
rp
PSW
4
rp
6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP ← AX
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
8
6
AX ← SP
6
PC ← addr16
6
PC ← PC + 2 + jdisp8
6
PCH ← A, PCL ← X
BC
$saddr16
$saddr16
$saddr16
$saddr16
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
BNC
BZ
6
6
BNZ
BT
6
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
10
10
8
10
10
10
8
BF
10
6
DBNZ
C, $addr16
6
saddr, $addr16
8
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
Set HALT Mode
DI
HALT
STOP
Set STOP Mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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17.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
#byte
A
r
sfr
saddr !addr16 PSW
[DE]
[HL]
$addr16
1
None
[HL + byte]
A
ADD
ADDC
SUB
SUBC
AND
OR
MOVNote MOV
XCHNote XCH
ADD
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROR
ROL
ADD
ADDC
SUB
SUBC
AND
OR
RORC
ROLC
ADDC
SUB
SUBC
XOR
CMP
AND
OR
XOR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
CMP
r
MOV
MOV
INC
DEC
B, C
sfr
DBNZ
DBNZ
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
MOV
MOV
[HL]
[HL + byte]
Note Except r = A.
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(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
AX
rpNote
saddrp
SP
None
AX
ADDW SUBW
CMPW
MOVW
XCHW
MOVW
MOVW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
saddrp
sp
MOVW
MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
$addr16
None
1st Operand
A.bit
BT
BF
SET1
CLR1
sfr.bit
BT
BF
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BT
BF
SET1
CLR1
BT
BF
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
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(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX
!addr16
[addr5]
$addr16
Basic instructions
BR
CALL
BR
CALLT
BR
BC
BNC
BZ
BNZ
Compound instructions
DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
These specifications are only target values, and may not be satisfied by mass-produced products.
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
P20 to P23, P32, P34, P40 to P47Note 1
Per pin
Ratings
−0.3 to +6.5
Unit
V
VDD
VSS
VI
−0.3 to +0.3
V
Input voltage
−0.3 to VDD + 0.3Note 2
−0.3 to VDD + 0.3Note 2
−0.3 to VDD + 0.3Note 2
−10
V
Output voltage
VO
VAN
IOH
V
Analog input voltage
Output current, high
V
mA
mA
Total of all pins
P20 to P23, P32,
−44
P40 to P47Note 1
Output current, low
IOL
Per pin
20
44
mA
mA
Total of all pins
P20 to P23, P32,
P40 to P47Note 1
Operating ambient
temperature
TA
In normal operation mode
−40 to +85
°C
°C
°C
During flash memory programming
Storage temperature
Tstg
−40 to +125
Notes 1. The P40 to P47 pins are provided only in the 78K0S/KY1+.
2. Must be 6.5 V or lower
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
X1 Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1
)
Resonator Recommended Circuit
Parameter
Conditions
MIN.
1
TYP. MAX.
10.0
Unit
VSS X1
X2
Ceramic
Oscillation
frequency (fX)Note 2
MHz
resonator
C1
C2
C2
V
SS X1
X2
Crystal
Oscillation
frequency (fX)Note 2
1
10.0
MHz
resonator
C1
External
clock
X1 input
2.7 V ≤ VDD ≤ 5.5 V
1
1
10.0
5.0
MHz
X1
frequency (fX)Note 2
2.0 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
X1 input high-
/low-level width
(tXH, tXL)
0.045
0.5
µs
2.0 V ≤ VDD < 2.7 V
0.09
1.0
Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on
clear (POC) circuit is 2.1 V 0.1 V.
2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above
figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
High-Speed Ring-OSC Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1
)
Resonator
Parameter
Conditions
2.7 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 2.7 V
MIN.
7.60
TYP. MAX.
Unit
MHz
MHz
On-chip high-speed Ring-OSC
Oscillation frequency (fX)Note 2
8.00
8.40
T.B.D
Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on
clear (POC) circuit is 2.1 V 0.1 V.
2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Low-Speed Ring-OSC Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote
)
Resonator
Parameter
Conditions
MIN.
120
TYP. MAX.
240 480
Unit
kHz
On-chip low-speed Ring-OSC
Oscillation frequency (fRL)
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear
(POC) circuit is 2.1 V 0.1 V.
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
DC Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote) (1/2)
Parameter
Symbol
Conditions
Per pin
Total
MIN.
TYP.
MAX.
–5
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
Output current, high
IOH1
Pins other than
P20 to P23
2.0 V ≤ VDD ≤ 5.5 V
4.0 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 4.0 V
2.0 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD ≤ 5.5 V
4.0 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 4.0 V
–25
–15
–5
IOH2
P20 to P23
Per pin
Total
–15
10
Output current, low
Input voltage, high
IOL
Per pin
Total of all pins
30
15
VIH1
VIH2
VIL1
VIL2
VOH1
P23 in external clock mode and pins other than
P20 and P21
0.8VDD
0.7VDD
0
VDD
P23 in other than external clock mode, P20 and
P21
VDD
V
V
V
V
Input voltage, low
P23 in external clock mode and pins other than
P20 and P21
0.2VDD
0.3VDD
P23 in other than external clock mode, P20 and
P21
0
Output voltage, high
Total of output pins other 4.0 V ≤ VDD ≤ 5.5 V
VDD – 1.0
than P20 to P23
IOH1 = –15 mA
IOH1 = –5 mA
IOH1 = –100 µA
2.0 V ≤ VDD < 4.0 V
VDD – 0.5
VDD – 1.0
V
V
VOH2
Total of pins P20 to P23
IOH2 = –10 mA
4.0 V ≤ VDD ≤ 5.5 V
IOH2 = –5 mA
2.0 V ≤ VDD < 4.0 V
IOH2 = –5 mA
VDD – 0.5
V
V
Output voltage, low
VOL
Total of output pins
IOL = 30 mA
4.0 V ≤ VDD ≤ 5.5 V
1.3
0.4
IOL = 10 mA
2.0 V ≤ VDD < 4.0 V
IOL = 400 µA
V
Input leakage current, high
Input leakage current, low
ILIH
ILIL
VI = VDD
VI = 0 V
VO = VDD
Pins other than X1
Pins other than X1
3
–3
3
µA
µA
µA
Output leakage current, high ILOH
Pins other than X2
Pins other than X2
Output leakage current, low
Pull-up resistance value
Pull-down resistance value
ILOL
RPU
RPD
VO = 0 V
VI = 0 V
–3
µA
kΩ
kΩ
10
10
30
30
100
100
P22, P23 reset status
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on clear
(POC) circuit is 2.1 V 0.1 V.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
DC Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1) (2/2)
Parameter
Supply
currentNote 2
Symbol
Conditions
MIN. TYP. MAX. Unit
6.1 12.2 mA
7.6 15.2
Note 3
IDD1
Crystal/ceramic fX = 10 MHz
When A/D converter is stopped
When A/D converter is operating
When A/D converter is stopped
When A/D converter is operating
When A/D converter is stopped
When A/D converter is operating
When peripheral functions are stopped
When peripheral functions are operating
When peripheral functions are stopped
When peripheral functions are operating
When peripheral functions are stopped
When peripheral functions are operating
When A/D converter is stopped
When A/D converter is operating
oscillation,
VDD = 5.0 V 10%Note 4
external clock
input oscillation
operating
fX = 6 MHz
5.5 11.0 mA
14.0
VDD = 5.0 V 10%Note 4
modeNote 6
fX = 5 MHz
3.0
4.5
1.7
6.0
9.0
3.8
6.7
3.0
6.0
1
mA
mA
mA
mA
VDD = 3.0 V 10%Note 5
IDD2
Crystal/ceramic fX = 10 MHz
oscillation,
external clock
input HALT
modeNote 6
VDD = 5.0 V 10%Note 4
fX = 6 MHz
1.3
VDD = 5.0 V 10%Note 4
fX = 5 MHz
0.48
VDD = 3.0 V 10%Note 5
2.1
IDD3
High-speed
Ring-OSC
operation
modeNote 7
fX = 8 MHz
5.5 11.0 mA
7.0 14.0
VDD = 5.0 V 10%Note 4
IDD4
High-speed
fX = 8 MHz
When peripheral functions are stopped
When peripheral functions are operating
1.4
3.2
5.9
mA
Ring-OSC HALT VDD = 5.0 V 10%Note 4
modeNote 7
IDD5
STOP mode
VDD = 5.0 V 10%
When low-speed Ring-OSC is stopped
When low-speed Ring-OSC is operating
When low-speed Ring-OSC is stopped
When low-speed Ring-OSC is operating
3.5 35.5 µA
17.5 63.5
VDD = 3.0 V 10%
3.5 15.5 µA
11.0 30.5
Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on
clear (POC) circuit is 2.1 V 0.1 V.
2. Total current flowing through the internal power supply (VDD). However, the current that flows through the
pull-up resistors of ports is not included.
3. IDD1 includes peripheral operation current.
4. When the processor clock control register (PCC) is set to 00H.
5. When the processor clock control register (PCC) is set to 02H.
6. When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using
the option byte.
7. When high-speed Ring-OSC clock is selected as the system clock source using the option byte.
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
AC Characteristics
Basic operation (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1
)
Parameter
Symbol
TCY
Conditions
MIN.
0.2
TYP.
MAX.
16
Unit
µs
µs
µs
µs
µs
µs
µs
µs
Cycle time (minimum
Crystal/ceramic oscillation
4.0 V ≤ VDD ≤ 5.5 V
3.0 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 3.0 V
2.0 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
2.0 V ≤ VDD < 2.7 V
instruction execution time)
clock, external clock input
0.33
0.4
16
16
1
16
High-speed Ring-OSC
clock
0.23
0.47
0.95
4.22
4.22
4.22
TI000 input high-level width, tTIH,
4.0 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 4.0 V
2/fsam+
0.1Note 2
low-level width
tTIL
2/fsam+
0.2Note 2
µs
µs
Interrupt input high-level
width, low-level width
tINTH,
tINTL
tRSL
1
RESET input low-level
width
2
µs
Notes1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on
clear (POC) circuit is 2.1 V 0.1 V.
2. Selection of fsam = fXP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler
mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP.
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
TCY vs. VDD (Crystal/Ceramic Oscillation Clock, External Clock Input)
60
16
10
µ
Guaranteed
operation range
1.0
0.4
0.33
0.1
1
2
3
4
5
6
2.7
Supply voltage VDD [V]
5.5
TCY vs. VDD (High-speed Ring-OSC Clock)
60
10
µ
4.22
Guaranteed
operation range
1.0
0.95
0.47
0.23
0.1
1
2
3
4
5
6
2.7
Supply voltage VDD [V]
5.5
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
AC Timing Test Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Clock Timing
1/fX
t
XL
tXH
X1 input
TI000 Timing
tTIL0
tTIH0
TI000
Interrupt Input Timing
t
INTL
tINTH
INTP0, INTP1
RESET Input Timing
tRSL
RESET
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
A/D Converter Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 VNote 1, VSS = 0 VNote 2
)
(1) A/D converter basic characteristics
Parameter
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
µs
µs
µs
µs
V
Resolution
Conversion time
tCONV
4.5 V ≤ VDD ≤ 5.5 V
4.0 V ≤ VDD < 4.5 V
2.85 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 2.85 V
3.0
100
100
100
100
VDD
4.8
6.0
14.0
Note 2
VSS
Analog input voltage
VAIN
(2) A/D Converter Characteristics (High-speed Ring-OSC Clock)
Parameter
Overall errorNotes 3, 4
Zero-scale errorNotes 3, 4
Symbol
AINL
Ezs
Conditions
MIN.
TYP.
MAX.
Unit
−0.1 to +0.2Note 5 -0.35 to +0.45 %FSR
−0.1 to +0.2Note 5 -0.35 to +0.45 %FSR
−0.1 to +0.2Note 5 -0.35 to +0.40 %FSR
Full-scale errorNotes 3, 4
Efs
Integral non-linearity errorNote 3
Differential non-linearity errorNote 3
ILE
1Note 5
1Note 5
3
LSB
LSB
DLE
1.5
(3) A/D Converter Characteristics (Crystal/Ceramic Oscillation Clock, External Clock)
Parameter
Overall errorNotes 1, 2
Symbol
AINL
Conditions
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
MIN.
TYP.
MAX.
Unit
−
−
−
−
−
−
0.15 to +0.40Note 5 −0.35 to +0.65 %FSR
0.15 to +0.30Note 5 −0.35 to +0.55 %FSR
0.15 to +0.40Note 5 −0.35 to +0.65 %FSR
0.15 to +0.30Note 5 −0.35 to +0.55 %FSR
0.15 to +0.30Note 5 −0.35 to +0.55 %FSR
0.15 to +0.30Note 5 −0.35 to +0.50 %FSR
Zero-scale errorNotes 3, 4
Ezs
Efs
Full-scale errorNotes 3, 4
Integral non-linearity errorNote 3
Differential non-linearity errorNote 3
ILE
DLE
1.5Note 5
1.5Note 5
1.0Note 5
1.0Note 5
3.0
4.0
2.5
2.5
LSB
LSB
LSB
LSB
Notes 1. In the 78K0S/KU1+ and 78K0S/KY1+, VDD functions alternately as the A/D converter reference voltage
input. When using the A/D converter, stabilize VDD at the supply voltage used (2.7 to 5.5 V).
2. In the 78K0S/KU1+ and 78K0S/KY1+, VSS functions alternately as the ground potential of the A/D
converter. Be sure to connect VSS to a stabilized GND (= 0 V).
3. Excludes quantization error ( 1/2 LSB).
4. This value is indicated as a ratio (%FSR) to the full-scale value.
5. A value when HALT mode is set by an instruction immediately after A/D conversion starts.
Caution The conversion accuracy may be degraded if the level of a port that is not used for A/D conversion is
changed during A/D conversion.
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
POC Circuit Characteristics (TA = −40 to +85°C)
Parameter
Detection voltage
Symbol
VPOC
Conditions
MIN.
2.0
TYP.
2.1
MAX.
2.2
Unit
V
Power supply rise time
tPTH
VDD: 0 V → 2.1 V
1.5
µs
Response delay time 1Note 1
tPTHD
When power supply rises, after reaching
detection voltage (MAX.)
3.0
1.0
ms
Response delay time 2Note 2
Minimum pulse width
tPD
ms
ms
When power supply falls
tPW
0.2
Note1. Time required from voltage detection to internal reset release.
2. Time required from voltage detection to internal reset signal generation.
POC Circuit Timing
Supply voltage
(VDD
)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
t
PW
t
PTH
tPTHD
t
PD
Time
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
LVI Circuit Characteristics (TA = −40 to +85°C)
Parameter
Detection voltage
Symbol
VLVI0
VLVI1
VLVI2
VLVI3
VLVI4
VLVI5
VLVI6
VLVI7
VLVI8
VLVI9
tLD
Conditions
MIN.
4.1
TYP.
4.3
MAX.
4.5
Unit
V
3.9
4.1
4.3
V
3.7
3.9
4.1
V
3.5
3.7
3.9
V
3.3
3.5
3.7
V
3.15
2.95
2.7
3.3
3.45
3.25
3.0
V
3.1
V
2.85
2.6
V
2.5
2.7
V
2.25
2.35
0.2
2.45
2.0
V
Response timeNote 1
ms
ms
ms
Minimum pulse width
tLW
0.2
Operation stabilization wait timeNote 2 tLWAIT
0.1
0.2
Notes 1. Time required from voltage detection to interrupt output or internal reset signal generation.
2. Time required from setting LVION to 1 to operation stabilization.
Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9
2. VPOC < VLVIm (m = 0 to 9)
LVI Circuit Timing
Supply voltage
(VDD
)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
tLW
tLWAIT
tLD
LVION
1
Time
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter
Symbol
VDDDR
tSREL
Conditions
MIN.
2.0
0
TYP.
MAX.
5.5
Unit
V
Data retention supply voltage
Release signal set time
µs
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CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Flash Memory Programming Characteristics (TA = –40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
IDD
Conditions
MIN.
TYP.
MAX.
7.0
Unit
Supply current
VDD = 5.5 V
mA
Erasure countNote
(per 1 block)
NERASE
TA = −10 to +85°C
TA = −40 to +85°C
1000
Times
T.B.D.
Times
Chip erase time
TCERASE
TA = −10 to +85°C,
NERASE ≤ 100
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
4.5 V ≤ VDD ≤ 5.5 V
3.5 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.5 V
0.90
1.00
s
s
1.20
s
TA = −10 to +85°C,
NERASE ≤ 1000
3.52
s
3.92
s
4.69
s
TA = −40 to +85°C,
NERASE ≤ 100
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
0.48
s
s
s
TA = −40 to +85°C,
NERASE ≤ 1000
s
s
s
Block erase time
TBERASE
TA = −10 to +85°C,
NERASE ≤ 100
s
0.53
s
0.63
s
TA = −10 to +85°C,
NERASE ≤ 1000
1.86
s
2.07
s
2.48
s
s
TA = −40 to +85°C,
NERASE ≤ 100
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
150
s
s
TA = −40 to +85°C,
NERASE ≤ 1000
s
s
s
Byte write time
Internal verify
TWRITE
TVERIFY
TBLKCHK
TA = −10 to +85°C, NERASE ≤ 1000
TA = −40 to +85°C, NERASE ≤ 1000
Per 1 block
µs
µs
ms
µs
µs
Years
Years
T.B.D.
6.8
Per 1 byte
27
Blank check
Per 1 block
480
Retention years
TA = −10 to +85°C, NERASE ≤ 1000
TA = −40 to +85°C, NERASE ≤ 1000
10
T.B.D.
Note Depending on the erasure count (NERASE), the erase time varies. Refer to the chip erase time and block erase
time parameters.
Remark When a product is first written after shipment, “erase → write” and “write only” are both taken as one rewrite.
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CHAPTER 19 PACKAGE DRAWING
19.1 Package drawing of the 78K0S/KU1+
8-PIN PLASTIC SOP (5.72 mm (225))
8
5
detail of lead end
P
1
4
A
H
I
F
J
G
S
B
L
N
S
C
K
M
D
M
E
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
+0.17
5.2
A
−0.20
B
C
0.78 MAX.
1.27 (T.P.)
+0.08
0.42
D
−0.07
E
F
G
H
I
0.1 0.1
1.59 0.21
1.49
6.5 0.3
4.4 0.15
1.1 0.2
J
+0.08
0.17
K
−0.07
L
M
N
0.6 0.2
0.12
0.10
+7°
3°
P
−3°
S8GM-50-225B-6
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CHAPTER 19 PACKAGE DRAWING
19.2 Package drawing of the 78K0S/KY1+
16-PIN PLASTIC SSOP (5.72 mm (225))
16
9
detail of lead end
P
1
8
A
H
I
F
G
J
S
C
B
L
N
S
M
D
M
K
E
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
H
I
5.2 0.3
0.475 MAX.
0.65 (T.P.)
0.22 0.08
0.125 0.075
1.565 0.235
1.44
6.2 0.3
4.4 0.2
J
0.9 0.2
+0.08
0.17
K
−0.07
L
M
N
P
0.5 0.2
0.10
0.10
5° 5°
P16GM-65-225B-5
287
Preliminary User’s Manual U16898EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the 78K0S/KU1+ and
78K0S/KY1+. Figure A-1 shows development tools.
• Compatibility with PC98-NX series
Unless stated otherwise, products which are supported by IBM PC/ATTM and compatibles can also be used with
the PC98-NX series. When using the PC98-NX series, therefore, refer to the explanations for IBM PC/AT and
compatibles.
• WindowsTM
Unless stated otherwise, “Windows” refers to the following operating systems.
•
•
•
•
Windows 98
Windows NTTM Ver. 4.0
Windows 2000
Windows XP
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tools (1/2)
(1) When using the in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A
Software package
• Software package
Language processing software
Debugging software
• Assembler package
• C compiler package
• Device file
• Integrated debugger
• System simulator
• C library source fileNote 1
Control software
• Project Manager
(Windows version only)Note 2
Host machine
Interface adapter
Power supply unit
Flash memory writing environment
Flash programmer
In-circuit emulatorNote 3
Emulation boardNote 4
Flash memory
writing adapter
Flash memory
Target cable
Pin header
Target system
Notes 1. The C library source file is not included in the software package.
2. The Project Manager PM plus is included in the assembler package.
PM plus is used only in the Windows environment.
3. All products other than the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A are optional.
4. The in-circuit emulator IE-789234-NS-EM1 is provided with the target cable.
289
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tools (2/2)
(2) When using the in-circuit emulator QB-78K0SKX1MINI
Software package
• Software package
Language processing software
Debugging software
• Assembler package
• C compiler package
• Device file
• Integrated debugger
• System simulator
• C library source fileNote 1
Control software
• Project Manager
(Windows version only)Note 2
Host machine
Power supply unit
Flash memory writing environment
Flash programmer
In-circuit emulatorNote 3
QB-78K0SMINI
Debug adapter
Flash memory
writing adapter
Flash memory
Target cable or emulation probe
Pin header
Target system
Notes 1. The C library source file is not included in the software package.
2. The Project Manager PM plus is included in the assembler package.
PM plus is used only in the Windows environment.
3. The in-circuit emulator QB-78K0SKX1MINI is provided with the integrated debugger ID78K0S-QB, the
flash memory programmer PG-FPL2, a power supply unit, and a target cable. Other products are
optional.
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APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0S
This is a package that bundles the software tools required for development of the 78K/0S Series.
The following tools are included.
RA78K0S, CC78K0S, ID78K0S-NS, SM+ for 78K0SNote 1, SM78K0SNotes 2, and device files
Software package
Part number: µS××××SP78K0S
Notes 1. SM+ for 78K0S is not included in SP78K0S Ver. 2.00 or earlier.
2. The SM78K0S does not support the 78K0S/Kx1+.
3. The DF789234 is not included in SP78K0S Ver. 2.00 or earlier.
Remark ×××× in the part number differs depending on the operating system to be used.
µS××××SP78K0S
××××
AB17
BB17
Host Machine
OS
Supply Medium
CD-ROM
PC-9800 series, IBM PC/AT
and compatibles
Japanese Windows
English Windows
A.2 Language Processing Software
RA78K0S
Program that converts program written in mnemonic into object code that can be executed by
microcontroller.
Assembler package
In addition, automatic functions to generate symbol table and optimize branch instructions are also
provided. Used in combination with device file (DF789234) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used under the Windows
environment by using PM plus of Windows (included in the assembler package).
Part number: µS××××RA78K0S
CC78K0S
Program that converts program written in C language into object codes that can be executed by
microcontroller.
C library package
Used in combination with assembler package (RA78K0S) and device file (DF789234) (both sold
separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used under the Windows
environment by using PM plus of Windows (included in the assembler package).
Part number: µS××××CC78K0S
DF789234Note 1
Device file
File containing the information inherent to the device.
Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, ID78K0S-QB, or SM+ for
78K0S) (all sold separately).
Part number: µS××××DF789234
CC78K0S-LNote 2
Source file of functions constituting object library included in C compiler package.
C library source file
Necessary for changing object library included in C compiler package according to customer’s
specifications.
Since this is the source file, its working environment does not depend on any particular operating
system.
Part number: µS××××CC78K0S-L
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APPENDIX A DEVELOPMENT TOOLS
Notes 1. DF789234 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, ID78K0S-QB
and SM+ for 78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
Remark ×××× in the part number differs depending on the host machine and operating system to be used.
µS××××RA78K0S
µS××××CC78K0S
µS××××CC78K0S-L
××××
AB17
Host Machine
OS
Supply Media
CD-ROM
PC-9800 series, IBM PC/AT
and compatibles
Japanese Windows
English Windows
HP-UXTM (Rel.10.10)
BB17
3P17
3K17
HP9000 series 700TM
SPARCstationTM
SunOSTM (Rel.4.1.4),
SolarisTM (Rel.2.5.1)
µS××××DF789234
××××
Host Machine
OS
Supply Media
3.5” 2HD FD
AB13
BB13
PC-9800 series, IBM PC/AT
and compatibles
Japanese Windows
English Windows
A.3 Control Software
PM plus
This is control software designed so that the user program can be efficiently developed
in the Windows environment. With this software, a series of user program
development operations, including starting the editor, build, and starting the debugger,
can be executed on the PM plus.
Project manager
<Caution>
The PM plus is included in the assembler package (RA78K0S). It can be used only in
the Windows environment.
A.4 Flash Memory Writing Tools
FlashPro4 (FL-PR4, PG-FP4)
Flash memory programmer
Flash programmer dedicated to the microcontrollers incorporating a flash memory
PG-FPL2
Flash programmer dedicated to the microcontrollers incorporating a flash memory
Provided with the in-circuit emulator QB-78K0SKX1MINI.
Flash memory programmer
FA-78F9202GR-AND-MXNote
FA-78F9212GR-JJG-MXNote
Flash memory writing adapter
Flash memory writing adapter. Used in connection with FlashPro4.
• FA-78F9202GR-AND-MX: For 78K0S/KU1+
• FA-78F9212GR-JJG-MX: For 78K0S/KY1+
Note Under development
Remark FL-PR4, FA-78F9202GR-AND-MX, and FA-78F9212GR-JJG-MX are products of Naito Densei Machida
Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191)
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APPENDIX A DEVELOPMENT TOOLS
A.5 Debugging Tools (Hardware)
A.5.1 When using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A
IE-78K0S-NS
In-circuit emulator for debugging hardware and software of application system using 78K/0S
In-circuit emulator
Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter,
emulation probe, and interface adapter for connecting the host machine.
IE-78K0S-NS-A
This in-circuit emulator has a coverage function in addition to the functions of the IE-78K0S-
NS, and enhanced debugging functions such as an enhanced tracer function and timer
function.
In-circuit emulator
IE-70000-MC-PS-B
AC adapter
Adapter for supplying power from 100 to 240 VAC outlet.
IE-70000-CD-IF-A
PC card interface
PC card and interface cable required when using a notebook type PC as the host machine
(PCMCIA socket supported).
IE-70000-PC-IF-C
Interface adapter
Adapter required when using IBM PC/AT and compatibles as the host machine (ISA bus
supported).
IE-70000-PCI-IF-A
Interface adapter
Adapter required when using a personal computer incorporating the PCI bus is used as the
host machine.
IE-789234-NS-EM1
Emulation board
Emulation board for emulating the peripheral hardware inherent to the device.
Used in combination with in-circuit emulator. A target cable is provided.
Specifications of pin header on 0.635 mm × 0.635 mm (height: 6 mm)
target system
A.5.2 When using in-circuit emulator QB-78K0SKX1MINI
QB-78K0SKX1MINI
In-circuit emulator
In-circuit emulator for debugging hardware and software of application system using
78K0S/Kx1+ Series. Supports integrated debugger (ID78K0S-QB). Used in combination with
AC adapter, target cable, and USB interface cable for connecting the host machine.
Specifications of pin header on 0.635 mm × 0.635 mm (height: 6 mm)
target system
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APPENDIX A DEVELOPMENT TOOLS
A.6 Debugging Tools (Software)
ID78K0S-NS
This debugger supports the in-circuit emulators for the 78K/0S Series. ID78K0S-NS is
Windows-based software.
(supporting in-circuit
emulator IE-78K0S-NS/
IE-78K0S-NS-A)
This debugger has enhanced debugging functions supporting C language. By using its window
integration function that associates the source program, disassemble display, and memory
display with trace results, the trace results can be displayed corresponding to the source
program.
Integrated debugger
It is used with a device file (DF789234) (sold separately).
Part number: µS××××ID78K0S-NS
ID78K0S-QB
This debugger supports the in-circuit emulators for the 78K0S/Kx1+ Series. ID78K0S-QB is
Windows-based software.
(supporting in-circuit
emulator
Provided with the debug function supporting C language, source programming, disassemble
display, and memory display are possible. This is used with the device file (DF789234) (sold
separately).
QB-78K0SKX1MINI)
Integrated debugger
It is provided with the in-circuit emulator QB-78K0SKX1MINI.
Ordering number: µS××××ID78K0S-QB (not for sale)
SM+ for 78K0SNotes 1
System simulator
This is a system simulator for the 78K/0S series. SM+ for 78K0S is Windows-based software.
This simulator can execute C-source-level or assembler-level debugging while simulating the
operations of the target system on the host machine.
By using SM+ for 78K0S, the logic and performance of the application can be verified
independently of hardware development. Therefore, the development efficiency can be
enhanced and the software quality can be improved.
This simulator is used with a device file (DF789234) (sold separately).
Part number: µS××××SM789234-B
DF789234Notes 2
Device file
This is a file that has device-specific information.
It is used with the RA78K0S, CC78K0S, ID78K0S-NS, ID78K0S-QB, and SM+ for 78K0S (all
sold separately).
Part number: µS××××DF789234
Notes 1. Under development
2. DF789234 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, ID78K0S-QB,
and SM+ for 78K0S.
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APPENDIX A DEVELOPMENT TOOLS
Remark ×××× in the part number differs depending on the operating system to be used and the supply medium.
µS××××ID78K0S-NS
µS××××ID78K0S-QB
µS××××SM789234-NS
××××
BB13
Host Machine
OS
Supply Medium
3.5” 2HD FD
CD-ROM
PC-9800 series, IBM PC/AT
and compatibles
English Windows
Japanese Windows
English Windows
AB17
BB17
µS××××DF789234
××××
Host Machine
OS
Supply Medium
3.5” 2HD FD
AB13
BB13
PC-9800 series, IBM PC/AT
and compatibles
Japanese Windows
English Windows
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APPENDIX B REGISTER INDEX
B.1 Register Index (Register Name)
8-bit A/D conversion result register (ADCRH) … 154
8-bit timer H compare register 01 (CMP01) … 122
8-bit timer H compare register 11 (CMP11) … 122
8-bit timer H mode register 1 (TMHMD1) … 123
10-bit A/D conversion result register (ADCR) … 153
16-bit timer capture/compare register 000 (CR000) … 82
16-bit timer capture/compare register 010 (CR010) … 84
16-bit timer counter 00 (TM00) … 82
16-bit timer mode control register 00 (TMC00) … 85
16-bit timer output control register 00 (TOC00) … 88
[A]
A/D converter mode register (ADM) … 150
Analog input channel specification register (ADS) … 153
[C]
Capture/compare control register 00 (CRC00) … 87
[E]
External interrupt mode register 0 (INTM0) … 168
[F]
Flash address pointer H compare register (FLAPHC)… 226
Flash address pointer L compare register (FLAPLC) … 226
Flash address pointer H (FLAPH) … 225
Flash address pointer L (FLAPL) … 225
Flash programming command register (FLCMD) … 225
Flash programming mode control register (FLPMC) … 221
Flash protect command register (PFCMD) … 222
Flash status register (PFS) … 223
Flash write buffer register (FLW) … 227
[I]
Interrupt mask flag register 0 (MK0) … 168
Interrupt request flag register 0 (IF0) … 167
[L]
Low-speed Ring-OSC mode register (LSRCM) … 67
Low-voltage detect register (LVIM) … 196
Low-voltage detection level select register (LVIS) … 197
[O]
Oscillation stabilization time select register (OSTS) … 68
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APPENDIX B REGISTER INDEX
[P]
Port mode control register 2 (PMC2) … 59, 90, 125, 154
Port mode register 2 (PM2) … 58, 90, 125, 154
Port mode register 3 (PM3) … 58
Port mode register 4 (PM4) … 58
Port register 2 (P2) … 59
Port register 3 (P3) … 59
Port register 4 (P4) … 59
Preprocessor clock control register (PPCC) … 66
Prescaler mode register 00 (PRM00) … 89
Processor clock control register (PCC) … 66
Pull-up resistor option register 2 (PU2) … 61
Pull-up resistor option register 3 (PU3) … 61
Pull-up resistor option register 4 (PU4) … 61
[R]
Reset control flag register (RESF) … 190
[W]
Watchdog timer enable register (WDTE) … 139
Watchdog timer mode register (WDTM) … 138
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APPENDIX B REGISTER INDEX
B.2 Register Index (Symbol)
[A]
ADCR:
ADCRH:
ADM:
10-bit A/D conversion result register … 153
8-bit A/D conversion result register … 154
A/D converter mode register … 150
ADS:
Analog input channel specification register … 153
[C]
CMP01:
CMP11:
CR000:
CR010:
CRC00:
8-bit timer H compare register 01 … 122
8-bit timer H compare register 11 … 122
16-bit timer capture/compare register 000 … 82
16-bit timer capture/compare register 010 … 84
Capture/compare control register 00 … 87
[F]
FLAPH:
Flash address pointer H … 225
FLAPHC: Flash address pointer H compare register … 226
FLAPL: Flash address pointer L … 225
FLAPLC: Flash address pointer L compare register … 226
FLCMD:
FLPMC:
FLW:
Flash programming command register … 225
Flash programming mode control register … 221
Flash write buffer register … 227
[I]
IF0:
Interrupt request flag register 0 … 167
External interrupt mode register 0 … 168
INTM0:
[L]
LSRCM:
LVIM:
LVIS:
Low-speed Ring-OSC mode register … 67
Low-voltage detect register … 196
Low-voltage detection level select register … 197
[M]
MK0:
Interrupt mask flag register 0 … 168
[O]
OSTS:
Oscillation stabilization time select register … 68
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APPENDIX B REGISTER INDEX
[P]
P2:
P3:
P4:
PCC:
Port register 2 … 59
Port register 3 … 59
Port register 4 … 59
Processor clock control register … 66
PFCMD: Flash protect command register … 222
PFS:
Flash status register … 223
PM2:
PM3:
PM4:
PMC2:
PPCC:
PRM00:
PU2:
Port mode register 2 … 58, 90, 125, 154
Port mode register 3 … 58
Port mode register 4 … 58
Port mode control register 2 … 59, 90, 125, 154
Preprocessor clock control register … 66
Prescaler mode register 00 … 89
Pull-up resistor option register 2 … 61
Pull-up resistor option register 3 … 61
Pull-up resistor option register 4 … 61
PU3:
PU4:
[R]
RESF:
Reset control flag register … 190
[T]
TM00:
TMC00:
16-bit timer counter 00 … 82
16-bit timer mode control register 00 … 85
TMHMD1: 8-bit timer H mode register 1 … 123
TOC00:
16-bit timer output control register 00 … 88
[W]
WDTE:
WDTM:
Watchdog timer enable register … 139
Watchdog timer mode register … 138
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APPENDIX C REVISION HISTORY
C.1 Major Revisions in This Edition
(1/2)
Page
Description
Addition of settings for port mode register 4 (PM4) when using 78K0S/KU1+
Deletion of high-speed Ring-OSC mode register (HSRCM)
Addition of Part Number to 1.3 Ordering Information
Modification of Type36 in Figure 2-1 Pin I/O Circuits
Addition of Note 4 to Table 3-3 Special Function Registers (1/2)
Addition of Remarks 1, 2 in Table 4-1 Port Functions
Addition of Figure 4-3 Block Diagram of P22
Throughout
p. 15
p. 27
p. 40
p. 51
p. 54
pp. 72, 74, 76
Modification of operation stop time in the following figures.
• Figure 5-8 Timing Chart of Default Start by High-Speed Ring-OSC Oscillator
• Figure 5-10 Timing Chart of Default Start by Crystal/Ceramic Oscillator
• Figure 5-12 Timing of Default Start by External Clock Input
pp. 82-84
Addition of Cautions to 6.2 Configuration of 16-Bit Timer/Event Counter 00 (1) 16-bit timer counter 00
(TM00), (2) 16-bit timer capture/compare register 000 (CR000), and (3) 16-bit timer capture/compare
register 010 (CR010)
p. 86
p. 89
p. 90
Addition of Cautions in Figure 6-5 Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Addition of Caution 6 to Figure 6-7 Format of 16-Bit Timer Output Control Register 00 (TOC00)
Modification of Caution 3 and addition of Caution 4 in Figure 6-8 Format of Prescaler Mode Register 00
(PRM00)
p. 95
Addition of (1) INTTM000 generation timing immediately after operation starts : The setting value +2 of
CR000 to 1 Figure 6-17 External Event Counter Operation Timing (with Rising Edge Specified)
p. 101
Modification of Note in Figure 6-24 Control Register Settings for Pulse Width Measurement with Free-
Running Counter and Two Capture Registers (with Rising Edge Specified)
p. 114
Modification and addition to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00
Modification of Table 8-1 Loop Detection Time of Watchdog Timer
p. 135
pp. 138, 139
p. 141
Addition of Caution 4 and modification to Figure 8-2 Format of Watchdog Timer Mode Register (WDTM)
Modification of Figure 8-4 Status Transition Diagram When “Low-Speed Ring-OSC Cannot Be Stopped”
Is Selected by Option Byte
p. 143
Modification of Figure 8-5 Status Transition Diagram When “Low-Speed Ring-OSC Can Be Stopped by
Software” Is Selected by Option Byte
pp. 144, 145
Modification of operation stop time in the following figures
• Figure 8-6 Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware)
• Figure 8-7 Operation in STOP Mode (WDT Operation Clock: Low-Speed Ring-OSC Clock)
p. 146
p. 147
Addition of Note to and modification of Figure 9-1 Timing of A/D Converter Sampling and A/D Conversion
Addition of Note 1 and Remark 2 to and modification of Table 9-1 Sampling Time and A/D Conversion
Time
p. 148
Modification of Figure 9-2 Block Diagram of A/D Converter
pp. 151, 152
Modification of Note 5, addition of Notes 1, 2, and Remark 2 to, and modification of Figure 9-3 Format of
A/D Converter Mode Register (ADM)
p. 157
Modification of Figure 9-11 Relationship Between Analog Input Voltage and A/D Conversion Result
pp. 162, 163
Modification of 9.6 (1) Operating current in STOP mode, (4) Noise countermeasures, and (6) Input
impedance of ANI0 to ANI3 pins
300
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APPENDIX C REVISION HISTORY
(2/2)
Page
Description
p. 162
p. 164
Modification of capacitor value in Figure 9-19 Analog Input Pin Connection
Modification of Figure 9-21 Internal Equivalent Circuit of ANIn Pin and Table 9-4 Resistance and
Capacitance Values (Reference Values) of Equivalent Circuit
p. 174
p. 178
Modification of description on operation stop time in 11.1.1 (2) STOP mode
Modification of Note in Figure 11-3 HALT Mode Release by Reset Input
pp. 180, 181
Modification of operation stop time in the following figures.
• Figure 11-4 Operation Timing When STOP Mode Is Released
• Figure 11-5 STOP Mode Release by Interrupt Request Generation
p. 182
Modification of Note in Figure 11-6 STOP Mode Release by Reset Input
pp. 184-187
Modification of the following figures
• Figure 12-1 Block Diagram of Reset Function
• Figure 12-2 Timing of Reset by RESET Input
• Figure 12-3 Timing of Reset by Overflow of Watchdog Timer
• Figure 12-4 Reset Timing by RESET Input in STOP Mode
p. 196
Addition of Note 1 to Figure 14-2 Format of Low-Voltage Detect Register (LVIM)
Addition of Note to Figure 14-3 Format of Low-Voltage Detection Level Select Register (LVIS)
Addition of Note to 14.5 Cautions for Low-Voltage Detector <Action> (2) When used as interrupt
Revision of CHAPTER 16 FLASH MEMORY
p. 197
p. 201
p. 207
pp. 274, 275,
Modification or addition of values in the following characteristics in CHAPTER 18 ELECTRICAL
277-280, 282, SPECIFICATIONS (TARGET VALUES)
285
• Absolute maximum ratings
Output current high, output current low, and operating ambient temperature
• X1 oscillator characteristics
• DC characteristics
• AC characteristics
Basic operation cycle time (minimum instruction execution time)
• A/D Converter Characteristics
• Flash memory programming characteristics
pp. 286, 287
pp. 289, 290
pp. 291, 292
p. 292
Modification of 19.1 Package drawing of the 78K0S/KU1+ and 19.2 Package drawing of the 78K0S/KY1+
Modification Figure A-1 Development Tools
Modification of device file names and Remark in A.2 Language Processing Software
Addition of project manager name to A.3 Control Software
p. 292
Addition of PG-FPL2 to A.4 Flash Memory Writing Tools,
p. 293
Modification of emulation board name used when the IE-78K0S-NS or IE-78K0S-NS-A is used, and addition of
Specification of pin header on target system to A.5.1 When using in-circuit emulator IE-78K0S-NS or
IE-78K0S-NS-A
p. 293
Addition of A.5.2 When using in-circuit emulator QB-78K0SKX1MINI
pp. 294, 295
Modification of system simulator name, device file name, and Remark in and addition of ID78K0S-QB to A.6
Debugging Tools (Software)
p. 300
Addition of APPENDIX C REVISION HISTORY
301
Preliminary User’s Manual U16994EJ2V0UD
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