UPD8882CY-A [NEC]
(10680 + 10680) PIXELS ?3 COLOR CCD LINEAR IMAGE SENSOR; （ 10680 + 10680 ）像素的？ 3彩色CCD线性图像传感器
| 型号： | UPD8882CY-A |
| 厂家： | 
NEC |
| 描述： | (10680 + 10680) PIXELS ?3 COLOR CCD LINEAR IMAGE SENSOR |
| 文件： | 总36页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD8882
(10680 + 10680) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The μPD8882 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The μPD8882 has 3 rows of (10680 + 10680) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
2400 dpi/A4 color image scanners.
FEATURES
• Valid photocell : (10680 + 10680) staggered pixels × 3
• Photocell’s size : 2.7 μm × 5.4 μm
• Line spacing
: 86.4 μm (16 lines) Red line - Green line, Green line - Blue line
43.2 μm (8 lines) Odd line - Even line (for each color)
• Color filter
• Resolution
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
: 96 dot/mm A4 (210 × 297 mm) size (shorter side)
2400 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
: Built-in amplifiers : 10.0 MHz Max. CCD transfer : 4.5 MHz Max./each CCD
: +12 V
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
μPD8882CY-A
Remark The μPD8882CY-A is a lead-free product.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17085EJ2V0DS00 (2nd edition)
Date Published May 2005 NS CP (K)
Printed in Japan
The mark
shows major revised points.
2004
μPD8882
BLOCK DIAGRAM
VOD GND GND φ RB
φ 2 φ 1
20
2
11
3
14 15
VOD
7
CCD analog shift register
Transfer gate
Photocell (Blue-odd)
13
12
10
φ
φ
φ
TG1
TG2
TG3
Transfer gate
CCD analog shift register
VOUT
VOUT
VOUT
1
2
3
21
CCD analog shift register
Transfer gate
Photocell (Blue-even)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
Photocell (Green-odd)
Transfer gate
CCD analog shift register
22
CCD analog shift register
Transfer gate
Photocell (Green-even)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
Photocell (Red-odd)
Transfer gate
CCD analog shift register
1
CCD analog shift register
Transfer gate
Photocell (Red-even)
Transfer gate
CCD analog shift register
4
19
9
8
φ
CLB
φ
SEL
φ 4 φ 3
2
Data Sheet S17085EJ2V0DS
μPD8882
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
• μPD8882CY-A
Output signal 3 (Red)
Ground
V
OUT
3
1
2
22
21
20
19
V
V
V
φ
OUT
OUT
OD
2
1
Output signal 2 (Green)
GND
Output signal 1 (Blue)
Output drain voltage
Reset gate clock
φ
3
RB
Reset feed-through level clamp clock
No connection
φ
4
SEL Dpi selector
CLB
NC
5
18 NC
17 NC
16 NC
No connection
No connection
NC
6
No connection
Output drain voltage
Shift register clock 3
Shift register clock 4
VOD
7
No connection
φ
3
4
8
15
14
13
12
φ
φ
φ
φ
1
Shift register clock 1
Shift register clock 2
φ
9
2
Transfer gate clock 3
(for Red)
Transfer gate clock 1
(for Blue)
φ
10
TG1
TG2
TG3
Transfer gate clock 2
(for Green)
GND 11
Ground
Caution Connect the No connection pins (NC) to GND.
3
Data Sheet S17085EJ2V0DS
μPD8882
PHOTOCELL STRUCTURE DIAGRAM
0.7
μ
m
μ
2.0 m
μ
Channel stopper
Aluminum
shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM-1 (Line spacing)
5.4 μm
5.4 μm
5.4 μm
5.4 μm
Blue odd photocell array
Blue even photocell array
Green odd photocell array
Green even photocell array
Red odd photocell array
Red even photocell array
8 lines
(43.2
μ
m)
m)
m)
m)
m)
16 lines
(86.4 m)
μ
8 lines
(43.2
μ
8 lines
(43.2
μ
16 lines
(86.4 m)
μ
8 lines
(43.2
μ
5.4
5.4
μ
μ
m
m
8 lines
(43.2
μ
4
Data Sheet S17085EJ2V0DS
μPD8882
PHOTOCELL ARRAY STRUCTURE DIAGRAM-2 (Odd-even pixel)
1
3
5
7
5.4
μm
43.2
μm
1.35
μ
m
4
37.8
μ
m
(8 lines)
2
6
8
5.4
μ
m
2.0
μ
m
0.7 μm
PHOTOCELL ARRAY STRUCTURE DIAGRAM-3 (Dummy, OB, for each color)
Dummy
Optical black
(96 pixels)
Invalid photocell
(8 pixels)
Valid photocell
(21360 pixels)
Invalid photocell
(4 pixels)
(56 pixels)
1
55 57
151 153 155 157 159 161 163
152 154 156 158 160 162 164
21517 21519
2
56 58
21518 21520
5
Data Sheet S17085EJ2V0DS
μPD8882
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Ratings
−0.3 to +15
−0.3 to +8
−0.3 to +8
−0.3 to +8
−0.3 to +8
−0.3 to +8
0 to +60
Unit
V
VOD
Shift register clock voltage
Vφ 1, Vφ 2, Vφ 3, Vφ 4
V
Reset gate clock voltage
Vφ RB
V
Reset feed-through level clamp clock voltage
Dpi select signal voltage
Vφ CLB
V
Vφ SEL
V
Transfer gate clock voltage
Operating ambient temperature Note
Storage temperature
Vφ TG1 to Vφ TG3
V
TA
°C
°C
Tstg
−40 to +70
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Min.
11.4
4.7
Typ.
12.0
5.0
0
Max.
12.6
5.5
Unit
V
VOD
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Vφ 1H, Vφ 2H, Vφ 3H, Vφ 4H
Vφ 1L, Vφ 2L, Vφ 3L, Vφ 4L
Vφ RBH
V
−0.3
4.5
+0.3
5.5
V
5.0
0
V
Reset gate clock low level
Vφ RBL
−0.3
4.5
+0.5
5.5
V
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Dpi select signal high level
Vφ CLBH
5.0
0
V
Vφ CLBL
−0.3
4.5
+0.5
5.5
V
Vφ SELH
5.0
0
V
Dpi select signal low level
Vφ SELL
−0.3
4.5
+0.5
5.5
V
Transfer gate clock high level
Transfer gate clock low level
Data rate (amplifier)
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ RB
5.0
0
V
−0.3
−
+0.5
10.0
4.5
V
2.0
0.5
MHz
MHz
Clock pulse frequency
fφ 1, fφ 2, fφ 3, fφ 4
−
6
Data Sheet S17085EJ2V0DS
μPD8882
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Symbol
Vsat
Test Conditions
Min.
2.0
−
Typ.
2.5
Max.
−
Unit
V
Red
SER
SEG
SEB
PRNU
ADS
DSNU
PW
0.877
0.926
1.445
6
−
lx•s
lx•s
lx•s
%
Green
Blue
−
−
−
−
Photo response non-uniformity
Average dark signal
VOUT = 1.0 V
−
20
Light shielding
Light shielding
−
0.1
4.0
8.0
450
1.0
3.70
3.51
2.25
7.0
−
mV
mV
mW
kΩ
Dark signal non-uniformity
Power consumption
−
2.0
−
280
0.4
Output impedance
ZO
−
Response
Red
RR
2.00
1.89
1.21
5.0
−
2.85
2.70
1.73
6.0
V/lx•s
V/lx•s
V/lx•s
V
Green
Blue
RG
RB
Offset level Note 1
Output fall delay time Note 2
VOS
td
VOUT = 1.0 V
25
ns
Total transfer efficiency
TTE
VOUT = 1.0 V
92
98
−
%
Clock pulse frequency = 4.5 MHz
Image lag
IL
VOUT = 1.0 V
VOUT = 1.0 V
−
−
0.5
1.0
3.0
4.0
−
%
Photo diode response imbalance
PDRI
%
Response peak
Red
−
630
540
460
−0.8
1.2
nm
nm
nm
mV
mV
Green
Blue
−
−
−
−
Reset feed-through noise Note 1
RFTN
74HC04, RS = 47 Ω Note 3
−2.0
−
+1.0
−
Random noise (CDS)
σCDS
Light shielding
Notes1. Refer to TIMING CHART 2-1 to 2-4.
2. When the fall time φ 1-600, φ 1-2400 (t1) is the Typ. value (refer to TIMING CHART 2-1 to 2-4).
3. Using application circuit example.
7
Data Sheet S17085EJ2V0DS
μPD8882
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V)
Parameter
Shift register clock pin capacitance 1
Shift register clock pin capacitance 2
Shift register clock pin capacitance 3
Shift register clock pin capacitance 4
Reset gate clock pin capacitance
Symbol
Pin name Pin No.
Min.
−
Typ.
600
600
600
600
20
Max.
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Cφ 1
φ 1
15
14
8
−
−
−
−
−
−
−
−
−
−
Cφ 2
Cφ 3
Cφ 4
Cφ RB
φ 2
−
φ 3
−
φ 4
9
−
φ RB
φ CLB
φ SEL
φ TG1
φ TG2
φ TG3
3
−
Reset feed-through level clamp clock pin capacitance Cφ CLB
4
−
20
Select signal and gain pin capacitance
Transfer gate clock pin capacitance
Cφ SEL
19
13
12
10
−
20
Cφ TG
−
20
−
20
−
20
Remark Cφ 1 to Cφ 4 show the equivalent capacity of the real drive including the capacity of between each clock pin
(φ 1 and φ 4).
8
Data Sheet S17085EJ2V0DS
TIMING CHART 1-1 (2400 dpi, bit clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
φ
φ
1
2
3
4
φ
RB
Note
Note
φ
φ
CLB
SEL
“H”
VOUT1 to VOUT3
Optical black
(96 pixels)
Valid photocell
(21360 pixels)
Invalid photocell
(8 pixels)
Invalid photocell
(4 pixels)
μ
Note Set the φ RB and the φ CLB to high during this period.
TIMING CHART 1-2 (2400 dpi, line clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
φ
φ
1
2
3
4
φ
RB
Note
Note
φ
φ
CLB
SEL
“H”
VOUT1 to VOUT3
Optical black
(96 pixels)
Valid photocell
(21360 pixels)
Invalid photocell
(8 pixels)
Invalid photocell
(4 pixels)
μ
Note Set the φ RB to high level and the φ CLB to low level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
TIMING CHART 1-3 (1200 dpi, bit clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
φ
φ
1
2
3
4
φ
RB
Note
Note
φ
φ
CLB
SEL
“L”
VOUT1 to VOUT3
Optical black
(48 pixels)
Valid photocell
(10680 pixels)
Invalid photocell
(4 pixels)
Invalid photocell
(2 pixels)
μ
Note Set the φ RB and the φ CLB to high level during this period.
TIMING CHART 1-4 (1200 dpi, line clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
φ
φ
1
2
3
4
φ
RB
Note
Note
φ
φ
CLB
SEL
“L”
VOUT1 to VOUT3
Optical black
(48 pixels)
Valid photocell
(10680 pixels)
Invalid photocell
(4 pixels)
Invalid photocell
(2 pixels)
μ
Note Set the φ RB to high level and the φ CLB to low level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
TIMING CHART 1-5 (600 dpi, bit clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
φ
φ
1
2
3
4
φ
RB
Note
Note
φ
φ
CLB
SEL
“L”
VOUT1 to VOUT3
Optical black
(24 pixels)
Valid photocell
(5340 pixels)
Invalid photocell
(2 pixels)
Invalid photocell
(1 pixels)
μ
Note Set the φ RB and the φ CLB to high level during this period.
TIMING CHART 1-6 (600 dpi, line clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
φ
φ
1
2
3
4
φ
RB
Note
Note
φ
φ
CLB
SEL
“L”
VOUT1 to VOUT3
Optical black
(24 pixels)
Valid photocell
(5340 pixels)
Invalid photocell
(2 pixels)
Invalid photocell
(1 pixels)
μ
Note Set the φ RB to high level and the φ CLB to low level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
TIMING CHART 1-7 (300 dpi, bit clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
φ
φ
1
2
3
4
φ
RB
Note
Note
φ
φ
CLB
SEL
“L”
V
OUT1 to VOUT3
Optical black
(12 pixels)
Valid photocell
(2670 pixels)
Invalid photocell
(1 pixels)
Invalid photocell
(1 pixels)
μ
Note Set the φ RB and the φ CLB to high level during this period.
TIMING CHART 1-8 (300 dpi, line clamp mode, for each color)
φ
TG1 to
φ
TG3
φ
φ
φ
φ
1
2
3
4
φ
RB
Note
Note
φ
φ
CLB
SEL
“L”
V
OUT1 to VOUT3
Optical black
(12 pixels)
Valid photocell
(2670 pixels)
Invalid photocell
(1 pixels)
Invalid photocell
(1 pixels)
μ
Note Set the φ RB to high level and φ CLB to low level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
μPD8882
TIMING CHART 2-1 (2400 dpi, for each color)
t1
t2
90%
φ
φ
1
2
10%
90%
10%
t1
t2
90%
10%
φ
φ
3
4
90%
10%
t19
t19
t5 t6
t3
t4
t4
t4
t4
90%
10%
φ
RB
t7 t11
t7 t11
t7 t11
t7 t11
90%
10%
φ
CLB
(Bit clamp mode)
t9 t8 t10
“H”
φ
CLB
(Line clamp mode)
“H”
SEL
φ
t
d
RFTN
V
OS
V
OUT
10%
Symbol
Min.
0
Typ.
30
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1, t2
−
−
−
−
−
−
−
−
−
−
t3
20
40
0
160
150
10
t4
t5, t6
t7
−5
20
0
+25
100
10
t8
t9, t10
t11
t19
td
10
110
−
25
500
25
17
Data Sheet S17085EJ2V0DS
μPD8882
TIMING CHART 2-2 (1200 dpi, for each color)
t1
t2
90%
φ
φ
1
2
10%
90%
10%
t19
t19
90%
10%
φ
φ
3
4
t5
t6
t5
t6
t3
t3
t4
t4
90%
10%
φ
RB
t9 t10
t8 t11
t9 t10
t7 t8 t11
t7
90%
10%
φ
CLB
(Bit clamp mode)
“H”
φ
CLB
(Line clamp mode)
“L”
SEL
φ
td
td
RFTN
VOS
VOUT
10%
10%
Symbol
t1, t2
Min.
0
Typ.
30
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
−
−
−
−
−
−
−
−
t3
20
40
0
160
150
10
t4
t5, t6
t7
−5
20
0
+25
100
10
t8
t9, t10
t11
t19
td
10
110
−
25
500
25
18
Data Sheet S17085EJ2V0DS
μPD8882
TIMING CHART 2-3 (600 dpi, for each color)
t2
t1
90%
10%
φ
1
90%
10%
φ
2
t19
t19
t2
t1
90%
φ
φ
3
4
10%
90%
10%
t5 t6
t4
t3
90%
10%
φ
RB
t9 t10
t8
t7
t11
90%
10%
φ
CLB
(Bit clamp mode)
“H”
φ
CLB
(Line clamp mode)
“L”
SEL
φ
td
RFTN
VOUT
10%
Symbol
Min.
Typ.
30
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1, t2
0
20
40
0
−
−
−
−
−
−
−
−
−
−
t3
160
150
10
t4
t5, t6
t7
−5
20
0
+25
100
10
t8
t9, t10
t11
t19
td
10
110
−
25
500
25
19
Data Sheet S17085EJ2V0DS
μPD8882
TIMING CHART 2-4 (300 dpi, for each color)
t2
t1
90%
10%
φ
1
90%
10%
φ
2
t19
t19
t2
t1
90%
φ
φ
3
4
10%
90%
10%
t5 t6
t4
t3
90%
10%
φ
RB
t9 t10
t8
t7
t11
90%
10%
φ
CLB
(Bit clamp mode)
“H”
φ
CLB
(Line clamp mode)
“L”
SEL
φ
td
RFTN
VOUT
10%
Symbol
Min.
Typ.
30
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1, t2
0
20
40
0
−
−
−
−
−
−
−
−
−
−
t3
160
150
10
t4
t5, t6
t7
−5
20
0
+25
100
10
t8
t9, t10
t11
t19
td
10
110
−
25
500
25
20
Data Sheet S17085EJ2V0DS
μPD8882
TIMING CHART 3
t13
t14
t12
90%
10%
90%
10%
φ
TG1 to φTG3
t15
t16
90%
φ
φ
1
3
90%
t17
t18
90%
90%
φ
RB
90%
90%
φ
CLB
(Line clamp mode)
Remark Inverse pulse of the φTG1 to φTG3 can be used as φCLB (when line clamp mode).
Symbol
Min.
5000
0
Typ.
10000
50
Max.
Unit
ns
t12
50000
t13, t14
t15, t16
t17, t18
−
−
−
ns
900
200
1000
400
ns
ns
φ1, φ2, φ3, φ4 cross points
φ
φ
φ
φ
2,
1,
4
3
2.0 V or more
2.0 V or more
Remark Adjust cross points of (φ1, φ2) and (φ3, φ4) with input resistance of each pin.
21
Data Sheet S17085EJ2V0DS
μPD8882
SELECTION OF RESOLUTION MODE
The μPD8882 has function of two readout modes, High Resolution Mode and Low Resolution Mode. These two
modes can be selected by φ SEL switch.
Read Mode
High Resolution Mode
Low Resolution Mode
Description
φ SEL
2400 dpi (Max.)
1200 dpi (Max.) (odd line readout mode)
High level
Low level
(1) High Resolution Mode
In this mode, both signals in even lines and odd lines can be read out. This mode enables 2400 dpi (Max.)
resolution with A4 size (210 × 297 mm, shorter side).
Please refer to TIMING CHART 1-1, 1-2 and 2-1.
(2) Low Resolution Mode
In this mode, only signal in odd photocell arrays can be read out.
This mode enables 1200 dpi (Max.) resolution with A4 size.
To use intermittent reset drive enable signal charges of adjacent pixels in odd line to add at the charge to voltage
conversion area. Then it can achieve low resolution with A4 size such as 600, 300 or 150 dpi.
Please refer to TIMING CHART 1-3 to 1-8, 2-2 to 2-4.
φ SEL TIMING CHART
After changing the dpi selector signal (φSEL), subsequent data of one line cannot be guaranteed (refer the follow
figure).
φ
TG1 to
φ
φ
TG3
SEL
VOUT1 to VOUT3
Invalid date 1 line
Valid date
22
Data Sheet S17085EJ2V0DS
μPD8882
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
x
Δ
PRNU (%) =
× 100
x
Δ
x : maximum of ⎪x
j
− x ⎪
21360
x
j
Σ
j = 1
21360
: Output voltage of valid pixel number j
x =
xj
V
OUT
x
Register Dark
DC level
Δ
x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
21360
d
j
Σ
j = 1
21360
ADS (mV) =
d
j
: Dark signal of valid pixel number j
23
Data Sheet S17085EJ2V0DS
μPD8882
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of ⎪d
j
− ADS ⎪j = 1 to 21360
d
j
: Dark signal of valid pixel number j
VOUT
ADS
Register Dark
DC level
DSNU
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
Light
ON
OFF
VOUT
V1
VOUT
V
1
IL (%) =
× 100
OUT
V
24
Data Sheet S17085EJ2V0DS
μPD8882
9. Photo diode response imbalance: PDRI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the
average output voltage of all the valid pixels.
n
2
2
n
∑
(V2j –1 – V2j
)
j = 1
PDRI (%) =
× 100
n
1
n
∑
V
j
j = 1
n : Number of valid pixels
Vj : Output voltage of each pixel
10. Offset level : VOS
DC level of output signal is defined as follows.
11. Reset feed-through noise : RFTN
Reset feed-through noise (RFTN) are defined as follows.
+
RFTN
–
V
OUT
VOS
25
Data Sheet S17085EJ2V0DS
μPD8882
12. Random noise (CDS) : σCDS
Random noise σCDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding). σCDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
“VDi”.
3. The output level is measured during the video output time averaged over 100 ns to get “VOi”.
4. The correlated double sampling output is defined by the following formula.
VCDSi = VDi – VOi
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation σ CDS using the following formula equation.
100
100
(VCDS
100
i
– V)2
1
Σ
σ
CDS (mV) =
, V =
VCDS
i
100 Σ
i = 1
i = 1
Reset feed-through
Video output
26
Data Sheet S17085EJ2V0DS
μPD8882
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T = +25°C)
A
8
2
4
1
2
1
0.5
0.2
0.25
0.1
0.1
0
10
20
30
40
50
1
5
10
Operating Ambient Temperature T
A
(°C)
Storage Time (ms)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T = +25°C)
A
100
80
R
B
G
60
40
20
G
B
0
400
500
600
700
800
Wavelength (nm)
27
Data Sheet S17085EJ2V0DS
μPD8882
APPLICATION CIRCUIT EXAMPLE
+5 V
+12 V
+
+
μ
PD8882
1
2
22
21
20
19
18
17
16
15
14
13
12
10 μF/16 V 0.1 μF
B3
V
OUT
3
V
OUT
2
1
B2
B1
0.1
0.1
μ
μ
F 47
μ
μ
F/25 V
+5 V
GND
V
OUT
R
S
3
+
φ
RB
φ
φ
RB
CLB
VOD
47
Ω
4
φ
CLB
φ
SEL
NC
NC
NC
F 10
F/16 V
47 Ω
47 Ω
5
NC
NC
φ
SEL
6
7
V
φ
φ
φ
OD
8
φ
φ
3
4
3
φ
φ
1
2
φ
φ
φ
1
4.7 Ω
4.7 Ω
10 Ω
4.7 Ω
9
4
2
4.7 Ω
10 Ω
10 Ω
10
11
TG3
φ
φ
TG1
TG2
TG
GND
Caution Connect the No connection pins (NC) to GND.
Remarks 1. φRB, φCLB, φTG1 to φTG3 and φSEL driving inverters shown in the above application circuit
example are the 74HC04.
φ1 to φ4 driving inverters shown in the above application circuit example are the 74HC04 (≤ 2.0
MHz) or the 74AC04 (> 2.0 MHz).
2. Inverters B1 to B3 in the above application circuit example are shown in the figure below.
B1 to B3 EQUIVALENT CIRCUIT
12 V
+
μ
47 F/25 V
100 Ω
CCD
2SC1842
2 kΩ
VOUT
100 Ω
28
Data Sheet S17085EJ2V0DS
μPD8882
PACKAGE DRAWING
μ
PD8882CY
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400))
(Unit : mm)
44.0 0.3
1st valid pixel
1
9.25 0.3
1.52 0.3
22
12
11
1
4
4
2.0
37.5
2
10.16 0.2
(1.72)
1.02 0.15
4.39 0.4
3
2.62 0.2
(5.42)
4.21 0.5
0.25 0.05
0.46 0.1
2.54 0.25
+0.7
10.16
−0.2
Name
Dimensions
42.7×8.35×0.8(0.7
Refractive index
5
Plastic cap
)
1.5
1 1st valid pixel
The center of the pin1
2 The surface of the CCD chip
3 The bottom of the package
4 Mirror finished surface
The top of the cap
The surface of the CCD chip
5 Thickness of mirror finished surface
22C-1CCD-PKG18
29
Data Sheet S17085EJ2V0DS
μPD8882
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Through-hole Device
μPD8882CY-A : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin)
Cautions 1.
2.
During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
Soldering by the solder flow method may have deleterious effects on prevention of plastic
cap soiling and heat resistance. So the method cannot be guaranteed.
30
Data Sheet S17085EJ2V0DS
μPD8882
NOTES ON HANDLING THE PACKAGES
1
DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Ethyl Alcohol
Symbol
EtOH
MeOH
IPA
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
NMP
2
MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
3
4
OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
31
Data Sheet S17085EJ2V0DS
μPD8882
[MEMO]
32
Data Sheet S17085EJ2V0DS
μPD8882
[MEMO]
33
Data Sheet S17085EJ2V0DS
μPD8882
[MEMO]
34
Data Sheet S17085EJ2V0DS
μPD8882
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
35
Data Sheet S17085EJ2V0DS
μPD8882
•
The information in this document is current as of May, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
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•
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•
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(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
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(2)
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defined above).
M8E 02. 11-1
相关型号：
UPD8894CY-A
CCD Sensor, 5340 Horiz pixels, 5340 Vert pixels, 2.50-2.80V, Rectangular, Through Hole Mount, PLASTIC, DIP-32
NEC
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