UPD98501N7-F6 [NEC]
LAN Controller, 3 Channel(s), 12.5MBps, CMOS, PBGA352, 35 X 35 MM, BGA-352;
| 型号： | UPD98501N7-F6 |
| 厂家： | 
NEC |
| 描述： | LAN Controller, 3 Channel(s), 12.5MBps, CMOS, PBGA352, 35 X 35 MM, BGA-352 时钟 局域网 数据传输 外围集成电路 |
| 文件： | 总44页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98501
NETWORK CONTROLLER
The µPD98501 is a high performance controller which can perform the protocol conversion between IP packets
and ATM cells, which is especially suitable for ADSL modem. It includes high performance MIPS based 64-bit
RISC processor VR4120A CPU core, ATM cell processor, Ethernet controller, USB controller block, UTOPIA2
interface and SDRAM interface.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µPD98501 User’s Manual: S14767E
FEATURES
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Includes high performance MIPS based 64-bit RISC processor VR4120A
Can perform RTOS and network middleware (M/W) on the chip
Includes interface for PROM and flash ROM used for storing boot program
Includes 32-bit RISC controller, as ATM cell processor
Software SAR processing by RISC controller affords flexibility for specification update
Supports CBR/VBR/UBR service classes
Includes 2-channel 10/100 Mbps Ethernet controllers compliant to IEEE802.3, IEEE802.3u and IEEE802.3x
Can directly connect external Ethernet PHY device through 3.3-V MII interface
Includes USB full speed function controller compliant to USB specification 1.1
Supports operation conforming to the USB Communication Device Class Specification
Can directly connect 64M-bit and 128M-bit SDRAM as external memory
Includes 8-bit 33 MHz UTOPIA level 2 interface compliant to ATM Forum af-phy-0039
Includes boundary scan function (JTAG) compliant to IEEE 1149.1
Includes Micro Wire interface
Includes 2-channel general purpose timers
Using advanced CMOS technology
Power supply voltage: 3.3 V (I/O), 2.5 V (Core)
Package 352-pin T-BGA
ORDERING INFORMATION
Part Number
Package
352-pin tape BGA (heat spreader type) (35 × 35)
µPD98501N7-F6
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14828EJ5V0DS00 (5th edition)
Date Published August 2002 NS CP (K)
Printed in Japan
2000
©
The mark
shows major revised points.
µPD98501
BLOCK DIAGRAM
µPD98501
VR4120A RISC
Processor
Core
Full-speed
USB
USB
Controller
PROM / Flash
SDRAM
3.3-V MII
Ethernet
Controller
#1, #2
System Controller
RS-232C/Micro Wire
Parallel Port
33-MHz UTOPIA-2
PHY Management
JTAG
ATM Cell Processor
Clock
JTAG
Control
Controller
Unit
2
Data Sheet S14828EJ5V0DS
µPD98501
PIN CONFIGURATION (Bottom View)
• 352-pin tape BGA (head spreader type) (35 × 35)
µPD98501N7-F6
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AF AE AD AC AB AA Y W V
U
T
R
P
N M
L
K
J
H
G
F
E
D
C
B
A
3
Data Sheet S14828EJ5V0DS
µPD98501
Pin Name
Pin No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
Pin Name
Pin No.
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
Pin Name
SCLK
Pin No.
E01
E02
E03
E04
E23
E24
E25
E26
F01
F02
F03
F04
F23
F24
F25
F26
G01
G02
G03
G04
G23
G24
G25
G26
H01
H02
H03
H04
H23
H24
H25
H26
J01
Pin Name
EVDD
Pin No.
L23
Pin Name
UMD0
Pin No.
V01
Pin Name
IC-Open
IVDD
SMA6
CLKSL
IC-PDn
PUMD_B
PUAVD
IC-PDn
IC-PDn
USBDP
IC-PDnR
IVDD
PSDVD
PSAGND
GND
L24
IC-PUp
GND
V02
SMA5
GND
L25
V03
IVDD
PUAGND
GND
L26
IVDD
V04
GND
IVDD
M01
M02
M03
M04
M23
M24
M25
M26
N01
N02
N03
N04
N23
N24
N25
N26
P01
P02
P03
P04
P23
P24
P25
P26
R01
R02
R03
R04
R23
R24
R25
R26
T01
T02
T03
T04
T23
T24
T25
T26
U01
U02
U03
U04
U23
U24
U25
U26
SMD16
SMD17
IVDD
V23
MI2RD1
MI2RD0
MI2MD
MI2RDV
SMA4
EVDD
UMAD4
UMAD2
EVDD
V24
EVDD
V25
IC-PUpR
IC-Open
IVDD
GND
V26
SRMCS_B
SRMOE_B
PSTBY
PSMD_B
UMAD1
UMAD0
IC-PUpR
IC-PUpR
SMD30
SMD31
IVDD
IC-PUpR
IC-PUpR
IC-PUpR
IC-PUpR
SMA19
SMA20
GND
W01
W02
W03
W04
W23
W24
W25
W26
Y01
SMA3
IVDD
UDRCLV
UDRD6
UDRD3
UDRD0
UDRCLK
GND
GND
EVDD
SMA2
UDRD1
IVDD
IVDD
MI2MCLK
MI2RD3
MI2RD2
SMA1
UDRAD3
UDRAD0
UDTE_B
UDTAD3
GND
EVDD
UDTAD4
UDTAD1
UDTD7
UDTD4
IVDD
IC-PUpR
IC-PUpR
IC-PUpR
IC-PUpR
SMA18
SMA17
SMA16
SMA15
MI2TD1
MI2TD0
IVDD
Y02
EVDD
Y03
SMA0
UDTD5
UDTCLK
UMRST_B
UDTD0
UMINT_B
UMAD11
UMMD
IC-PDn
IC-Open
IC-Open
PUDVD
PUDGND
PUSTBY
GND
GND
Y04
SDCKE1
GND
IC-PUpR
IC-PUpR
IC-PUpR
IC-PUpR
SMD27
GND
Y23
UMRDY_B
UMRD_B
EVDD
Y24
IC-PDnR
IC-PDnR
GND
Y25
Y26
UMAD7
GND
AA01
AA02
AA03
AA04
AA23
AA24
AA25
AA26
AB01
AB02
AB03
AB04
AB23
AB24
AB25
AB26
AC01
AC02
AC03
AC04
AC05
AC06
AC07
AC08
AC09
AC10
AC11
AC12
IVDD
GND
PSAVD
PSDGND
GND
SMD28
SMD29
IC-PUpR
IC-PUpR
UMD7
SDCLK1
SDCS_B
EVDD
GND
SMA14
EVDD
IC-PDn
USBCLK
IC-PDn
IC-Open
USBDM
IC-PDnR
GND
MITD1
MITD0
IVDD
SMA13
SMA12
MI2TCLK
MI2COL
MI2TD3
MI2TD2
SMA11
IVDD
GND
IVDD
SDRAS_B
SDCAS_B
EVDD
EVDD
J02
GND
IC-Open
GND
J03
SMD25
SMD26
IVDD
J04
SDCLK0
GND
UDRSC
UDRD5
UDRD2
GND
UDRE_B
UDRD7
UDRD4
UDRAD4
UDRAD1
UDTCLV
EVDD
J23
J24
UMD6
MICRS
MITD3
MITD2
SDWE_B
SDCKE0
SMD15
SMD10
SMD6
J25
UMD5
GND
J26
UMD4
SMA10
MI2TER
MI2CRS
IVDD
UDRAD2
IVDD
K01
K02
K03
K04
K23
K24
K25
K26
L01
L02
L03
L04
SMD22
SMD23
EVDD
UDTSC
UDTAD2
UDTAD0
EVDD
IVDD
SMD24
UMD3
GND
UDTD6
UDTD3
GND
SMA9
EVDD
SMA8
EVDD
UDTD2
UDTD1
UMSL_B
UMWR_B
UMAD9
UMAD8
UMD2
SMA7
SMD1
GND
UMD1
EVDD
EXNMI_B
POM5
UMAD10
UMAD6
UMAD5
UMAD3
SMD18
SMD19
SMD20
SMD21
MI2TE
MI2RCLK
EVDD
POM2
POM0
MI2RER
URSDI
4
Data Sheet S14828EJ5V0DS
µPD98501
Pin No.
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
Pin Name
EVDD
Pin No.
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE01
AE02
AE03
AE04
AE05
AE06
Pin Name
IVDD
Pin No.
AE07
AE08
AE09
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF01
AF02
AF03
Pin Name
GND
Pin No.
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
Pin Name
SMD5
IC-Open
EVDD
URCLK
URDSR_B/MWDO
URRTS_B/MWDI
IVDD
ENDCEN
POM6
SMD7
SMD0
GND
POM3
RST_B
EVDD
IC-PUpR
JRSTB_B
JDO
GND
IC-Open
IC-PDn
IC-Open
IC-Open
JMS
URDCD_B/MWCS
URDTR_B
GND
POM4
POM1
IC-PDn
ROMSEL0
MIRD2
GND
IVDD
IC-Open
IC-PUpR
IC-PUpR
BIG
URCTS_B/MWSK
URSDO
IC-PDn
IC-Open
IC-Open
IVDD
EVDD
MITER
MITCLK
MICOL
GND
ROMSEL1
MIMCLK
MIRD0
IVDD
JCK
MIMD
IC-PDn
IC-PDn
MIRD3
IVDD
IC-PUpR
GND
SMD11
SMD14
SMD8
MIRER
IVDD
JDI
IVDD
SSEL
GND
GND
MIRCLK
MITE
IC-PDn
GND
SMD4
EVDD
IVDD
SMD9
GND
MIRD1
GND
EXINT_B
POM7
SMD3
SMD13
SMD12
SMD2
MIRDV
Special pin name description:
IC-PDn: Pull Down
IC-PDnR: Pull Down with Resistor
IC-PUp: Pull Up
IC-PUpR: Pull Up with Resistor
Remark In this document, XXX_B stands for active low pin.
5
Data Sheet S14828EJ5V0DS
µPD98501
CONTENTS
1. PIN FUNCTIONS.................................................................................................................................... 7
1.1 Power Supply ................................................................................................................................. 7
1.2 System PLL Power Supply............................................................................................................ 7
1.3 USB PLL Power Supply................................................................................................................. 7
1.4 System Control Interface............................................................................................................... 8
1.5 Memory Interface ........................................................................................................................... 8
1.6 ATM Interface ................................................................................................................................. 9
1.7 Ethernet Interface......................................................................................................................... 10
1.8 USB Interface................................................................................................................................ 11
1.9 UART/Micro Wire Interface.......................................................................................................... 11
1.10 Parallel Port Interface ................................................................................................................ 11
1.11 Boundary Scan Interface........................................................................................................... 11
1.12 I.C. - Open ................................................................................................................................... 12
1.13 I.C. - Pull Down........................................................................................................................... 12
1.14 I.C. - Pull Down with Resistor ................................................................................................... 12
1.15 I.C. - Pull Up................................................................................................................................ 12
1.16 I.C. - Pull Up with Resistor ........................................................................................................ 12
2. ELECTRICAL SPECIFICATIONS........................................................................................................ 13
3. PACKAGE DRAWING ......................................................................................................................... 41
4. RECOMMENDED SOLDERING CONDITIONS.................................................................................. 42
6
Data Sheet S14828EJ5V0DS
µPD98501
1. PIN FUNCTIONS
Symbol of I/O column indicates following status in this section.
I
:Input
O
:Output
I/O :Bidirection
I/OZ :Bidirection (Include Hi-Z state)
I/OD :Bidirection (Open drain output)
OZ :Output (Include Hi-Z state)
OD :Output (Open drain)
1.1 Power Supply
Pin Name
Pin No.
I/O
Active Level
Function
GND
A03, A05, AB23, AC16, AC23, AD01, AE02,
AE07, AE14, AF01, AF19, AF23, C16, C26, D10,
D21, D22, E04, G04, H02, H26, P26, T03, T26,
W03, Y23, Y26, A19, AA02, AD05, AE11, AF25,
B07, B10, B14, D03, J02, L25, M04, N03, V04
GND (0 V)
IVDD
A02, A10, A14, AA01, AA26, AD14, AE24, AF11,
B16, D18, E23, J01, J23, L26, M03, P25, V03,
A11, AD07, AD10, AD26, AE01, AE19, AF17,
C10, C21, G03, T02, T25, W23
Internal logic core power
supply (+2.5 V)
EVDD
A07, A12, AA23, AB03, AC06, AC13, AC15,
AD20, AE03, AF08, B08, B20, C24, E01, E26,
K24, N04, R02, U04, U25, Y02, A06, D17, K03
External (I/O) power supply
(+3.3 V)
1.2 System PLL Power Supply
Pin Name
PSAGND
Pin No.
E03
I/O
Active Level
Function
Analog ground (0 V)
PSAVD
PSDGND
PSDVD
D01
D02
E02
Analog power supply (+2.5 V)
Digital ground (0 V)
Digital power supply (+2.5 V)
1.3 USB PLL Power Supply
Pin Name
PUAGND
Pin No.
A04
I/O
Active Level
Function
Analog ground (0 V)
PUAVD
PUDGND
PUDVD
C05
B05
B04
Analog power supply (+2.5 V)
Digital ground (0 V)
Digital power supply (+2.5 V)
7
Data Sheet S14828EJ5V0DS
µPD98501
1.4 System Control Interface
Pin Name
Pin No.
I/O
Active
Level
Function
SCLK
C01
I
I
I
I
I
I
I
I
I
I
I
I
System clock (33 MHz)
CLKSL
C02
Clock select (L: 100 MHz/H: 66 MHz) for VR4120A and SDRAM
System PLL mode control input (L: normal, H: through) Note
System PLL standby mode control input (L: active, H: standby)
USB PLL mode control (L: normal, H: through) Note
USB PLL standby mode control (L: active, H: standby)
VR4120A big endian mode
PSMD_B
PSTBY
F04
L
H
L
F03
PUMD_B
PUSTBY
BIG
C04
B06
H
H
AE18
AE08
AD08
AC08
AF07
AC21, AD21
ENDCEN
EXINT_B
EXNMI_B
RST_B
Endian conversion enable
L
L
L
External interrupt
External non-maskable interrupt
System reset
ROMSEL0, ROMSEL1
ROM access bus width
(ROMSEL1/0 = L/L: 32-bit, L/H: 16-bit, H/L: 8-bit)
SSEL
AF21
I
UART/Micro Wire Select (L: UART, H: Micro Wire)
Note PSMD_B and PUMD_B pins shall be connected to GND.
1.5 Memory Interface
Pin Name
SDCLK0, SDCLK1
SDCKE0, SDCKE1
SDCS_B
Pin No.
I/O
O
O
O
O
O
O
O
O
O
Active Level
Function
AB04, AA03
AC02, Y04
AA04
SDRAM clock
H
L
L
L
L
L
L
SDRAM clock enable
SDRAM chip select
SDRAS_B
AB01
SDRAM row address strobe
SDRAM column address strobe
SDRAM/PROM/FLASH write enable
PROM/FLASH chip select
PROM/FLASH output enable
Memory address
SDCAS_B
AB02
SDWE_B
AC01
SRMCS_B
F01
SRMOE_B
F02
SMA0 - SMA20
Y03, Y01, W04, W02, W01, V02,
V01, U03, U02, U01, T04, T01,
R04, R03, R01, P04, P03, P02,
P01, N01, N02
SMD0-SMD31
AF06, AC07, AE06, AE05, AD06,
AF04, AC05, AF05, AD04, AE04,
AC04, AD02, AF03, AF02, AD03,
AC03, M01, M02, L01, L02, L03,
L04, K01, K02, K04, J03, J04,
H01, H03, H04, G01, G02
I/O
Memory data
8
Data Sheet S14828EJ5V0DS
µPD98501
1.6 ATM Interface
(1) UTOPIA management interface
Pin Name
UMMD
Pin No.
I/O
O
I
Active Level
Function
A26
A24
C23
C22
A22
B23
B24
Management mode select
Interrupt from PHY
Management read enable
Management data ready
PHY reset
UMINT_B
L
L
L
L
L
L
UMRD_B
O
I
UMRDY_B
UMRST_B
UMSL_B
O
O
O
O
PHY select
UMWR_B
Management write enable
PHY address
UMAD0 - UMAD11
F24, F23, E25, D26, E24, D25,
D24, C25, B26, B25, D23, A25
UMD0 - UMD7
L23, K26, K25, K23, J26, J25,
J24, H25
I/O
Management data
(2) UTOPIA data interface
Pin Name
Pin No.
I/O
O
I
Active Level
Function
Receive clock
UDRCLK
C15
UDRCLV
C11
D11
B11
H
L
Receive cell available
Receive enable
UDRE_B
O
I
UDRSC
H
Receive cell start
Receive PHY address
Receive data
UDRAD0 - UDRAD4
UDRD0 - UDRD7
A16, D15, B15, A15, D14
O
I
C14, A13, B13, C13, D13, B12,
C12, D12
UDTCLK
A21
O
I
Transmit clock
UDTCLV
D16
H
L
Transmit Cell Available
Transmit enable
UDTE_B
A17
O
O
O
O
UDTSC
B17
H
Transmit Cell start position
Transmit PHY address
Transmit data
UDTAD0 - UDTAD4
UDTD0 - UDTD7
B19, C18, B18, A18, C17
A23, B22, B21, D20, C20, A20,
D19, C19
9
Data Sheet S14828EJ5V0DS
µPD98501
1.7 Ethernet Interface
(1) Ethernet interface (Channel 1)
Pin Name
Pin No.
I/O
Active Level
Function
MIRCLK
MIMCLK
MIMD
AE25
AD22
AD24
AC26
AB24
AF26
AD25
I
O
I/O
I
MII - Receive clock (2.5 MHz/25 MHz)
MII - Management clock
MII – Management data
MII - Collision
MICOL
MICRS
I
MII - Carrier sense
MIRDV
I
MII - Receive data valid
MII - Receive error
MIRER
I
MIRD0 - MIRD3
MITCLK
MITE
AD23, AF24, AC22, AE23
I
MII - Receive data
AC25
I
MII - Transmit clock (2.5 MHz/25 MHz)
MII - Transmit enable
MII - Transmit error
AE26
O
O
O
MITER
AC24
MITD0 - MITD3
AA25, AA24, AB26, AB25
MII - Transmit data
(2) Ethernet interface (Channel 2)
Pin Name
Pin No.
I/O
Active Level
Function
MII - Receive clock (2.5 MHz/25 MHz)
MII - Management clock
MII - Management data
MII - Collision
MI2RCLK
MI2MCLK
MI2MD
U24
W24
V25
R24
T24
V26
U26
I
O
I/O
I
MI2COL
MI2CRS
I
MII - Carrier sense
MI2RDV
I
MII - Receive data valid
MII - Receive error
MI2RER
I
MI2RD0 - MI2RD3
MI2TCLK
MI2TE
V24, V23, W26, W25
I
MII - Receive data
R23
I
MII - Transmit clock (2.5 MHz/25 MHz)
MII - Transmit enable
MII - Transmit error
U23
O
O
O
MI2TER
T23
MI2TD0 - MI2TD3
P24, P23, R26, R25
MII - Transmit data
10
Data Sheet S14828EJ5V0DS
µPD98501
1.8 USB Interface
Pin Name
USBCLK
Pin No.
D05
I/O
I
Active Level
Function
External USB clock (12 MHz)
USB data (−)
USBDM
D08
C08
I/O
I/O
USBDP
USB data (+)
1.9 UART/Micro Wire Interface
Pin Name
URCLK
Pin No.
I/O
I
Active Level
Function
AD11
AF13
AC12
AE13
AD13
UART external clock (18.432 MHz)
UART serial data output
UART serial data input
UART data terminal ready
UART data request to send
Micro Wire data in
URSDO
O
I
URSDI
URDTR_B
URRTS_B
/MWDI
O
O
I
L
L
URCTS_B
/MWSK
AF12
AE12
AD12
I
L
L
L
UART clear to send
O
I
Micro Wire sampling clock out
UART data carrier detect
Micro Wire chip select
UART data set ready
URDCD_B
/MWCS
O
I
URDSR_B
/MWDO
O
Micro Wire data out
Remark For the function multiplexed pins (AD13, AF12, AE12, AD12), function is determined as follows.
SSEL = L: UART operation mode
SSEL = H: Micro Wire operation mode
1.10 Parallel Port Interface
Pin Name
Pin No.
I/O
O
Active Level
Function
POM0 - POM7
AC11, AF10, AC10, AE10,
AF09, AC09, AE09, AD09
Parallel port signal output
1.11 Boundary Scan Interface
Pin Name
Pin No.
I/O
Active Level
Function
B-SCAN clock
JCK
AE20
AF20
AC19
AD19
AC18
I
JDI
I
B-SCAN input-data
B-SCAN output-data
B-SCAN mode select
B-SCAN reset
JDO
OZ
JMS
I
I
JRSTB_B
L
11
Data Sheet S14828EJ5V0DS
µPD98501
1.12 I.C. - Open
Pin Name
IC-Open
Pin No.
I/O
O
Active Level
Active Level
Active Level
Function
Leave open
A09, B09, A01, B02, D07, B03, AC14, AD15,
AD17, AD18, AE15, AF15, AF16
1.13 I.C. - Pull Down
Pin Name
Pin No.
I/O
I
Function
Connect to GND
IC-PDn
AF22, C03, B01, D04, C06, D06, C07, AE21,
AC20, AD16, AE22, AF14
1.14 I.C. - Pull Down with Resistor
Pin Name
IC-PDnR
Pin No.
I/O
I/O
Function
C09, D09, Y24, Y25
Connect to GND via pull-
down resistor
1.15 I.C. - Pull Up
Pin Name
Pin No.
I/O
I
Active Level
Function
IC-PUp
L24
Connect to EVDD
1.16 I.C. - Pull Up with Resistor
Pin Name
Pin No.
I/O
I/O
Active Level
Function
IC-PUpR
A08, H24, H23, G26, G25, G24, G23, F26, F25,
N26, N25, N24, N23, M26, M25, M23, M24,
AC17, AE16, AE17, AF18
Connect to EVDD via pull-up
resistor
12
Data Sheet S14828EJ5V0DS
µPD98501
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
IVDD
Conditions
Internal logic core
Ratings
−0.5 to +3.6
−0.5 to +4.6
−0.5 to +4.6
−0.5 to +4.6
30
Unit
V
V
EVDD
VI1/VO1
VI2/VO2
IO1
I/O buffer
Input/output voltage
Output current
LVTTL-level pin
V
USB I/O buffer
V
LVTTL-level pin, IOL = 9 mA
USB I/O buffer, IOL = 18 mA
mA
mA
°C
IO2
55
−60 to +150
Storage temperature
Tstg
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
IVDD
Conditions
MIN.
2.35
3.15
0
TYP.
2.5
MAX.
2.65
3.45
0.8
Unit
V
EVDD
VIL1
3.3
V
Low level input voltage
High level input voltage
LVTTL-level pin
V
VIL2
USB I/O/ buffer, refer to (9) USB
Interface Parameter
0.8
V
(Single-end operation)
VIH1
VIH2
LVTTL-level pin
2.0
2.0
V
V
USB I/O/ buffer, refer to (9) USB
Interface Parameter
(Single-end operation)
USB differential input voltage
Operating ambient temperature
VIDF
USB I/O buffer, refer to (9) USB
Interface Parameter
0.2
0
V
(Differential operation)
°C
TA
70
13
Data Sheet S14828EJ5V0DS
µPD98501
DC Characteristics (IVDD = 2.5 0.15 V, EVDD = 3.3 0.15 V, TA = 0 to +70 °C)
Parameter
Supply current
Symbol
IIDD
Conditions
MIN.
TYP.
MAX.
Unit
1100
200
10
mA
mA
µA
µA
V
EIDD
ILI
Input leakage current
Off state output current
Low level output voltage
VI = EVDD or GND
10
IOZ
VO = EVDD or GND
VOL1
VOL2
LVTTL-level pin, IOL = 9 mA
0.4
0.3
USB I/O buffer, refer to (9) USB
V
Interface Parameter
High level output voltage
VOH1
VOH2
LVTTL-level pin, IOH= 9mA
2.4
2.8
V
V
USB I/O buffer, refer to (9) USB
EVDD
Interface Parameter
Capacitance (TA = 25°C, VDD = 0 V)
Parameter
Input Capacitance
Symbol
Conditions
fC = 1 MHz,
MIN.
TYP.
MAX.
Unit
pF
CI
4
4
4
8
8
8
Output Capacitance
I/O Capacitance
CO
CIO
Unmeasured pins returned to 0 V
pF
pF
14
Data Sheet S14828EJ5V0DS
µPD98501
Pin Classifications
Input pins
Number
of Pins
Category
Application Pins
LVTTL-level pin
VI1,
BIG, CLKSL, ENDCEN, EXINT_B, EXNMI_B, JCK, JDI, JMS,
JRSTB_B, MI2COL, MI2CRS, MI2MD, MI2RCLK, MI2RD[3:0],
MI2RDV, MI2RER, MI2TCLK, MICOL, MICRS, MIMD, MIRCLK,
MIRD[3:0], MIRDV, MIRER, MITCLK, MWDI, PSMD_B, PSTBY,
PUMD_B, PUSTBY, ROMSEL[1:0], RST_B, SCLK, SMD[31:0],
SSEL, UDRCLV, UDRD[7:0], UDRSC, UDTCLV, UMD[7:0],
UMINT_B, UMRDY_B, URCLK, URCTS_B, URDCD_B,
URDSR_B, URSDI, USBCLK
100
VIL1/VIH1
USB I/O buffer
VI2,
USBDP, USBDM
2
VIL2/VIH2,
VIDF
Output pins
Number
of Pins
Category
IO1
Application Pins
LVTTL-level pin
VO1,
JDO, MI2MCLK, MI2MD, MI2TD[3:0], MI2TE, MI2TER, MIMCLK,
MIMD, MITD[3:0], MITE, MITER, MWCS, MWDO, MWSK,
POM[7:0], SDCAS_B, SDCKE0, SDCKE1, SDCLK0, SDCLK1,
SDCS_B, SDRAS_B, SDWE_B, SMA[20:0], SMD[31:0],
SRMCS_B, SRMOE_B, UDRAD[4:0], UDRCLK, UDRE_B,
UDTAD[4:0], UDTCLK, UDTD[7:0], UDTE_B, UDTSC,
UMAD[11:0], UMD[7:0], UMMD, UMRD_B, UMRST_B, UMSL_B,
UMWR_B, URDTR_B, URRTS_B, URSDO
142
VOL1/VOH1
USB I/O buffer
IO2
VO2,
USBDP, USBDM
2
VOL2/VOH2
AC Characteristics (IVDD = 2.5 0.15 V, EVDD = 3.3 0.15 V, TA = 0 to +70 °C)
(1) AC Test Waveform
Input signal
Ouput signal
0.5EVDD
0.5EVDD
Test points
Test points
0.5EVDD
0.5EVDD
15
Data Sheet S14828EJ5V0DS
µPD98501
(2) Clock parameter
Clock Cycle
Clock High Width
Clock Low Width
(2)-1 Clock input
Parameter
Symbol
tCYSCK
tWHSCK
tWLSCK
tCYMTK
tWHMTK
tWLMTK
tCYMRK
tWHMRK
tWLMRK
tCY2TK
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK input cycle
30.0
40.0
0.4 × tCYSCK
0.4 × tCYSCK
40.0
0.6 × tCYSCK
0.6 × tCYSCK
400.0
SCLK input high level width
SCLK input low level width
MITCLK input cycle
0.4 × tCYMTK
0.4 × tCYMTK
40.0
0.6 × tCYMTK
0.6 × tCYMTK
400.0
MITCLK input high level width
MITCLK input low level width
MIRCLK input cycle
0.4 × tCYMRK
0.4 × tCYMRK
40.0
0.6 × tCYMRK
0.6 × tCYMRK
400.0
MIRCLK input high level width
MIRCLK input low level width
MI2TCLK input cycle
0.4 × tCY2TK
0.4 × tCY2TK
40.0
0.6 × tCY2TK
0.6 × tCY2TK
400.0
MI2TCLK input high level width
MI2TCLK input low level width
MI2RCLK input cycle
tWH2TK
tWL2TK
tCY2RK
tWH2RK
tWL2RK
tCYUBK
tWHUBK
tWLUBK
tCYJCK
0.4 × tCY2RK
0.4 × tCY2RK
83.1
0.6 × tCY2RK
0.6 × tCY2RK
84.6
MI2RCLK input high level width
MI2RCLK input low level width
USBCLK input cycle
0.4 × tCYUBK
0.4 × tCYUBK
100.0
0.6 × tCYUBK
0.6 × tCYUBK
1000.0
USBCLK input high level width
USBCLK input low level width
JCK input cycle
0.4 × tCYJCK
0.4 × tCYJCK
0.6 × tCYJCK
0.6 × tCYJCK
JCK input high level width
JCK input low level width
tWHJCK
tWLJCK
16
Data Sheet S14828EJ5V0DS
µPD98501
(2)-2 Clock output
Parameter
Symbol
tCYSK0
Conditions
Load 10 pF
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDCLK0 output cycle
10.0
15.0
0.4 × tCYSK0
0.4 × tCYSK0
10.0
0.6 × tCYSK0
0.6 × tCYSK0
15.0
SDCLK0 output high level width
SDCLK0 output low level width
SDCLK1 output cycle
tWHSK0
tWLSK0
tCYSK1
tWHSK1
tWLSK1
tCYUTK
tWHUTK
tWLUTK
tCYURK
tWHURK
tWLURK
tCYMCK
tWHMCK
tWLMCK
tCYM2K
tWHM2K
tWLM2K
Load 10 pF
Load 10 pF
Load 10 pF
Load 10 pF
Load 10 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
0.4 × tCYSK1
0.4 × tCYSK1
30.0
0.6 × tCYSK1
0.6 × tCYSK1
SDCLK1 output high level width
SDCLK1 output low level width
UDTCLK output cycle
0.4 × tCYUTK
0.4 × tCYUTK
30.0
UDTCLK output high level width
UDTCLK output low level width
UDRCLK output cycle
0.4 × tCYURK
0.4 × tCYURK
420.0
UDRCLK output high level width
UDRCLK output low level width
MIMCLK output cycle
0.4 × tCYMCK
0.4 × tCYMCK
420.0
MIMCLK output high level width
MIMCLK output low level width
MI2MCLK output cycle
0.4 × tCYM2K
0.4 × tCYM2K
MI2MCLK output high level width
MI2MCLK output low level width
17
Data Sheet S14828EJ5V0DS
µPD98501
(3) Reset, PLL parameter
IVDD, EVDD
PSTBY (System PLL),
PUSTBY (USB PLL)
tWHPSY, tWHUSY
SCLK
(System clock)
External OSC
Unstable Period
Internal PLL OSC
tWLPLK, tWLULK
Stable Period
RST_B
(System Reset)
tWLRSB
Parameter
RST_B input low level width
PSTBY hold high level width
PSTBY lookup time
Symbol
tWLRSB
Conditions
MIN.
MAX.
Unit
6.0 × tCYSCK
ns
µ s
µ s
µ s
µ s
tWHPSY
tWLPLK
tWHUSY
tWLULK
1
Load 50 pF
1000
1
PUSTBY hold high level width
PUSTBY lookup time
Load 50 pF
1000
(4) Interrupt interface parameter
tWLEIT, tWLENM
EXINT_B
EXNMI_B
(input)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
4.0 × tCYSK0
4.0 × tCYSK0
EXINT_B input low level width
EXNMI_B input low level width
tWLEIN
tWLENM
ns
18
Data Sheet S14828EJ5V0DS
µPD98501
(5) SDRAM interface parameter
SDCLK0
(output)
tDSE0SK0
tDSE0SK0
SDCKE0
(output)
tDSCSSK0
tDSRASK0
tDSCASK0
tDSWESK0
tDSCSSK0
tDSRASK0
tDSCASK0
tDSWESK0
SDCS_B
(output)
SDRAS_B
(output)
SDCAS_B
(output)
SDWE_B
(output)
tDSMASK0
tDSMASK0
SMA[20:0]
(output)
tDSMDSK0
tDSMDSK0
tDSMDSK0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SMD[31:0]
(output)
tASMDSK0
tFSMDSK0
tSSMDSK0 tHSMDSK0
SMD[31:0]
(input)
Parameter
Symbol
tDSE0SK0
tDSCSSK0
tDSRASK0
tDSCASK0
tDSWESK0
tDSMASK0
tASMDSK0
Conditions
MIN.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SDCKE0 output delay from SDCLK0
SDCS_B output delay from SDCLK0
SDRAS_B output delay from SDCLK0
SDCAS_B output delay from SDCLK0
SDWE_B output delay from SDCLK0
SMA[20:0] output delay from SDCLK0
Load 30 pF
Load 30 pF
Load 30 pF
Load 30 pF
Load 50 pF
Load 50 pF
Load 50 pF
7.5
7.5
7.5
7.5
7.5
7.5
SMD[31:0] output floating to active delay
from SDCLK0
SMD[31:0] output delay from SDCLK0
tDSMDSK0
tFSMDSK0
Load 50 pF
Load 50 pF
1.0
7.5
7.5
ns
ns
SMD[31:0] output active to floating delay
from SDCLK0
SMD[31:0] input setup to SDCLK0
SMD[31:0] input hold from SDCLK0
tSSMDSK0
tHSMDSK0
4.0
1.0
ns
ns
19
Data Sheet S14828EJ5V0DS
µPD98501
SDCLK1
(output)
tDSE1SK1
tDSE0SK1
SDCKE1
(output)
tDSCSSK1
tDSRASK1
tDSCASK1
tDSWESK1
tDSCSSK1
tDSRASK1
tDSCASK1
tDSWESK1
SDCS_B
(output)
SDRAS_B
(output)
SDCAS_B
(output)
SDWE_B
(output)
tDSMASK1
tDSMASK1
SMA[20:0]
(output)
tDSMDSK1
tDSMDSK1
tDSMDSK1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SMD[31:0]
(output)
tASMDSK1
tFSMDSK1
tSSMDSK1 tHSMDSK1
SMD[31:0]
(input)
Parameter
Symbol
tDSE1SK1
tDSCSSK1
tDSRASK1
tDSCASK1
tDSWESK1
tDSMASK1
tASMDSK1
Conditions
MIN.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SDCKE1 output delay from SDCLK1
SDCS_B output delay from SDCLK1
SDRAS_B output delay from SDCLK1
SDCAS_B output delay from SDCLK1
SDWE_B output delay from SDCLK1
SMA[20:0] output delay from SDCLK1
Load 30 pF
Load 30 pF
Load 30 pF
Load 30 pF
Load 50 pF
Load 50 pF
Load 50 pF
7.5
7.5
7.5
7.5
7.5
7.5
SMD[31:0] output floating to active delay
from SDCLK1
SMD[31:0] output delay from SDCLK1
tDSMDSK1
tFSMDSK1
Load 50 pF
Load 50 pF
1.0
7.5
7.5
ns
ns
SMD[31:0] output active to floating delay
from SDCLK1
SMD[31:0] input setup to SDCLK1
SMD[31:0] input hold from SDCLK1
tSSMDSK1
tHSMDSK1
4.0
1.0
ns
ns
20
Data Sheet S14828EJ5V0DS
µPD98501
(6) Flash ROM interface parameter
<Read cycle>
T0
T1
T2
T3
T4
T5
T6
FAT (=4)
SDCLK
(internal)
tSSMAROE
tHSMAROE
SMA[20:0]
(output)
tSRCSROE
tHRCSROE
SRMCS_B
(output)
tHSWEROE
tSSWEROE
SDWE_B
(output)
tWLROE
tWHROE
SRMOE_B
(output)
tSSMDROE
tHSMDROE
Hi-Z
Hi-Z
SMD[31:0]
(input)
Parameter
Symbol
Condition
Load 50 pF
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.0 × tCYSK0 − 8.0
1.0 × tCYSK0 − 8.0
5.0 × tCYSK0 − 8.0
SMA[20:0] setup to SRMOE_B
SMA[20:0] hold from SRMOE_B
SRMCS_B setup to SRMOE_B
SRMCS_B hold from SRMOE_B
SDWE_B setup time to SRMOE_B
SDWE_B hold time from SRMOE_B
SRMOE_B low level pulse width
SRMOE_B high level pulse width
SMD[31:0] setup to SRMOE_B
SMD[31:0] hold from SRMOE_B
tSSMAROE
tHSMAROE
tSRCSROE
tHRCSROE
tSSWEROE
tHSWEROE
tWLROE
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5.0
2.0 × tCYSK0 − 8.0
4.0 × tCYSK0 − 8.0
5.0 × tCYSK0 − 8.0
1.0 × tCYSK0 − 8.0
10.0
tWHROE
tSSMDROE
tHSMDROE
0
21
Data Sheet S14828EJ5V0DS
µPD98501
<Write cycle>
T0
T1
T2
T3
T4
T5
T6
FAT (=4)
SDCLK
(internal)
tSSMASWE
tHSMASWE
SMA[20:0]
(output)
tSRCSSWE
tHRCSSWE
SRMCS_B
(output)
tWHSWE
tWLSWE
SDWE_B
(output)
tSROESWE
tHROESWE
SRMOE_B
(output)
tHSMDSWE
tSSMDSWE
Hi-Z
Hi-Z
SMD[31:0]
(output)
tASMDSWE
tFSMDSWE
Parameter
Symbol
tSSMASWE
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.0 × tCYSK0 − 8.0
2.0 × tCYSK0 − 8.0
4.0 × tCYSK0 − 8.0
1.0 × tCYSK0 − 8.0
4.0 × tCYSK0 − 8.0
2.0 × tCYSK0 − 8.0
3.0 × tCYSK0 − 8.0
7.0 × tCYSK0 − 8.0
4.0 × tCYSK0 − 8.0
SMA[20:0] setup to SDWE_B
SMA[20:0] hold from SDWE_B
SRMCS_B setup to SDWE_B
SRMCS_B hold from SDWE_B
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
tHSMASWE
tSRCSSWE
tHRCSSWE
tSROESWE
tHROESWE
tWLSWE
SRMOE_B setup time to SDWE_B
SRMOE_B hold time from SDWE_B
SDWE_B low level pulse width
SDWE_B high level pulse width
SMD[31:0] setup to SDWE_B
SMD[31:0] hold from SDWE_B
tWHSWE
tSSMDSWE
tHSMDSWE
tASMDSWE
1.0 × tCYSK0 + 8.0
4.0 × tCYSK0 − 8.0
SMD[31:0] output floating to active
delay from SDWE_B
1.0 × tCYSK0 + 8.0
SMD[31:0] output active to floating
delay from SDWE_B
tFSMDSWE
Load 50 pF
ns
22
Data Sheet S14828EJ5V0DS
µPD98501
(7) ATM interface parameter
(7)-1 UTOPIA2 interface
<Data transmission>
UDTCLK
(output)
tSUTLUTK tHUTLUTK
UDTCLV
(input)
tDUTAUTK
UDTAD[4:0]
(output)
tDUTDUTK
tDUTEUTK
tDUTSUTK
UDTD[7:0]
(output)
UDTE_B
(output)
UDTSC
(output)
Parameter
Symbol
tSUTLUTK
Conditions
MIN.
8.0
1.0
1.0
1.0
1.0
1.0
MAX.
Unit
ns
ns
ns
ns
ns
ns
UDTCLV setup time to UDTCLK
UDTCLV hold time from UDTCLK
UDTAD[4:0] output delay from UDTCLK
UDTD[7:0] output delay from UDTCLK
UDTE_B output delay from UDTCLK
UDTSC output delay from UDTCLK
tHUTLUTK
tDUTAUTK
tDUTDUTK
tDUTEUTK
tDUTSUTK
Load 50 pF
15.0
15.0
15.0
15.0
Load 50 pF
Load 50 pF
Load 50 pF
23
Data Sheet S14828EJ5V0DS
µPD98501
<Data reception>
UDRCLK
(output)
tSURLURK tHURLURK
UDRCLV
(input)
tDURAURK
UDRAD[4:0]
(output)
tSURDURK tHURDURK
UDRD[7:0]
(input)
tDUREURK
UDRE_B
(output)
tSURSURK tHURSURK
UDRSC
(input)
Parameter
Symbol
Conditions
MIN.
8.0
MAX.
15.0
Unit
ns
UDRCLV setup time to UDRCLK
UDRCLV hold time from UDRCLK
tSURLURK
tHURLURK
tDURAURK
1.0
ns
UDRAD[4:0] output delay from
UDRCLK
Load 50 pF
1.0
ns
UDRD[7:0] setup to from UDRCLK
UDRD[7:0] hold time from UDRCLK
UDRE_B output delay from UDRCLK
UDRSC setup time to UDRCLK
UDRSC hold time from UDRCLK
tSURDURK
tHURDURK
tDUREURK
tSURSURK
tHURSURK
8.0
1.0
1.0
8.0
1.0
ns
ns
ns
ns
ns
Load 50 pF
15.0
24
Data Sheet S14828EJ5V0DS
µPD98501
(7)-2 UTOPIA management interface
<Interface signals>
tWLURT
UMRST_B
(output)
tWLUIT
UMINT_B
(input)
Parameter
Symbol
tWLURT
Conditions
MIN.
MAX.
Unit
ns
3.0 × tCYSCK
3.0 × tCYSCK
UMRST_B low level pulse width
UMINT_B low level pulse width
tWLUIT
ns
25
Data Sheet S14828EJ5V0DS
µPD98501
<Read cycle : Intel mode>
tSUMAURD
tHUMAURD
tHUSLURD
tHUWRURD
UMAD[11:0]
(output)
tSUSLURD
UMSL_B
(output)
tSUWRURD
UMWR_B
(output)
tWLURD
UMRD_B
(output)
tSURYURD
tHURYURD
UMRDY_B
(input)
tSUMDURD
tHUMDURD
Hi-Z
Hi-Z
UMD[7:0]
(input)
Parameter
Symbol
Conditions
Load 50 pF
MIN.
10
4
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UMAD[11:0] setup to UMRD_B
UMAD[11:0] hold from UMRD_B
UMSL_B setup to UMRD_B
UMSL_B hold from UMRD_B
UMWR_B setup to UMRD_B
UMWR_B hold from UMRD_B
UMRD_B low level pulse width
UMRDY_B setup to UMRD_B
UMRDY_B hold from UMRD_B
UMD[7:0] setup to UMRD_B
UMD[7:0] hold from UMRD_B
tSUMAURD
tHUMAURD
tSUSLURD
tHUSLURD
tSUWRURD
tHUWRURD
tWLURD
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5
0
5
0
50
25
10
15
15
tSURYURD
tHURYURD
tSUMDURD
tHUMDURD
26
Data Sheet S14828EJ5V0DS
µPD98501
<Read cycle : Motorola mode>
tSUMADSR
tHUMADSR
tHUSLDSR
tHRWDSR
UMAD[11:0]
(output)
tSUSLDSR
UMSL_B
(output)
tSRWDSR
UMWR_B
(as R/W : output)
tWLDSR
UMRD_B
(as DS : output)
tSDAKDSR
tHDAKDSR
UMRDY_B
(as DACK : input)
tSUMDDSR
tHUMDDSR
Hi-Z
Hi-Z
UMD[7:0]
(input)
Parameter
UMAD[11:0] setup to DS
UMAD[11:0] hold from DS
UMSL_B setup to DS
UMSL_B hold from DS
R/W setup to DS
Symbol
Conditions
Load 50 pF
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUMADSR
tHUMADSR
tSUSLDSR
tHUSLDSR
tSRWDSR
tHRWDSR
tWLDSR
10
4
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5
0
5
R/W hold from DS
0
DS low level pulse width
DACK setup to DS
50
25
10
15
15
tSDAKDSR
tHDAKDSR
tSUMDDSR
tHUMDDSR
DACK hold from DS
UMD[7:0] setup to DS
UMD[7:0] hold from DS
27
Data Sheet S14828EJ5V0DS
µPD98501
<Write cycle : Intel mode>
tSUMAUWR
tHUMAUWR
UMAD[11:0]
(output)
tSUSLUWR
tHUSLUWR
UMSL_B
(output)
tWLUWR
UMWR_B
(output)
tSURDUWR
tHURDUWR
UMRD_B
(output)
tSURYUWR
tHURYUWR
UMRDY_B
(input)
tSUMDUWR
tHUMDUWR
Hi-Z
Hi-Z
UMD[7:0]
(output)
tAUMDUWR
tFUMDUWR
Parameter
Symbol
Conditions
MIN.
10
4
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UMAD[11:0] setup to UMWR_B
UMAD[11:0] hold from UMWR_B
UMSL_B setup to UMWR_B
UMSL_B hold from UMWR_B
UMRD_B setup to UMWR_B
UMRD_B hold from UMWR_B
UMWR_B low level pulse width
UMRDY_B setup to UMWR_B
UMRDY_B hold from UMWR_B
UMD[7:0] setup to UMWR_B
UMD[7:0] hold from UMWR_B
UMD[7:0] active time to UMWR_B
UMD[7:0] floating time from UMWR_B
tSUMAUWR
tHUMAUWR
tSUSLUWR
tHUSLUWR
tSURDUWR
tHURDUWR
tWLUWR
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5
0
5
0
50
25
10
15
4
tSURYUWR
tHURYUWR
tSUMDUWR
tHUMDUWR
tAUMDUWR
tFUMDUWR
Load 50 pF
Load 50 pF
15
4
28
Data Sheet S14828EJ5V0DS
µPD98501
<Write cycle : Motorola mode>
tSUMADSW
tHUMADSW
tHUSLDSW
tHRWDSW
UMAD[11:0]
(output)
tSUSLDSW
UMSL_B
(output)
tSRWDSW
UMWR_B
(as R/W : output)
tWLDSW
UMRD_B
(as DS : output)
tSDAKDSW
tHDAKDSW
UMRDY_B
(as DACK : input)
tSUMDDSW
tHUMDDSW
Hi-Z
Hi-Z
UMD[7:0]
(output)
tAUMDDSW
tFUMDDSW
Parameter
UMAD[11:0] setup to DS
UMAD[11:0] hold from DS
UMSL_B setup to DS
UMSL_B hold from DS
R/W setup to DS
Symbol
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUMADSW
tHUMADSW
tSUSLDSW
tHUSLDSW
tSRWDSW
tHRWDSW
tWLDSW
Load 50 pF
10
4
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5
0
5
R/W hold from DS
0
DS low level pulse width
DACK setup to DS
50
25
10
15
4
tSDAKDSW
tHDAKDSW
tSUMDDSW
tHUMDDSW
tAUMDDSW
tFUMDDSW
DACK hold from DS
UMD[7:0] setup to DS
UMD[7:0] hold from DS
UMD[7:0] active time to DS
UMD[7:0] floating time from DS
Load 50 pF
Load 50 pF
15
4
29
Data Sheet S14828EJ5V0DS
µPD98501
(8) Ethernet interface parameter
(8)-1 Ethernet 1
<MII data transmission>
MITCLK
(input)
tDMTEMTK
tDMTEMTK
MITE
(output)
tDMTDMTK
tDMTDMTK
MITD[3:0]
(output)
tDMTRMTK
tDMTRMTK
MITER
(output)
Parameter
Symbol
tDMTEMTK
tDMTDMTK
Conditions
MIN.
MAX.
Unit
ns
MITE output delay from MITCLK
Load 50 pF
Load 50 pF
0
0
20 Note
20 Note
MITD[3:0] output delay from
MITCLK
ns
MITER output delay from MITCLK
tDMTRMTK
Load 50 pF
0
20 Note
ns
Note In MII Spec., Maximum output delay is specified as 25 ns
30
Data Sheet S14828EJ5V0DS
µPD98501
<MII data reception>
MIRCLK
(input)
tSMRVMRK
tHMRVMRK
MIRDV
(input)
tSMRDMRK
tHMRDMRK
MIRD[3:0]
(input)
tSMRRMRK
tHMRRMRK
MIRER
(input)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
MIRDV setup time to MIRCLK
MIRDV hold time from MIRCLK
tSMRVMRK
tHMRVMRK
tSMRDMRK
tHMRDMRK
tSMRRMRK
tHMRRMRK
10
10
10
10
10
10
MIRD[3:0] setup time to MIRCLK
MIRD[3:0] hold time from MIRCLK
MIRER setup time to MIRCLK
MIRER hold time from MIRCLK
<MII interface signals>
tWHMCL
MICOL
(input)
tWHMCS
MICRS
(input)
Parameter
Symbol
tWHMCL
Conditions
MIN.
MAX.
Unit
ns
2.0 × tCYMTK
2.0 × tCYMTK
MICOL high level pulse width
MICRS high level pulse width
tWHMCS
ns
31
Data Sheet S14828EJ5V0DS
µPD98501
<MII management interface>
MIMCLK
(output)
tSMMDMCK tHMMDMCK
MIMD
(input)
tAMMDMCK
tDMMDMCK
tFMMDMCK
MIMD
(output)
Parameter
Symbol
tSMMDMCK
tHMMDMCK
tAMMDMCK
tDMMDMCK
tFMMDMCK
Condition
MIN.
20
0
MAX.
Unit
ns
MIMD setup to MIMCLK
MIMD hold from MIMCLK
ns
MIMD active delay from MIMCLK
MIMD output delay from MIMCLK
MIMD floating delay from MIMCLK
Load 50 pF
10
10
10
ns
Load 50 pF
Load 50 pF
20
ns
ns
32
Data Sheet S14828EJ5V0DS
µPD98501
(8)-2 Ethernet 2
<MII data transmission>
MI2TCLK
(input)
tD2TE2TK
tD2TE2TK
MI2TE
(output)
tD2TD2TK
tD2TD2TK
MI2TD[3:0]
(output)
tD2TR2TK
tD2TR2TK
MI2TER
(output)
Parameter
Symbol
tD2TE2TK
tD2TD2TK
tD2TR2TK
Conditions
Load 50 pF
MIN.
MAX.
Unit
ns
MI2TE output delay from MI2TCLK
MI2TD[3:0] output delay from MI2TCLK
MI2TER output delay from MI2TCLK
0
0
0
20 Note
20 Note
20 Note
Load 50 pF
Load 50 pF
ns
ns
Note In MII Spec., Maximum output delay is specified as 25 ns
33
Data Sheet S14828EJ5V0DS
µPD98501
<MII data reception>
MI2RCLK
(input)
tS2RV2RK
tH2RV2RK
MI2RDV
(input)
tS2RD2RK
tH2RD2RK
MI2RD[3:0]
(input)
tS2RR2RK
tH2RR2RK
MI2RER
(input)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
MI2RDV setup time to MI2RCLK
MI2RDV hold time from MI2RCLK
MI2RD[3:0] setup time to MI2RCLK
MI2RD[3:0] hold time from MI2RCLK
MI2RER setup time to MI2RCLK
MI2RER hold time from MI2RCLK
tS2RV2RK
tH2RV2RK
tS2RD2RK
tH2RD2RK
tS2RR2RK
tH2RR2RK
10
10
10
10
10
10
<MII interface signals>
tWH2CL
MI2COL
(input)
tWH2CS
MI2CRS
(input)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
2.0 × tCY2TK
2.0 × tCY2TK
MI2COL high level pulse width
MI2CRS high level pulse width
tWH2CL
tWH2CS
ns
34
Data Sheet S14828EJ5V0DS
µPD98501
<MII management interface>
MI2MCLK
(output)
tS2MD2CK tH2MD2CK
MI2MD
(input)
tA2MD2CK
tD2MD2CK
tF2MD2CK
MI2MD
(output)
Parameter
Symbol
tS2MD2CK
tH2MD2CK
tA2MD2CK
tD2MD2CK
tF2MD2CK
Condition
MIN.
20
0
MAX.
Unit
ns
MI2MD setup to MI2MCLK
MI2MD hold from MI2MCLK
ns
MI2MD active delay from MI2MCLK
MI2MD output delay from MI2MCLK
MI2MD floating delay from MI2MCLK
Load 50 pF
Load 50 pF
Load 50 pF
10
10
10
ns
20
ns
ns
35
Data Sheet S14828EJ5V0DS
µPD98501
(9) USB interface parameter
External Circuitry
The USB line I/O signals (refer to chapter 1.8 USB interface) need 4 external resistors to adjust the output
impedance (R1 and R2 = 22 Ω each), to code the full speed USB mode (R3 = 1.5 kΩ) and to protect the output driver
of the USBDM pin (R4 = 51 kΩ). The following figure shows a typical connection diagram.
R3
EVDD = 3.3 V
µPD98501
R1
R2
USBDP
to USB Connector
USBDM
GND
R4
Parameter: USBDM, USBDP
<Data signal rise and fall>
Rise time
Fall time
90%
90%
CL
CL
Differential
Data Lines
10%
10%
tF
tR
<Differential data jitter>
tPERIOD = 1/tDRATE
Crossover points
Differential
Data Lines
n × tPERIOD + tDJ1
Next transitions
Paired transitions
n × tPERIOD + tDJ2
<Differential-to-EOP transition skew and EOP width>
tPERIOD = 1/tDRATE
Crossover
points extended
Crossover points
Differential
Data Lines
n × tPERIOD + tDEOP
tEOPT, tEOPR
36
Data Sheet S14828EJ5V0DS
µPD98501
<Differential transition interval width>
tPERIOD = 1/tDRATE
VIL
Differential
Data Lines
tFST
<Receiver jitter tolerance>
tPERIOD = 1/tDRATE
Differential
Data Lines
tJR1
tJR2
Next transitions
n x tPERIOD + tJR1
Paired transitions
(n+1) x tPERIOD + tJR2
Parameter
Symbol
tR
Condition
MIN.
1.0
MAX.
Unit
ns
Rise time
Load 50 pF
Load 50 pF
tR/tF
20.0
20.0
Fall time
tF
1.0
ns
Differential rise and fall time matching
Full-speed data rate
Source jitter total
tFRFM
tDRATE
90.0
11.97
111.1
12.13
%
Mbps
ns
(including frequency tolerance):
To next transition
−3.5
−4.0
−2.0
+3.5
+4.0
+5.0
tDJ1
For paired transitions
tDJ2
Source jitter for differential transition to
SE0 transition
tDEOP
ns
ns
Receiver jitter:
−18.5
−9.0
+18.5
+9.0
To next transition
tJR1
For paired transitions
Source SE0 interval of EOP
Receiver SE0 interval of EOP
tJR2
tEOPT
tEOPR
tFST
160.0
82.0
175.0
ns
ns
ns
Width of SE0 interval during differential
transition
14.0
37
Data Sheet S14828EJ5V0DS
µPD98501
(10) Parallel port interface parameter
SDCLK0
tDPOM
POM[7:0]
(output)
Parameter
Symbol
Conditions
Load 50 pF
MIN.
0.0
MAX.
8.0
Unit
ns
POM[7:0] output delay
tDPOM
(11) UART interface parameter
T
BAUDOUT
(internal)
tWLUDO
START
URSDO
(output)
DATA(5-8) PARITY STOP START
tWLUDI
URSDI
(input)
START
DATA(5-8)
PARITY STOP START
Remark The BAUDOUT is equal to the 16X of transmisson baud rate (1/T = 16 × Baud Rate). Customize Baud
Rates can be achieved by selecting proper divisor values for MSB and LSB of baud rate generator.
Parameter
URCLK input frequency
URSDO low level width
URSDI low level width
Symbol
fCYUCK
tWLUDO
tWLUDI
Conditions
MIN.
MAX.
Unit
MHz
ns
18.432
16 × T
16 × T
ns
38
Data Sheet S14828EJ5V0DS
µPD98501
(12) Micro Wire interface parameter
tWHWSK
tWLWSK
tCYWSK
URCTS_B
(as MWSK : output)
tSWSKWCS
tSWCSWSK
tHWCSWSK
URDCD_B
(as MWCS :output)
tAWDOWSK
tDWDOWSK
tDWDOWSK
tFWDOWSK
URDSR_B
(as MWDO : output)
tSWDIWSK
tHWDIWSK
Hi-Z
Hi-Z
Hi-Z
URRTS_B (Read)
(as MWDI : input)
tAWDIWSK
tFWDIWSK
Hi-Z
URRTS_B (Status)
(as MWDI : input)
Parameter
MWSK clock cycle
Symbol
tCYWSK
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
400 × tCYSK0
190 × tCYSK0
190 × tCYSK0
90 × tCYSK0
90 × tCYSK0
90 × tCYSK0
190 × tCYSK0
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
MWSK high time
tWHWSK
MWSK low time
tWLWSK
MWSK setup to MWSK
MWCS setup to MWSK
MWCS hold from MWSK
tSWSKWCS
tSWCSWSK
tHWCSWSK
tAWDOWSK
MWDO output active to floating delay
from MWSK
190 × tCYSK0
190 × tCYSK0
MWDO output delay from MWSK
tDWDOWSK
tFWDOWSK
Load 50 pF
Load 50 pF
ns
ns
MWDO output floating to active delay
from MWSK
10 × tCYSK0
10 × tCYSK0
MWDI setup to MWSK
tSWDIWSK
tHWDIWSK
tAWDIWSK
tFWDIWSK
ns
ns
ns
ns
MWDI hold from MWSK
100 × tCYSK0
40 × tCYSK0
MWCS to status time from MWSK
MWCS to MWDO in 3-state
39
Data Sheet S14828EJ5V0DS
µPD98501
(13) JTAG boundary-scan
JCK
(input)
tSJMS
tHJMS
JMS
(input)
tSJDI
tHJDI
JDI
(input)
tDJDO
tDJDO
JDO
(output)
tWLJRT
JRST_B
(input)
Parameter
JMS Setup Time
Symbol
Conditions
MIN.
15
MAX.
Unit
ns
ns
ns
ns
ns
ns
tSJMS
tHJMS
tSJDI
JMS Hold Time
15
JDI Setup Time
15
JDI Hold Time
tHJDI
15
JDO Output Delay
JRSTB_B Low Pulse Width
tDJDO
tWLJRT
Load 50 pF
25
5 × tCYJCK
40
Data Sheet S14828EJ5V0DS
µPD98501
3. PACKAGE DRAWING
352-PIN TAPE BGA (HEAT SPREADER TYPE) (35x35)
A
A1
A
B
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Q
R
S
T
A2
B W
D
8
7
5
3
6
4
2
1
AE AC AA W U R N L J G E C A
AF AD AB Y V Y P M K H F D B
X
C
Index area
Y
J
H
G
A
L
B
S
K
S
F
E
ITEM MILLIMETERS
M
φ
φ
M
S
S
A B
A
A
A
B
C
D
E
F
35.00 0.20
23.00 MAX.
23.00 MAX.
34.60 0.15
34.60 0.15
35.00 0.20
1.625
M
P
1
2
detail of A part
(Z)
detail of B part
1.27 (T.P.)
0.60 0.10
G
+0.20
0.80
H
J
−0.10
+0.30
1.40
N
−0.20
K
L
0.15
φ
0.75 0.15
M
N
P
Q
R
S
T
0.30
0.25 MIN.
0.10
3.0
2.0
2.0
3.0
W
X
Y
Z
20.19
20.19
C0.4
0.20
S352N7-127-F6-2
41
Data Sheet S14828EJ5V0DS
µPD98501
4. RECOMMENDED SOLDERING CONDITIONS
The µPD98501 should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 4-1. Surface Mounting Type Soldering Conditions
µPD98501N7-F6: 352-pin tape BGA (heat spreader type) (35 × 35)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher),
Count: three times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C
for 10 hours)
IR35-107-3
VPS
Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher),
Count: three times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C
for 10 hours)
VP15-107-3
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together.
42
Data Sheet S14828EJ5V0DS
µPD98501
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
43
Data Sheet S14828EJ5V0DS
µPD98501
VR4120A is a trademark of NEC Corporation.
Micro Wire is a trademark of National Semiconductor Corp.
Ethernet is a trademark of Xerox Corp.
MIPS is a trademark of MIPS Technologies, Inc.
•
The information in this document is current as of August, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
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No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
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Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
相关型号：
UPD98501N7-F6-A
3 CHANNEL(S), 100Mbps, LOCAL AREA NETWORK CONTROLLER, PBGA352, 35 X 35 MM, BGA-352
RENESAS
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