74ABT16240ADGG [NEXPERIA]
16-bit inverting buffer/line driver; 3-stateProduction;
| 型号： | 74ABT16240ADGG |
| 厂家： | 
Nexperia |
| 描述： | 16-bit inverting buffer/line driver; 3-stateProduction 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总11页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ABT16240A
16-bit inverting buffer/line driver; 3-state
Rev. 7 — 7 July 2021
Product data sheet
1. General description
The 74ABT16240A is a 16-bit inverting buffer/line driver with 3-state outputs. The device can be
used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output
enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE
causes the outputs to assume a high-impedance OFF-state. This device is fully specified for
partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the
potentially damaging backflow current through the device when it is powered down.
2. Features and benefits
•
Supply voltage range from 4.5 V to 5.5 V
•
•
•
•
•
•
•
•
•
•
•
•
•
BiCMOS high speed and output drive
Direct interface with TTL levels
Power-up 3-state
IOFF circuitry provides partial Power-down mode operation
Latch-up protection exceeds 500 mA per JESD78B class II level A
16-bit bus interface
Multiple VCC and GND pins minimize switching noise
3-state buffers
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Output capability: +64 mA and -32 mA
Live insertion and extraction permitted
ESD protection:
•
•
HBM JESD-A114E exceeds 2000 V
CDM JESD22-C101-C exceeds 1000 V
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74ABT16240ADGG
-40 °C to +85 °C
TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1
body width 6.1 mm
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
4. Functional diagram
1
1OE
2OE
3OE
4OE
EN1
EN2
EN3
EN4
1A0
1A1
1A2
1A3
1OE
2A0
2A1
2A2
2A3
2OE
1Y0
1Y1
1Y2
1Y3
3A0
3A1
3A2
3A3
3OE
4A0
4A1
4A2
4A3
4OE
3Y0
3Y1
3Y2
3Y3
47
46
44
43
1
2
3
5
6
36
35
33
32
25
30
29
27
26
24
13
14
16
17
48
25
24
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
3A0
3A1
3A2
3A3
4A0
4A1
4A2
4A3
1
1
1
1
1
2
3
4
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
2Y0
2Y1
2Y2
2Y3
4Y0
4Y1
4Y2
4Y3
41
40
38
37
48
8
9
19
20
22
23
11
12
001aad261
001aad262
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
2 / 11
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
5. Pinning information
5.1. Pinning
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y0
1Y1
GND
1Y2
1Y3
2OE
1A0
1A1
GND
1A2
1A3
2
3
4
5
6
7
V
V
CC
CC
8
2Y0
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
3Y2
3Y3
2A0
2A1
GND
2A2
2A3
3A0
3A1
GND
3A2
3A3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
74ABT16240A
V
V
CC
CC
4Y0
4Y1
4A0
4A1
GND
4A2
4A3
3OE
GND
4Y2
4Y3
4OE
001aaj891
Fig. 3. Pin configuration SOT362-1 (TSSOP48)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1OE, 2OE, 3OE, 4OE
1Y0, 1Y1, 1Y2, 1Y3
GND
1, 48, 25, 24
2, 3, 5, 6
1 to 4 output enable (LOW active)
1 data output
ground (0 V)
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
VCC
supply voltage
2 data output
3 data output
4 data output
4 data input
2Y0, 2Y1, 2Y2, 2Y3
3Y0, 3Y1, 3Y2, 3Y3
4Y0, 4Y1, 4Y2, 4Y3
4A0, 4A1, 4A2, 4A3
3A0, 3A1, 3A2, 3A3
2A0, 2A1, 2A2, 2A3
1A0, 1A1, 1A2, 1A3
8, 9, 11, 12
13, 14, 16, 17
19, 20, 22, 23
30, 29, 27, 26
36, 35, 33, 32
41, 40, 38, 37
47, 46, 44, 43
3 data input
2 data input
1 data input
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
3 / 11
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Control
Input
nAn
L
Output
nOE
L
nYn
H
L
H
L
H
X
Z
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
VI
Parameter
Conditions
Min Max Unit
supply voltage
-0.5 +7.0
[1] -1.2 +7.0
[1] -0.5 +5.5
V
input voltage
V
VO
output voltage
output in OFF-state or HIGH-state
VI < 0 V
V
IIK
input clamping current
output clamping current
output current
-18
-
-
mA
mA
IOK
VO < 0 V
-50
IO
output in LOW-state
output in HIGH-state
-
-
-
128 mA
-64 mA
150 °C
Tj
junction temperature
storage temperature
[2]
Tstg
-65 +150 °C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
8. Recommended operating conditions
Table 5. Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
4.5
0
Typ Max Unit
supply voltage
-
-
-
-
-
-
-
-
-
5.5
VCC
-
V
input voltage
V
VIH
HIGH-level input voltage
LOW-level Input voltage
HIGH-level output current
LOW-level output current
2.0
-
V
VIL
0.8
-
V
IOH
-32
-
mA
IOL
32 mA
64 mA
10 ns/V
+85 °C
duty cycle ≤ 50 %; fi ≥ 1 kHz
in free air
-
Δt/ΔV
Tamb
input transition rise and fall rate
ambient temperature
-
-40
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
4 / 11
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
9. Static characteristics
Table 6. Static characteristics
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C Unit
Min Typ Max
Min
Max
VIK
input clamping
voltage
VCC = 4.5 V; IIK = -18 mA
-1.2
-0.9
-
-1.2
-
V
VOH
HIGH-level output
voltage
VI = VIL or VIH
VCC = 4.5 V; IOH = -3 mA
VCC = 5.0 V; IOH = -3 mA
VCC = 4.5 V; IOH = -32 mA
2.5
3.0
2.0
-
2.9
3.4
2.4
-
-
-
2.5
3.0
2.0
-
-
V
V
V
V
-
-
VOL
LOW-level output
voltage
VCC = 4.5 V; IOL = 64 mA;
VI = VIL or VIH
0.42 0.55
0.55
II
input leakage current VCC = 5.5 V; VI = VCC or GND
-
-
±0.01 ±1.0
±5.0 ±100
-
-
±1.0 μA
±100 μA
IOFF
power-off leakage
current
VCC = 0 V; VI or VO ≤ 4.5 V
IO(pu/pd) power-up/power-
VCC = 2.0 V; VO = 0.5 V;
[1]
-
±5.0 ±50
-
±50
μA
down output current VI = GND or VCC; nOE = HIGH
IOZ
OFF-state output
current
VCC = 5.5 V; VI = VIL or VIH
output HIGH-state at VO = 5.5 V
output LOW-state at VO = 0.5 V
-
-
-
1.0
-1.0
1.0
10
-10
50
-
-
-
10
-10
50
μA
μA
μA
ICEX
output high leakage HIGH-state; VO = 5.5 V;
current
VCC = 5.5 V; VI = GND or VCC
VCC = 5.5 V; VO = 2.5 V
VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state
IO
output current
supply current
[2] -180 -70
-50
-180
-50
mA
ICC
-
-
-
-
0.5
8
1.0
19
-
-
-
-
1.0
19
mA
mA
mA
μA
outputs LOW-state
outputs 3-state
0.5
10
1.0
200
1.0
200
ΔICC
additional supply
current
per input pin; VCC = 5.5 V;
one input at 3.4 V and other inputs
at VCC or GND
[3]
[4]
CI
input capacitance
VI = 0 V or VCC
-
-
4
6
-
-
-
-
-
-
pF
pF
CI/O
input/output
capacitance
outputs disabled; VO = 0 V or VCC
[1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms.
From VCC = 2.1 V to VCC = 5 V ± 10 %, a transition time of up to 100 μs is permitted.
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[3] This is the increase in supply current for each input at 3.4 V.
[4] This data sheet limit may vary among suppliers.
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
5 / 11
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V. For test circuit, see Fig. 6.
Symbol Parameter
Conditions
25 °C; VCC = 5.0 V
-40 °C to +85 °C; Unit
VCC = 5.0 V ± 0.5 V
Min
Typ Max
Min
Max
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
LOW to HIGH
propagation delay
nAn to nYn, see Fig. 4
nAn to nYn, see Fig. 4
1.0
2.0
1.5
2.4
2.3
2.7
2.5
3.0
3.0
3.3
3.2
4.1
3.6
1.0
3.7
ns
ns
ns
ns
ns
ns
HIGH to LOW
propagation delay
1.0
1.2
1.2
1.3
1.3
1.0
1.2
1.0
1.6
1.4
3.5
4.2
4.2
4.7
4.1
OFF-state to HIGH nOE to nYn; see Fig. 5
propagation delay
OFF-state to LOW nOE to nYn; see Fig. 5
propagation delay
HIGH to OFF-state nOE to nYn; see Fig. 5
propagation delay
LOW to OFF-state nOE to nYn; see Fig. 5
propagation delay
10.1. Waveforms and test circuit
V
I
input nAn
V
V
M
M
0 V
t
t
PLH
PHL
V
OH
output nYn
V
V
M
M
V
OL
001aaj028
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 4. Input (nAn) to output (nYn) propagation delay
V
I
V
nOE input
M
GND
3.5 V
t
t
PLZ
PZL
V
nYn output
M
V
+ 0.3 V
OL
V
OL
t
t
PHZ
PZH
V
OH
V
- 0.3 V
OH
V
nYn output
M
0 V
001aaj892
VM = 1.5 V
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 5. 3-state output enable and disable times
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
6 / 11
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
t
W
V
I
90 %
90 %
negative
pulse
V
V
M
M
10 %
10 %
0 V
t
t
t
r
f
V
EXT
V
t
CC
r
f
V
I
R
L
L
90 %
90 %
V
V
I
O
positive
pulse
PULSE
GENERATOR
V
V
M
DUT
M
10 %
10 %
C
R
L
0 V
R
T
t
W
001aai298
001aac764
VM = 1.5 V
a. Input pulse definition
b. Test circuit for 3-state outputs
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig. 6. Test circuit for measuring switching times
Table 8. Test data
Input
VI
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH
open
tPLZ, tPZL
tPLH, tPHL
open
3.0 V
1 MHz
500 ns
2.5 ns
50 pF
500 Ω
7.0 V
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
7 / 11
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
11. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
A
H
E
y
Z
48
25
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
24
detail X
w
b
p
e
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
Unit
max
(1)
(2)
A
A
A
A
b
c
D
E
e
H
L
1
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
°
8
0
0.15 1.05
0.05 0.85
0.28 0.2 12.6 6.2
0.17 0.1 12.4 6.0
8.3
7.9
0.8 0.50
0.4 0.35
0.8
0.4
mm nom 1.2
min
0.25
0.5
0.25 0.08 0.1
°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
sot362-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
03-02-19
13-08-05
SOT362-1
MO-153
Fig. 7. Package outline SOT362-1 (TSSOP48)
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
8 / 11
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
12. Abbreviations
Table 9. Abbreviations
Acronym
BiCMOS
DUT
Description
Bipolar CMOS
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Charged Device Model
Transistor-Transistor Logic
HBM
CDM
TTL
13. Revision history
Table 10. Revision history
Document ID
74ABT16240A v.7
Modifications:
Release date
20210707
Data sheet status
Change notice
Supersedes
Product data sheet
-
74ABT16240A v.6
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Fig. 7: Package outline drawing SOT362-1 (TSSOP48) updated.
Type number 74ABT16240ADL (SOT370-1/SSOP48) removed.
Section 1 and Section 2 updated.
74ABT16240A v.6
Modifications:
20111103
Product data sheet
-
74ABT16240A v.5
•
Legal pages updated
74ABT16240A v.5
74ABT16240A v.4
74ABT16240A v.3
20100525
20090325
20040212
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
-
74ABT16240A v.4
74ABT16240A v.3
74ABT_H16240A v.2
74ABT_H16240A
-
-
01-A15420
74ABT_H16240A v.2 19980225
853-1880 19019
-
74ABT_H16240A
19961001
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
9 / 11
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
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14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
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and products using Nexperia products, and Nexperia accepts no liability for
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Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
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[2] The term 'short data sheet' is explained in section "Definitions".
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Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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modifications or additions. Nexperia does not give any representations or
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data sheet shall define the specification of the product as agreed between
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accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
10 / 11
Nexperia
74ABT16240A
16-bit inverting buffer/line driver; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................3
6. Functional description................................................. 4
7. Limiting values............................................................. 4
8. Recommended operating conditions..........................4
9. Static characteristics....................................................5
10. Dynamic characteristics............................................ 6
10.1. Waveforms and test circuit........................................ 6
11. Package outline.......................................................... 8
12. Abbreviations..............................................................9
13. Revision history..........................................................9
14. Legal information......................................................10
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 7 July 2021
©
74ABT16240A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 7 — 7 July 2021
11 / 11
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