74AHCT594PW_技术文档

74AHC594; 74AHCT594

8-bit shift register with output register

Rev. 4 — 7 July 2021

Product data sheet

1. General description

The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with

Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that

feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding

clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is

provided for cascading purposes.

Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect

both clocks together, the shift register will always be one count pulse ahead of the storage register.

2. Features and benefits

•

Wide supply voltage range from 2.0 V to 5.5 V

•

Balanced propagation delays

All inputs have Schmitt-trigger action

Overvoltage tolerant inputs to 5.5 V

High noise immunity

CMOS low power dissipation

8-bit serial-in, parallel-out shift register with storage

Independent direct overriding clears on shift and storage registers

Independent clocks for shift and storage registers

Latch-up performance exceeds 100 mA per JESD 78 Class II Level A

Input levels:

•

For 74AHC594: CMOS level

For 74AHCT594: TTL level

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Multiple package options

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Applications

•

Serial-to parallel data conversion

Remote control holding register

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

4. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74AHC594D

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74AHCT594D

74AHC594PW

74AHCT594PW

74AHC594BQ

74AHCT594BQ

TSSOP16

plastic thin shrink small outline package; 16 leads; SOT403-1

body width 4.4 mm

DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 16 terminals;

body 2.5 × 3.5 × 0.85 mm

SOT763-1

5. Functional diagram

14

DS

11

10

SHCP

SHR

8-STAGE SHIFT REGISTER

8-BIT STORAGE REGISTER

9

Q7S

12

13

STCP

STR

15

1

2

3

4

5

6

7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

mbc320

Fig. 1. Functional diagram

SHCP STCP

11 12

13

12

10

11

STR

R2

C2

STCP

SHR

Q7S

9

15

1

R1 SRG8

C1/

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

SHCP

14

15

1

DS

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q7S

1D

2D

2

DS

14

3

2

3

4

5

6

7

10

13

9

SHR STR

mbc319

mbc322

Fig. 2. Logic symbol

Fig. 3. IEC logic symbol

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74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

2 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

STAGE 0

STAGES 1 TO 6

STAGE 7

DS

Q7S

D

Q

FFSH0

CP

D

Q

D

Q

FFSH7

CP

R

SHCP

SHR

D

FFST0

CP

D

FFST7

CP

Q

R

STCP

STR

mbc321

Q0

Q1 Q2 Q3 Q4 Q5 Q6

Q7

Fig. 4. Logic diagram

6. Pinning information

6.1. Pinning

74AHC594

74AHCT594

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

Q1

Q2

Q3

Q4

Q5

Q6

Q7

V

CC

Q0

DS

STR

STCP

SHCP

SHR

Q7S

9

GND

001aae343

Fig. 5. Pin configuration SOT109-1 (SO16)

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74AHC_AHCT594

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Product data sheet

Rev. 4 — 7 July 2021

3 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

74AHC594

74AHCT594

terminal 1

index area

2

3

4

5

6

7

15

14

13

12

11

10

Q2

Q0

Q3

Q4

Q5

Q6

Q7

DS

STR

STCP

SHCP

SHR

74AHC594

74AHCT594

(1)

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Q1

Q2

Q3

Q4

Q5

Q6

Q7

V

CC

Q0

DS

STR

STCP

SHCP

SHR

Q7S

001aae345

Transparent top view

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND

GND

001aae344

Fig. 6. Pin configuration SOT403-1 (TSSOP16)

Fig. 7. Pin configuration SOT763-1 (DHVQFN16)

6.2. Pin description

Table 2. Pin description

Symbol

Description

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

15, 1, 2, 3, 4, 5, 6, 7

parallel data output

GND

Q7S

SHR

SHCP

STCP

STR

DS

8

ground (0 V)

9

serial data output

10

11

12

13

14

16

shift register reset input (active LOW)

shift register clock input

storage register clock input

storage register reset input (active LOW)

serial data input

V_CC

supply voltage

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74AHC_AHCT594

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Product data sheet

Rev. 4 — 7 July 2021

4 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

7. Functional description

Table 3. Function table

H = HIGH voltage state; L = LOW voltage state; ↑ = LOW to HIGH transition; X = don’t care; NC = no change.

Input

Output

Q7S

L

Function

SHCP STCP SHR STR

DS

X

Qn

NC

L

X

↑

X

↑

L

X

L

a LOW-state on SHR only affects the shift register

a LOW-state on STR only affects the storage register

empty shift register loaded into storage register

X

L

X

NC

H

X

L

X

H

Q6S

NC

logic HIGH level shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).

X

↑

H

X

NC

QnS

contents of shift register stages (internal QnS) are transferred to

the storage register and parallel output stages

Q6S

contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

SHCP

DS

STCP

SHR

STR

Q0

Q1

Q6

Q7

Q7S

mbc323

Fig. 8. Timing diagram

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74AHC_AHCT594

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Product data sheet

Rev. 4 — 7 July 2021

5 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

8. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

V_I

Parameter

Conditions

Min

-0.5

-20

-25

-

Max

+7.0

-

Unit

V

supply voltage

input voltage

V

I_IK

input clamping current

output clamping current

output current

V_I< -0.5 V

[1]

mA

°C

I_OK

V_O< -0.5 V or V_O> V_CC+ 0.5 V

V_O= -0.5 V to (V_CC+ 0.5 V)

+20

+25

+75

-

I_O

I_CC

supply current

I_GND

T_stg

P_tot

ground current

-75

-65

-

storage temperature

total power dissipation

+150

500

T_amb= -40 °C to +125 °C

[2]

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SOT109-1 (SO16) package: P_totderates linearly with 12.4 mW/K above 110 °C.

For SOT403-1 (TSSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

For SOT763-1 (DHVQFN16) package: P_totderates linearly with 11.2 mW/K above 106 °C.

9. Recommended operating conditions

Table 5. Operating conditions

Symbol Parameter

Conditions

74AHC594

74AHCT594

Unit

Min

2.0

0

Typ

Max

5.5

Min

4.5

0

Typ

Max

5.5

V_CC

V_I

supply voltage

input voltage

5.0

V

-

5.5

-

5.5

V_O

output voltage

ambient temperature

0

-

V_CC

+125

100

20

0

-

V_CC

T_amb

Δt/ΔV

-40

-

+25

-40

-

+25

+125 °C

input transition rise and fall rate V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

-

ns/V

-

20

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74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

6 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

10. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

74AHC594

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

V_CC= 3.0 V

V_CC= 5.5 V

V_CC= 2.0 V

V_CC= 3.0 V

V_CC= 5.5 V

V_I= V_IHor V_IL

1.5

-

1.5

-

1.5

-

V

2.1

3.85

-

3.85

-

3.85

-

V_IL

LOW-level

input voltage

-

0.5

0.9

1.65

-

0.5

0.9

1.65

-

0.5

0.9

1.65

V_OH

HIGH-level

output voltage

I_O= -50 μA; V_CC= 2.0 V

1.9

2.9

4.4

2.0

3.0

4.5

-

1.9

2.9

-

1.9

2.9

-

V

I_O= -50 μA; V_CC= 3.0 V

I_O= -50 μA; V_CC= 4.5 V

4.4

I_O= -4.0 mA; V_CC= 3.0 V 2.58

I_O= -8.0 mA; V_CC= 4.5 V 3.94

2.48

3.80

2.40

3.70

-

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 50 μA; V_CC= 2.0 V

-

0

-

0.1

-

0.1

-

0.1

V

I_O= 50 μA; V_CC= 3.0 V

I_O= 50 μA; V_CC= 4.5 V

I_O= 4 mA; V_CC= 3.0 V

I_O= 8 mA; V_CC= 4.5 V

V

0.1

V

0.36

0.1

0.44

1.0

0.55

2.0

V

-

V

I_I

input leakage V_I= 5.5 V or GND;

current V_CC= 0 V to 5.5 V

-

μA

I_CC

C_I

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

-

4.0

10

-

40

10

-

80

10

μA

pF

input

V_I= V_CCor GND

3

capacitance

©

74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

7 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

Symbol Parameter

74AHCT594

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

2.0

-

2.0

-

V

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= -50 μA; V_CC= 4.5 V

4.4

4.5

-

4.4

-

4.4

-

V

I_O= -8.0 mA; V_CC= 4.5 V 3.94

V_I= V_IHor V_IL

3.80

3.70

V_OL

LOW-level

output voltage

I_O= 50 μA; V_CC= 4.5 V

I_O= 8 mA; V_CC= 4.5 V

input leakage V_I= 5.5 V or GND;

current V_CC= 0 V to 5.5 V

-

0

-

0.1

0.36

0.1

-

0.1

0.44

1.0

-

0.1

0.55

2.0

V

I_I

-

μA

I_CC

ΔI_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

-

4.0

-

40

-

80

μA

additional

per input pin;

1.35

1.5

mA

supply current V_I= V_CC- 2.1 V; other pins

at V_CCor GND; I_O= 0 A;

V_CC= 4.5 V to 5.5 V

C_I

input

V_I= V_CCor GND

-

3

10

-

10

-

10

pF

capacitance

11. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 15.

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

74AHC594

t_PLH

LOW to HIGH SHCP to Q7S; see Fig. 9

propagation

delay

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

5.2

8.5

2.2

3.0

9.7

2.2

3.0

10.6 ns

14.3 ns

C_L= 50 pF

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

7.4 11.5

13.2

-

3.8

4.8

6.3

8.0

1.7

2.4

7.2

9.1

1.7

2.4

7.8

ns

C_L= 50 pF

10.0 ns

STCP to Qn; see Fig. 10

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

5.1

8.3

2.3

3.3

9.5

2.3

3.3

10.6 ns

14.7 ns

C_L= 50 pF

7.3 11.9

13.6

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

3.5

4.8

5.7

7.8

1.8

2.6

6.5

9.0

1.8

2.6

7.1

9.8

ns

C_L= 50 pF

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74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

8 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

t_PHL

HIGH to LOW SHCP to Q7S; see Fig. 9

propagation

delay

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

5.5

8.9

2.3

3.0

10.2

13.9

2.3

3.0

11.0 ns

15.1 ns

C_L= 50 pF

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

7.4 12.1

-

4.1

5.4

6.7

8.8

1.9

2.5

7.6

1.9

2.5

8.2

ns

C_L= 50 pF

10.1

11.0 ns

STCP to Qn; see Fig. 10

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

5.5

9.1

2.4

3.2

10.4

13.8

2.4

3.2

11.3 ns

15.0 ns

C_L= 50 pF

7.3 12.0

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

3.7

5.2

6.0

8.5

1.9

2.6

6.9

9.7

1.9

2.6

7.5

ns

C_L= 50 pF

10.5 ns

SHR to Q7S; see Fig. 13

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

5.7

9.5

2.3

3.6

10.8

14.0

2.3

3.6

11.7 ns

15.2 ns

C_L= 50 pF

7.5 12.2

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

4.1

5.4

6.7

8.8

2.0

2.8

7.6

2.0

2.8

8.2

ns

C_L= 50 pF

10.1

11.0 ns

STR to Qn; see Fig. 12

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

5.8

9.6

2.8

3.8

11.0

14.4

2.8

3.8

12.0 ns

15.6 ns

C_L= 50 pF

7.7 12.5

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

4.1

5.4

7.2

9.4

2.2

3.0

8.2

2.2

3.0

8.9

ns

C_L= 50 pF

10.7

11.6 ns

f_max

maximum

frequency

SHCP or STCP;

see Fig. 9 and Fig. 10

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

80

90

125

170

-

70

80

-

65

70

-

MHz

t_W

pulse width

SHCP and STCP HIGH or

LOW; see Fig. 9 and Fig. 10

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

6.0

5.5

-

6.5

6.0

-

7.0

6.5

-

ns

SHR and STR HIGH or

LOW; see Fig. 13 and Fig. 12

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

5.0

-

5.0

5.2

-

5.5

5.7

-

ns

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74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

9 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

t_su

set-up time

DS to SHCP; see Fig. 11

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

SHR to STCP; see Fig. 14

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

SHCP to STCP; see Fig. 10

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

DS to SHCP; see Fig. 11

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

3.5

3.0

-

3.5

3.0

-

4.0

3.5

-

ns

8.0

5.0

-

9.0

5.0

-

9.5

5.5

-

ns

8.0

5.0

-

8.5

5.0

-

9.0

5.5

-

ns

t_h

hold time

1.5

2.0

-

1.5

2.0

-

2.0

2.5

-

ns

t_rec

recovery time SHR to SHCP; see Fig. 13

V_CC= 3.0 V to 3.6 V

4.2

2.9

-

4.8

3.3

-

5.3

3.8

-

ns

V_CC= 4.5 V to 5.5 V

STR to STCP; see Fig. 12

V_CC= 3.0 V to 3.6 V

4.6

3.2

-

5.3

3.7

-

5.8

4.3

-

ns

pF

V_CC= 4.5 V to 5.5 V

C_PD

power

f_i= 1 MHz; V_I= GND to V_CC[2]

55

dissipation

capacitance

74AHCT594; V_CC= 4.5 V to 5.5 V

t_PLHLOW to HIGH SHCP to Q7S; see Fig. 9

propagation

delay

C_L= 15 pF

C_L= 50 pF

-

3.8

4.8

6.3

8.0

1.7

2.2

7.2

9.1

1.7

2.2

7.8

9.9

ns

STCP to Qn; see Fig. 10

C_L= 15 pF

-

3.5

4.6

5.7

7.7

1.8

2.6

6.5

8.8

1.8

2.6

7.1

9.6

ns

C_L= 50 pF

t_PHL

HIGH to LOW SHCP to Q7S; see Fig. 9

propagation

delay

C_L= 15 pF

-

4.1

5.4

6.7

8.8

1.8

2.4

7.6

1.8

2.4

8.3

ns

C_L= 50 pF

10.1

11.0 ns

STCP to Qn; see Fig. 10

C_L= 15 pF

-

3.7

5.2

6.1

8.5

1.9

2.6

6.9

9.7

1.9

2.6

7.2

ns

C_L= 50 pF

10.5 ns

SHR to Q7S; see Fig. 13

C_L= 15 pF

-

4.3

5.4

7.0

8.8

2.4

2.7

8.0

2.4

2.7

8.7

ns

C_L= 50 pF

10.1

11.0 ns

STR to Qn; see Fig. 12

C_L= 15 pF

-

4.5

5.7

7.4

9.4

-

2.3

3.1

80

8.4

10.7

-

2.3

3.1

70

9.2

11.7 ns

MHz

ns

C_L= 50 pF

f_max

maximum

frequency

SHCP or STCP;

90

160

-

see Fig. 9 and Fig. 10

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74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

10 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

t_W

pulse width

SHCP and STCP HIGH or

LOW; see Fig. 9 and Fig. 10

5.5

-

6.0

-

6.5

-

ns

SHR and STR HIGH or

5.2

-

5.5

-

6.0

-

LOW; see Fig. 13 and Fig. 12

t_su

set-up time

hold time

DS to SHCP; see Fig. 11

SHR to STCP; see Fig. 14

SHCP to STCP; see Fig. 10

DS to SHCP; see Fig. 11

3.0

5.0

2.0

2.9

3.4

-

3.0

5.0

2.0

3.3

3.8

-

3.5

5.5

2.5

3.8

4.3

-

ns

pF

-

t_h

-

t_rec

recovery time SHR to SHCP; see Fig. 13

STR to STCP; see Fig. 12

-

C_PD

power

f_i= 1 MHz; V_I= GND to V_CC[2]

55

dissipation

capacitance

[1] Typical values are measured at nominal supply voltage (V_CC= 3.3 V and V_CC= 5.0 V).

[2] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PDx V_CC²x f_ix N + Σ(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_Lx V_CC²x f_o) = sum of the outputs.

11.1. Waveforms and test circuit

1/f

max

SHCP input

V

M

t

W

t

PHL

PLH

Q7S output

V

M

t

TLH

THL

001aae341

Measurement points are given in Table 8.

Fig. 9. Shift register clock pulse width, maximum frequency and input to output propagation delays

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74AHC_AHCT594

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Product data sheet

Rev. 4 — 7 July 2021

11 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

V

SHCP input

M

t

su

1/f

max

V

t

M

STCP input

Qn outputs

t

W

t

PHL

PLH

V

M

mla512

Measurement points are given in Table 8.

Fig. 10. Shift register clock to storage register clock set-up time and storage clock pulse width, maximum

frequency and input to output propagation delays

V

SHCP input

M

t

su

t

h

V

DS input

M

V

Q7 output

M

001aae342

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 11. Shift register clock to data input set-up and hold times

V

M

STR input

t

W

t

rec

V

M

STCP input

t

PHL

V

M

Qn outputs

mbc325

Measurement points are given in Table 8.

Fig. 12. Storage register reset pulse width, input to output propagation delay and recovery time

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74AHC_AHCT594

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Product data sheet

Rev. 4 — 7 July 2021

12 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

V

M

SHR input

SHCP input

Q7S output

t

W

t

rec

V

M

t

PHL

V

M

mbc324

Measurement points are given in Table 8.

Fig. 13. Shift register reset pulse width, input to output propagation delay and recovery time

V

M

SHR input

t

su

V

M

STCP input

V

M

Qn outputs

mbc326

Measurement points are given in Table 8.

Fig. 14. Shift register reset to storage register clock set-up time

Table 8. Measurement points

Type

Input

V_M

Output

V_M

74AHC594

0.5 x V_CC

1.5 V

0.5 x V_CC

74AHCT594

©

74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

13 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

t

W

V

I

90 %

negative

pulse

V

M

10 %

GND

t

r

f

t

f

r

V

I

90 %

positive

pulse

M

10 %

GND

t

W

V

CC

V

I

V

O

G

DUT

R

T

C

L

001aah768

For test data see Table 9.

Definitions for test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

Fig. 15. Test circuit for measuring switching times

Table 9. Test data

Type

Input

V_I

Load

Test

t_r, t_f

C_L

74AHC594

V_CC

3.0 V

≤ 3.0 ns

15 pF, 50 pF

t_PLH, t_PHL

74AHCT594

©

74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

14 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

12. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.0100

0.0075

0.010 0.057

0.004 0.049

0.019

0.014

0.39

0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig. 16. Package outline SOT109-1 (SO16)

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74AHC_AHCT594

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Product data sheet

Rev. 4 — 7 July 2021

15 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

1

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig. 17. Package outline SOT403-1 (TSSOP16)

©

74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

16 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

SOT763-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

7

L

1

8

9

E

h

e

16

15

10

D

h

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

1

b

c

E

h

e

y

D

E

L

v

w

y

1

h

max.

0.05 0.30

0.00 0.18

3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT763-1

- - -

MO-241

- - -

Fig. 18. Package outline SOT763-1 (DHVQFN16)

©

74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

17 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

13. Abbreviations

Table 10. Abbreviations

Acronym

CDM

CMOS

DUT

Description

Charged Device Model

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

LSTTL

MM

Low-power Schottky Transistor-Transistor Logic

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

20210707 Product data sheet

Type numbers 74AHC594DB and 74AHCT594DB (SOT338-1/SSOP16) removed.

20200625 Product data sheet 74AHC_AHCT594 v.2

Change notice Supersedes

74AHC_AHCT594 v.4

Modifications:

-

74AHC_AHCT594 v.3

•

74AHC_AHCT594 v.3

Modifications:

-

•

The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Section 2 updated.

Table 4: Derating values for P_tottotal power dissipation updated.

74AHC_AHCT594 v.2

Modifications:

20080609

Product data sheet

-

74AHC_AHCT594 v.1

•

The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•

Legal texts have been adapted to the new company name where appropriate.

Table 6: the conditions for input leakage current have been changed.

74AHC_AHCT594 v.1

20060704

Product data sheet

-

©

74AHC_AHCT594

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 July 2021

18 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

15. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

©

74AHC_AHCT594

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Product data sheet

Rev. 4 — 7 July 2021

19 / 20

Nexperia

74AHC594; 74AHCT594

8-bit shift register with output register

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Applications.................................................................. 1

4. Ordering information....................................................2

5. Functional diagram.......................................................2

6. Pinning information......................................................3

6.1. Pinning.........................................................................3

6.2. Pin description.............................................................4

7. Functional description................................................. 5

8. Limiting values............................................................. 6

9. Recommended operating conditions..........................6

10. Static characteristics..................................................7

11. Dynamic characteristics.............................................8

11.1. Waveforms and test circuit.......................................11

12. Package outline........................................................ 15

13. Abbreviations............................................................18

14. Revision history........................................................18

15. Legal information......................................................19

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 7 July 2021

©

74AHC_AHCT594

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Product data sheet

Rev. 4 — 7 July 2021

20 / 20


型号：	74AHCT594PW
厂家：	Nexperia
描述：	8-bit shift register with output registerProduction
文件：	总20页 (文件大小：301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AHCT594PW [NEXPERIA]

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