74ALVCH16373DGG [NEXPERIA]
2.5 V/3.3 V 16-bit D-type transparent latch; 3-stateProduction;型号: | 74ALVCH16373DGG |
厂家: | Nexperia |
描述: | 2.5 V/3.3 V 16-bit D-type transparent latch; 3-stateProduction 驱动 光电二极管 逻辑集成电路 |
文件: | 总14页 (文件大小:233K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Rev. 8 — 22 November 2021
Product data sheet
1. General description
The 74ALVCH16373 is a 16-bit D-type transparent latch with bus hold inputs and 3-state outputs.
The device can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The
device features two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each
controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the
latches are transparent, a latch output will change each time its corresponding D-input changes.
When nLE is LOW the latches store the information that was present at the inputs a set-up time
preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a
high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. This
device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables
the output, preventing the potentially damaging backflow current through the device when it is
powered down.
2. Features and benefits
•
Wide supply voltage range from 1.2 V to 3.6 V
•
•
•
•
•
•
•
•
CMOS low power dissipation
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Latch-up performance exceeds 100 mA per JESD78 Class II Level B
Output drive capability 50 Ω transmission lines at 85 °C
Complies with JEDEC standards:
•
•
•
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
•
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
•
•
Current drive ±24 mA at VCC = 3.0 V
Specified from -40 °C to +85 °C
3. Ordering information
Table 1. Ordering information
Type number
Temperature range Package
Name
Description
Version
74ALVCH16373DGG -40 °C to +85 °C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
4. Functional diagram
1
24
1
1OE
1LE
2OE
2LE
1EN
C1
48
24
25
1OE
2OE
2EN
C4
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
5
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
3D
1
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
6
8
5
9
6
11
12
13
14
16
17
19
20
22
23
8
9
11
12
13
14
16
17
19
20
22
23
4D
2
1LE
48
2LE
25
001aam007
001aam009
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
V
CC
data input
to internal circuit
mna705
Fig. 3. Bus hold circuit
1D0
D
Q
1Q0
2D0
D
Q
2Q0
LATCH
LATCH
1
9
LE LE
LE LE
1LE
2LE
1OE
2OE
to 7 other channels
to 7 other channels
001aam010
Fig. 4. Logic diagram
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
2 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
5. Pinning information
5.1. Pinning
74ALVCH16373
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q0
1Q1
GND
1Q2
1Q3
1LE
1D0
1D1
GND
1D2
1D3
2
3
4
5
6
7
V
V
CC
CC
8
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
V
CC
CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
2D4
2D5
GND
2D6
2D7
2LE
001aam008
Fig. 5. Pin configuration SOT362-1 (TSSOP48)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1OE, 2OE
1, 24
output enable input (active LOW)
data outputs
1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7
2, 3, 5, 6, 8, 9, 11, 12
2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7
13, 14, 16, 17, 19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
data outputs
GND
ground (0 V)
VCC
positive supply voltage
data inputs
1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7
2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7
1LE, 2LE
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
48, 25
data inputs
latch enable input (active HIGH)
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
3 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;
L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;
Z = high-impedance OFF-state.
Inputs
Internal latches
Outputs nQn
Operating mode
nOE
L
nLE
H
H
L
nDn
L
H
l
L
L
enable and read register
(transparent mode)
L
H
L
H
L
L
latch and read register
(hold mode)
L
L
h
l
H
L
H
Z
Z
H
L
latch register and disable
outputs
H
L
h
H
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-0.5
-
Max
+4.6
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
control inputs
data inputs
[1]
[1]
+4.6
VCC + 0.5
±50
V
IOK
VO
output clamping current
output voltage
VO > VCC or VO < 0 V
mA
V
[1]
-0.5
-
VCC + 0.5
±50
IO
output current
VO = 0 V to VCC
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
100
ground current
-100
-65
-
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +85 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
4 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
maximum speed performance
CL = 30 pF
2.3
3.0
1.2
0
-
-
-
-
-
-
-
-
-
2.7
3.6
3.6
VCC
5.5
VCC
+85
20
V
CL = 50 pF
V
low voltage applications
data inputs
V
VI
input voltage
V
control inputs
0
V
VO
output voltage
0
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
in free air
-40
0
°C
ns/V
ns/V
VCC = 2.3 V to 3.0 V
VCC = 3.0 V to 3.6 V
0
10
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = -40 °C to +85 °C
VIH
HIGH-level input
voltage
VCC = 1.2 V
VCC
-
-
V
V
V
V
V
V
V
V
VCC = 1.8 V
0.7VCC
0.9
1.2
1.5
-
-
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
1.7
-
-
2.0
VIL
LOW-level input
voltage
-
-
-
-
0
VCC = 1.8 V
0.9
1.2
1.5
0.2VCC
0.7
0.8
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI = VIH or VIL
VOH
HIGH-level output
voltage
IO = -100 μA; VCC = 1.8 V to 3.6 V
IO = -6 mA; VCC = 1.8 V
IO = -6 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -18 mA; VCC = 2.3 V
IO = -24 mA; VCC = 3.0 V
VI = VIH or VIL
VCC - 0.2
VCC
-
-
-
-
-
-
-
V
V
V
V
V
V
V
VCC - 0.4 VCC - 0.1
VCC - 0.3 VCC - 0.08
VCC - 0.5 VCC - 0.17
VCC - 0.5 VCC - 0.14
VCC - 0.6 VCC - 0.26
VCC - 1.0 VCC - 0.28
VOL
LOW-level output
voltage
IO = 100 μA; VCC = 1.8 V to 3.6 V
IO = 6 mA; VCC = 1.8 V
IO = 6 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 18 mA; VCC = 2.3 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
-
-
-
0
0.20
0.30
0.20
0.40
0.40
0.60
0.55
V
V
V
V
V
V
V
0.09
0.07
0.15
0.14
0.23
0.27
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
5 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
II
input leakage current VCC = 1.8 V to 3.6 V
control input; VI = 5.5 V or GND
-
-
0.1
0.1
5
5
μA
μA
data input; VI = VCC or GND
VI = VIH or VIL; VO = VCC or GND
VCC = 1.8 V to 2.7 V
IOZ
ILIZ
ICC
ΔICC
OFF-state output
current
-
-
0.1
0.1
5
μA
μA
VCC = 2.7 V to 3.6 V
10
OFF-state input
leakage current
VI = VCC or GND
VCC = 1.8 V to 2.7 V
-
-
0.1
0.1
10
15
μA
μA
VCC = 3.6 V
supply current
VI = VCC or GND; IO = 0 A;
VCC = 1.8 V to 2.7 V
-
-
0.2
0.2
40
40
μA
μA
VCC = 2.7 V to 3.6 V
additional supply
current
VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V
per control input
-
5
500
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
pF
per data I/O input
-
150
750
IBHL
IBHH
IBHLO
IBHHO
CI
bus hold LOW current VCC = 2.3 V; VI = 0.7 V
VCC = 3.0 V; VI = 0.8 V
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
45
-
-
-
-
-
-
-
-
-
-
75
150
bus hold HIGH current VCC = 2.3 V; VI = 1.7 V
VCC = 3.0 V; VI = 2.0 V
-45
-75
300
450
-300
-450
-
-
-175
bus hold LOW
overdrive current
VCC = 2.7 V
VCC = 3.6 V
VCC = 2.7 V
VCC = 3.6 V
-
-
-
bus hold HIGH
overdrive current
-
input capacitance
5.0
[1] All typical values are measured at Tamb = 25 °C.
[2] Valid for data inputs of bus hold parts only.
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
6 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 10.
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = -40 °C to +85 °C
tpd
propagation delay
nDn to nQn; see Fig. 6
VCC = 1.2 V
[2]
[3]
-
8.8
3.2
2.1
2.3
2.1
-
ns
ns
ns
ns
ns
VCC = 1.8 V
1.5
1.0
1.0
1.0
5.7
3.9
3.7
3.3
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
nLE to nQn; see Fig. 7
VCC = 1.2 V
[4]
[2]
-
7.4
3.4
2.2
2.2
2.2
-
ns
ns
ns
ns
ns
VCC = 1.8 V
1.5
1.0
1.0
1.0
5.9
3.9
3.5
3.2
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
VCC = 3.0 V to 3.6 V
nOE to nQn; see Fig. 8
VCC = 1.2 V
[4]
[5]
ten
enable time
-
8.9
4.0
2.6
2.9
2.3
-
ns
ns
ns
ns
ns
VCC = 1.8 V
1.5
1.0
1.0
1.0
7.3
5.2
4.9
4.2
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
VCC = 3.0 V to 3.6 V
nOE to nQn; see Fig. 8
VCC = 1.2 V
[4]
[6]
tdis
disable time
-
8.9
3.2
2.2
3.1
2.8
-
ns
ns
ns
ns
ns
VCC = 1.8 V
1.5
1.0
1.0
1.0
5.6
4.1
4.7
4.1
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
[4]
VCC = 3.0 V to 3.6 V
nLE HIGH; see Fig. 7
VCC = 1.8 V
tW
pulse width
set-up time
3.5
3.0
3.0
2.5
1.0
1.0
1.0
1.0
-
-
-
-
ns
ns
ns
ns
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
[4]
VCC = 3.0 V to 3.6 V
nDn to nLE; see Fig. 9
VCC = 1.8 V
tsu
1.0
1.0
1.0
1.0
-0.1
-0.1
-0.1
0.0
-
-
-
-
ns
ns
ns
ns
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
[4]
VCC = 3.0 V to 3.6 V
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74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
7 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
th
hold time
nDn to nLE; see Fig. 9
VCC = 1.8 V
1.2
1.5
1.5
1.2
0.1
0.2
0.4
0.2
-
-
-
-
ns
ns
ns
ns
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
VCC = 3.0 V to 3.6 V
per flip-flop; VI = GND to VCC
outputs enabled
[4]
[7]
CPD
power dissipation
capacitance
-
-
16
10
-
-
pF
pF
outputs disabled
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
.
[3] Typical values are measured at VCC = 2.5 V.
[4] Typical values are measured at VCC = 3.3 V.
[5] ten is the same as tPZL and tPZH
.
[6] tdis is the same as tPLZ and tPHZ
.
[7] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of the outputs.
10.1. Waveforms and test circuit
V
I
V
V
t
nDn input
M
M
GND
t
PHL
PLH
V
OH
nQn output
V
V
M
M
V
OL
001aam011
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig. 6. Propagation delay, input (nDn) to data output (nQn)
V
I
nLE input
V
V
V
t
M
M
M
GND
t
W
t
PHL
PLH
V
OH
nQn output
V
V
M
M
V
OL
001aam012
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig. 7. Propagation delay, latch enable input (nLE) to data output (nQn), and pulse width
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
8 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
V
I
nOE input
V
V
M
M
t
GND
t
PLZ
PZL
V
CC
nQn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
nQn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal795
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig. 8. 3-state enable and disable times
V
I
nDn input
nLE input
V
M
GND
t
t
h
h
t
t
su
su
V
I
V
M
GND
001aam013
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 9. Data setup and hold times for input (nDn) to input (nLE)
Table 8. Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
2.3 V to 2.7 V and < 2.3 V VCC
0.5 × VCC
1.5 V
1.5 V
0.5 × VCC
1.5 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOH - 0.15 V
VOH - 0.3 V
VOH - 0.3 V
2.7 V
2.7 V
2.7 V
3.0 V to 3.6 V
1.5 V
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
9 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 10. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
tPHZ, tPZH
2.3 V to 2.7 V and
< 2.3 V
VCC
≤ 2.0 ns
30 pF
500 Ω
2 × VCC
GND
2.7 V
2.7 V
2.7 V
2.5 ns
2.5 ns
50 pF
50 pF
500 Ω
500 Ω
open
open
2 × VCC
2 × VCC
GND
GND
3.0 V to 3.6 V
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
10 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
11. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
A
H
E
y
Z
48
25
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
24
detail X
w
b
p
e
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
Unit
max
(1)
(2)
A
A
A
A
b
c
D
E
e
H
L
1
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
°
8
0
0.15 1.05
0.05 0.85
0.28 0.2 12.6 6.2
0.17 0.1 12.4 6.0
8.3
7.9
0.8 0.50
0.4 0.35
0.8
0.4
mm nom 1.2
min
0.25
0.5
0.25 0.08 0.1
°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
sot362-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
03-02-19
13-08-05
SOT362-1
MO-153
Fig. 11. Package outline SOT362-1 (TSSOP48)
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
11 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
ESD
DUT
HBM
MM
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Device Under Test
Human Body Model
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
Release date
20211122
Data sheet status
Change notice Supersedes
74ALVCH16373 v.8
Modifications:
Product data sheet
-
74ALVCH16373 v.7
•
Section 1 and Section 2 updated.
74ALVCH16373 v.7
Modifications:
20190130 Product data sheet
-
74ALVCH16373 v.6
•
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Type number 74ALVCH16373DL (SOT370-1) removed.
Package outline drawing SOT362-1 (TSSOP48) updated.
74ALVCH16373 v.6
Modifications:
20120710
Product data sheet
-
-
74ALVCH16373 v.5
74ALVCH16373 v.4
•
Table 8 corrected (errata).
74ALVCH16373 v.5
Modifications:
20111117
Product data sheet
•
Legal pages updated.
74ALVCH16373 v.4
74ALVCH16373 v.3
74ALVCH16373 v.2
74ALVCH16373 v.1
20100531
19990920
19980629
19970321
Product data sheet
Product specification
Product specification
Product specification
-
-
-
-
74ALVCH16373 v.3
74ALVCH16373 v.2
74ALVCH16373 v.1
-
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
12 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
13 / 14
Nexperia
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................3
6. Functional description................................................. 4
7. Limiting values............................................................. 4
8. Recommended operating conditions..........................5
9. Static characteristics....................................................5
10. Dynamic characteristics............................................ 7
10.1. Waveforms and test circuit........................................ 8
11. Package outline........................................................ 11
12. Abbreviations............................................................12
13. Revision history........................................................12
14. Legal information......................................................13
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 22 November 2021
©
74ALVCH16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 22 November 2021
14 / 14
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