74ALVCH16600DGG_技术文档

74ALVCH16600

18-bit universal bus transceiver; 3-state

Rev. 3 — 15 January 2018

Product data sheet

1 General description

The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-state

bus compatible outputs in both send and receive directions. Data flow in each direction

is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA),

and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if

CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in

the flip-flop on the HIGH-to-LOW transition of CPAB. When OEAB is LOW, the outputs

are active. When OEAB is HIGH, the outputs are in the high-impedance state. The HIGH

clock can be controlled with the clock-enable inputs (CEBA and CEAB).

Data flow for B-to-A is similar to that of A-to-B, but uses OEBA, LEBA and CPBA.

To ensure the high impedance state during power up or power down, OEBA and OEAB

should be tied to V_CCthrough a pullup resistor; the minimum value of the resistor is

determined by the current-sinking/current-sourcing capability of the driver.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic

level.

2 Features and benefits

• CMOS low power consumption

• MultiByte flow-through standard pin-out architecture

• Low inductance multiple V_CCand GND pins for minimum noise and ground bounce

• Direct interface with TTL levels (2.7 V to 3.6 V)

• Bus hold on data inputs

• Output drive capability 50 Ω transmission lines at 85 °C

• Current drive ±24 mA at 3.0 V

• Complies with JEDEC standards:

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V)

• ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

– CDM JESD22-C101E exceeds 1000 V

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

3 Ordering information

Table 1.ꢀOrdering information

Type number

Package

Temperature range

Name

Description

Version

74ALVCH16600DGG −40 °C to +85 °C

TSSOP56

plastic thin shrink small outline package;

56 leads; body width 6.1 mm

SOT364-1

4 Functional diagram

1

OEAB

CEAB

CPAB

LEAB

EN1

G2

56

55

2

2C3

C3

G2

27

29

30

28

OEBA

CEBA

CPBA

LEBA

EN4

G5

A0

A1

B0

3

5

54

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

5C6

C6

B1

A2

B2

6

G5

A3

B3

8

3

54

A4

B4

A0

B0

3D

4

1

9

A5

B5

6D

10

12

13

14

15

16

17

19

20

21

23

24

26

5

6

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

A6

B6

A1

A2

B1

A7

B7

B2

8

A8

B8

A3

B3

9

A9

B9

A4

B4

10

12

13

14

15

16

17

19

20

21

23

24

26

A10

A11

A12

A13

A14

A15

A16

A17

B10

B11

B12

B13

B14

B15

B16

B17

A5

B5

A6

B6

A7

B7

A8

B8

A9

B9

A10

A11

A12

A13

A14

A15

A16

A17

B10

B11

B12

B13

B14

B15

B16

B17

OEAB

LEAB

CPAB

CEAB

OEBA

LEBA

CPBA

CEBA

1

2

27

28

30

29

55

aaa-028028

aaa-028029

Figure 1.ꢀLogic symbol

Figure 2.ꢀIEC logic symbol

V

CC

data input

to internal circuit

001aal733

Figure 3.ꢀBus hold circuit

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

2 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

CPBA

LEBA

CEBA

OEBA

CPAB

LEAB

CEAB

OEAB

CE

C1

CP

Bn

An

1D

CE

C1

CP

1D

18 identical channels

to 17 other channels

aaa-028030

Figure 4.ꢀLogic diagram (one section)

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

3 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

5 Pinning information

5.1 Pinning

74ALVCH16600

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

OEAB

LEAB

A0

CEAB

CPAB

B0

2

3

4

GND

A1

GND

B1

5

6

A2

B2

7

V

CC

A3

8

B3

9

A4

A5

B4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

B5

GND

A6

GND

B6

A7

B7

A8

B8

A9

B9

A10

A11

GND

A12

A13

A14

B10

B11

GND

B12

B13

B14

V

CC

A15

A16

B15

B16

GND

A17

GND

B17

OEBA

LEBA

CPBA

CEBA

aaa-028031

Figure 5.ꢀPin configuration for TSSOP56

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

4 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

5.2 Pin description

Table 2.ꢀPin description

Symbol

Description

A0, A1, A2, A3, A4, A5, A6, A7, A8,

3, 5, 6, 8, 9, 10, 12, 13, 14,

data inputs/outputs

A9, A10, A11, A12, A13, A14, A15, A16, A17 15, 16, 17, 19, 20, 21, 23, 24, 26

B0, B1, B2, B3, B4, B5, B6, B7, B8, 54, 52, 51, 49, 48, 47, 45, 44, 43,

B9, B10, B11, B12, B13, B14, B15, B16, B17 42, 41, 40, 38, 37, 36, 34, 33, 31

data outputs/inputs

OEAB, OEBA

LEAB, LEBA

CPBA, CPAB

CEBA, CEAB

1, 27

A to B / B to A output enable input

(active LOW)

2, 28

A to B / B to A latch enable inputs

(active HIGH)

30, 55

29, 56

B to A / A to B clock inputs

(active LOW)

B to A / A to B clock enable inputs

(active LOW)

GND

V_CC

4, 11, 18, 25, 32, 39, 46, 53

7, 22, 35, 50

ground (0 V)

supply voltage

6 Functional description

Table 3.ꢀFunction selection ^{[1] [2]}

Operating mode

Inputs

Outputs

CEAB

OEAB

LEAB

CPAB

An

X

H

L

Bn

Z

Disabled

X

H

L

H

L

X

H

L

X

↓

Transparent

H

L

Hold

X

h

NC

H

Clock data & Display

L

↓

l

L

Hold data & Display

L

H

L

X

NC

L

[1] A-to-B data flow is shown; B-to-A flow is similar but uses CEBA, OEBA, LEBA, and CPBA.

[2] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the enable or clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the enable or clock transition;

X = don’t care;

NC = no change

↓ = HIGH-to-LOW enable or clock transition;

Z = high-impedance OFF-state.

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

5 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

7 Limiting values

Table 4.ꢀLimiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

-0.5

-50

-

Max

Unit

V_CC

V_I

supply voltage

input voltage

+4.6

V

[1]

data inputs

V_CC+ 0.5 V

+4.6

V_CC+ 0.5 V

control inputs

V

V_O

I_IK

output voltage

input clamping current

output clamping current

output current

V_I< 0 V

-

mA

I_OK

I_O

V_O> V_CCor V_O< 0 V

V_O= 0 V to V_CC

±50

100

-

mA

°C

-

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

-100

−65

-

storage temperature

total power dissipation

+150

600

[2]

T_amb= −40 °C to +85 °C

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For TSSOP56 packages: above 55 °C derate linearly with 8 mW/K.

8 Recommended operating conditions

Table 5.ꢀRecommended operating conditions

Symbol Parameter

Conditions

Min

Max

Unit

V_CC

supply voltage

V_CC= 2.5 V:

2.3

2.7

V

for maximum speed performance at C_L= 30 pF

V_CC= 3.3 V:

3.0

3.6

V

for maximum speed performance at C_L= 50 pF

V_I

input voltage

0

V_CC

+85

20

V

V_O

output voltage

V

T_amb

Δt/ΔV

ambient temperature

in free air

−40

0

°C

input transition rise and fall rate V_CC= 2.3 V to 3.0 V

V_CC= 3.0 V to 3.6 V

ns/V

0

10

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

6 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

9 Static characteristics

Table 6.ꢀStatic characteristics

At recommended operating conditions. T_amb= -40 °C to +85 °C; Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

1.7

2.0

-

Typ ^[1]

Max

-

Unit

V

V_IH

HIGH-level input

V_CC= 2.3 to 2.7 V

1.2

voltage

V_CC= 2.7 to 3.6 V

1.5

-

V

V_IL

LOW-level input

voltage

V_CC= 2.3 to 2.7 V

1.2

0.7

0.8

V

V_CC= 2.7 to 3.6 V

-

1.5

V

V_OH

HIGH-level output

voltage

V_I= V_IHor V_IL

I_O= -100 μA; V_CC= 2.3 V to 3.6 V

I_O= -6 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.7 V

I_O= -12 mA; V_CC= 3.0 V

I_O= -24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

V_CC- 0.2

V_CC

-

V

V_CC- 0.3 V_CC- 0.08

V_CC- 0.6 V_CC- 0.26

V_CC- 0.5 V_CC- 0.14

V_CC- 0.6 V_CC- 0.09

V_CC- 1.0 V_CC- 0.28

V_OL

LOW-level output

voltage

I_O= 100 μA; V_CC= 2.3 V to 3.6 V

I_O= 6 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

GND

0.07

0.15

0.14

0.27

0.1

-

0.20

V

0.40

V

-

0.70

V

-

0.40

V

-

0.55

V

I_I

input leakage current V_I= V_CCor GND; V_CC= 2.3 V to 3.6 V

-

5

-

μA

I_BHL

bus hold LOW

current

V_CC= 2.3 V; V_I= 0.7 V

V_CC= 3.0 V; V_I= 0.8 V

V_CC= 2.3 V; V_I= 1.7 V

V_CC= 3.0 V; V_I= 2.0 V

V_CC= 3.6 V

45

75

-45

-75

500

150

-

I_BHH

bus hold HIGH

current

-

-175

-

I_BHLO

I_BHHO

I_OZ

bus hold LOW

overdrive current

-

bus hold HIGH

overdrive current

V_CC= 3.6 V

-500

-

μA

OFF-state output

current

V_CC= 2.7 V to 3.6 V; V_I= V_IHor V_IL;

V_O= V_CCor GND

0.1

10

I_CC

supply current

V_CC= 2.3 to 3.6 V; V_I= V_CCor GND; I_O= 0 A

-

0.2

40

μA

ΔI_CC

additional supply

current

V_I= V_CC- 0.6 V; I_O= 0 A;

V_CC= 2.3 V to 3.6 V

150

750

C_I

input capacitance

-

4.0

8.0

-

pF

C_I/O

input/output

capacitance

[1] All typical values are measured at T_amb= 25 °C.

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

7 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

10 Dynamic characteristics

Table 7.ꢀDynamic characteristics

Voltages are referenced to GND (ground = 0 V). T_amb= -40 °C to +85 °C; For test circuit, see Figure 10.

Symbol Parameter

Conditions

Min

Typ ^[1]

Max

Unit

[2]

t_pd

propagation delay

An to Bn; Bn to An; Figure 6

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

-

3.1

2.8

5.2

4.7

4.2

ns

V_CC= 3.0 V to 3.6 V

LEAB to Bn; LEBA to An; Figure 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

-

3.6

3.4

3.1

6.2

5.5

4.9

ns

V_CC= 3.0 V to 3.6 V

CPAB to Bn; CPBA to An; Figure 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

-

3.8

2.9

7.3

6.8

5.7

ns

V_CC= 3.0 V to 3.6 V

OEAB to Bn; OEBA to An; Figure 8

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.3

t_en

t_dis

t_w

enable time

disable time

pulse width

1.0

-

3.1

3.3

2.8

6.5

6.3

5.2

ns

V_CC= 3.0 V to 3.6 V

OEAB to Bn; OEBA to An; Figure 8

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.1

1.0

-

2.8

3.3

3.2

5.1

4.7

4.4

ns

V_CC= 3.0 V to 3.6 V

LEAB HIGH; LEBA HIGH; Figure 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.2

3.3

1.6

1.0

-

ns

V_CC= 3.0 V to 3.6 V

CPAB HIGH or LOW;

CPBA HIGH or LOW; Figure 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

3.3

2.0

1.4

1.1

-

ns

V_CC= 3.0 V to 3.6 V

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

8 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

Symbol Parameter

Conditions

Min

Typ ^[1]

Max

Unit

t_su

set-up time

An to CPAB; Bn to CPBA; Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.3

1.2

−0.1

−0.4

−0.1

-

ns

V_CC= 3.0 V to 3.6 V

An to LEAB; Bn to LEBA; Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.2

1.1

0.1

−0.2

0.3

-

ns

V_CC= 3.0 V to 3.6 V

CEAB to CPAB; CEBA to CPBA; Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

0.7

0.8

−0.4

−0.7

−0.2

-

ns

V_CC= 3.0 V to 3.6 V

An to CPAB; Bn to CPBA; Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

t_h

hold time

1.5

1.8

1.5

0.6

0.4

-

ns

V_CC= 3.0 V to 3.6 V

An to LEAB; Bn to LEBA; Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.2

1.6

1.3

0.6

0.1

-

ns

V_CC= 3.0 V to 3.6 V

CEAB to CPAB; CEBA to CPBA; Figure 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.4

1.7

1.4

2.0

0.6

0.4

-

ns

V_CC= 3.0 V to 3.6 V

f_max

maximum frequency CPAB, CPBA; Figure 7

V_CC= 2.3 V to 2.7 V

150

335

350

362

-

MHz

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

[3]

C_PD

power dissipation

capacitance

per latch; V_I= GND to V_CC

output enabled

-

21

3

-

pF

output disabled

[1] Typical values are measured at T_amb= 25 °C

Typical values for V_CC= 2.3 V to 2.7 V are measured at V_CC= 2.5 V

Typical values for V_CC= 3.0 V to 3.6 V are measured at V_CC= 3.3 V

[2] t_pdis the same as t_PHLand t_PLH; t_enis the same as t_PZHand t_PZL; t_disis the same as t_PHZand t_PLZ

.

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW):

P_D= C_PD× V_CC²× f_i× N + ∑(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

∑(C_L× V_CC²× f_o) = sum of outputs.

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

9 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

10.1 Waveforms and test circuit

V

I

An, Bn

input

V

t

V

t

M

GND

PHL

PLH

V

OH

Bn, An

output

V

M

001aal734

V

OL

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Figure 6.ꢀThe input An, Bn to output Bn, An propagation delay times.

1/f

max

CPBA, CPAB

input

V

I

V

M

LEBA, LEAB

input

GND

t

W

t

PLH

PHL

V

OH

An, Bn

output

V

M

V

M

V

OL

aaa-028032

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Figure 7.ꢀLatch enable input LEAB, LEBA and clock input CPAB, CPBA to output Bn, An propagation delay times;

pulse width and f_maxof CPAB and CPBA

V

I

OEAB, OEBA

input

V

t

M

GND

t

PLZ

PZL

V

CC

An, Bn output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

An, Bn output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

aaa-028033

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Figure 8.ꢀ3-state enable and disable times.

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

10 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

V

I

An, Bn

input

V

M

V

t

V

M

GND

t

su

t

h

su

V

I

CPAB, CPBA,

LEAB, LEBA

input

V

M

GND

aaa-028034

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Figure 9.ꢀData set-up and hold times for An and Bn inputs to LEAB, LEBA, CPAB or CPBA inputs.

Table 8.ꢀMeasurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

V_X

V_Y

2.3 V to 2.7 V

2.7 V

V_CC

0.5 V_CC

1.5 V

0.5 V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH- 0.15 V

V_OH- 0.3 V

2.7 V

3.0 V to 3.6 V

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

11 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Figure 10.ꢀTest circuit for measuring switching times

Table 9.ꢀTest data

Supply voltage

V_CC

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2 × V_CC

t_PHZ, t_PZH

GND

2.3 V to 2.7 V

2.7 V

V_CC

≤ 2.0 ns

≤ 2.5 ns

30 pF

50 pF

500 Ω

2.7 V

open

GND

3.0 V to 3.6 V

open

GND

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

12 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

11 Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Figure 11.ꢀPackage outline SOT364-1 (TSSOP56)

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

13 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

12 Abbreviations

Table 10.ꢀAbbreviations

Acronym

CDM

Description

Charged Device Model

CMOS

DUT

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

TTL

Transistor-Transistor Logic

13 Revision history

Table 11.ꢀRevision history

Document ID

Release date

20180115

Data sheet status

Change notice

Supersedes

74ALVCH16600 v.3

Modifications:

Product data sheet

-

74ALVCH16600 v.2

• The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

74ALVCH16600 v.2

74ALVCH16600 v.1

19980924

19980801

Product specification

-

74ALVCH16600 v.1

-

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

14 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

14 Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

14.2 Definitions

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

Draft — The document is a draft version only. The content is still under

such equipment or applications and therefore such inclusion and/or use is at

internal review and subject to formal approval, which may result in

the customer’s own risk.

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

Short data sheet — A short data sheet is an extract from a full data sheet

without further testing or modification. Customers are responsible for the

with the same product type number(s) and title. A short data sheet is

design and operation of their applications and products using Nexperia

intended for quick reference only and should not be relied upon to contain

products, and Nexperia accepts no liability for any assistance with

detailed and full information. For detailed and full information see the

applications or customer product design. It is customer’s sole responsibility

relevant full data sheet, which is available on request via the local Nexperia

to determine whether the Nexperia product is suitable and fit for the

sales office. In case of any inconsistency or conflict with the short data sheet,

customer’s applications and products planned, as well as for the planned

the full data sheet shall prevail.

application and use of customer’s third party customer(s). Customers should

provide appropriate design and operating safeguards to minimize the risks

associated with their applications and products. Nexperia does not accept

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

any liability related to any default, damage, costs or problem which is based

Nexperia and its customer, unless Nexperia and customer have explicitly

on any weakness or default in the customer’s applications or products, or

agreed otherwise in writing. In no event however, shall an agreement be

the application or use by customer’s third party customer(s). Customer is

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

responsible for doing all necessary testing for the customer’s applications

and products using Nexperia products in order to avoid a default of the

applications and the products or of the application or use by customer’s third

party customer(s). Nexperia does not accept any liability in this respect.

14.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

Limited warranty and liability — Information in this document is believed

damage to the device. Limiting values are stress ratings only and (proper)

to be accurate and reliable. However, Nexperia does not give any

operation of the device at these or any other conditions above those

representations or warranties, expressed or implied, as to the accuracy

given in the Recommended operating conditions section (if present) or the

or completeness of such information and shall have no liability for the

Characteristics sections of this document is not warranted. Constant or

consequences of use of such information. Nexperia takes no responsibility

repeated exposure to limiting values will permanently and irreversibly affect

for the content in this document if provided by an information source outside

the quality and reliability of the device.

of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation -

lost profits, lost savings, business interruption, costs related to the removal

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

or replacement of any products or rework charges) whether or not such

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

damages are based on tort (including negligence), warranty, breach of

in a valid written individual agreement. In case an individual agreement is

contract or any other legal theory. Notwithstanding any damages that

concluded only the terms and conditions of the respective agreement shall

customer might incur for any reason whatsoever, Nexperia's aggregate and

apply. Nexperia hereby expressly objects to applying the customer’s general

cumulative liability towards customer for the products described herein shall

terms and conditions with regard to the purchase of Nexperia products by

customer.

be limited in accordance with the Terms and conditions of commercial sale of

Nexperia.

No offer to sell or license — Nothing in this document may be interpreted

Right to make changes — Nexperia reserves the right to make changes

or construed as an offer to sell products that is open for acceptance or

to information published in this document, including without limitation

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

15 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications. In the event that customer

uses the product for design-in and use in automotive applications to

automotive specifications and standards, customer (a) shall use the product

without Nexperia's warranty of the product for such automotive applications,

use and specifications, and (b) whenever customer uses the product for

automotive applications beyond Nexperia's specifications such use shall be

solely at customer’s own risk, and (c) customer fully indemnifies Nexperia

for any liability, damages or failed product claims resulting from customer

design and use of the product for automotive applications beyond Nexperia's

standard warranty and Nexperia's product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

14.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

74ALVCH16600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 15 January 2018

16 / 17

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

Contents

1

General description ............................................ 1

2

3

4

5

5.1

5.2

6

7

8

Features and benefits .........................................1

Ordering information .......................................... 2

Functional diagram .............................................2

Pinning information ............................................ 4

Pinning ...............................................................4

Pin description ...................................................5

Functional description ........................................5

Limiting values ....................................................6

Recommended operating conditions ................6

Static characteristics ..........................................7

Dynamic characteristics .....................................8

Waveforms and test circuit .............................. 10

Package outline .................................................13

Abbreviations .................................................... 14

Revision history ................................................ 14

Legal information ..............................................15

9

10

10.1

11

12

13

14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 15 January 2018

Document identifier: 74ALVCH16600


型号：	74ALVCH16600DGG
厂家：	Nexperia
描述：	18-bit universal bus transceiver; 3-stateProduction 光电二极管输出元件逻辑集成电路
文件：	总17页 (文件大小：205K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74ALVCH16600DGG [NEXPERIA]

相关型号：

74ALVCH16600DGG,11

74ALVCH16600DGG-T

74ALVCH16600DGGRE4

74ALVCH16600DGGRG4

74ALVCH16600DGGY

74ALVCH16600DL

74ALVCH16600DL-T

74ALVCH16600DLG4

74ALVCH16600DLRG4

74ALVCH16601

74ALVCH16601DG

74ALVCH16601DG-T