74ALVCH16652DGG_技术文档

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

Rev. 3 — 12 September 2018

Product data sheet

1. General description

The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-

type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the

data bus or from the internal storage registers.

Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock

inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable

(nOEAB and nOEBA) control inputs.

Depending on the select inputs nSAB and nSBA data can directly go from input to output (real-time

mode) or data can be controlled by the clock (storage mode), when OE inputs permit this operating

mode.

The output enable inputs nOEAB and nOEBA determine the operation mode of the transceiver.

When nOEAB is LOW, no data transmission from nBn to nAn is possible and when nOEBA is

HIGH, no data transmission from nBn to nAn is possible.

When nSAB and nSBA are in the real-time transfer mode, it is also possible to store data without

using the internal D-type flip-flops by simultaneously enabling nOEAB and nOEBA. In this

configuration each output reinforces its input.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

2. Features and benefits

•

Wide supply voltage range of 1.2 V to 3.6 V

•

CMOS low power consumption

Direct interface with TTL levels

Current drive ±24 mA at V_CC= 3.0 V.

MULTIBYTE flow-through standard pin-out architecture

Low inductance multiple V_CCand GND pins for minimum noise and ground bounce

All data inputs have bushold

Output drive capability 50 Ω transmission lines at 85 °C

Complies with JEDEC standards:

•

JESD8-5 (2.3 V to 2.7 V)

JESD8B/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

CDM JESD22-C101E exceeds 1000 V

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74ALVCH16652DGG −40 °C to +85 °C

TSSOP56

plastic thin shrink small outline package; 56 leads; SOT364-1

body width 6.1 mm

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

4. Functional diagram

5

6

52

51

49

48

47

45

44

43

15

16

17

19

20

21

23

24

42

1A0

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1B0

1B1

1B2

1B3

1B4

1B5

1B6

1B7

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2B0

41

2B1

8

40

2B2

9

38

2B3

10

12

13

14

37

2B4

36

V

CC

2B5

2B6

2B7

34

33

56

1

29

28

26

31

27

30

1OEBA

1OEAB

1SAB

2OEBA

2OEAB

2SAB

data input

to internal circuit

3

54

2

1SBA

2SBA

1CPAB

1CPBA

2CPAB

2CPBA

55

aaa-029035

001aad245

Fig. 1. Logic symbol

Fig. 2. Bus hold circuit

56

29

2OEBA

1OEBA

1OEAB

1CPBA

1SBA

EN1[BA]

EN2[AB]

C3

EN7[BA]

1

28

30

31

27

26

2OEAB

2CPBA

2SBA

EN8[AB]

C9

55

54

2

G4

G10

1CPAB

1SAB

C5

2CPAB

2SAB

C11

3

G6

G12

52

42

≥1

1

4

3D

1

1B0

≥1

7

10

9D

8

2B0

5

15

1A0

2A0

10 1

5D

1

6

≥1

2

11D

12

1 12

≥1

6

51

49

48

47

45

44

43

16

17

19

20

21

23

24

41

40

38

37

36

34

33

1A1

1A2

1A3

1A4

1A5

1A6

1A7

1B1

1B2

1B3

1B4

1B5

1B6

1B7

2A1

2A2

2A3

2A4

2A5

2A6

2A7

2B1

2B2

2B3

2B4

2B5

2B6

2B7

8

9

10

12

13

14

aaa-029036

Fig. 3. IEC logic symbol

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

2 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

nOEBA

nOEAB

nSBA

nCPBA

nSAB

nCPAB

V

CC

S

D

nAn

Y

1

MUX

Q

D

2

FF

n

CP

V

CC

S

1

D

Y

MUX

nBn

D

Q

D

2

FF

n

CP

8 IDENTICAL CHANNELS

aaa-028365

Fig. 4. Logic diagram (one section)

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

3 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

5. Pinning information

5.1. Pinning

74ALVCH16652

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1OEAB

1CPAB

1SAB

GND

1OEBA

1CPBA

1SBA

GND

2

3

4

5

1A0

1B0

6

1A1

1B1

7

V

CC

8

1A2

1A3

1A4

GND

1A5

1A6

1A7

2A0

2A1

2A2

GND

2A3

2A4

2A5

1B2

1B3

1B4

GND

1B5

1B6

1B7

2B0

2B1

2B2

GND

2B3

2B4

2B5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

V

CC

2A6

2A7

2B6

2B7

GND

2SAB

2CPAB

2OEAB

2SBA

2CPBA

2OEBA

aaa-029037

Fig. 5. Pin configuration for TSSOP56 (SOT364-1)

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

4 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

5.2. Pin description

Table 2. Pin description

Symbol

Description

1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7

2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7

1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7

2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7

1OEBA, 2OEBA

5, 6, 8, 9, 10, 12, 13, 14

data input/output

15, 16, 17, 19, 20, 21, 23, 24

data input/output

52, 51, 49, 48, 47, 45, 44, 43

data output/input

42, 41, 40, 38, 37, 36, 34, 33

data output/input

56, 29

output enable inputs (active-LOW)

output enable inputs (active-HIGH)

select input A-to-B

clock input A-to-B

1OEAB, 2OEAB

1, 28

1SAB, 2SAB

3, 26

1CPAB, 2CPAB

2, 27

1SBA, 2SBA

54, 31

select input B-to-A

clock input B-to-A

1CPBA, 2CPBA

55, 30

GND

4, 11, 18, 25, 32, 39, 46, 53

7, 22, 35, 50

ground (0 V)

V_CC

supply voltage

6. Functional description

Table 3. Function selection

H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition;

Operating mode

Inputs

Data I/O

nAn

nOEAB nOEBA nCPAB nCPBA nSAB

nSBA

nBn

isolation, store A and B data

store A, hold B[1]

L

H

X

L

↑

X

L

X

L

input

L

H or L

input

X

H

L

↑

H or L

input

unspecified[1]

output

store A in both registers

store B, hold A[1]

↑

input

H or L

↑

X

L

unspecified[1] input

store B in both registers

real-time B data to A bus

stored B data to A bus

real-time A data to B bus

stored A data to B bus

L

↑

output

input

L

X

L

input

L

X

H or L

X

H

X

H

input

H

L

X

output

H or L

X

H

input

stored A data to B bus and

stored B data to A bus

H or L

output

[1] The data output functions may be enabled or disabled by various signals at the nOEAB and nOEBA inputs. Data input functions are

always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs.

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

5 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

V_I

Parameter

Conditions

Min

-0.5

-50

-

Max

+4.6

Unit

V

supply voltage

input voltage

[1]

V

V_O

output voltage

V_CC+ 0.5 V

I_IK

input clamping current

output clamping current

V_I< 0 V

-

mA

I_OK

V_O> V_CCor V_O< 0 V

±50

100

-

mA

°C

I_{O (sink/source)}output sink or source current V_O= 0 V to V_CC

-

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

-100

−65

-

storage temperature

total power dissipation

+150

600

T_amb= −40 °C to +85 °C

[2]

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For TSSOP56 packages: above 55 °C derate linearly with 8 mW/K.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter

Conditions

Min

1.2

2.3

Typ

2.4

2.5

Max

3.6

Unit

V

V_CC

supply voltage

for low-voltage applications

for maximum speed performance;

30 pF output load

2.7

V

for maximum speed performance;

50 pF output load

3.0

3.3

3.6

V

V_I

input voltage

0

-

V_CC

+85

20

V

V_O

output voltage

V

T_amb

Δt/ΔV

ambient temperature

input transition rise and fall rate

in free air

-40

-

°C

V_CC= 2.3 V to 3.0 V

V_CC= 3.0 V to 3.6 V

ns/V

-

10

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

6 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V). T_amb= -40 °C to +85 °C

Symbol Parameter

Conditions

Min

1.7

2.0

-

Typ[1]

1.2

Max

-

Unit

V

V_IH

HIGH-level

V_CC= 2.3 V to 2.7 V

input voltage

V_CC= 2.7 V to 3.6 V

1.5

-

V

V_IL

LOW-level

V_CC= 2.3 V to 2.7 V

1.2

0.7

0.8

V

input voltage

V_CC= 2.7 V to 3.6 V

-

1.5

V

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= -100 μA; V_CC= 2.3 V to 3.6 V

I_O= -6 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.7 V

I_O= -12 mA; V_CC= 3.0 V

I_O= -24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

V_CC- 0.2

V_CC- 0.3

V_CC- 0.6

V_CC- 0.5

V_CC- 0.6

V_CC- 1.0

V_CC

-

V

V_CC- 0.08

V_CC- 0.26

V_CC- 0.14

V_CC- 0.09

V_CC- 0.28

V_OL

LOW-level

output voltage

I_O= 100 μA; V_CC= 2.3 V to 3.6 V

I_O= 6 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

V_CC= 2.3 V to 3.6 V; V_I= V_CCor GND

-

GND

0.07

0.15

0.14

0.27

0.1

0.20

0.40

0.70

0.40

0.55

5

V

I_I

input

μA

leakage current

I_OZ

I_CC

ΔI_CC

I_BHL

OFF-state

output current

V_CC= 2.3 V to 3.6 V; V_I= V_IHor V_IL;

V_O= V_CCor GND

-

0.1

0.2

10

40

μA

supply current

V_CC= 2.3 V to 3.6 V; V_I= V_CCor GND;

I_O= 0 A

additional

supply current

per data I/O pin; V_CC= 2.3 V to 3.6 V;

V_I= V_CC- 0.6 V; I_O= 0 A

150

750

bus hold LOW

current

V_CC= 2.3 V; V_I= 0.7 V

V_CC= 3.0 V; V_I= 0.8 V

V_CC= 2.3 V; V_I= 1.7 V

V_CC= 3.0 V; V_I= 2.0 V

V_CC= 3.6 V

45

75

-

150

-

μA

I_BHH

bus hold HIGH

current

-45

-75

500

-175

-

I_BHLO

I_BHHO

C_I

bus hold LOW

overdrive current

bus hold HIGH

overdrive current

V_CC= 3.6 V

-500

-

μA

pF

input capacitance

4.0

[1] All typical values are measured at T_amb= 25 °C.

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

7 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit, see Fig. 11.

Symbol Parameter

Conditions

Min

Typ [1]

Max

Unit

t_pd

propagation delay

nAn to nBn; nBn to nAn; see Fig. 6

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

[2]

1.0

-

2.7

2.8

2.6

4.8

4.5

3.9

ns

V_CC= 3.0 V to 3.6 V

nCPAB to nBn; nCPBA to nAn; see Fig. 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

-

3.4

3.1

2.9

6.8

5.2

4.5

ns

V_CC= 3.0 V to 3.6 V

nSAB to nBn; nSBA to nAn; see Fig. 8

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.4

1.0

-

3.4

3.5

3.1

5.6

6.4

5.3

ns

V_CC= 3.0 V to 3.6 V

nOEAB to nBn; see Fig. 10

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.3

t_en

t_dis

t_w

enable time

disable time

pulse width

[3]

[4]

1.0

-

2.6

2.4

2.2

4.5

4.6

4.0

ns

V_CC= 3.0 V to 3.6 V

nOEBA to nAn; see Fig. 10

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

3.3

-

2.8

3.0

2.2

4.5

4.6

4.0

ns

V_CC= 3.0 V to 3.6 V

nOEAB to nBn; see Fig. 10

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

1.6

-

2.7

3.4

2.7

4.5

5.1

4.5

ns

V_CC= 3.0 V to 3.6 V

nOEBA to nAn; see Fig. 10

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.4

3.3

-

2.5

3.1

2.9

4.5

5.1

4.5

ns

V_CC= 3.0 V to 3.6 V

1.1

nCPAB HIGH or LOW; nCPBA HIGH or LOW;

see Fig. 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.2

3.3

1.2

1.0

0.7

-

ns

V_CC= 3.0 V to 3.6 V

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

8 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

Symbol Parameter

Conditions

Min

Typ [1]

Max

Unit

t_su

set-up time

nAn to nCPAB; nBn to nCPBA; see Fig. 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.2

1.7

1.4

0.2

0.3

-

ns

V_CC= 3.0 V to 3.6 V

nAn to nCPAB; nBn to nCPBA; see Fig. 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

t_h

hold time

0.6

0.4

0.7

0.1

0.2

-

ns

V_CC= 3.0 V to 3.6 V

f_max

maximum frequency nCPAB; nCPBA; see Fig. 7

V_CC= 2.3 V to 2.7 V

150

300

320

-

MHz

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

C_PD

power dissipation

capacitance

per channel; V_I= GND to V_CC

output enabled

[5]

-

22

-

pF

output disabled

4.0

[1] Typical values are measured at T_amb= 25 °C

Typical values for V_CC= 2.3 V to 2.7 V are measured at V_CC= 2.5 V

Typical values for V_CC= 3.0 V to 3.6 V are measured at V_CC= 3.3 V

[2] t_pdis the same as t_PHLand t_PLH

[3] t_enis the same as t_PZHand t_PZL

[4] t_disis the same as t_PHZand t_PLZ

.

[5] C_PDis used to determine the dynamic power dissipation (P_Din μW):

P_D= C_PDx V_CC²x f_ix N + ∑(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

∑(C_Lx V_CC²x f_o) = sum of outputs.

10.1. Waveforms and test circuit

V

I

nAn, nBn input

GND

V

M

t

PLH

PHL

V

OH

nBn, nAn output

V

M

V

OL

aaa-027928

See Table 8 for measurement points.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 6. Input (nAn, nBn) to output (nBn, nAn) propagation delays

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

9 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

1/f

max

V

I

nCPAB, nCPBA

input

V

M

GND

t

W

t

PLH

PHL

V

OH

nBn, nAn output

V

M

V

OL

aaa-029020

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 7. Clock input (nCPAB, nCPBA) to data output (nBn, nAn) propagation delays,

clock pulse width (nCPAB, nCPBA) and maximum clock frequency (nCPAB, nCPBA)

V

I

V

M

nSAB, nSBA input

GND

M

t

PLH

PHL

V

OH

nBn, nAn output

V

M

V

OL

aaa-029038

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 8. Select source inputs (nSAB, nSBA) to data output (nBn, nAn) propagation delays

V

I

nAn, nBn input

GND

V

h

V

M

t

su

t

h

su

V

I

V

M

nCPBA, nCPAB input

M

GND

aaa-029022

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 9. Data set-up and hold times for nAn, nBn inputs to nCPAB and nCPBA inputs

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

10 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

V

I

nOEAB

input

V

M

nOEBA

GND

t

PZL

PLZ

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

output

V

HIGH-to-OFF

OFF-to-HIGH

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

aaa-029039

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 10. 3-state enable and disable times.

Table 8. Measurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

V_X

V_Y

2.3 V to 2.7 V

2.7 V

V_CC

0.5 x V_CC

1.5 V

0.5 x V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH- 0.15 V

V_OH- 0.3 V

2.7 V

3.0 V to 3.6 V

1.5 V

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

11 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig. 11. Test circuit for measuring switching times

Table 9. Test data

Supply voltage

V_CC

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2 × V_CC

t_PHZ, t_PZH

GND

2.3 V to 2.7 V

2.7 V

V_CC

≤ 2.0 ns

≤ 2.5 ns

30 pF

50 pF

500 Ω

2.7 V

open

GND

3.0 V to 3.6 V

open

GND

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

12 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

11. Application information

H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition

aaa-028366

aaa-028367

nOEAB nOEBA nCPAB nCPBA nSAB

nSBA

nOEAB nOEBA nCPAB nCPBA nSAB

nSBA

L

X

L

H

X

L

X

Fig. 12. Real time transfer bus B to bus A

Fig. 13. Real time transfer bus A to bus B

aaa-028369

aaa-028368

nOEAB nOEBA nCPAB nCPBA nSAB

nSBA

nOEAB nOEBA nCPAB nCPBA nSAB

nSBA

H

L

H

L

H or L

X

H

X

H

X

H

X

L

H

X

H

↑

X

↑

X

↑

X

H or L

H

H or L

↑

Fig. 15. Transfer A stored data to B bus or B stored data

to A bus or both at the same time

Fig. 14. Store from bus A, B or A and B in one register

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

13 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

aaa-028370

nOEAB nOEBA nCPAB nCPBA nSAB

nSBA

aaa-028371

X

L

H

L

↑

X

L

nOEAB nOEBA nCPAB nCPBA nSAB

H or L H or L

nSBA

L

H

X

Fig. 16. Store bus A in both registers or store bus B in

both registers

Fig. 17. Isolation

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

14 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

12. Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig. 18. Package outline SOT364-1 (TSSOP56)

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

15 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

13. Abbreviations

Table 10. Abbreviations

Acronym

Description

CDM

CMOS

DUT

ESD

HBM

TTL

Charged Device Model

Complementary Metal-Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date

20180912

Data sheet status

Change notice Supersedes

- 74ALVCH16652 v.2

74ALVCH16652 v.3

Modifications:

Product data sheet

•

The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

Legal texts have been adapted to the new company name where appropriate.

74ALVCH16652 v.2

74ALVCH16652 v.1

19991123

19980831

Product specification

-

74ALVCH16652 v.1

-

Preliminary specification

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

16 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

15. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

17 / 18

Nexperia

74ALVCH16652

16-bit transceiver/register with dual enable; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................4

5.1. Pinning.........................................................................4

5.2. Pin description.............................................................5

6. Functional description................................................. 5

7. Limiting values............................................................. 6

8. Recommended operating conditions..........................6

9. Static characteristics....................................................7

10. Dynamic characteristics............................................ 8

10.1. Waveforms and test circuit........................................ 9

11. Application information............................................13

12. Package outline........................................................ 15

13. Abbreviations............................................................16

14. Revision history........................................................16

15. Legal information......................................................17

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 12 September 2018

©

74ALVCH16652

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 12 September 2018

18 / 18


型号：	74ALVCH16652DGG
厂家：	Nexperia
描述：	16-bit transceiver/register with dual enable; 3-stateProduction
文件：	总18页 (文件大小：255K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74ALVCH16652DGG [NEXPERIA]

相关型号：

74ALVCH16652DGG,11

74ALVCH16652DGG-T

74ALVCH16652DGG:11

74ALVCH16652DGGS

74ALVCH16652DL

74ALVCH16652DL-T

74ALVCH16652PV

74ALVCH16821

74ALVCH16821DGG

74ALVCH16821DGG-T

74ALVCH16821DGGRE4

74ALVCH16821DGGRG4