74ALVCH16821DGG [NXP]
20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State; 20位总线接口D型触发器;正边沿触发三态
| 型号： | 74ALVCH16821DGG |
| 厂家： | 
NXP |
| 描述： | 20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State |
| 文件： | 总12页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ALVCH16821
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
Product specification
IC24 Data Handbook
1998 May 29
Philips
Semiconductors
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
FEATURES
• Wide supply voltage range of 1.2V to 3.6V
DESCRIPTION
The 74ALVCH16821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
• Complies with JEDEC standard no. 8-1A
• Current drive ± 24 mA at 3.0 V
• CMOS low power consumption
• Direct interface with TTL levels
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
TM
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple V and ground pins for minimum noise
CC
and ground bounce
The 74ALVCH16821 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
• All data inputs have bus hold
• Output drive capability 50Ω transmission lines @ 85°C
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t = t ≤ 2.5ns
r f
amb
SYMBOL
/t
PARAMETER
Propagation delay
CONDITIONS
= 2.5V, C = 30pF
TYPICAL
UNIT
ns
V
CC
V
CC
2.6
2.5
L
t
PHL PLH
nCP to nQ
= 3.3V, C = 50pF
n
L
C
C
Input capacitance
5.0
33
17
pF
I
Outputs enabled
Outputs disabled
1
Power dissipation capacitance per buffer
V = GND to V
I CC
pF
PD
V
CC
V
CC
= 2.5V, C = 30pF
250
350
L
F
max
Maximum clock frequency
MHz
= 3.3V, C = 50pF
L
NOTE:
1.
C
is used to determine the dynamic power dissipation (P in mW):
D
PD
2
2
P
D
= C × V
× f + S (C × V
× f ) where:
CC o
PD
CC
i
L
f = input frequency in MHz; C = output load capacitance in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
S (C × V
× f ) = sum of outputs.
L
CC
o
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
74ALVCH16821 DL
ACH16821 DL
74ALVCH16821 DGG
ACH16821 DGG
SOT364-1
2
1998 May 29
853-2066 19467
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
PIN DESCRIPTION
FUNCTION TABLE
PIN NUMBER
SYMBOL
FUNCTION
INPUTS
OUTPUT
Q
55, 54, 52, 51, 49,
48, 47, 45, 44, 43
nOE
CP
Dx
1D0 - 1D9
Data inputs
L
L
↑
↑
L
H
X
X
L
H
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
2D0 - 2D9
1Q0 - 1Q9
2Q0 - 2Q9
1OE, 2OE
1CP, 2CP
GND
L
}
Q0
Z
2, 3, 5, 6, 8,
9, 10, 12, 13, 14
H
X
Data outputs
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
H = HIGH voltage level
L
X
Z
↑
=
=
=
=
=
LOW voltage level
Don’t care
High impedance OFF state
LOW to HIGH clock transition
Output enable inputs
(active-Low)
1, 28
Clock pulse inputs
(active rising edge)
}
Not a LOW-to-HIGH clock transition
56, 29
LOGIC SYMBOL
4, 11, 18, 25,
32, 39, 46, 53
Ground (0V)
1
56
Positive supply
voltage
7, 22, 35, 50
V
CC
1OE
1CP
2
1Q0
55
PIN CONFIGURATION
1D0
1Q1
1Q2
54
52
51
49
48
47
45
44
43
3
5
1D1
1D2
1OE
1Q0
1Q1
GND
1Q2
1Q3
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CP
1D0
1D1
GND
1D2
1D3
6
1Q3
1Q4
1Q5
1Q6
1D3
1D4
3
8
4
9
1D5
1D6
5
10
6
1Q7
1Q8
1Q9
12
13
14
1D7
1D8
V
7
V
CC
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
8
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
9
1D9
2D0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2Q0
2Q1
2Q2
42
41
40
15
16
17
2D1
2D2
2Q3
2Q4
19
20
21
38
37
2D3
2D4
2Q5
2Q6
36
34
2D5
2D6
23
24
26
27
33
31
30
2Q7
2Q8
2Q9
2D7
2D8
2D9
2CP
29
2OE
28
V
V
CC
CC
2Q6
2Q7
GND
2Q8
2Q9
2OE
2D6
2D7
GND
2D8
2D9
2CP
SH00127
SH00001
3
1998 May 29
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
LOGIC SYMBOL (IEEE/IEC)
1
1OE
1CP
2OE
2CP
EN2
C1
EN4
C3
56
28
29
55
54
52
51
49
48
47
45
44
2
3
1D
2
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
5
6
8
9
10
12
13
43
42
41
40
38
37
36
34
33
31
30
14
15
16
17
19
20
21
23
24
26
27
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
4
3D
SH00003
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
D
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
SH00004
4
1998 May 29
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
2.3
2.7
V
CC
V
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
3.0
3.6
V
DC Input voltage range
0
0
V
V
V
V
I
CC
V
O
DC output voltage range
CC
T
amb
Operating free-air temperature range
–40
+85
°C
V
CC
V
CC
= 2.3 to 3.0V
= 3.0 to 3.6V
0
0
20
10
t , t
r
Input rise and fall times
ns/V
f
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +4.6
–50
UNIT
V
V
CC
I
IK
DC input diode current
V t0
I
mA
1
For control pins
–0.5 to +4.6
V
DC input voltage
V
I
1
For data inputs
uV or V t 0
–0.5 to V +0.5
CC
I
DC output diode current
DC output voltage
V
O
"50
mA
V
OK
CC
O
V
O
Note 1
= 0 to V
CC
–0.5 to V +0.5
CC
I
O
DC output source or sink current
V
O
"50
"100
mA
mA
°C
I
, I
DC V or GND current
GND CC
CC
T
stg
Storage temperature range
–65 to +150
Power dissipation per package
–plastic medium-shrink (SSOP)
–plastic thin-medium-shrink (TSSOP) above +55°C derate linearly with 8 mW/K
For temperature range: –40 to +125 °C
above +55°C derate linearly with 11.3 mW/K
850
600
P
TOT
mW
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5
1998 May 29
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
1.7
TYP
1.2
1.5
1.2
1.5
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 to 2.7V
V
HIGH level Input voltage
LOW level Input voltage
V
V
IH
= 2.7 to 3.6V
= 2.3 to 2.7V
= 2.7 to 3.6V
2.0
0.7
0.8
V
IL
= 2.3 to 3.6V; V = V or V ; I = –100µA
V
*0.2
V
CC
I
IH
IL
O
CC
= 2.3V; V = V or V ; I = –6mA
V
V
V
V
V
0.3
0.6
0.5
0.6
V
V
V
V
V
0.08
0.26
0.14
0.09
0.28
*
*
*
*
*
I
IH
IL
O
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 2.3V; V = V or V ; I = –12mA
*
*
*
*
I
IH
IL
O
V
OH
HIGH level output voltage
V
= 2.7V; V = V or V ; I = –12mA
I
IH
IL
O
= 3.0V; V = V or V ; I = –12mA
I
IH
IL
O
= 3.0V; V = V or V
I
= –24mA
*1.0
CC
I
IH
IL; O
= 2.3 to 3.6V; V = V or V ; I = 100µA
GND
0.07
0.15
0.14
0.27
0.20
0.40
0.70
0.40
0.55
V
V
I
IH
IL
O
= 2.3V; V = V or V ; I = 6mA
I
IH
IL
O
= 2.3V; V = V or V ; I = 12mA
V
OL
LOW level output voltage
I
IH
IL
O
= 2.7V; V = V or V ; I = 12mA
V
I
IH
IL
O
= 3.0V; V = V or V
I = 24mA
IL; O
I
IH
V
= 2.3 to 3.6V;
CC
CC
I
Input leakage current
0.1
0.1
5
µA
µA
I
V = V or GND
I
V
V
= 2.7 to 3.6V; V = V or V ;
I IH IL
CC
O
I
3-State output OFF-state current
10
OZ
= V or GND
CC
I
Quiescent supply current
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 to 3.6V; V = V or GND; I = 0
0.2
150
–
40
µA
µA
CC
I
CC
O
∆I
Additional quiescent supply current
= 2.3V to 3.6V; V = V – 0.6V; I = 0
750
CC
I
CC
O
2
= 2.3V; V = 0.7V
45
I
I
Bus hold LOW sustaining current
Bus hold HIGH sustaining current
µA
µA
BHL
2
2
2
= 3.0V; V = 0.8V
75
–45
–75
500
–500
150
I
= 2.3V; V = 1.7V
I
I
BHH
= 3.0V; V = 2.0V
–175
I
2
I
Bus hold LOW overdrive current
Bus hold HIGH overdrive current
= 3.6V
µA
µA
BHLO
2
I
= 3.6V
BHHO
NOTES:
1. All typical values are at T
= 25°C.
amb
2. Valid for data inputs of bus hold parts.
6
1998 May 29
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
AC CHARACTERISTICS FOR V = 2.3V TO 2.7V RANGE
CC
GND = 0V; t = t ≤ 2.0ns; C = 30pF
r
f
L
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 2.5V ± 0.2V
UNIT
1
MIN
TYP
MAX
Propagation delay
nCP to nQ
t
/t
1, 4
2, 4
2, 4
1.0
2.6
2.8
2.2
5.8
ns
ns
ns
PLH PHL
n
3-State output enable time
nOE to nQ
t
t
/t
1.0
1.0
6.6
5.7
PZH PZL
n
n
3-State output disable time
nOE to nQ
/t
PHZ PLZ
n
n
t
nCP pulse width HIGH or LOW
Set up time nD to nCP
3, 4
3, 4
3, 4
1, 4
3.0
1.4
0.4
150
1.8
0.3
0.0
250
ns
ns
W
t
SU
n
t
Hold time nD to nCP
ns
h
n
F
max
Maximum clock pulse frequency
MHz
NOTE:
1. All typical values are at V = 2.5V and T
= 25°C.
CC
amb
AC CHARACTERISTICS FOR V = 3.0V TO 3.6V RANGE AND V = 2.7V
CC
CC
GND = 0V; t = t ≤ 2.5ns; C = 50pF
r
f
L
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3 ± 0.3V
V
CC
= 2.7V
UNIT
1
1
MIN
TYP
MAX
MIN
TYP
MAX
Propagation delay
nCP to nQ
t
/t
1, 4
2, 4
2, 4
3, 4
1.0
2.5
4.5
5.1
4.6
1.0
1.0
1.0
3.3
2.8
3.2
3.1
5.3
6.2
5.0
ns
ns
ns
ns
PHL PLH
n
3-State output enable time
nOE to nQ
t
t
/t
1.0
1.0
3.3
2.3
2.8
0.2
PZH PZL
n
n
3-State output disable time
nOE to nQ
/t
PHZ PLZ
n
n
nCP pulse width HIGH or
LOW
t
1.7
0.3
W
t
Set up time nD to nCP
3, 4
3, 4
1.0
0.8
0.2
0.4
1.2
0.6
ns
ns
SU
n
t
h
Hold time nD to nCP
–0.3
n
Maximum clock pulse
frequency
F
max
1, 4
150
350
150
300
MHz
NOTES:
1. All typical values are at T
= 25°C.
amb
7
1998 May 29
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
AC WAVEFORMS
V
CC
= 2.3 TO 2.7 V RANGE
1. V = 0.5 V
M
V
I
2. V = V + 0.15V
X
OL
V
nCP INPUT
GND
M
3. V = V – 0.15V
Y
OH
t
su
t
su
4. V = V
I
CC
t
h
t
h
5. V and V are the typical output voltage drop that occur with
OL
OH
V
I
the output load.
V
nD INPUT
n
M
V
CC
= 3.0 TO 3.6 V RANGE AND V = 2.7 V
GND
CC
1. V = 1.5 V
M
V
OH
2. V = V + 0.3V
X
OL
nQ OUTPUT
3. V = V – 0.3V
n
Y
OH
V
M
V
OL
4. V = 2.7 V
I
5. V and V are the typical output voltage drop that occur with
SH00129
OL
OH
the output load.
Waveform 3. Set up and hold times.
TEST CIRCUIT
1/f
MAX
V
I
S
1
2 * V
V
V
nCP INPUT
GND
CC
CC
M
Open
GND
t
w
t
PLH
t
PHL
V
R
R
= 500 Ω
= 500 Ω
OH
L
L
V
V
O
I
nQ OUTPUT
n
V
V
M
M
PULSE
GENERATOR
D.U.T.
V
OL
R
T
C
L
SH00128
Waveform 1. The input (nCP) to output propagation delays.
Test Circuit for switching times
V
I
DEFINITIONS
R
C
R
= Load resistor
L
L
T
= Load capacitance includes jig and probe capacitance
= Termination resistance should be equal to Z of pulse generators.
V
nOE INPUT
GND
M
OUT
SWITCH POSITION
TEST
S
V
V
I
1
CC
t
t
PZL
PLZ
t
t
Open
< 2.7V
V
CC
V
PLH/ PHL
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
t
t
t
2.7–3.6V
2.7V
PLZ/ PZL
2 < V
CC
V
M
t
V
GND
PHZ/ PZH
X
V
OL
SV00906
t
t
PZH
PHZ
Waveform 4. Load circuitry for switching times
V
OH
OUTPUT
V
Y
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
SW00308
Waveform 2. The 3-State enable and disable times.
8
1998 May 29
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
9
1998 May 29
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
10
1998 May 29
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
NOTES
11
1998 May 29
Philips Semiconductors
Product specification
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
74ALVCH16821
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04553
Document order number:
Philips
Semiconductors
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