74ALVT16373DGG [NEXPERIA]
16-bit transparent D-type latch; 3-stateProduction;型号: | 74ALVT16373DGG |
厂家: | Nexperia |
描述: | 16-bit transparent D-type latch; 3-stateProduction 信息通信管理 光电二极管 逻辑集成电路 |
文件: | 总14页 (文件大小:238K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74ALVT16373
16-bit transparent D-type latch; 3-state
Rev. 5 — 14 July 2021
Product data sheet
1. General description
The 74ALVT16373 is a 16-bit D-type transparent latch with 3-state outputs. The device can be
used as two 8-bit transparent latches or a single 16-bit transparent latch. The device features
two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling
8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are
transparent, a latch output will change each time its corresponding D-input changes. When nLE is
LOW the latches store the information that was present at the inputs a set-up time preceding the
HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance
OFF-state. Operation of the nOE input does not affect the state of the latches. Bus hold data inputs
eliminate the need for external pull-up resistors to define unused inputs
2. Features and benefits
•
Wide supply voltage range from 2.3 to 3.6 V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Overvoltage tolerant inputs to 5.5 V
BiCMOS high speed and output drive
16-bit transparent latch
5 V I/O compatible
3-state buffers
Output capability: +64 mA/–32 mA
Direct interface with TTL levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5 V bus
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
ESD protection:
•
•
MIL STD 883 method 3015: exceeds 2000 V
MM exceeds 200 V
•
Specified from -40 °C to 85 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74ALVT16373DGG -40 °C to +85 °C
TSSOP48
plastic thin shrink small outline package; 48 leads;
body width 6.1 mm
SOT362-1
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
4. Functional diagram
1
1EN
C3
1OE
1LE
2OE
2LE
1
24
48
24
25
2EN
C4
1OE
2OE
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
3
2
3
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1
3D
5
6
5
8
6
9
8
11
12
13
14
16
17
19
20
22
23
9
11
12
13
14
16
17
19
20
22
23
4D
2
1LE
48
2LE
25
mgu768
mgu770
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
1D0
1Q0
2D0
2Q0
D
Q
D
Q
LATCH
1
LATCH
9
LE LE
LE LE
1LE
2LE
1OE
2OE
to 7 other channels
to 7 other channels
mgu769
Fig. 3. Logic diagram
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
2 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
5. Pinning information
5.1. Pinning
74ALVT16373
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q0
1Q1
GND
1Q2
1Q3
1LE
1D0
1D1
GND
1D2
1D3
2
3
4
5
6
7
V
V
CC
CC
8
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
V
CC
CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
2D4
2D5
GND
2D6
2D7
2LE
aaa-028126
Fig. 4. Pin configuration SOT362-1 (TSSOP48)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
1, 24
data inputs
2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7
data inputs
1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7
data outputs
2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7
data outputs
1OE, 2OE
1LE, 2LE
GND
output enable inputs (active LOW)
latch enable inputs (active HIGH)
ground (0 V)
48, 25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
VCC
supply voltage
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
3 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
↓ = HIGH-to-LOW LE transition;
X = don’t care; NC = No change; Z = high-impedance OFF-state.
Operating mode
Inputs
Internal
latches
Outputs
nQn
nOE
L
nLE
H
H
↓
nDn
enable and read register (transparent mode)
latch and read register
L
L
L
L
H
l
H
H
L
L
L
L
↓
h
H
H
NC
Z
Hold
L
L
X
NC
NC
nDn
Latch register and disable outputs
H
H
L
X
H
nDn
Z
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-0.5
-50
-50
-
Max
+4.6
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
[1]
[1]
V
VO
IIK
output voltage
output in OFF-state or HIGH-state
VI < 0 V
V
input clamping current
output clamping current
output current
mA
mA
mA
mA
°C
°C
IOK
IO
VO < 0 V
-
output in LOW-state
output in HIGH-state
128
-
-64
-65
-
Tstg
Tj
storage temperature
junction temperature
+150
+150
[2]
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
4 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V Unit
Min
Max
2.7
5.5
-8
Min
Max
3.6
5.5
-32
32
VCC
VI
supply voltage
2.3
3.0
V
input voltage
0
-
0
-
V
IOH
IOL
HIGH-level output current
LOW-level output current
mA
mA
mA
none
-
8
-
current duty cycle ≤ 50 %;
fi ≥ 1 kHz
-
24
-
64
Δt/ΔV
Tamb
input transition rise
and fall rate
outputs enabled
-
10
-
10
ns/V
°C
ambient temperature
free-air
-40
+85
-40
+85
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; Tamb = -40 °C to +85 °C; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VCC = 2.5 V ± 0.2 V
Conditions
Min
Typ[1]
Max
Unit
VIK
VIH
VIL
input clamping voltage
VCC = 2.3 V; IIK = -18 mA
-
-0.85
-1.2
-
V
V
V
V
V
V
V
V
HIGH-level input voltage
LOW-level input voltage
1.7
-
-
-
0.7
-
VOH
HIGH-level output voltage VCC = 2.3 V to 2.7 V; IO = -100 μA
VCC = 2.3 V; IO = -8 mA
VCC - 0.2
-
-
1.8
-
VOL
LOW-level output voltage
VCC = 2.3 V; IO = 100 μA
VCC = 2.3 V; IO = 24 mA
-
-
-
0.07
0.3
-
0.2
0.5
0.55
VOL(pu) power-up LOW-level output VCC = 2.7 V; IO = 1 mA;
[2]
[3]
voltage
VI = VCC or GND
II
input leakage current
all input pins
VCC = 0 V or 2.7 V; VI = 5.5 V
control pins
-
-
0.1
0.1
10
±1
μA
μA
VCC = 2.7 V; VI = VCC or GND
data pins;
[3]
VCC = 2.7 V; VI = VCC
VCC = 2.7 V; VI = 0 V
-
-
-
-
-
-
0.1
0.1
0.1
90
1
-5
μA
μA
μA
μA
μA
μA
IOFF
IBHL
IBHH
IEX
power-off leakage current
bus hold LOW current
bus hold HIGH current
external current
VCC = 0 V; VI or VO = 0 V to 4.5 V
data inputs; VCC = 2.3 V; VI = 0.7 V
data inputs; VCC = 2.3 V; VI = 1.7 V
±100
-
[4]
[4]
-10
10
-
output in HIGH-state when VO > VCC
;
125
VO = 5.5 V; VCC = 2.3 V
IO(pu/pd) power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
VI = GND or VCC; nOE = don’t care
;
[5]
-
1
100
μA
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
5 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
IOZ
OFF-state output current
VCC = 2.7 V; VI = VIL or VIH
output HIGH: VO = 2.3V
output LOW: VO = 0.5 V
VCC = 2.7 V; VI = GND or VCC; IO = 0 A
outputs HIGH
-
-
0.5
0.5
5
μA
μA
-5
ICC
supply current
-
-
-
-
0.04
2.3
0.1
4.5
0.1
0.4
mA
mA
mA
mA
outputs LOW
outputs disabled
[6]
[7]
0.04
0.04
ΔICC
additional supply current
per input pin; VCC = 2.3 V to 2.7 V;
one input at VCC - 0.6 V;
other inputs at VCC or GND
CI
input capacitance
output capacitance
VI = 0 V or VCC
-
-
3
9
-
-
pF
pF
CO
Outputs disabled; VO = 0 V or 3 V
VCC = 3.3 V ± 0.3 V
VIK
VIH
VIL
input clamping voltage
VCC = 3.0 V; IIK = -18 mA
-
-0.85
-
-1.2
-
V
V
V
V
V
V
V
V
V
V
HIGH-level input voltage
LOW-level input voltage
2.0
-
-
0.8
-
VOH
HIGH-level output voltage VCC = 3.3 V ± 0.3 V; IO = -100 μA
VCC = 3.0 V; IO = -32 mA
VCC - 0.2
VCC
2.3
0.07
0.25
0.3
0.4
-
2.0
-
VOL
LOW-level output voltage
VCC = 3.0 V; IO = 100 μA
VCC = 3.0 V; IO = 16 mA
VCC = 3.0 V; IO = 32 mA
VCC = 3.0 V; IO = 64 mA
-
-
-
-
-
0.2
0.4
0.5
0.55
0.55
VOL(pu) power-up LOW-level output VCC = 3.6 V; IO = 1 mA;
[2]
[3]
voltage
VI = VCC or GND
II
input leakage current
all input pins
VCC = 0 V or 3.6 V; VI = 5.5 V
control pins
-
-
0.1
0.1
10
±1
μA
μA
VCC = 3.6 V; VI = VCC or GND
data pins
[3]
VCC = 3.6 V; VI = VCC
VCC = 3.6 V; VI = 0 V
VCC = 0 V; VI or VO = 0 V to 4.5 V
data inputs; VCC = 3 V; VI = 0.8 V
data inputs; VCC = 3 V; VI = 2.0 V
-
-
0.5
0.1
0.1
130
-140
-
1
μA
μA
μA
μA
μA
μA
-5
IOFF
IBHL
IBHH
IBHLO
power-off leakage current
bus hold LOW current
bus hold HIGH current
-
±100
75
-75
500
-
-
-
bus hold LOW
overdrive current
data inputs; VCC = 3.6 V;
VI = 0 V to 3.6 V
[8]
[8]
IBHHO
IEX
bus hold HIGH
overdrive current
data inputs; VCC = 3.6 V;
VI = 0 V to 3.6 V
-500
-
-
μA
μA
μA
external current
output in HIGH-state when VO > VCC
VO = 5.5 V; VCC = 3.0 V
;
-
-
10
1
125
±100
IO(pu/pd) power-up/power-down
output current
VCC ≤ 1.2 V; VO = 0.5 V to VCC
;
[9]
VI = GND or VCC; nOE = don’t care
VCC = 3.6 V; VI = VIL or VIH
output HIGH: VO = 3.0V
IOZ
OFF-state output current
-
-
0.5
0.5
5
μA
μA
output LOW: VO = 0.5 V
-5
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
6 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
ICC
supply current
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs HIGH
-
-
-
-
0.04
3.5
0.1
5
mA
mA
mA
mA
outputs LOW
outputs disabled
[6]
[7]
0.05
0.04
0.1
0.4
ΔICC
additional supply current
per input pin; VCC = 3 V to 3.6 V;
one input at VCC - 0.6 V;
other inputs at VCC or GND
CI
input capacitance
output capacitance
VI = 0 V or VCC
-
-
3
9
-
-
pF
pF
CO
output disabled; VO = 0 V or 3 V
[1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.
All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.
[2] For valid test results, data must not be loaded into the latches after applying power.
[3] Unused pins at VCC or GND.
[4] Not guaranteed.
[5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms.
From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only.
[6] ICC with outputs disabled is measured with outputs pulled to VCC or GND.
[7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
[8] This is the bus hold overdrive current required to force the input to the opposite logic state.
[9] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms.
From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only.
10. Dynamic characteristics
Table 7. Dynamic characteristics
At recommended operating conditions; Tamb = -40 °C to +85 °C; voltages are referenced to GND (ground = 0 V);
for test circuit see Fig. 9.
Symbol Parameter
VCC = 2.5 V ± 0.2 V
Conditions
Min
Typ[1]
Max
Unit
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
tsu(L)
th(H)
th(L)
tWH
LOW to HIGH propagation delay
nDn to nQn; see Fig. 5
nDn to nQn; see Fig. 5
nLE to nQn; see Fig. 6
nLE to nQn; see Fig. 6
nOE to nQn; see Fig. 7
nOE to nQn; see Fig. 7
nOE to nQn; see Fig. 7
nOE to nQn; see Fig. 7
nDn to nLE; see Fig. 8
nDn to nLE; see Fig. 8
nDn to nLE; see Fig. 8
nDn to nLE; see Fig. 8
nLE; see Fig. 6
1.0
1.0
1.5
1.5
2.0
1.5
1.5
1.0
0
2.0
2.4
2.6
2.8
3.5
2.6
2.7
2.0
-0.7
0.2
-0.2
0.7
-
3.2
4.2
4.2
4.5
5.5
4.7
4.5
3.5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HIGH to LOW propagation delay
LOW to HIGH propagation delay
HIGH to LOW propagation delay
OFF-state to HIGH propagation delay
OFF-state to LOW propagation delay
HIGH to OFF-state propagation delay
LOW to OFF-state propagation delay
set-up time HIGH
set-up time LOW
1.5
0.5
1.5
1.5
-
hold time HIGH
-
hold time LOW
-
pulse width HIGH
-
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
7 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
Symbol Parameter
VCC = 3.3 V ± 0.3 V
Conditions
Min
Typ[1]
Max
Unit
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
tsu(L)
th(H)
th(L)
tWH
LOW to HIGH propagation delay
nDn to nQn; see Fig. 5
nDn to nQn; see Fig. 5
nLE to nQn; see Fig. 6
nLE to nQn; see Fig. 6
nOE to nQn; see Fig. 7
nOE to nQn; see Fig. 7
nOE to nQn; see Fig. 7
nOE to nQn; see Fig. 7
nDn to nLE; see Fig. 8
nDn to nLE; see Fig. 8
nDn to nLE; see Fig. 8
nDn to nLE; see Fig. 8
nLE; see Fig. 6
0.5
0.5
1.0
1.0
1.5
1.0
1.5
1.5
0.5
0.8
0.8
1.0
1.5
1.6
1.8
2.0
2.3
2.3
1.9
2.9
2.3
-0.2
0.2
0
2.5
2.9
3.1
3.3
4.0
3.1
4.5
3.7
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HIGH to LOW propagation delay
LOW to HIGH propagation delay
HIGH to LOW propagation delay
OFF-state to HIGH propagation delay
OFF-state to LOW propagation delay
HIGH to OFF-state propagation delay
LOW to OFF-state propagation delay
set-up time HIGH
set-up time LOW
-
hold time HIGH
-
hold time LOW
0.2
-
-
pulse width HIGH
-
[1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.
All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.
10.1. Waveforms and test circuit
V
I
V
I
nLE input
V
V
V
t
V
V
M
M
M
nDn input
M
M
GND
GND
t
W
t
t
PHL
PLH
t
PHL
PLH
V
OH
V
OH
nQn output
V
V
M
M
nQn output
V
V
M
M
V
OL
001aam012
V
OL
001aam011
Measurement points are given in Table 8.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that
occur with the output load.
VOL and VOH are typical voltage output levels that
occur with the output load.
Fig. 6. Latch enable input (nLE) to data output (nQn)
propagation delays and pulse width
Fig. 5. Input (nDn) to output (nQn) propagation delays
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
8 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
V
I
nOE input
V
V
t
M
M
GND
t
PLZ
PZL
3.0 V or V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
aaa-028124
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 7. OFF-state to HIGH or LOW and HIGH or LOW to OFF-state propagation delays
V
I
nDn input
V
M
GND
t
t
h
h
t
t
su
su
V
I
nLE input
V
M
GND
001aam013
Measurement points are given in Table 8.
Fig. 8. Input (nDn) to input (nLE) data set-up and hold times
Table 8. Measurement points
VCC
Input
VI
Output
VM
VM
VX
VY
VCC ≤ 2.7 V
VCC ≥ 3.0 V
VCC
3.0 V
0.5 x VCC
1.5 V
0.5 x VCC
1.5 V
VOL + 0.15 V
VOL + 0.3 V
VOH - 0.15 V
VOH - 0.3 V
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
9 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
t
W
V
I
90 %
90 %
negative
pulse
V
V
M
M
10 %
V
0 V
EXT
t
t
t
r
f
V
CC
t
R
r
f
L
L
V
V
O
I
V
I
G
DUT
90 %
positive
pulse
V
V
M
M
R
T
C
L
R
10 %
10 %
0 V
t
W
001aac221
mna616
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig. 9. Test circuit for measuring switching times
Table 9. Test data
Input
VI
Load
CL
VEXT
fi
tW
tr, tf
RL
tPHZ, tPZH tPLZ, tPZL
tPLH, tPHL
3.0 V or VCC
≤ 10 MHz 500 ns
≤ 2.5 ns
50 pF
500 Ω
GND
6 V or VCC x 2 open
whichever is less
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
10 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
11. Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
A
H
E
y
Z
48
25
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
24
detail X
w
b
p
e
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
Unit
max
(1)
(2)
A
A
A
A
b
c
D
E
e
H
L
1
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
°
8
0
0.15 1.05
0.05 0.85
0.28 0.2 12.6 6.2
0.17 0.1 12.4 6.0
8.3
7.9
0.8 0.50
0.4 0.35
0.8
0.4
mm nom 1.2
min
0.25
0.5
0.25 0.08 0.1
°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
sot362-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
03-02-19
13-08-05
SOT362-1
MO-153
Fig. 10. Package outline SOT362-1 (TSSOP48)
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
11 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
BiCMOS
DUT
Description
Bipolar Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Military
MIL
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
74ALVT16373 v.5
Modifications:
Release date
20210714
Data sheet status
Change notice
Supersedes
Product data sheet
-
74ALVT16373 v.4
•
•
Section 1 and Section 2 updated.
Type number 74ALVT16373DL (SOT370-1/SSOP48) removed.
74ALVT16373 v.4
Modifications:
20180202
Product data sheet
-
74ALVT16373 v.3
•
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
Legal texts have been adapted to the new company name where appropriate.
74ALVT16373 v.3
74ALVT16373 v.2
74ALVT16373 v.1
19991018
19980213
19960529
Product specification
Product specification
Product specification
-
-
-
74ALVT16373 v.2
74ALVT16373 v.1
-
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
12 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
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Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
13 / 14
Nexperia
74ALVT16373
16-bit transparent D-type latch; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................3
6. Functional description................................................. 4
7. Limiting values............................................................. 4
8. Recommended operating conditions..........................5
9. Static characteristics....................................................5
10. Dynamic characteristics............................................ 7
10.1. Waveforms and test circuit........................................ 8
11. Package outline........................................................ 11
12. Abbreviations............................................................12
13. Revision history........................................................12
14. Legal information......................................................13
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 14 July 2021
©
74ALVT16373
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 14 July 2021
14 / 14
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