74ALVT16823DGG [NEXPERIA]

18-bit bus-interface D-type flip-flop with reset and enable; 3-stateProduction;


型号：	74ALVT16823DGG
厂家：	Nexperia
描述：	18-bit bus-interface D-type flip-flop with reset and enable; 3-stateProduction 驱动信息通信管理光电二极管逻辑集成电路
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74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable;

3-state

Rev. 6 — 20 October 2020

Product data sheet

1. General description

The 74ALVT16823 is an 18-bit positive-edge triggered D-type flip-flop with 3-state outputs, reset

and enable.

The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock

(nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling

9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the

set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE

causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not

affect the state of the flip-flops. A LOW on nMR will reset the flip-flops LOW. Bus hold data inputs

eliminate the need for external pull-up resistors to define unused inputs

2. Features and benefits

•

Wide supply voltage range from 2.3 V to 3.6 V

•

Overvoltage tolerant inputs to 5.5 V

BiCMOS high speed and output drive

Direct interface with TTL levels

Bus hold on data inputs

Power-up 3-state

I_OFFcircuitry provides partial Power-down mode operation

Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops

Ideal where high speed, light loading, or increased fan-in are required with MOS

microprocessors

•

Live insertion and extraction permitted

Power-up reset

No bus current loading when output is tied to 5 V bus

Output capability: +64 mA to -32 mA

Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

ESD protection:

•

MIL STD 883, method 3015: exceeds 2000 V

MM: exceeds 200 V

•

Specified from -40 °C to 85 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74ALVT16823DGG -40 °C to +85 °C

TSSOP56 plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

4. Functional diagram

EN1

1OE

1MR

1CE

1CP

2OE

2MR

2CE

2CP

3C4

EN5

7C8

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

1,2

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1Q8

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2Q8

5,6

data input

to internal circuit

001aad242

001aad245

Fig. 1. IEC logic symbol

Fig. 2. Bushold circuit (one data input)

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

2 / 16

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

nCE

nCP

nD0

nD1

nD2

nD3

nD4

nD5

nD6

nD7

nD8

nMR

nOE

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

nQ6

nQ7

nQ8

001aad243

Fig. 3. Logic diagram

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

3 / 16

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

5. Pinning information

5.1. Pinning

1MR

1OE

1Q0

GND

1Q1

1Q2

1CP

1CE

1D0

GND

1D1

1D2

1Q3

1Q4

1Q5

GND

1Q6

1Q7

1Q8

2Q0

2Q1

2Q2

GND

2Q3

2Q4

2Q5

1D3

1D4

1D5

GND

1D6

1D7

1D8

2D0

2D1

2D2

GND

2D3

2D4

2D5

74ALVT16823

2Q6

2Q7

GND

2Q8

2OE

2MR

2D6

2D7

GND

2D8

2CE

2CP

001aad403

Fig. 4. Pin configuration SOT364-1 (TSSOP56)

5.2. Pin description

Table 2. Pin description

Symbol

1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8 54, 52, 51, 49, 48, 47, 45, 44, 43 data inputs

1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7, 1Q8 3, 5, 6, 8, 9, 10, 12, 13, 14 data outputs

Description

2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8 42, 41, 40, 38, 37, 36, 34, 33, 31 data inputs

2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7, 2Q8 15, 16, 17, 19, 20, 21, 23, 24, 26 data outputs

1MR, 2MR

1OE, 2OE

1CP, 2CP

1CE, 2CE

GND

1, 28

master reset input (active-LOW)

output enable inputs (active LOW)

clock pulse inputs (active rising edge)

clock enable input (active-LOW)

ground (0 V)

2, 27

56, 29

55, 30

4, 11, 18, 25, 32, 39, 46, 53

7, 22, 35, 50

V_CC

supply voltage

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

4 / 16

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74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

NC = no change; X = don’t care; Z = high-impedance OFF-state;

↑ = LOW-to-HIGH clock transition; ↑ = not a LOW-to-HIGH clock transition.

Operating mode

Input

nOE

Output

nMR

nCE

nCP

nDn

nQn

clear

load and read data

↑

hold

↑

high-impedance

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

-0.5

Max

+4.6

+7.0

-50

Unit

V_CC

V_I

supply voltage

input voltage

[1]

V_O

I_IK

output voltage

output in OFF-state or HIGH-state

V_I< 0 V

input clamping current

°C

I_OK

I_O

output clamping current V_O< 0 V

-50

output current

output in LOW-state

output in HIGH-state

128

-64

-65

T_stg

T_j

storage temperature

junction temperature

+150

150

[2]

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter

V_CC= 2.5 V

Conditions

Min

Typ

Max

Unit

V_CC

V_I

supply voltage

2.3

2.7

5.5

-8

input voltage

I_OH

I_OL

HIGH-level output current

LOW-level output current

ns/V

°C

none

current duty cycle ≤ 50 %; f ≥ 1 kHz

+85

Δt/Δv

T_amb

input transition rise or fall rate outputs enabled

ambient temperature

in free air

-40

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

5 / 16

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74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Symbol Parameter

V_CC= 3.3 V

Conditions

Min

Typ

Max

Unit

V_CC

V_I

supply voltage

3.0

3.6

5.5

-32

input voltage

I_OH

I_OL

HIGH-level output current

LOW-level output current

ns/V

°C

none

current duty cycle ≤ 50 %; f ≥ 1 kHz

Δt/Δv

T_amb

input transition rise or fall rate outputs enabled

ambient temperature in free air

-40

+85

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

T_amb= −40 °C to +85 °C

Unit

Min

Typ[1]

Max

V_CC= 2.5 V ± 0.2 V

V_IK

V_IH

V_IL

input clamping voltage

V_CC= 2.3 V; I_IK= -18 mA

-0.85

-1.2

HIGH-level input voltage

LOW-level input voltage

1.7

0.7

V_OH

HIGH-level output voltage V_CC= 2.3 V to 2.7 V; I_O= -100 μA

V_CC= 2.3 V; I_O= -8 mA

V_CC- 0.2

V_CC

2.5

0.07

0.3

1.8

V_OL

LOW-level output voltage V_CC= 2.3 V; I_O= 100 μA

V_CC= 2.3 V; I_O= 24 mA

0.2

0.5

0.4

0.55

V_CC= 2.3 V; I_O= 8 mA

V_OL(pu)power-up LOW-level

output voltage

V_CC= 2.7 V; I_O= 1 mA; V_I= V_CCor GND

[2]

[3]

I_I

input leakage current

control pins

V_CC= 2.7 V; V_I= V_CCor GND

V_CC= 0 V to 2.7 V; V_I= 5.5 V

I/O data pins

0.1

±1

μA

V_CC= 2.7 V; V_I= V_CC

V_CC= 2.7 V; V_I= 0 V

0.1

+0.1

100

-70

μA

-5

I_OFF

I_BHL

I_BHH

I_EX

power-off leakage current V_CC= 0 V; V_Ior V_O= 0 V to 4.5 V

±100 μA

bus hold LOW current

bus hold HIGH current

external current

data inputs; V_CC= 2.3 V; V_I= 0.7 V

data inputs; V_CC= 2.3 V; V_I= 1.7 V

[4]

μA

output HIGH-state when V_O> V_CC

;

125

V_O= 5.5 V; V_CC= 2.3 V

I_O(pu\pd)power-up/power-down

output current

V_CC≤ 1.2 V; V_O= 0.5 V to V_CC

V_I= GND or V_CC

;

[5]

±100 μA

I_OZ

OFF-state output current

V_CC= 2.7 V; V_I= V_ILor V_IH

output HIGH state; V_O= 2.3 V

output LOW-state; V_O= 0.5 V

0.5

μA

+0.5

-5

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

6 / 16

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Symbol Parameter

Conditions

T_amb= −40 °C to +85 °C

Unit

Min

Typ[1]

Max

I_CC

supply current

V_CC= 2.7 V; V_I= GND or V_CC; I_O= 0 A

outputs HIGH-state

0.04

2.7

0.1

4.5

0.1

0.4

outputs LOW-state

outputs disabled

[6]

[7]

0.04

ΔI_CC

additional supply current

per input pin; V_CC= 2.3 V to 2.7 V;

one input at V_CC- 0.6 V,

other inputs at V_CCor GND

C_I

input capacitance

output capacitance

V_I= 0 V or V_CC

C_O

V_I/O= 0 V or 3.0 V

V_CC= 3.3 V ± 0.3 V

V_IK

V_IH

V_IL

input clamping voltage

V_CC= 3.0 V; I_IK= -18 mA

-0.85

-1.2

HIGH-level input voltage

LOW-level input voltage

2.0

0.8

V_OH

HIGH-level output voltage V_CC= 3.0 V to 3.6 V; I_O= -100 μA

V_CC= 3.0 V; I_O= -32 mA

V_CC- 0.2

V_CC

2.3

0.07

0.25

0.3

0.4

2.0

V_OL

LOW-level output voltage V_CC= 3.0 V; I_O= 100 μA

V_CC= 3.0 V; I_O= 16 mA

0.2

0.4

0.5

0.55

V_CC= 3.0 V; I_O= 32 mA

V_CC= 3.0 V; I_O= 64 mA

V_OL(pu)power-up LOW-level

output voltage

V_CC= 3.6 V; I_O= 1 mA; V_I= V_CCor GND

[2]

[3]

I_I

input leakage current

control pins

V_CC= 3.6 V; V_I= V_CCor GND

V_CC= 0 V or 3.6 V; V_I= 5.5 V

I/O data pins

0.1

±1

μA

V_CC= 3.6 V; V_I= V_CC

V_CC= 3.6 V; V_I= 0 V

0.5

+0.1

0.1

130

-140

μA

-5

I_OFF

I_BHL

I_BHH

I_BHLO

power-off leakage current V_CC= 0 V; V_Ior V_O= 0 V to 4.5 V

±100 μA

bus hold LOW current

bus hold HIGH current

data inputs; V_CC= 3 V; V_I= 0.8 V

data inputs; V_CC= 3 V; V_I= 2.0 V

-75

500

μA

bus hold LOW overdrive

current

data inputs; V_CC= 3.6 V; V_I= 0 V to 3.6 V [8]

I_BHHO

I_EX

bus hold HIGH overdrive

current

data inputs; V_CC= 3.6 V; V_I= 0 V to 3.6 V [8] −500

μA

external current

output HIGH-state when V_O> V_CC

V_O= 5.5 V; V_CC= 3.0 V

;

125

I_O(pu\pd)power-up/power-down

output current

V_CC≤ 1.2 V; V_O= 0.5 V to V_CC

;

[9]

±100 μA

V_I= GND or V_CC

I_OZ

OFF-state output current

V_CC= 3.6 V; V_I= V_ILor V_IH

output HIGH state; V_O= 3.0 V

output LOW-state; V_O= 0.5 V

0.5

μA

+0.5

-5

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

7 / 16

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Symbol Parameter

Conditions

T_amb= −40 °C to +85 °C

Unit

Min

Typ[1]

Max

I_CC

supply current

V_CC= 3.6 V; V_I= GND or V_CC; I_O= 0 A

outputs HIGH-state

0.06

3.9

0.1

5.5

0.1

0.4

outputs LOW-state

outputs disabled

[6]

[7]

0.06

0.04

ΔI_CC

additional supply current

per input pin; V_CC= 3 V to 3.6 V;

one input at V_CC- 0.6 V,

other inputs at V_CCor GND

C_I

input capacitance

output capacitance

V_I= 0 V or V_CC

C_O

V_I/O= 0 V or 3.0 V

[1] All typical values for V_CC= 2.5 V ± 0.2 V are measured at V_CC= 2.5 V and T_amb= 25 °C.

All typical values for V_CC= 3.3 V ± 0.3 V are measured at V_CC= 3.3 V and T_amb= 25 °C.

[2] For valid test results, data must not be loaded into the flip-flops after applying power.

[3] Unused pins at V_CCor GND.

[4] Not guaranteed.

[5] This parameter is valid for any V_CCbetween 0 V and 1.2 V with a transition time of up to 10 ms.

From V_CC= 1.2 V to V_CC= 2.5 V ± 0.2 V a transition time of 100 μs is permitted. This parameter is valid for T_amb= 25 °C only.

[6] I_CCis measured with outputs pulled up to V_CCor pulled down to ground.

[7] This is the increase in supply current for each input at the specified voltage level other than V_CCor GND.

[8] This is the bus hold overdrive current required to force the input to the opposite logic state.

[9] This parameter is valid for any V_CCbetween 0 V and 1.2 V with a transition time of up to 10 ms.

From V_CC= 1.2 V to V_CC= 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for T_amb= 25 °C only.

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9.

Symbol Parameter

Conditions

T_amb= −40 °C to +85 °C

Unit

Min

Typ[1]

Max

V_CC= 2.5 V ± 0.2 V

t_PLH

t_PHL

LOW to HIGH propagation delay

nCP to nQn; see Fig. 5

nMR to nQn; see Fig. 7

nOE to nQn; see Fig. 8

nDn to nCP; see Fig. 6

nCE to nCP; see Fig. 6

nDn to nCP; see Fig. 6

nCE to nCP; see Fig. 6

nDn to nCP; see Fig. 6

nCE to nCP; see Fig. 6

nDn to nCP; see Fig. 6

nCE to nCP; see Fig. 6

1.5

1.4

1.5

2.1

1.8

1.7

1.4

1.0

1.8

0.5

0.1

1.0

0.1

1.0

2.9

2.7

3.4

3.0

2.3

0.5

0.2

1.3

-0.1

-1.4

0.2

-0.5

-0.1

4.5

4.2

5.0

4.7

4.3

3.3

HIGH-to-LOW propagation delay

t_PZH

t_PZL

t_PHZ

t_PLZ

t_su(H)

OFF-state to HIGH propagation delay

OFF-state to LOW propagation delay

HIGH to OFF-state propagation delay

LOW to OFF-state propagation delay

set-up time HIGH

t_su(L)

t_h(H)

t_h(L)

set-up time LOW

hold time HIGH

hold time LOW

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

8 / 16

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74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Symbol Parameter

Conditions

T_amb= −40 °C to +85 °C

Unit

Min

2.0

3.0

2.0

150

Typ[1]

0.8

2.1

0.8

1.3

Max

t_WH

t_WL

pulse width HIGH

nCP; see Fig. 5

nCP

pulse width LOW

nMR; see Fig. 7

nMR to nCP; see Fig. 7

CP; see Fig. 5

t_rec

recovery time

f_max

maximum frequency

MHz

V_CC= 3.3 V ± 0.3 V

t_PLHLOW to HIGH propagation delay

t_PHL

nCP to nQn; see Fig. 5

nMR to nQn; see Fig. 7

nOE to nQn; see Fig. 8

nDn to nCP; see Fig. 6

nCE to nCP; see Fig. 6

nDn to nCP; see Fig. 6

nCE to nCP; see Fig. 6

nDn to nCP; see Fig. 6

nCE to nCP; see Fig. 6

nDn to nCP; see Fig. 6

nCE to nCP; see Fig. 6

nCP; see Fig. 5

1.0

1.7

1.4

2.2

1.8

1.0

1.6

0.5

0.1

1.0

0.1

1.0

1.5

2.5

2.0

250

2.3

2.1

2.3

2.7

2.3

3.1

2.6

0.5

0.1

1.1

-0.5

-0.7

0.5

-0.5

-0.1

0.7

1.4

1.5

1.1

3.1

MHz

HIGH-to-LOW propagation delay

2.9

t_PZH

t_PZL

t_PHZ

t_PLZ

t_su(H)

OFF-state to HIGH propagation delay

OFF-state to LOW propagation delay

HIGH to OFF-state propagation delay

LOW to OFF-state propagation delay

set-up time HIGH

4.0

3.5

4.0

3.5

t_su(L)

t_h(H)

t_h(L)

set-up time LOW

hold time HIGH

hold time LOW

t_WH

t_WL

pulse width HIGH

pulse width LOW

nCP

nMR; see Fig. 7

t_rec

recovery time

nMR to nCP; see Fig. 7

CP; see Fig. 5

f_max

maximum frequency

[1] All typical values for V_CC= 2.5 V ± 0.2 V are measured at V_CC= 2.5 V and T_amb= 25 °C.

All typical values for V_CC= 3.3 V ± 0.3 V are measured at V_CC= 3.3 V and T_amb= 25 °C.

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

9 / 16

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74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

10.1. Waveforms and test circuit

1/f

max

nCP input

GND

PHL

PLH

nQn output

001aaa256

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 5. Propagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width HIGH and maximum clock

frequency

input nDn,

nCE

GND

h(L)

su(H)

h(H)

su(L)

input nCP

GND

001aad401

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 6. Data set-up and hold times

input nMR

GND

rec

input nCP

GND

PHL

output nQn

001aad400

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 7. Master reset pulse width, master reset to output delay and master reset to clock recovery time

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

10 / 16

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74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

nOE input

GND

PLZ

PZL

nQn output

LOW-to-OFF

OFF-to-LOW

PZH

PHZ

nQn output

HIGH-to-OFF

OFF-to-HIGH

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aal795

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 8. OFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays

Table 8. Measurement points

V_CC

Input

V_M

Output

V_M

V_X

V_Y

≤ 2.7 V

≥ 3.0 V

0.5 x V_CC

1.5 V

0.5 x V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH- 0.15 V

V_OH- 0.3 V

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

EXT

DUT

001aae331

Test data is given in Table 9.

Definitions test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= Test voltage for switching times.

Fig. 9. Test circuit for measuring switching times

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

11 / 16

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Table 9. Test data

Input

Load

C_L

V_EXT

V_I

f_i

t_W

t_r, t_f

R_L

t_PHZ, t_PZHt_PLZ, t_PZL

t_PLH, t_PHL

3.0 V or V_CC

≤ 10 MHz 500 ns

≤ 2.5 ns

50 pF

500 Ω

GND

6 V or V_CC× 2 open

whichever is less

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

12 / 16

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

11. Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

(1)

(2)

UNIT

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

1.2

0.5

0.25

0.08

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig. 10. Package outline SOT364-1 (TSSOP56)

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

13 / 16

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

BiCMOS

DUT

ESD

MIL

Bipolar Complementary Metal Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Military

Machine Model

MOS

TTL

Metal-Oxide Semiconductor

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

20201020 Product data sheet

Change notice Supersedes

- 74ALVT16823 v.5

74ALVT16823 v.6

Modifications:

•

Type number 74ALVT16823DL (SOT371-1 / SSOP56) removed.

Section 1 and Section 2 updated.

74ALVT16823 v.5

Modifications:

20180122

Product data sheet

74ALVT16823 v.4

•

The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

Legal texts have been adapted to the new company name where appropriate.

74ALVT16823 v.4

Modifications:

20050802

Product data sheet

74ALVT16823 v.3

•

The format of this data sheet has been redesigned to comply with the new presentation

and information standard of Philips Semiconductors.

•

Section 2: modified ‘Jedec Std 17’ into ‘JESD78’

Section 10: changed propagation delays.

74ALVT16823 v.3

74ALVT16823 v.2

74ALVT16823 v.1

19980612

19980303

Product specification

74ALVT16823 v.2

74ALVT16823 v.1

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

14 / 16

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

74ALVT16823

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 20 October 2020

15 / 16

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................4

5.1. Pinning.........................................................................4

5.2. Pin description.............................................................4

6. Functional description................................................. 5

7. Limiting values............................................................. 5

8. Recommended operating conditions..........................5

9. Static characteristics....................................................6

10. Dynamic characteristics............................................ 8

10.1. Waveforms and test circuit...................................... 10

11. Package outline........................................................ 13

12. Abbreviations............................................................14

13. Revision history........................................................14

14. Legal information......................................................15

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 20 October 2020

74ALVT16823

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 20 October 2020

16 / 16

74ALVT16823DGG [NEXPERIA]

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