74AUP1G00GW-Q100 [NEXPERIA]
Low-power 2-input NAND gateProduction;
| 型号： | 74AUP1G00GW-Q100 |
| 厂家： | 
Nexperia |
| 描述： | Low-power 2-input NAND gateProduction 逻辑集成电路 |
| 文件： | 总14页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1G00-Q100
Low-power 2-input NAND gate
Rev. 3.1 — 11 July 2023
Product data sheet
1. General description
The 74AUP1G00-Q100 is a single 2-input NAND gate. Schmitt-trigger action at all inputs makes
the circuit tolerant of slower input rise and fall times. This device ensures very low static and
dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully
specified for partial power down applications using IOFF. The IOFF circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Complies with JEDEC standards:
•
•
•
•
•
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 Vto 2.7 V)
JESD8C (2.7 V to 3.6 V)
•
ESD protection:
•
•
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
•
•
•
•
•
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1G00GW-Q100 -40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads; SOT353-1
body width 1.25 mm
4. Marking
Table 2. Marking
Type number
Marking code [1]
74AUP1G00GW-Q100
pA
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
B
1
2
1
2
B
A
&
4
Y
4
Y
A
mna097
mna098
mna099
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram
6. Pinning information
6.1. Pinning
GW package
SOT353-1 (TSSOP5)
1
2
3
5
B
A
V
Y
CC
4
GND
aaa-035731
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
2 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
6.2. Pin description
Table 3. Pin description
Symbol
Pin
1
Description
B
data input
A
2
data input
GND
Y
3
ground (0 V)
data output
supply voltage
4
VCC
5
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
A
L
B
L
Y
H
H
H
L
L
H
L
H
H
H
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-50
-0.5
-0.5
-
Max
+4.6
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
[1]
+4.6
-
IOK
VO
output clamping current
output voltage
VO < 0 V
mA
Active mode
[1]
[1]
VCC + 0.5 V
Power-down mode; VCC = 0 V
VO = 0 V to VCC
+4.6
±20
+50
-
V
IO
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[2]
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
3 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
Conditions
Min
0.8
0
Max
3.6
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
3.6
V
VO
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
-40
0
+125
200
°C
ns/V
Δt/ΔV
input transition rise and fall rate
VCC = 0.8 V to 3.6 V
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 25 °C
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
VCC = 0.8 V
0.70×VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65×VCC
-
1.6
-
-
2.0
VIL
LOW-level input voltage
-
-
-
-
0.30×VCC
0.35×VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = -20 μA; VCC = 0.8 V to 3.6 V
VCC - 0.1
0.75×VCC
1.11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = -1.1 mA; VCC = 1.1 V
IO = -1.7 mA; VCC = 1.4 V
IO = -1.9 mA; VCC = 1.65 V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level output voltage VI = VIH or VIL
IO = 20 μA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.3×VCC
0.31
V
V
V
V
V
V
V
V
0.31
0.31
0.44
0.31
0.44
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
4 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
Symbol Parameter
Conditions
Min
Typ
Max
±0.1
±0.2
±0.2
Unit
μA
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
-
-
-
-
IOFF
ΔIOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
μA
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
μA
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.5
μA
ΔICC
CI
additional supply current
input capacitance
VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
[1]
-
-
-
-
40
-
μA
pF
pF
0.8
1.7
CO
output capacitance
-
Tamb = -40 °C to +85 °C
VIH HIGH-level input voltage
VCC = 0.8 V
0.70×VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.65×VCC
-
1.6
-
-
2.0
VIL
LOW-level input voltage
-
-
-
-
0.30×VCC
0.35×VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = -20 μA; VCC = 0.8 V to 3.6 V
VCC - 0.1
0.7×VCC
1.03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = -1.1 mA; VCC = 1.1 V
IO = -1.7 mA; VCC = 1.4 V
IO = -1.9 mA; VCC = 1.65 V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
1.30
1.97
1.85
2.67
2.55
VOL
LOW-level output voltage VI = VIH or VIL
IO = 20 μA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.3×VCC
0.37
V
V
IO = 1.7 mA; VCC = 1.4 V
V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
0.35
V
0.33
V
IO = 3.1 mA; VCC = 2.3 V
0.45
V
IO = 2.7 mA; VCC = 3.0 V
0.33
V
IO = 4.0 mA; VCC = 3.0 V
0.45
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
±0.5
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
±0.5
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
±0.6
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
0.9
50
μA
μA
ΔICC
additional supply current
VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V
[1]
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
5 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = -40 °C to +125 °C
VIH
HIGH-level input voltage
VCC = 0.8 V
0.75×VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
0.70×VCC
-
1.6
-
-
2.0
VIL
LOW-level input voltage
-
-
-
-
0.25×VCC
0.30×VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output voltage VI = VIH or VIL
IO = -20 μA; VCC = 0.8 V to 3.6 V
VCC - 0.11
0.6×VCC
0.93
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = -1.1 mA; VCC = 1.1 V
IO = -1.7 mA; VCC = 1.4 V
IO = -1.9 mA; VCC = 1.65 V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
1.17
1.77
1.67
2.40
2.30
VOL
LOW-level output voltage VI = VIH or VIL
IO = 20 μA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
0.33×VCC
0.41
V
V
IO = 1.7 mA; VCC = 1.4 V
V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
0.39
V
0.36
V
IO = 3.1 mA; VCC = 2.3 V
0.50
V
IO = 2.7 mA; VCC = 3.0 V
0.36
V
IO = 4.0 mA; VCC = 3.0 V
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
±0.75
±0.75
±0.75
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
-
-
1.4
75
μA
μA
ΔICC
additional supply current
VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V
[1]
[1] One input at VCC - 0.6 V, other input at VCC or GND.
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
6 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 5
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = 25 °C; CL = 5 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 0.8 V
[2]
[2]
[2]
[2]
-
17.5
5.3
3.8
3.1
2.5
2.2
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.5
2.0
1.6
1.3
1.0
11.0
6.8
5.3
4.0
3.6
Tamb = 25 °C; CL = 10 pF
tpd propagation delay
A, B to Y; see Fig. 4
VCC = 0.8 V
-
21.0
6.1
4.4
3.7
3.0
2.8
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.4
2.4
2.0
1.4
1.3
13.0
7.9
6.2
4.7
4.3
Tamb = 25 °C; CL = 15 pF
tpd propagation delay
A, B to Y; see Fig. 4
VCC = 0.8 V
-
24.5
6.9
5.0
4.1
3.5
3.2
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.4
2.8
2.0
1.7
1.6
14.8
8.9
7.0
5.3
4.9
Tamb = 25 °C; CL = 30 pF
tpd propagation delay
A, B to Y; see Fig. 4
VCC = 0.8 V
-
34.8
9.2
6.5
5.4
4.6
4.3
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.6
3.0
2.6
2.4
2.3
20.1
11.8
9.3
7.1
6.5
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
7 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
Symbol Parameter
Tamb = 25 °C
Conditions
Min
Typ [1]
Max
Unit
CPD
power dissipation
capacitance
f = 1 MHz; VI = GND to VCC
VCC = 0.8 V
[3]
-
-
-
-
-
-
2.6
2.8
2.9
3.1
3.6
4.2
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of the outputs.
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 5
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Max
Min
Max
CL = 5 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1]
[1]
[1]
2.1
1.8
1.4
1.1
1.0
12.2
7.8
6.2
4.7
4.2
2.1
1.8
1.4
1.1
1.0
13.5
8.6
6.9
5.2
4.7
ns
ns
ns
ns
ns
CL = 10 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.2
2.2
1.9
1.3
1.2
14.4
9.2
7.3
5.6
4.9
2.2
2.2
1.9
1.3
1.2
15.9
10.2
8.1
ns
ns
ns
ns
ns
6.2
5.4
CL = 15 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.1
2.5
2.0
1.5
1.4
16.5
10.5
8.3
3.1
2.5
2.0
1.5
1.4
18.2
11.6
9.2
ns
ns
ns
ns
ns
6.4
7.1
5.7
6.3
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
8 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
Symbol Parameter
CL = 30 pF
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Max
Min
Max
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1]
4.1
2.9
2.3
2.1
2.1
22.6
14.0
11.1
8.5
4.1
2.9
2.3
2.1
2.1
24.9
15.4
12.3
9.4
ns
ns
ns
ns
ns
7.6
8.4
[1] tpd is the same as tPLH and tPHL
.
11.1. Waveforms and test circuit
V
I
V
A, B input
GND
M
t
t
PHL
PLH
V
OH
V
Y output
M
mna612
V
OL
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig. 4. The data input (A or B) to output (Y) propagation delays
Table 10. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
0.5 × VCC
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
VCC
≤ 3.0 ns
V
V
EXT
CC
5 kΩ
V
I
V
O
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Fig. 5. Test circuit for measuring switching times
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
9 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
Table 11. Test data
Supply voltage
Load
VEXT
VCC
CL
RL [1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 kΩ or 1 MΩ open
GND
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ.
For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
10 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
12. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
B
E
A
X
c
(5x)
y
H
E
v
M
A
e
1
5
4
pin 1 index
A
A
2
A
1
1
2
3
A
3
θ
L
w
M B
p
b
p
(5x)
detail X
e
e
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
(1)
(1)
A
A
A
A
b
c
D
E
e
e
1
H
E
L
p
v
w
y
θ
1
2
3
p
max 1.1 0.1 1.0
0.8 0.8
0.30 0.25 2.2 1.35
0.15 0.08 1.8 1.15
2.4 0.46
1.8 0.26
8°
0°
mm
0.15
0.65 1.3
0.3 0.1 0.1
0
min
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot353-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
21-12-15
21-12-16
SOT353-1
SC-88A
MO-203
Fig. 6. Package outline SOT353-1 (TSSOP5)
©
74AUP1G00_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
11 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
13. Abbreviations
Table 12. Abbreviations
Acronym
Description
DUT
ESD
HBM
Device Under Test
ElectroStatic Discharge
Human Body Model
14. Revision history
Table 13. Revision history
Document ID
Release date
20230711
Data sheet status
Change notice Supersedes
- 74AUP1G00_Q100 v.2
74AUP1G00_Q100 v.3.1
Modifications:
Product data sheet
•
Section 2: ESD specification updated according to the latest JEDEC standard.
20220113 Product data sheet 74AUP1G00_Q100 v.1
Section 1 and Section 2 updated.
74AUP1G00_Q100 v.2
Modifications:
-
•
•
•
Table 5: Derating values for Ptot total power dissipation updated.
Fig. 6: Package outline drawing for SOT353-1 (TSSOP5) has changed.
74AUP1G00_Q100 v.1
20190404
Product data sheet
-
-
©
74AUP1G00_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
12 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
15. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
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Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
13 / 14
Nexperia
74AUP1G00-Q100
Low-power 2-input NAND gate
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................4
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit........................................ 9
12. Package outline........................................................ 11
13. Abbreviations............................................................12
14. Revision history........................................................12
15. Legal information......................................................13
© Nexperia B.V. 2023. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 11 July 2023
©
74AUP1G00_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 3.1 — 11 July 2023
14 / 14
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