74AUP2G97 [NEXPERIA]

Low-power dual PCB configurable multiple function gate;


型号：	74AUP2G97
厂家：	Nexperia
描述：	Low-power dual PCB configurable multiple function gate PC
文件：	总16页 (文件大小：259K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AUP2G97

Low-power dual PCB configurable multiple function gate

Rev. 3 — 22 July 2019

Product data sheet

1. General description

The 74AUP2G97 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate

within the device can be configured as any of the following logic functions MUX, AND, OR, NAND,

NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to V_CCor GND.

This device ensures very low static and dynamic power consumption across the entire V_CCrange

from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

•

Wide supply voltage range from 0.8 V to 3.6 V

•

High noise immunity

ESD protection:

•

HBM JESD22-A114F exceeds 5000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Low static power consumption; I_CC= 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD 78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial power-down mode operation

Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range

-40 °C to +125 °C

Name

Description

Version

74AUP2G97DP

74AUP2G97GU

TSSOP10 plastic thin shrink small outline package; 10 leads; SOT552-1

body width 3 mm

-40 °C to +125 °C

XQFN10

plastic, extremely thin quad flat package; no leads; SOT1160-1

10 terminals; body 1.40 × 1.80 × 0.50 mm

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74AUP2G97

Low-power dual PCB configurable multiple function gate

4. Marking

Table 2. Marking

Type number

Marking code [1]

74AUP2G97DP

74AUP2G97GU

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

aaa-015396

Fig. 1. Logic symbol (one gate)

6. Pinning information

6.1. Pinning

74AUP2G97

terminal 1

index area

74AUP2G97

GND

Transparent top view

aaa-015399

aaa-015397

Fig. 2. Pin configuration SOT552-1 (TSSOP10)

Fig. 3. Pin configuration SOT1160-1 (XQFN10)

74AUP2G97

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Product data sheet

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74AUP2G97

Low-power dual PCB configurable multiple function gate

6.2. Pin description

Table 3. Pin description

Symbol

Description

SOT1160-1

SOT552-1

1, 6

2, 7

3, 8

9, 4

1A, 2A

1B, 2B

1C, 2C

1Y, 2Y

GND

10, 5

1, 6

2, 7

8, 3

data input

data output

ground (0 V)

supply voltage

V_CC

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level.

Input

Output

7.1. Logic configurations

Table 5. Function selection table

Logic function

Figure

2-input MUX

see Fig. 4

see Fig. 5

see Fig. 6

see Fig. 7

see Fig. 8

see Fig. 9

see Fig. 10

2-input AND

2-input OR with one input inverted

2-input NAND with one input inverted

2-input AND with one input inverted

2-input NOR with one input inverted

2-input OR

Inverter

Buffer

74AUP2G97

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Product data sheet

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74AUP2G97

Low-power dual PCB configurable multiple function gate

2, 7

3, 8

2, 7

3, 8

1, 6

9, 4

1, 6

9, 4

aaa-015401

aaa-015402

Pin numbers are not valid for SOT1160-1 package

Fig. 4. 2-input MUX

Pin numbers are not valid for SOT1160-1 package

Fig. 5. 2-input AND gate

2, 7

3, 8

2, 7

3, 8

1, 6

9, 4

1, 6

9, 4

aaa-015403

aaa-015404

Pin numbers are not valid for SOT1160-1 package

Fig. 6. 2-input NAND gate with input A inverted or

2-input OR gate with input C inverted

Fig. 7. 2-input NOR gate with input B inverted or

2-input AND gate with input C inverted

2, 7

3, 8

2, 7

3, 8

1, 6

9, 4

1, 6

9, 4

aaa-015405

aaa-015406

Pin numbers are not valid for SOT1160-1 package

Fig. 8. 2-input OR gate

Pin numbers are not valid for SOT1160-1 package

Fig. 9. Inverter

2, 7

3, 8

1, 6

9, 4

aaa-015407

Pin numbers are not valid for SOT1160-1 package

Fig. 10. Buffer

74AUP2G97

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Product data sheet

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74AUP2G97

Low-power dual PCB configurable multiple function gate

8. Limiting values

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

-0.5

-50

-0.5

-50

-0.5

Max

+4.6

Unit

V_CC

I_IK

supply voltage

input clamping current

input voltage

V_I< 0 V

V_I

[1]

+4.6

I_OK

V_O

I_O

output clamping current

output voltage

V_O< 0 V

Active mode and Power-down mode

V_O= 0 V to V_CC

+4.6

±20

output current

°C

I_CC

I_GND

T_stg

P_tot

supply current

ground current

-50

-65

storage temperature

total power dissipation

+150

250

T_amb= -40 °C to +125 °C

[2]

[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SOT552-1 (TSSOP10) packages: P_totderates linearly with 8.3 mW/K above 120 °C.

For SOT1160-1 (XQFN10) packages: P_totderates linearly with 7.1 mW/K above 115 °C.

9. Recommended operating conditions

Table 7. Recommended operating conditions

Symbol Parameter

Conditions

Min

0.8

Max

3.6

Unit

V_CC

V_I

supply voltage

input voltage

output voltage

3.6

V_O

Active mode

V_CC

3.6

Power-down mode; V_CC= 0 V

T_amb

ambient temperature

-40

+125

°C

10. Static characteristics

Table 8. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

T_amb= 25 °C

Conditions

Min

Typ

Max

Unit

V_OH

HIGH-level output voltage V_I= V_T+or V_T-

I_O= -20 μA; V_CC= 0.8 V to 3.6 V

V_CC- 0.1

0.75 × V_CC

1.11

I_O= -1.1 mA; V_CC= 1.1 V

I_O= -1.7 mA; V_CC= 1.4 V

I_O= -1.9 mA; V_CC= 1.65 V

I_O= -2.3 mA; V_CC= 2.3 V

I_O= -3.1 mA; V_CC= 2.3 V

I_O= -2.7 mA; V_CC= 3.0 V

I_O= -4.0 mA; V_CC= 3.0 V

1.32

2.05

1.9

2.72

2.6

74AUP2G97

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Product data sheet

Rev. 3 — 22 July 2019

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74AUP2G97

Low-power dual PCB configurable multiple function gate

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_OL

LOW-level output voltage V_I= V_T+or V_T-

I_O= 20 μA; V_CC= 0.8 V to 3.6 V

0.1

0.3 × V_CC

0.31

I_O= 1.1 mA; V_CC= 1.1 V

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

I_O= 3.1 mA; V_CC= 2.3 V

I_O= 2.7 mA; V_CC= 3.0 V

I_O= 4.0 mA; V_CC= 3.0 V

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

0.31

0.44

0.31

0.44

I_I

input leakage current

±0.1

μA

I_OFF

ΔI_OFF

power-off leakage current V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

±0.2

additional power-off

leakage current

V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V to 0.2 V

±0.2

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

V_CC= 0.8 V to 3.6 V

0.5

μA

ΔI_CC

C_I

additional supply current

input capacitance

V_I= V_CC- 0.6 V; I_O= 0 A; V_CC= 3.3 V

V_CC= 0 V to 3.6 V; V_I= GND or V_CC

V_O= GND; V_CC= 0 V

[1]

μA

1.1

1.7

C_O

output capacitance

T_amb= -40 °C to +85 °C

V_OHHIGH-level output voltage V_I= V_T+or V_T-

I_O= -20 μA; V_CC= 0.8 V to 3.6 V

I_O= -1.1 mA; V_CC= 1.1 V

I_O= -1.7 mA; V_CC= 1.4 V

I_O= -1.9 mA; V_CC= 1.65 V

I_O= -2.3 mA; V_CC= 2.3 V

I_O= -3.1 mA; V_CC= 2.3 V

I_O= -2.7 mA; V_CC= 3.0 V

I_O= -4.0 mA; V_CC= 3.0 V

V_CC- 0.1

0.7 × V_CC

1.03

1.30

1.97

1.85

2.67

2.55

V_OL

LOW-level output voltage V_I= V_T+or V_T-

I_O= 20 μA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

0.1

0.3 × V_CC

0.37

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

0.35

0.33

I_O= 3.1 mA; V_CC= 2.3 V

0.45

I_O= 2.7 mA; V_CC= 3.0 V

0.33

I_O= 4.0 mA; V_CC= 3.0 V

0.45

I_I

input leakage current

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

±0.5

μA

I_OFF

ΔI_OFF

power-off leakage current V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

±0.5

additional power-off

leakage current

V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V to 0.2 V

±0.6

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

V_CC= 0.8 V to 3.6 V

0.9

μA

ΔI_CC

additional supply current

V_I= V_CC- 0.6 V; I_O= 0 A; V_CC= 3.3 V

[1]

74AUP2G97

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Product data sheet

Rev. 3 — 22 July 2019

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74AUP2G97

Low-power dual PCB configurable multiple function gate

Symbol Parameter

Conditions

Min

Typ

Max

Unit

T_amb= -40 °C to +125 °C

V_OH

HIGH-level output voltage V_I= V_T+or V_T-

I_O= -20 μA; V_CC= 0.8 V to 3.6 V

V_CC- 0.11

0.6 × V_CC

0.93

I_O= -1.1 mA; V_CC= 1.1 V

I_O= -1.7 mA; V_CC= 1.4 V

I_O= -1.9 mA; V_CC= 1.65 V

I_O= -2.3 mA; V_CC= 2.3 V

I_O= -3.1 mA; V_CC= 2.3 V

I_O= -2.7 mA; V_CC= 3.0 V

I_O= -4.0 mA; V_CC= 3.0 V

1.17

1.77

1.67

2.40

2.30

V_OL

LOW-level output voltage V_I= V_T+or V_T-

I_O= 20 μA; V_CC= 0.8 V to 3.6 V

I_O= 1.1 mA; V_CC= 1.1 V

0.11

0.33 × V_CC

0.41

I_O= 1.7 mA; V_CC= 1.4 V

I_O= 1.9 mA; V_CC= 1.65 V

I_O= 2.3 mA; V_CC= 2.3 V

0.39

0.36

I_O= 3.1 mA; V_CC= 2.3 V

0.50

I_O= 2.7 mA; V_CC= 3.0 V

0.36

I_O= 4.0 mA; V_CC= 3.0 V

0.50

I_I

input leakage current

V_I= GND to 3.6 V; V_CC= 0 V to 3.6 V

±0.75

μA

I_OFF

ΔI_OFF

power-off leakage current V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V

additional power-off

leakage current

V_Ior V_O= 0 V to 3.6 V; V_CC= 0 V to 0.2 V

I_CC

supply current

V_I= GND or V_CC; I_O= 0 A;

V_CC= 0.8 V to 3.6 V

1.4

μA

ΔI_CC

additional supply current

V_I= V_CC- 0.6 V; I_O= 0 A; V_CC= 3.3 V

[1]

[1] One input at V_CC- 0.6 V, other input at V_CCor GND.

10.1. Transfer characteristics

Table 9. Transfer characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit, see Fig. 16.

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to Unit

+125 °C

Min Typ Max Min Max Min Max

V_T+

positive-going

threshold voltage

see Fig. 11 and Fig. 12

V_CC= 0.8 V

0.30

0.53

0.74

0.91

1.37

1.88

0.60 0.30 0.60 0.30 0.62

0.90 0.53 0.90 0.53 0.92

1.11 0.74 1.11 0.74 1.13

1.29 0.91 1.29 0.91 1.31

1.77 1.37 1.77 1.37 1.80

2.29 1.88 2.29 1.88 2.32

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3.0 V

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Low-power dual PCB configurable multiple function gate

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to Unit

+125 °C

Min Typ Max Min Max Min Max

V_T-

negative-going

threshold voltage

see Fig. 11 and Fig. 12

V_CC= 0.8 V

0.10

0.26

0.39

0.47

0.69

0.88

0.60 0.10 0.60 0.10 0.60

0.65 0.26 0.65 0.26 0.65

0.75 0.39 0.75 0.39 0.75

0.84 0.47 0.84 0.47 0.84

1.04 0.69 1.04 0.69 1.04

1.24 0.88 1.24 0.88 1.24

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3.0 V

V_H

hysteresis voltage

(V_T+- V_T-); see Fig. 11,

Fig. 12, Fig. 13 and Fig. 14

V_CC= 0.8 V

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3.0 V

0.07

0.08

0.18

0.27

0.53

0.79

0.50 0.07 0.50 0.07 0.50

0.46 0.08 0.46 0.08 0.46

0.56 0.18 0.56 0.18 0.56

0.66 0.27 0.66 0.27 0.66

0.92 0.53 0.92 0.53 0.92

1.31 0.79 1.31 0.79 1.31

10.2. Waveforms transfer characteristics

T+

T-

mna208

T+

T-

mna207

V_T+and V_T-limits at 70 % and 20 %.

Fig. 11. Transfer characteristic

Fig. 12. Definition of V_T+, V_T-and V_H

001aad691

001aad692

240

1200

(µA)

160

800

400

0.4

0.8

1.2

1.6

2.0

1.0

2.0

3.0

V (V)

Fig. 13. Typical transfer characteristics; V_CC= 1.8 V

Fig. 14. Typical transfer characteristics; V_CC= 3.0 V

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Product data sheet

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74AUP2G97

Low-power dual PCB configurable multiple function gate

11. Dynamic characteristics

Table 10. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit, see Fig. 16.

Symbol Parameter Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min Typ [1] Max

Min

Max

Min

Max

C_L= 5 pF

t_pd

propagation nA, nB, nC to nY; see Fig. 15

[2]

delay

V_CC= 0.8 V

23.0

6.6

4.7

3.9

3.2

2.8

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

2.8

2.3

2.2

2.0

1.9

12.6

7.6

6.2

4.5

3.9

2.5

2.0

1.7

1.5

13.0

8.2

6.8

5.1

4.1

2.5

2.0

1.7

1.5

13.2 ns

8.6 ns

7.2 ns

5.3 ns

4.3 ns

C_L= 10 pF

t_pd

propagation nA, nB, nC to nY; see Fig. 15

delay

V_CC= 0.8 V

26.6

7.4

5.3

4.5

3.7

3.4

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

3.2

2.6

2.5

2.4

2.3

14.3

8.7

7.0

5.2

4.6

2.9

2.8

2.3

2.1

1.9

14.9

9.4

7.8

5.9

4.9

2.9

2.8

2.3

2.1

1.9

15.2 ns

9.8 ns

8.2 ns

6.1 ns

5.1 ns

C_L= 15 pF

t_pdpropagation nA, nB, nC to nY; see Fig. 15

delay

V_CC= 0.8 V

30.1

8.2

5.9

5.0

4.2

3.8

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

3.6

2.9

2.8

2.7

2.5

16.0

9.6

7.8

5.8

5.1

3.2

3.1

2.5

2.4

2.2

16.7

10.4

8.7

3.2

3.1

2.5

2.4

2.2

17.0 ns

10.9 ns

9.1 ns

6.9 ns

5.7 ns

6.5

5.5

C_L= 30 pF

t_pd

propagation nA, nB, nC to nY; see Fig. 15

delay

V_CC= 0.8 V

38.3

10.5

7.4

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

4.6

3.7

3.5

3.4

3.2

20.9

12.2

9.9

4.0

3.8

3.2

3.1

2.8

21.8

13.3

11.1

8.3

4.0

3.8

3.2

3.1

2.8

22.2 ns

14.0 ns

11.8 ns

8.8 ns

7.4 ns

6.3

5.3

7.4

4.9

6.6

7.0

74AUP2G97

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Product data sheet

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Low-power dual PCB configurable multiple function gate

Symbol Parameter Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min Typ [1] Max

Min

Max

Min

Max

C_L= 5 pF, 10 pF, 15 pF and 30 pF

C_PD

power

dissipation

capacitance

f_i= 1 MHz; V_I= GND to V_CC

V_CC= 0.8 V

[3]

2.6

2.8

2.9

3.1

3.7

4.3

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[1] All typical values are measured at nominal V_CC

[2] t_pdis the same as t_PLHand t_PHL

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

74AUP2G97

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Product data sheet

Rev. 3 — 22 July 2019

10 / 16

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Low-power dual PCB configurable multiple function gate

11.1. Waveforms and test circuit

nA, nB, nC input

GND

PLH

PHL

nY output

PHL

PLH

nY output

aaa-015383

Measurement points are given in Table 11.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 15. Input nA, nB and nC to output nY propagation delay times

Table 11. Measurement points

Supply voltage

V_CC

Output

V_M

Input

V_M

V_I

t_r= t_f

0.8 V to 3.6 V

0.5 × V_CC

V_CC

≤ 3.0 ns

EXT

5 kΩ

DUT

001aac521

Test data is given in Table 12.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig. 16. Test circuit for measuring switching times

Table 12. Test data

Supply voltage Load

V_EXT

V_CC

C_L

R_L[1]

t_PLH, t_PHL

open

t_PZH, t_PHZ

t_PZL, t_PLZ

0.8 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ

GND

2V_CC

[1] For measuring enable and disable times, R_L= 5 kΩ.

For measuring propagation delays, setup and hold times and pulse width R_L= 1 MΩ.

74AUP2G97

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Product data sheet

Rev. 3 — 22 July 2019

11 / 16

Nexperia

74AUP2G97

Low-power dual PCB configurable multiple function gate

12. Package outline

TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm

SOT552-1

(A )

pin 1 index

detail X

w M

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

0.15

0.05

0.95

0.80

0.30

0.15

0.23

0.15

3.1

2.9

3.1

2.9

5.0

4.8

0.7

0.4

0.67

0.34

6°

0°

1.1

0.5

0.95

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-07-29

03-02-18

SOT552-1

Fig. 17. Package outline SOT552-1 (TSSOP10)

74AUP2G97

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Product data sheet

Rev. 3 — 22 July 2019

12 / 16

Nexperia

74AUP2G97

Low-power dual PCB configurable multiple function gate

XQFN10: plastic, extremely thin quad flat package; no leads;

10 terminals; body 1.40 x 1.80 x 0.50 mm

SOT1160-1

terminal 1

index area

detail X

C A B

terminal 1

index area

2 mm

scale

Dimensions

(1)

Unit

max 0.5 0.05

mm nom

min

0.25 1.5 1.9

0.127 0.20 1.4 1.8

0.15 1.3 1.7

0.45 0.55

0.4 0.40 0.50 0.1 0.05 0.05 0.05

0.35 0.45

0.4

0.8

0.00

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot1160-1_po

Issue date

References

Outline

version

European

projection

IEC

- - -

JEDEC

- - -

JEITA

- - -

09-12-28

09-12-29

SOT1160-1

Fig. 18. Package outline SOT1160-1 (XQFN10)

74AUP2G97

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Product data sheet

Rev. 3 — 22 July 2019

13 / 16

Nexperia

74AUP2G97

Low-power dual PCB configurable multiple function gate

13. Abbreviations

Table 13. Abbreviations

Acronym

Description

CDM

DUT

ESD

HBM

Charged Device Model

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

PCB

Printed-Circuit Board

14. Revision history

Table 14. Revision history

Document ID

74AUP2G97 v.3

Modifications:

Release date

Data sheet status

Product data sheet

Change notice Supersedes

- 74AUP2G97 v.2

20190722

•

The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Type number 74AUP2G97GF (SOT1081-2) removed.

74AUP2G97 v.2

Modifications:

20151202

Product data sheet

74AUP2G97 v.1

•

Maximum value temperature range TSSOP10 (74AUP2G97DP) changed from 85 °C to 125 °C.

Removed 74AUP2G97GM (SOT1049-3).

74AUP2G97 v.1

20141104

Product data sheet

74AUP2G97

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Product data sheet

Rev. 3 — 22 July 2019

14 / 16

Nexperia

74AUP2G97

Low-power dual PCB configurable multiple function gate

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

15. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

74AUP2G97

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Product data sheet

Rev. 3 — 22 July 2019

15 / 16

Nexperia

74AUP2G97

Low-power dual PCB configurable multiple function gate

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Marking..........................................................................2

5. Functional diagram.......................................................2

6. Pinning information......................................................2

6.1. Pinning.........................................................................2

6.2. Pin description.............................................................3

7. Functional description................................................. 3

7.1. Logic configurations.....................................................3

8. Limiting values............................................................. 5

9. Recommended operating conditions..........................5

10. Static characteristics..................................................5

10.1. Transfer characteristics..............................................7

10.2. Waveforms transfer characteristics............................8

11. Dynamic characteristics.............................................9

11.1. Waveforms and test circuit.......................................11

12. Package outline........................................................ 12

13. Abbreviations............................................................14

14. Revision history........................................................14

15. Legal information......................................................15

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 22 July 2019

74AUP2G97

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 22 July 2019

16 / 16

74AUP2G97 [NEXPERIA]

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