74AVC2T45GT中文资料_数据手册_规格书

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver;

3-state

Rev. 10 — 4 November 2021

Product data sheet

1. General description

The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level translation.

It features two data input-output ports (nA and nB), a direction control input (DIR) and dual-supply

pins (V_CC(A)and V_CC(B)). Both V_CC(A)and V_CC(B)can be supplied at any voltage between 0.8 V

and 3.6 V making the device suitable for translating between any of the low voltage nodes

(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to V_CC(A)and pins nB

are referenced to V_CC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR

allows transmission from nB to nA.

The device is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing any damaging backflow current through the device when it is

powered down. In Suspend mode when either V_CC(A)or V_CC(B)are at GND level, both A and B are

in the high-impedance OFF-state.

2. Features and benefits

•

Wide supply voltage range:

•

V_CC(A): 0.8 V to 3.6 V

V_CC(B): 0.8 V to 3.6 V

•

High noise immunity

Complies with JEDEC standards:

•

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F Class 3B exceeds 8000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101C exceeds 1000 V

Maximum data rates:

•

500 Mbit/s (1.8 V to 3.3 V translation)

320 Mbit/s (<1.8 V to 3.3 V translation)

320 Mbit/s (translate to 2.5 V or 1.8 V)

280 Mbit/s (translate to 1.5 V)

240 Mbit/s (translate to 1.2 V)

•

Suspend mode

Latch-up performance exceeds 100 mA per JESD 78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial Power-down mode operation

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

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74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74AVC2T45DP

74AVC2T45DC

74AVC2T45GT

74AVC2T45GF

74AVC2T45GN

74AVC2T45GS

74AVC2T45GX

-40 °C to +125 °C

-40 °C to +85 °C

TSSOP8

plastic thin shrink small outline package; 8 leads; SOT505-2

body width 3 mm; lead length 0.5 mm

VSSOP8

XSON8

X2SON8

plastic very thin shrink small outline package;

8 leads; body width 2.3 mm

SOT765-1

SOT833-1

SOT1089

SOT1116

SOT1203

SOT1233-2

plastic extremely thin small outline package;

no leads; 8 terminals; body 1 × 1.95 × 0.5 mm

extremely thin small outline package; no leads;

8 terminals; body 1.35 × 1 × 0.5 mm

extremely thin small outline package; no leads;

8 terminals; body 1.2 × 1.0 × 0.35 mm

extremely thin small outline package; no leads;

8 terminals; body 1.35 × 1.0 × 0.35 mm

plastic thermal enhanced extremely thin

small outline package; no leads; 8 terminals;

body 1.35 × 0.8 × 0.32 mm

4. Marking

Table 2. Marking

Type number

Marking code[1]

74AVC2T45DP

74AVC2T45DC

74AVC2T45GT

74AVC2T45GF

74AVC2T45GN

74AVC2T45GS

74AVC2T45GX

B45

B5

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

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Product data sheet

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74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

5. Functional diagram

5

DIR

1A

2

1A

7

6

1B

3

2A

2B

V

CC(B)

CC(A)

V

CC(A)

CC(B)

001aag577

001aag578

Fig. 1. Logic symbol

Fig. 2. Logic diagram

6. Pinning information

6.1. Pinning

74AVC2T45

V

1

2

3

4

8

7

6

5

V

CC(B)

CC(A)

1A

1B

74AVC2T45

2A

2B

1

2

3

4

8

7

6

5

V

CC(B)

CC(A)

1A

1B

GND

DIR

2A

2B

GND

DIR

001aag580

Transparent top view

001aag579

Fig. 3. Pin configuration SOT505-2 (TSSOP8) and

SOT765-1 (VSSOP8)

Fig. 4. Pin configuration SOT833-1, SOT1089,

SOT1116 and SOT1203 (XSON8)

74AVC2T45

1

V

7

1B

2B

CC(A)

8

V

CC(B)

1A

2

6

4

GND

2A

3

5

DIR

aaa-034160

Transparent top view

Fig. 5. Pin configuration SOT1233-2 (X2SON8)

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Product data sheet

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74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

6.2. Pin description

Table 3. Pin description

Symbol

1

Description

V_CC(A)

1A

supply voltage A (referenced to pins 1A, 2A and DIR)

data input or output

2

2A

3

data input or output

GND

DIR

2B

4

ground (0 V)

5

direction control

6

data input or output

1B

7

data input or output

V_CC(B)

8

supply voltage B (referenced to pins 1B and 2B)

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

Supply voltage

V_CC(A), V_CC(B)

0.8 V to 3.6 V

GND [3]

Input

Input/output [1]

DIR [2]

nA

nB

L

nA = nB

input

Z

input

nB = nA

Z

H

X

[1] The input circuit of the data I/O is always active.

[2] The DIR input circuit is referenced to V_CC(A)

[3] If at least one of V_CC(A)or V_CC(B)is at GND level, the device goes into Suspend mode.

.

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Product data sheet

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74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

-0.5

-50

-0.5

-50

-0.5

-

Max

+4.6

-

Unit

V

V_CC(A)supply voltage A

V_CC(B)supply voltage B

V

I_IK

input clamping current

V_I< 0 V

mA

V

V_I

input voltage

[1]

+4.6

-

I_OK

V_O

output clamping current

output voltage

V_O< 0 V

mA

Active mode

[1][2][3]

[1]

V_CCO+ 0.5 V

Suspend or 3-state mode

V_O= 0 V to V_CCO

I_CC(A)or I_CC(B)

+4.6

±50

100

-

V

I_O

output current

mA

°C

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

-100

-65

-

storage temperature

total power dissipation

+150

250

T_amb= -40 °C to +125 °C

[4]

mW

[1] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] V_CCOis the supply voltage associated with the output port.

[3] V_CCO+ 0.5 V should not exceed 4.6 V.

[4] For SOT505-2 (TSSOP8) package: P_totderates linearly with 4.6 mW/K above 96 °C.

For SOT765-1 (VSSOP8) package: P_totderates linearly with 4.9 mW/K above 99 °C.

For SOT833-1 (XSON8) package: P_totderates linearly with 3.1 mW/K above 68 °C.

For SOT1089 (XSON8) package: P_totderates linearly with 4.0 mW/K above 88 °C.

For SOT1116 (XSON8) package: P_totderates linearly with 4.2 mW/K above 90 °C.

For SOT1203 (XSON8) package: P_totderates linearly with 3.6 mW/K above 81 °C.

For SOT1233-2 (X2SON8) package: P_totderates linearly with 7.7 mW/K above 118 °C.

9. Recommended operating conditions

Table 6. Recommended operating conditions

Symbol Parameter

Conditions

Min

0.8

0

Max

3.6

Unit

V

V_CC(A)supply voltage A

V_CC(B)supply voltage B

3.6

V

V_I

input voltage

3.6

V

V_O

output voltage

Active mode

[1]

[2]

0

V_CCO

3.6

V

Suspend or 3-state mode

0

V

T_amb

ambient temperature

-40

-

+125

5

°C

ns/V

Δt/ΔV

input transition rise and fall rate

V_CCI= 0.8 V to 3.6 V

[1] V_CCOis the supply voltage associated with the output port.

[2] V_CCIis the supply voltage associated with the input port.

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74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

10. Static characteristics

Table 7. Typical static characteristics at T_amb= 25 °C

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_OH

V_OL

I_I

HIGH-level output

voltage

V_I= V_IHor V_IL; I_O= -1.5 mA;

V_CC(A)= V_CC(B)= 0.8 V

-

0.69

-

V

LOW-level output

voltage

V_I= V_IHor V_IL; I_O= 1.5 mA;

V_CC(A)= V_CC(B)= 0.8 V

-

0.07

±0.025

±0.5

±0.1

1.0

-

±0.25

±2.5

±1

V

input leakage

current

DIR input; V_I= 0 V or 3.6 V;

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

μA

pF

I_OZ

I_OFF

OFF-state output

current

A or B port; V_O= 0 V or V_CCO

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

;

[1][2]

power-off leakage

current

A port; V_Ior V_O= 0 V to 3.6 V; V_CC(A)= 0 V;

V_CC(B)= 0.8 V to 3.6 V

B port; V_Ior V_O= 0 V to 3.6 V; V_CC(B)= 0 V;

V_CC(A)= 0.8 V to 3.6 V

±1

C_I

input capacitance

DIR input; V_I= 0 V or 3.3 V;

V_CC(A)= V_CC(B)= 3.3 V

-

C_I/O

input/output

capacitance

A and B port; Suspend mode;

V_O= V_CCOor GND; V_CC(A)= V_CC(B)= 3.3 V

[2]

4.0

-

[1] For I/O ports, the parameter I_OZincludes the input leakage current.

[2] V_CCOis the supply voltage associated with the output port.

Table 8. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Max

Min

Max

V_IH

HIGH-level

data input

[1]

input voltage

V_CCI= 0.8 V

0.70V_CCI

0.65V_CCI

1.6

-

0.70V_CCI

0.65V_CCI

1.6

-

V

V_CCI= 1.1 V to 1.95 V

V_CCI= 2.3 V to 2.7 V

V_CCI= 3.0 V to 3.6 V

2

DIR input

V_CC(A)= 0.8 V

0.70V_CC(A)

-

0.70V_CC(A)

-

V

V_CC(A)= 1.1 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

0.65V_CC(A)

1.6

2

1.6

2

V_IL

LOW-level

data input

[1]

input voltage

V_CCI= 0.8 V

-

0.30V_CCI

0.35V_CCI

0.7

-

0.30V_CCI

0.35V_CCI

0.7

V

V_CCI= 1.1 V to 1.95 V

V_CCI= 2.3 V to 2.7 V

V_CCI= 3.0 V to 3.6 V

0.9

DIR input

V_CC(A)= 0.8 V

-

0.30V_CC(A)

0.35V_CC(A)

0.7

-

0.30V_CC(A)

0.35V_CC(A)

0.7

V

V_CC(A)= 1.1 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

0.9

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Product data sheet

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74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Max

Min

Max

V_OH

HIGH-level

V_I= V_IHor V_IL

[2]

output voltage

I_O= -100 μA;

V_CCO- 0.1

-

V_CCO- 0.1

-

V

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

I_O= -3 mA; V_CC(A)= V_CC(B)= 1.1 V

I_O= -6 mA; V_CC(A)= V_CC(B)= 1.4 V

I_O= -8 mA; V_CC(A)= V_CC(B)= 1.65 V

I_O= -9 mA; V_CC(A)= V_CC(B)= 2.3 V

I_O= -12 mA; V_CC(A)= V_CC(B)= 3.0 V

V_I= V_IHor V_IL

0.85

1.05

1.2

-

0.85

1.05

1.2

-

V

1.75

2.3

1.75

2.3

V_OL

LOW-level

output voltage

I_O= 100 μA;

-

0.1

-

0.1

V

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

I_O= 3 mA; V_CC(A)= V_CC(B)= 1.1 V

I_O= 6 mA; V_CC(A)= V_CC(B)= 1.4 V

I_O= 8 mA; V_CC(A)= V_CC(B)= 1.65 V

I_O= 9 mA; V_CC(A)= V_CC(B)= 2.3 V

I_O= 12 mA; V_CC(A)= V_CC(B)= 3.0 V

-

0.25

0.35

0.45

0.55

0.7

-

0.25

0.35

0.45

0.55

0.7

V

I_I

input leakage DIR input; V_I= 0 V or 3.6 V;

±1

±1.5

μA

current

V_CC(A)= V_CC(B)= 0.8 V to 3.6 V

I_OZ

I_OFF

OFF-state

output current V_CC(A)= V_CC(B)= 3.6 V

A or B port; V_O= 0 V or V_CCO

;

[2][3]

-

±5

-

±7.5

±35

μA

power-off

leakage

current

A port; V_Ior V_O= 0 V to 3.6 V;

V_CC(A)= 0 V; V_CC(B)= 0.8 V to 3.6 V

B port; V_Ior V_O= 0 V to 3.6 V;

V_CC(B)= 0 V; V_CC(A)= 0.8 V to 3.6 V

I_CC

supply current A port; V_I= 0 V or V_CCI; I_O= 0 A

[1]

V_CC(A)= 0.8 V to 3.6 V;

V_CC(B)= 0.8 V to 3.6 V

-

8

-

11.5

μA

V_CC(A)= 3.6 V; V_CC(B)= 0 V

V_CC(A)= 0 V; V_CC(B)= 3.6 V

B port; V_I= 0 V or V_CCI; I_O= 0 A

-

8

-

11.5

-

μA

-2

-8

V_CC(A)= 0.8 V to 3.6 V;

V_CC(B)= 0.8 V to 3.6 V

-

8

-

11.5

μA

V_CC(A)= 3.6 V; V_CC(B)= 0 V

V_CC(A)= 0 V; V_CC(B)= 3.6 V

A plus B port (I_CC(A)+ I_CC(B));

-2

-

-8

-

μA

8

11.5

23

-

16

-

I_O= 0 A; V_I= 0 V or V_CCI

V_CC(A)= 0.8 V to 3.6 V;

V_CC(B)= 0.8 V to 3.6 V

;

[1] V_CCIis the supply voltage associated with the data input port.

[2] V_CCOis the supply voltage associated with the output port.

[3] For I/O ports, the parameter I_OZincludes the input leakage current.

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Product data sheet

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74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

11. Dynamic characteristics

Table 9. Typical dynamic characteristics at V_CC(A)= 0.8 V and T_amb= 25 °C

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7

Symbol Parameter

Conditions

V_CC(B)

Unit

0.8 V

[1] 15.5

[2] 12.2

[2] 11.7

[3] 27.2

[3] 27.7

1.2 V

8.1

1.5 V

1.8 V

7.7

2.5 V

8.4

3.3 V

t_pd

t_dis

t_en

propagation delay A to B

7.6

12.3

12.2

7.6

9.2

ns

B to A

12.7

12.2

7.9

12.2

8.2

12.0

12.2

8.7

11.8 ns

12.2 ns

10.2 ns

22.0 ns

21.4 ns

disable time

enable time

DIR to A

DIR to B

DIR to A

DIR to B

20.6

20.3

19.9

19.8

20.4

19.9

20.7

20.6

[1] t_pdis the same as t_PLHand t_PHL

[2] t_disis the same as t_PLZand t_PHZ

[3] t_enis the same as t_PZLand t_PZH

t_enis a calculated value using the formula shown in Section 12.4

Table 10. Typical dynamic characteristics at V_CC(B)= 0.8 V and T_amb= 25 °C

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7

Symbol Parameter

Conditions

V_CC(A)

1.5 V

Unit

0.8 V

[1] 15.5

[2] 12.2

[2] 11.7

[3] 27.2

[3] 27.7

1.2 V

12.7

8.1

1.8 V

12.2

7.7

2.5 V

12.0

8.4

3.3 V

t_pd

t_dis

t_en

propagation delay A to B

12.3

7.6

11.8 ns

B to A

9.2

3.4

8.6

ns

disable time

enable time

DIR to A

DIR to B

DIR to A

DIR to B

4.9

3.8

3.7

2.8

9.2

9.0

8.8

8.7

17.3

17.6

16.6

16.1

16.5

15.9

17.1

14.8

17.8 ns

15.2 ns

[1] t_pdis the same as t_PLHand t_PHL

[2] t_disis the same as t_PLZand t_PHZ

[3] t_enis the same as t_PZLand t_PZH

t_enis a calculated value using the formula shown in Section 12.4

Table 11. Typical power dissipation capacitance at V_CC(A)= V_CC(B)and T_amb= 25 °C

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

V_CC(A)and V_CC(B)

Unit

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

C_PD

power dissipation

capacitance

[1][2]

A port: (direction A to B);

B port: (direction B to A)

1

9

2

pF

A port: (direction B to A);

B port: (direction A to B)

11

12

14

17

[1] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PDx V_CC²x f_ix N + ∑(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_Lx V_CC²x f_o) = sum of the outputs.

[2] f_i= 10 MHz; V_I= GND to V_CC; t_r= t_f= 1 ns; C_L= 0 pF; R_L= ∞ Ω.

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Product data sheet

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74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

Table 12. Dynamic characteristics for temperature range -40 °C to +85 °C

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7.

Symbol Parameter Conditions

V_CC(B)

Unit

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

± 0.1 V

± 0.15 V

± 0.2 V

± 0.3 V

Min Max Min Max Min Max Min Max Min Max

t_pd

t_dis

t_en

propagation A to B

delay

[1]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

1.0 9.0 0.7 6.8 0.6 6.1 0.5 5.7 0.5 6.1 ns

1.0 8.0 0.7 5.4 0.6 4.6 0.5 3.7 0.5 3.5 ns

V_CC(A)= 1.65 V to 1.95 V 1.0 7.7 0.6 5.1 0.5 4.3 0.5 3.4 0.5 3.1 ns

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

1.0 7.2 0.5 4.7 0.5 3.9 0.5 3.0 0.5 2.6 ns

1.0 7.1 0.5 4.5 0.5 3.7 0.5 2.8 0.5 2.4 ns

B to A

[1]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

1.0 9.0 0.8 8.0 0.7 7.7 0.6 7.2 0.5 7.1 ns

1.0 6.8 0.8 5.4 0.7 5.1 0.6 4.7 0.5 4.5 ns

V_CC(A)= 1.65 V to 1.95 V 1.0 6.1 0.7 4.6 0.5 4.4 0.5 3.9 0.5 3.7 ns

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

1.0 5.7 0.6 3.8 0.5 3.4 0.5 3.0 0.5 2.8 ns

1.0 6.1 0.6 3.6 0.5 3.1 0.5 2.6 0.5 2.4 ns

disable time DIR to A

[2]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 ns

1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 ns

V_CC(A)= 1.65 V to 1.95 V 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 ns

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 ns

1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns

DIR to B

[2]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

2.2 8.4 1.8 6.7 2.0 6.9 1.7 6.2 2.4 7.2 ns

2.0 7.6 1.8 5.9 1.6 6.0 1.2 4.8 1.7 5.5 ns

V_CC(A)= 1.65 V to 1.95 V 1.8 7.7 1.8 5.7 1.4 5.8 1.0 4.5 1.5 5.2 ns

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

1.7 7.3 2.0 5.2 1.5 5.1 0.6 4.2 1.1 4.8 ns

1.7 7.2 0.7 5.5 0.6 5.5 0.7 4.1 1.7 4.7 ns

enable time DIR to A

[3][4]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

V_CC(A)= 1.65 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

-

17.4

14.4

13.8

13.0

13.3

-

14.7

11.3

10.3

9.0

-

14.6

11.1

10.2

8.5

-

13.4

9.5

8.4

7.2

6.7

-

14.3 ns

10.0 ns

8.9 ns

7.6 ns

7.1 ns

9.1

8.6

DIR to B

[3][4]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

V_CC(A)= 1.65 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

-

17.8

14.3

13.2

11.4

11.8

-

15.6

11.7

10.6

8.9

-

14.9

10.9

9.8

-

14.5

10.0

8.9

-

14.9 ns

9.8 ns

8.6 ns

6.8 ns

7.1 ns

8.1

7.2

9.2

8.4

7.5

[1] t_pdis the same as t_PLHand t_PHL

[2] t_disis the same as t_PLZand t_PHZ

[3] t_enis the same as t_PZLand t_PZH

[4] t_enis a calculated value using the formula shown in Section 12.4

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

9 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7.

Symbol Parameter Conditions

V_CC(B)

Unit

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

± 0.1 V

± 0.15 V

± 0.2 V

± 0.3 V

Min Max Min Max Min Max Min Max Min Max

t_pd

t_dis

t_en

propagation A to B

delay

[1]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 ns

1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns

V_CC(A)= 1.65 V to 1.95 V 1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns

1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns

B to A

[1]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns

1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns

V_CC(A)= 1.65 V to 1.95 V 1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns

1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns

disable time DIR to A

[2]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns

1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns

V_CC(A)= 1.65 V to 1.95 V 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns

1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns

DIR to B

[2]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns

2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns

V_CC(A)= 1.65 V to 1.95 V 1.8 8.5 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns

1.7 7.9 0.7 6.1 0.6 6.1 0.7 4.6 1.7 5.2 ns

enable time DIR to A

[3][4]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

V_CC(A)= 1.65 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

-

19.1

15.8

15.3

14.3

14.7

-

16.2

12.5

11.4

10.0

10.1

-

16.1

12.3

11.3

9.5

-

14.9

10.5

9.3

-

15.9 ns

11.1 ns

9.9 ns

8.4 ns

7.9 ns

8.0

9.6

7.5

DIR to B

[3][4]

V_CC(A)= 1.1 V to 1.3 V

V_CC(A)= 1.4 V to 1.6 V

V_CC(A)= 1.65 V to 1.95 V

V_CC(A)= 2.3 V to 2.7 V

V_CC(A)= 3.0 V to 3.6 V

-

19.6

15.8

14.6

12.7

13.1

-

17.2

13.0

11.8

9.9

-

16.5

12.1

10.9

9.0

-

16.0

11.1

9.9

-

16.5 ns

10.9 ns

9.6 ns

7.6 ns

7.9 ns

8.0

10.2

9.3

8.3

[1] t_pdis the same as t_PLHand t_PHL

[2] t_disis the same as t_PLZand t_PHZ

[3] t_enis the same as t_PZLand t_PZH

[4] t_enis a calculated value using the formula shown in Section 12.4

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

10 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

11.1. Waveforms and test circuit

V

I

V

nA, nB input

GND

M

t

PLH

PHL

V

OH

nB, nA output

V

M

001aak114

V

OL

Measurement points are given in Table 14.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 6. The data input (nA, nB) to output (nB, nA) propagation delay times

V

I

DIR input

V

M

t

GND

t

PLZ

PZL

V

CCO

output

V

LOW-to-OFF

OFF-to-LOW

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

output

HIGH-to-OFF

V

M

OFF-to-HIGH

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aae968

Measurement points are given in Table 14.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 7. Enable and disable times

Table 14. Measurement points

Supply voltage

Input [1]

V_M

Output [2]

V_M

V_CC(A), V_CC(B)

1.1 V to 1.6 V

1.65 V to 2.7 V

3.0 V to 3.6 V

V_X

V_Y

0.5V_CCI

0.5V_CCO

V_OL+ 0.1 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH- 0.1 V

V_OH- 0.15 V

V_OH- 0.3 V

[1] V_CCIis the supply voltage associated with the data input port.

[2] V_CCOis the supply voltage associated with the output port.

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

11 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 15.

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance.

V_EXT= External voltage for measuring switching times.

Fig. 8. Test circuit for measuring switching times

Table 15. Test data

Supply voltage

V_CC(A), V_CC(B)

1.1 V to 1.6 V

1.65 V to 2.7 V

3.0 V to 3.6 V

Input

V_I[1]

V_CCI

Load

C_L

V_EXT

Δt/ΔV [2]

≤ 1.0 ns/V

R_L

t_PLH, t_PHL

t_PZH, t_PHZ

GND

t_PZL, t_PLZ[3]

2V_CCO

15 pF

2 kΩ

open

GND

2V_CCO

GND

2V_CCO

[1] V_CCIis the supply voltage associated with the data input port.

[2] dV/dt ≥ 1.0 V/ns

[3] V_CCOis the supply voltage associated with the output port.

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

12 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

12. Application information

12.1. Unidirectional logic level-shifting application

The circuit given in Fig. 9 is an example of the 74AVC2T45 being used in an unidirectional logic

level-shifting application.

V

CC2

CC1

74AVC2T45

V

CC(B)

V

CC(A)

1A

CC1

CC2

1

2

3

4

8

7

6

5

1B

2A

2B

GND

DIR

system-1

system-2

001aag581

Fig. 9. Unidirectional logic level-shifting application

Table 16. Unidirectional logic level-shifting application

1

Name

V_CC(A)

1A

Function

V_CC1

OUT1

OUT2

GND

DIR

Description

supply voltage of system-1 (0.8 V to 3.6 V)

output level depends on V_CC1voltage

device GND

2

3

2A

4

GND

DIR

5

the GND (LOW level) determines B port to A port direction

input threshold value depends on V_CC2voltage

supply voltage of system-2 (0.8 V to 3.6 V)

6

2B

IN2

7

1B

IN1

8

V_CC(B)

V_CC2

©

74AVC2T45

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Product data sheet

Rev. 10 — 4 November 2021

13 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

12.2. Bidirectional logic level-shifting application

Fig. 10 shows the 74AVC2T45 being used in a bidirectional logic level-shifting application. Since

the device does not have an output enable (OE) pin, the system designer should take precautions

to avoid bus contention between system-1 and system-2 when changing directions.

V

CC2

CC1

CC2

74AVC2T45

PULL-UP/DOWN

V

PULL-UP/DOWN

CC(A)

1A

CC(B)

I/O-1

I/O-2

1

2

3

4

8

7

6

5

1B

2A

2B

GND

DIR

DIR CTRL

system-1

system-2

001aag582

System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down.

Fig. 10. Bidirectional logic level-shifting application

Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then

from system-2 to system-1.

Table 17. Bidirectional logic level-shifting application

H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.

State

DIR CTRL I/O-1

I/O-2

input

Z

Description

1

2

H

output

Z

system-1 data to system-2

system-2 is getting ready to send data to

system-1. I/O-1 and I/O-2 are disabled. The

bus-line state depends on the pull-up or

pull-down.

3

4

L

Z

DIR bit is set LOW. I/O-1 and I/O-2 still are

disabled. The bus-line state depends on the

pull-up or pull-down.

input

output

system-2 data to system-1

System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down.

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

14 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

12.3. Power-up considerations

The device is designed such that no special power-up sequence is required other than GND being

applied first.

Table 18. Typical total supply current (I_CC(A)+ I_CC(B)

)

V_CC(A)

V_CC(B)

0 V

0

Unit

0.8 V

0.1

0.7

2.3

1.2 V

0.1

0.3

1.4

1.5 V

0.1

0.9

1.8 V

0.1

0.5

2.5 V

0.1

0.7

0.3

0.1

3.3 V

0.1

2.3

1.4

0.9

0.5

0.1

0 V

μA

0.8 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.1

12.4. Enable times

The enable times for the 74AVC2T45 are calculated from the following formulas:

•

t_en(DIR to nA) = t_dis(DIR to nB) + t_pd(nB to nA)

t_en(DIR to nB) = t_dis(DIR to nA) + t_pd(nA to nB)

In a bidirectional application, these enable times provide the maximum delay from the time

the DIR bit is switched until an output is expected. For example, if the 74AVC2T45 initially is

transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled

before presenting it with an input. After the B port has been disabled, an input signal applied to it

appears on the corresponding A port after the specified propagation delay.

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

15 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

13. Package outline

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

D

E

A

X

c

H

v

M

y

A

E

Z

5

8

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

4

e

w

M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

A

b

c

D

E

e

H

E

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

max.

0.15

0.00

0.95

0.75

0.38

0.22

0.18

0.08

3.1

2.9

3.1

2.9

4.1

3.9

0.47

0.33

0.70

0.35

8°

0°

mm

1.1

0.65

0.5

0.2

0.13

0.1

0.25

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-01-16

SOT505-2

- - -

Fig. 11. Package outline SOT505-2 (TSSOP8)

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

16 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

D

E

A

X

c

y

H

E

v

A

Z

5

8

Q

A

2

A

(A )

3

1

pin 1 index

θ

L

p

detail X

1

4

L

e

w

b

p

0

5 mm

scale

Dimensions (mm are the original dimensions)

A

(1)

(2)

(1)

Unit

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

max

mm nom

min

0.15 0.85

0.00 0.60

0.27 0.23 2.1 2.4

0.17 0.08 1.9 2.2

3.2

3.0

0.40 0.21

0.15 0.19

0.4

8°

0°

1

0.12

0.5

0.4

0.2 0.08 0.1

0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

sot765-1_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

07-06-02

16-05-31

SOT765-1

MO-187

Fig. 12. Package outline SOT765-1 (VSSOP8)

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

17 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

SOT833-1

b

1

2

3

4

4×

(2)

L

1

e

8

7

6

5

e

1

8×

(2)

A

1

D

E

terminal 1

index area

0

1

2 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

1

UNIT

b

D

E

e

1

L

1

max max

0.25

0.17

2.0

1.9

1.05

0.95

0.35 0.40

0.27 0.32

mm

0.5 0.04

0.6

0.5

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

07-11-14

07-12-07

SOT833-1

- - -

MO-252

Fig. 13. Package outline SOT833-1 (XSON8)

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

18 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1 x 0.5 mm

SOT1089

E

terminal 1

index area

D

A

1

detail X

(2)

(4×)

e

L

(2)

(8×)

b

4

5

e

1

8

terminal 1

index area

L

X

1

0

0.5

1 mm

scale

Dimensions

Unit

(1)

A

b

D

E

e

1

L

1

max 0.5 0.04 0.20 1.40 1.05

0.35 0.40

0.15 1.35 1.00 0.55 0.35 0.30 0.35

0.12 1.30 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1089_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

MO-252

JEITA

10-04-09

10-04-12

SOT1089

Fig. 14. Package outline SOT1089 (XSON8)

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

19 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.2 x 1.0 x 0.35 mm

SOT1116

b

4

(2)

1

2

3

(4×)

L

1

e

8

7

6

5

e

1

(2)

(8×)

A

1

A

D

E

terminal 1

index area

0

0.5

scale

1 mm

Dimensions

Unit

(1)

A

b

D

E

e

1

L

1

max 0.35 0.04 0.20 1.25 1.05

0.35 0.40

0.15 1.20 1.00 0.55 0.3 0.30 0.35

0.12 1.15 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1116_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

10-04-02

10-04-07

SOT1116

Fig. 15. Package outline SOT1116 (XSON8)

©

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Product data sheet

Rev. 10 — 4 November 2021

20 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1.0 x 0.35 mm

SOT1203

b

4

(2)

(4×)

1

2

3

L

1

e

8

7

6

5

e

1

(2)

(8×)

A

1

A

D

E

terminal 1

index area

0

L

0.5

scale

1 mm

Dimensions

Unit

(1)

A

b

D

E

e

1

L

1

max 0.35 0.04 0.20 1.40 1.05

0.35 0.40

0.15 1.35 1.00 0.55 0.35 0.30 0.35

0.12 1.30 0.95 0.27 0.32

mm nom

min

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

sot1203_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

10-04-02

10-04-06

SOT1203

Fig. 16. Package outline SOT1203 (XSON8)

©

74AVC2T45

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Product data sheet

Rev. 10 — 4 November 2021

21 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

X2SON8: plastic thermal enhanced extremely thin small outline package; no leads;

8 terminals; body 1.35 x 0.8 x 0.32 mm

SOT1233-2

C

Seating

Plane

X

y

C

A

B

D

E

A

3

u

C

A

detail X

1

2x

pin 1

index area

u

C

2x

e

b

(6x)

y

C

1

v

w

C

A

B

1

2

3

pin 1

index area

8

4

D

h

L

(6x)

7

6

5

b

1

(6x)

e

1

0

1 mm

scale

Dimensions (mm are the original dimensions)

Unit

A

b

D

h

E

e

L

u

v

w

y

1

3

1

max 0.35 0.04

0.25

0.20

0.15

0.27

1.35 0.22 0.80 0.50 0.54 0.22 0.05 0.10 0.05 0.05 0.05

0.17 0.17

0.27

0.10

(Typ.)

0.11

(ref)

nom

min

mm

0.32 0.02

0.30 0.00

sot1233-2_po

Issue date

19-11-12

References

Outline

version

European

projection

IEC

JEDEC

- - -

JEITA

SOT1233-2

Fig. 17. Package outline SOT1233-2 (X2SON8)

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

22 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

14. Abbreviations

Table 19. Abbreviations

Acronym

Description

CDM

DUT

ESD

HBM

MM

Charged Device Model

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

15. Revision history

Table 20. Revision history

Document ID

74AVC2T45 v.10

Modifications:

Release date

20211104

Data sheet status

Change notice Supersedes

- 74AVC2T45 v.9

Product data sheet

•

Type number 74AVC2T45GX (SOT1233-2/X2SON8) added.

Section 8: Derating values for P_tottotal power dissipation updated.

74AVC2T45 v.9

Modifications:

20180925

Type number 74AVC2T45GD (SOT996-2) removed.

20171013 Product data sheet

Product data sheet

-

74AVC2T45 v.8

•

74AVC2T45 v.8

Modifications:

-

74AVC2T45 v.7

•

The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

Legal texts have been adapted to the new company name where appropriate.

74AVC2T45 v.7

Modifications:

20130208

Product data sheet

-

74AVC2T45 v.6

•

For type number 74AVC2T45GD XSON8U has changed to XSON8.

74AVC2T45 v.6

74AVC2T45 v.5

74AVC2T45 v.4

74AVC2T45 v.3

74AVC2T45 v.2

74AVC2T45 v.1

20111208

20101130

20090505

20090129

20080620

20070703

Product data sheet

-

74AVC2T45 v.5

74AVC2T45 v.4

74AVC2T45 v.3

74AVC2T45 v.2

74AVC2T45 v.1

-

©

74AVC2T45

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 10 — 4 November 2021

23 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

16. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

©

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Product data sheet

Rev. 10 — 4 November 2021

24 / 25

Nexperia

74AVC2T45

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................2

4. Marking..........................................................................2

5. Functional diagram.......................................................3

6. Pinning information......................................................3

6.1. Pinning.........................................................................3

6.2. Pin description.............................................................4

7. Functional description................................................. 4

8. Limiting values............................................................. 5

9. Recommended operating conditions..........................5

10. Static characteristics..................................................6

11. Dynamic characteristics.............................................8

11.1. Waveforms and test circuit.......................................11

12. Application information........................................... 13

12.1. Unidirectional logic level-shifting application............13

12.2. Bidirectional logic level-shifting application..............14

12.3. Power-up considerations......................................... 15

12.4. Enable times............................................................15

13. Package outline........................................................ 16

14. Abbreviations............................................................23

15. Revision history........................................................23

16. Legal information......................................................24

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 4 November 2021

©

74AVC2T45

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Product data sheet

Rev. 10 — 4 November 2021

25 / 25

是否Rohs认证：	符合	生命周期：	Active
包装说明：	VSON,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.57
系列：	AVC	JESD-30 代码：	R-PDSO-N8
JESD-609代码：	e3	长度：	1.95 mm
逻辑集成电路类型：	BUS TRANSCEIVER	湿度敏感等级：	1
位数：	2	功能数量：	1
端口数量：	2	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	VSON
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	9.9 ns
座面最大高度：	0.5 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	0.8 V	标称供电电压 (Vsup)：	1.2 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	1 mm	Base Number Matches：	1

型号	制造商	描述	价格	文档
74AVC2T45GT,115	NXP	74AVC2T45 - Dual-bit, dual-supply voltage level translator/transceiver; 3-state SON 8-Pin	获取价格
74AVC2T45GT-Q100	NEXPERIA	Dual-bit, dual-supply voltage level translator/transceiver 3-state	获取价格
74AVC2T45GX	NEXPERIA	Dual-bit, dual-supply voltage level translator/transceiver; 3-stateProduction	获取价格
74AVC2T45_09	NXP	Dual-bit, dual-supply voltage level translator/transceiver; 3-state	获取价格
74AVC32T245	NEXPERIA	32-bit dual supply translating transceiver with configurable voltage translation 3-state	获取价格
74AVC32T245EC	NEXPERIA	32-bit dual supply translating transceiver with configurable voltage translation 3-state	获取价格
74AVC4T245	NXP	4-bit dual supply translating transceiver with configurable voltage translation; 3-state	获取价格
74AVC4T245	SGMICRO	4-Bit Dual-Supply Translating Transceiver with Configurable Voltage Translation and 3-State Outputs	获取价格
74AVC4T245-Q100	NEXPERIA	4-bit dual supply translating transceiver with configurable voltage translation 3-state	获取价格
74AVC4T245BQ	NXP	4-bit dual supply translating transceiver with configurable voltage translation; 3-state	获取价格

74AVC2T45GT

74AVC2T45GT 概述

74AVC2T45GT 规格参数

74AVC2T45GT 数据手册

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