74CBTLV3126-Q100 [NEXPERIA]

4-bit bus switch;
74CBTLV3126-Q100
型号: 74CBTLV3126-Q100
厂家: Nexperia    Nexperia
描述:

4-bit bus switch

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74CBTLV3126-Q100  
4-bit bus switch  
Rev. 3 — 9 October 2018  
Product data sheet  
1. General description  
The 74CBTLV3126-Q100 provides a 4-bit high-speed bus switch with separate output enable  
inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be made with  
minimal propagation delay. The switch is disabled (high-impedance OFF-state) when the output  
enable (nOE) input is LOW.  
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to  
the GND through a pull-down resistor. The current-sinking capability of the driver determines the  
minimum value of the resistor.  
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times  
across the entire VCC range from 2.3 V to 3.6 V.  
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing the damaging backflow current through the device when it is  
powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Supply voltage range from 2.3 V to 3.6 V  
Standard ’126’-type pinout  
High noise immunity  
Complies with JEDEC standard:  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
5 Ω switch connection between two ports  
Rail to rail switching on data I/O ports  
CMOS low power consumption  
Latch-up performance exceeds 250 mA per JESD78B Class I level A  
IOFF circuitry provides partial Power-down mode operation  
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74CBTLV3126PW-Q100  
74CBTLV3126BQ-Q100  
-40 °C to +125 °C  
TSSOP14  
plastic thin shrink small outline package;  
14 leads; body width 4.4 mm  
SOT402-1  
-40 °C to +125 °C  
DHVQFN14 plastic dual in-line compatible  
SOT762-1  
thermal enhanced very thin quad  
flat package; no leads; 14 terminals;  
body 2.5 × 3 × 0.85 mm  
4. Functional diagram  
1OE  
1A  
1B  
2B  
3B  
4B  
2OE  
2A  
3OE  
3A  
4OE  
4A  
nA  
nB  
nOE  
001aaj023  
001aal245  
Fig. 1. Logic symbol  
Fig. 2. Logic diagram (one switch)  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
2 / 16  
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
5. Pinning information  
5.1. Pinning  
74CBTLV3126-Q100  
terminal 1  
index area  
2
3
4
5
6
13  
12  
11  
10  
9
1A  
4OE  
4A  
1B  
2OE  
2A  
4B  
(1)  
3OE  
3A  
GND  
2B  
74CBTLV3126-Q100  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
V
CC  
aaa-006848  
4OE  
4A  
Transparent top view  
1B  
(1) This is not a supply pin. The substrate is  
attached to this pad using conductive die attach  
material. There is no electrical or mechanical  
requirement to solder this pad. However, if it is  
soldered, the solder land should remain floating or  
be connected to GND.  
2OE  
2A  
4B  
3OE  
3A  
2B  
GND  
8
3B  
aaa-006849  
Fig. 3. Pin configuration SOT402-1 (TSSOP14)  
Fig. 4. Pin configuration SOT762-1 (DHVQFN14)  
5.2. Pin description  
Table 2. Pin description  
Symbol  
Pin  
Description  
1OE, 2OE, 3OE, 4OE  
1A, 2A, 3A, 4A  
1B, 2B, 3B, 4B  
GND  
1, 4, 10, 13  
2, 5, 9, 12  
3, 6, 8, 11  
7
output enable input  
A input/output  
B output/input  
ground (0 V)  
VCC  
14  
supply voltage  
6. Functional description  
Table 3. Function table  
H = HIGH voltage level; L = LOW voltage level.  
Output enable input nOE  
Function switch  
OFF-state  
L
H
ON-state  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
3 / 16  
 
 
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
7. Limiting values  
Table 4. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
-0.5  
-0.5  
-0.5  
-50  
-50  
-
Max  
+4.6  
+4.6  
VCC + 0.5  
-
Unit  
V
VCC  
VI  
supply voltage  
input voltage  
control inputs  
[1]  
[2]  
V
VSW  
IIK  
switch voltage  
enable and disable mode  
VI < -0.5 V  
V
input clamping current  
switch clamping current  
switch current  
mA  
mA  
mA  
mA  
mA  
°C  
ISK  
VI < -0.5 V  
-
ISW  
ICC  
IGND  
Tstg  
Ptot  
VSW = 0 V to VCC  
±128  
+100  
-
supply current  
-
ground current  
-100  
-65  
-
storage temperature  
total power dissipation  
+150  
500  
Tamb = -40 °C to +125 °C  
[3]  
mW  
[1] The minimum input voltage rating may be exceeded if the input clamping current ratings are observed.  
[2] The switch voltage ratings may be exceeded if switch clamping current ratings are observed  
[3] For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.  
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.  
8. Recommended operating conditions  
Table 5. Recommended operating conditions  
Symbol Parameter  
Conditions  
Min  
2.3  
0
Max  
3.6  
Unit  
V
VCC  
VI  
supply voltage  
input voltage  
control inputs  
3.6  
V
VSW  
Tamb  
Δt/ΔV  
switch voltage  
enable and disable mode  
0
VCC  
+125  
200  
V
ambient temperature  
input transition rise and fall rate  
-40  
0
°C  
ns/V  
pin nOE; VCC = 2.3 V to 3.6 V  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
4 / 16  
 
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
9. Static characteristics  
Table 6. Static characteristics  
At recommended operating conditions voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Tamb = -40 °C to +85 °C  
Tamb  
=
Unit  
-40 °C to +125 °C  
Min  
1.7  
2.0  
-
Typ [1]  
Max  
-
Min  
1.7  
2.0  
-
Max  
-
VIH  
VIL  
II  
HIGH-level input VCC = 2.3 V to 2.7 V  
-
-
-
-
-
V
voltage  
VCC = 3.0 V to 3.6 V  
-
-
V
LOW-level input VCC = 2.3 V to 2.7 V  
0.7  
0.9  
±1.0  
0.7  
0.9  
±20  
V
voltage  
VCC = 3.0 V to 3.6 V  
-
-
V
input leakage  
current  
pin nOE; VI = GND to VCC  
VCC = 3.6 V  
;
-
-
μA  
IS(OFF) OFF-state  
leakage current  
VCC = 3.6 V; see Fig. 5  
-
-
-
-
-
-
-
-
±1  
±1  
-
-
-
-
±20  
±20  
±50  
50  
μA  
μA  
μA  
μA  
IS(ON)  
IOFF  
ICC  
ON-state leakage VCC = 3.6 V; see Fig. 6  
current  
power-off leakage VI or VO = 0 V to 3.6 V;  
current  
±10  
10  
VCC = 0 V  
supply current  
VI = GND or VCC; IO = 0 A;  
VSW = GND or VCC  
;
VCC = 3.6 V  
ΔICC  
additional supply pin nOE; VI = VCC - 0.6 V;  
[2]  
-
-
300  
-
2000  
μA  
current  
VSW = GND or VCC  
;
VCC = 3.6 V  
CI  
input capacitance pin nOE; VCC = 3.3 V;  
VI = 0 V to 3.3 V  
-
-
-
0.9  
5.2  
-
-
-
-
-
-
-
-
-
pF  
pF  
pF  
CS(OFF) OFF-state  
capacitance  
VCC = 3.3 V; VI = 0 V to 3.3 V  
CS(ON) ON-state  
capacitance  
VCC = 3.3 V; VI = 0 V to 3.3 V  
14.3  
[1] All typical values are measured at Tamb = 25 °C.  
[2] One input at 3 V, other inputs at VCC or GND.  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
5 / 16  
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
9.1. Test circuits  
V
V
CC  
CC  
nOE  
nB  
nOE  
nA  
V
V
IH  
IL  
I
S
nA  
nB  
A
A
A
I
S
I
S
V
I
GND  
V
O
V
I
GND  
V
O
001aal249  
001aal250  
VI = VCC or GND and VO = GND or VCC  
.
VI = VCC or GND and VO = open circuit.  
Fig. 5. Test circuit for measuring OFF-state leakage  
current (one switch)  
Fig. 6. Test circuit for measuring ON-state leakage  
current (one switch)  
9.2. ON resistance  
Table 7. Resistance RON  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7.  
Symbol Parameter Conditions Tamb = -40 °C to +85 °C Tamb  
-40 °C to +125 °C  
=
Unit  
Min  
Typ [1]  
Max  
Min  
Max  
RON  
ON resistance VCC = 2.3 V to 2.7 V;  
see Fig. 8 to Fig. 10  
[2]  
ISW = 64 mA; VI = 0 V  
ISW = 24 mA; VI = 0 V  
ISW = 15 mA; VI = 1.7 V  
-
-
-
4.2  
4.2  
8.4  
8.0  
8.0  
-
-
-
15.0  
15.0  
60.0  
Ω
Ω
Ω
40.0  
VCC = 3.0 V to 3.6 V;  
see Fig. 11 to Fig. 13  
ISW = 64 mA; VI = 0 V  
ISW = 24 mA; VI = 0 V  
ISW = 15 mA; VI = 2.4 V  
-
-
-
4.0  
4.0  
6.2  
7.0  
7.0  
-
-
-
11.0  
11.0  
25.5  
Ω
Ω
Ω
15.0  
[1] Typical values are measured at Tamb = 25 °C and nominal VCC  
.
[2] Measured by the voltage drop between the A and B terminals at the indicated current through the switch.  
ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
6 / 16  
 
 
 
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
9.3. ON resistance test circuit and graphs  
001aai109  
11  
R
ON  
(Ω)  
9
7
5
3
V
SW  
(1)  
(2)  
V
V
CC  
(3)  
(4)  
nOE  
nA  
V
IH  
nB  
0
0.5  
1.0  
1.5  
2.0  
2.5  
V (V)  
I
V
GND  
I
SW  
I
(1) Tamb = 125 °C.  
(2) Tamb = 85 °C.  
(3) Tamb = 25 °C.  
(4) Tamb = -40 °C.  
001aal251  
RON = VSW / ISW  
.
Fig. 7. Test circuit for measuring ON resistance  
(one switch)  
Fig. 8. ON resistance as a function of input voltage;  
VCC = 2.5 V; ISW = 15 mA  
001aai110  
001aai111  
11  
11  
R
ON  
(Ω)  
R
ON  
(Ω)  
9
7
5
3
9
7
5
3
(1)  
(2)  
(1)  
(2)  
(3)  
(4)  
(3)  
(4)  
0
0.5  
1.0  
1.5  
2.0  
2.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
V (V)  
I
V (V)  
I
(1) Tamb = 125 °C.  
(2) Tamb = 85 °C.  
(3) Tamb = 25 °C.  
(4) Tamb = -40 °C.  
(1) Tamb = 125 °C.  
(2) Tamb = 85 °C.  
(3) Tamb = 25 °C.  
(4) Tamb = -40 °C.  
Fig. 9. ON resistance as a function of input voltage;  
VCC = 2.5 V; ISW = 24 mA  
Fig. 10. ON resistance as a function of input voltage;  
VCC = 2.5 V; ISW = 64 mA  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
7 / 16  
 
 
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
001aai105  
001aai106  
8
8
6
4
2
R
ON  
(Ω)  
R
ON  
(Ω)  
6
4
2
(1)  
(2)  
(1)  
(2)  
(3)  
(4)  
(3)  
(4)  
0
1
2
3
4
0
1
2
3
4
V (V)  
V (V)  
I
I
(1) Tamb = 125 °C.  
(2) Tamb = 85 °C.  
(3) Tamb = 25 °C.  
(4) Tamb = -40 °C.  
(1) Tamb = 125 °C.  
(2) Tamb = 85 °C.  
(3) Tamb = 25 °C.  
(4) Tamb = -40 °C.  
Fig. 11. ON resistance as a function of input voltage;  
VCC = 3.3 V; ISW = 15 mA  
Fig. 12. ON resistance as a function of input voltage;  
VCC = 3.3 V; ISW = 24 mA  
001aai107  
7.5  
R
ON  
(Ω)  
6.5  
5.5  
4.5  
3.5  
2.5  
(1)  
(2)  
(3)  
(4)  
0
1
2
3
4
V (V)  
I
(1) Tamb = 125 °C.  
(2) Tamb = 85 °C.  
(3) Tamb = 25 °C.  
(4) Tamb = -40 °C.  
Fig. 13. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 64 mA  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
8 / 16  
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
10. Dynamic characteristics  
Table 8. Dynamic characteristics  
GND = 0 V; for test circuit see Fig. 17  
Symbol Parameter  
Conditions  
Tamb = -40 °C to +85 °C  
Tamb  
=
Unit  
-40 °C to +125 °C  
Min  
Typ [1]  
Max  
Min  
Max  
tpd  
ten  
tdis  
propagation  
delay  
nA to nB or nB to nA; see Fig. 15 [2][3]  
VCC = 2.3 V to 2.7 V  
-
-
-
-
0.13  
0.20  
-
-
0.20  
0.31  
ns  
ns  
VCC = 3.0 V to 3.6 V  
enable time  
nOE to nA or nB; see Fig. 16  
VCC = 2.3 V to 2.7 V  
[4]  
[5]  
1.0  
1.0  
2.5  
2.2  
4.5  
4.2  
1.0  
1.0  
6.0  
6.0  
ns  
ns  
VCC = 3.0 V to 3.6 V  
disable time nOE to nA or nB; see Fig. 16  
VCC = 2.3 V to 2.7 V  
1.0  
1.0  
2.6  
3.4  
4.7  
4.8  
1.0  
1.0  
6.5  
6.5  
ns  
ns  
VCC = 3.0 V to 3.6 V  
[1] All typical values are measured at Tamb = 25 °C and at nominal VCC  
.
[2] The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the load capacitance,  
when driven by an ideal voltage source (zero output impedance).  
[3] tpd is the same as tPLH and tPHL  
[4] ten is the same as tPZH and tPZL  
[5] tdis is the same as tPHZ and tPLZ  
.
.
.
10.1. Additional dynamic characteristics  
Table 9. Additional dynamic characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V);  
Symbol Parameter  
Conditions  
Tamb = 25 °C  
Typ  
Unit  
Min  
Max  
f(-3dB)  
-3 dB frequency response  
VI = GND or VCC; tr = tf ≤ 2.5 ns;  
-
406  
-
MHz  
VCC = 3.3 V; RL = 50 Ω; see Fig. 14  
V
0.5 V  
CC  
CC  
nOE  
nB  
V
IH  
R
L
nA  
GND  
f
i
dB  
aaa-025605  
nOE connected to VCC; fi is biased at 0.5VCC. Adjust fi voltage to obtain 0 dBm level at output.  
Increase fi frequency until dB meter reads -3 dB.  
Fig. 14. Test circuit for measuring the frequency response when channel is in ON-state  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
9 / 16  
 
 
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
10.2. Waveforms and test circuit  
V
I
V
V
M
input  
0 V  
M
t
t
PLH  
PHL  
V
OH  
V
V
M
output  
M
V
OL  
001aai367  
Measurement points are given in Table 10.  
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.  
Fig. 15. The data input (nA or nB) to output (nB or nA) propagation delays  
V
I
nOE input  
V
M
GND  
t
t
PZL  
PLZ  
V
CC  
output  
LOW-to-OFF  
OFF-to-LOW  
V
M
V
X
V
OL  
t
t
PZH  
PHZ  
V
OH  
V
Y
output  
HIGH-to-OFF  
OFF-to-HIGH  
V
M
GND  
switch  
enabled  
switch  
disabled  
switch  
enabled  
001aal252  
Measurement points are given in Table 10.  
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.  
Fig. 16. Enable and disable times  
Table 10. Measurement points  
Supply voltage  
VCC  
Input  
Output  
VM  
VM  
VI  
VX  
VY  
2.3 V to 2.7 V  
3.0 V to 3.6 V  
0.5VCC  
0.5VCC  
VCC  
VCC  
0.5VCC  
0.5VCC  
VOL + 0.15 V  
VOL + 0.3 V  
VOH - 0.15 V  
VOH - 0.3 V  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
10 / 16  
 
 
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
0 V  
t
W
V
EXT  
R
V
CC  
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
001aae331  
Test data is given in Table 11.  
Definitions for test circuit:  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.  
VEXT = External voltage for measuring switching times.  
Fig. 17. Test circuit for measuring switching times  
Table 11. Test data  
Supply voltage Load  
VEXT  
VCC  
CL  
RL  
tr = tf  
tPLH, tPHL  
open  
tPZH, tPHZ  
GND  
tPZL, tPLZ  
2VCC  
2.3 V to 2.7 V  
3.0 V to 3.6 V  
30 pF  
50 pF  
500 Ω  
500 Ω  
≤ 2.0 ns  
≤ 2.0 ns  
open  
GND  
2VCC  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
11 / 16  
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
11. Package outline  
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm  
SOT402-1  
D
E
A
X
c
y
H
v
M
A
E
Z
8
14  
Q
(A )  
3
A
2
A
A
1
pin 1 index  
θ
L
p
L
1
7
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
5.1  
4.9  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.72  
0.38  
mm  
1.1  
0.65  
1
0.2  
0.13  
0.1  
0.25  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT402-1  
MO-153  
Fig. 18. Package outline SOT402-1 (TSSOP14)  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
12 / 16  
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;  
14 terminals; body 2.5 x 3 x 0.85 mm  
SOT762-1  
B
A
E
D
A
A
1
c
detail X  
terminal 1  
index area  
C
terminal 1  
index area  
e
1
v
w
C A  
C
B
y
y
C
1
e
b
2
6
L
1
7
8
E
h
e
14  
k
13  
9
D
h
X
k
0
2
4 mm  
w
scale  
Dimensions (mm are the original dimensions)  
(1) (1)  
(1)  
Unit  
A
A
b
c
D
D
h
E
E
e
e
k
L
v
y
y
1
1
h
1
max  
nom  
min  
1
0.05 0.30  
0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5  
0.00 0.18 2.9 1.35 2.4 0.85  
3.1 1.65 2.6 1.15  
0.5  
0.4 0.1 0.05 0.05 0.1  
0.2 0.3  
mm  
2
Note  
sot762-1_po  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
JEDEC  
JEITA  
15-04-10  
15-05-05  
SOT762-1  
MO-241  
Fig. 19. Package outline SOT762-1 (DHVQFN14)  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
13 / 16  
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
12. Abbreviations  
Table 12. Abbreviations  
Acronym  
Description  
CMOS  
DUT  
ESD  
HBM  
MIL  
Complementary Metal-Oxide Semiconductor  
Device Under Test  
ElectroStatic Discharge  
Human Body Model  
Military  
MM  
Machine Model  
13. Revision history  
Table 13. Revision history  
Document ID  
Release date  
20181009  
Data sheet status  
Change notice Supersedes  
- 74CBTLV3126_Q100 v.2  
74CBTLV3126_Q100 v.3  
Modifications:  
Product data sheet  
The format of this data sheet has been redesigned to comply with the identity guidelines  
of Nexperia.  
Legal texts have been adapted to the new company name where appropriate.  
74CBTLV3126_Q100 v.2  
Modifications:  
20161109  
Product data sheet  
Product data sheet  
-
-
74CBTLV3126_Q100 v.1  
-
Section 10.1 added.  
74CBTLV3126_Q100 v.1  
20130403  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
14 / 16  
 
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
equipment, nor in applications where failure or malfunction of an Nexperia  
product can reasonably be expected to result in personal injury, death or  
severe property or environmental damage. Nexperia and its suppliers accept  
no liability for inclusion and/or use of Nexperia products in such equipment or  
applications and therefore such inclusion and/or use is at the customer's own  
risk.  
14. Legal information  
Data sheet status  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Document status Product  
Definition  
[1][2]  
status [3]  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. Nexperia makes no representation  
or warranty that such applications will be suitable for the specified use  
without further testing or modification.  
Objective [short]  
data sheet  
Development  
This document contains data from  
the objective specification for  
product development.  
Preliminary [short]  
data sheet  
Qualification  
Production  
This document contains data from  
the preliminary specification.  
Customers are responsible for the design and operation of their applications  
and products using Nexperia products, and Nexperia accepts no liability for  
any assistance with applications or customer product design. It is customer’s  
sole responsibility to determine whether the Nexperia product is suitable  
and fit for the customer’s applications and products planned, as well as  
for the planned application and use of customer’s third party customer(s).  
Customers should provide appropriate design and operating safeguards to  
minimize the risks associated with their applications and products.  
Product [short]  
data sheet  
This document contains the product  
specification.  
[1] Please consult the most recently issued document before initiating or  
completing a design.  
[2] The term 'short data sheet' is explained in section "Definitions".  
[3] The product status of device(s) described in this document may have  
changed since this document was published and may differ in case of  
multiple devices. The latest product status information is available on  
the internet at https://www.nexperia.com.  
Nexperia does not accept any liability related to any default, damage, costs  
or problem which is based on any weakness or default in the customer’s  
applications or products, or the application or use by customer’s third party  
customer(s). Customer is responsible for doing all necessary testing for the  
customer’s applications and products using Nexperia products in order to  
avoid a default of the applications and the products or of the application or  
use by customer’s third party customer(s). Nexperia does not accept any  
liability in this respect.  
Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. Nexperia does not give any representations or  
warranties as to the accuracy or completeness of information included herein  
and shall have no liability for the consequences of use of such information.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those  
given in the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is  
intended for quick reference only and should not be relied upon to contain  
detailed and full information. For detailed and full information see the relevant  
full data sheet, which is available on request via the local Nexperia sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of commercial sale — Nexperia products are  
sold subject to the general terms and conditions of commercial sale, as  
published at http://www.nexperia.com/profile/terms, unless otherwise agreed  
in a valid written individual agreement. In case an individual agreement is  
concluded only the terms and conditions of the respective agreement shall  
apply. Nexperia hereby expressly objects to applying the customer’s general  
terms and conditions with regard to the purchase of Nexperia products by  
customer.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
Nexperia and its customer, unless Nexperia and customer have explicitly  
agreed otherwise in writing. In no event however, shall an agreement be  
valid in which the Nexperia product is deemed to offer functions and qualities  
beyond those described in the Product data sheet.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Disclaimers  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
Limited warranty and liability — Information in this document is believed  
to be accurate and reliable. However, Nexperia does not give any  
representations or warranties, expressed or implied, as to the accuracy  
or completeness of such information and shall have no liability for the  
consequences of use of such information. Nexperia takes no responsibility  
for the content in this document if provided by an information source outside  
of Nexperia.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
In no event shall Nexperia be liable for any indirect, incidental, punitive,  
special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal  
or replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Trademarks  
Notice: All referenced brands, product names, service names and  
trademarks are the property of their respective owners.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, Nexperia’s aggregate and cumulative liability towards customer  
for the products described herein shall be limited in accordance with the  
Terms and conditions of commercial sale of Nexperia.  
Right to make changes — Nexperia reserves the right to make changes  
to information published in this document, including without limitation  
specifications and product descriptions, at any time and without notice. This  
document supersedes and replaces all information supplied prior to the  
publication hereof.  
Suitability for use in automotive applications — This Nexperia product  
has been qualified for use in automotive applications. Unless otherwise  
agreed in writing, the product is not designed, authorized or warranted to  
be suitable for use in life support, life-critical or safety-critical systems or  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
15 / 16  
 
Nexperia  
74CBTLV3126-Q100  
4-bit bus switch  
Contents  
1. General description......................................................1  
2. Features and benefits.................................................. 1  
3. Ordering information....................................................2  
4. Functional diagram.......................................................2  
5. Pinning information......................................................3  
5.1. Pinning.........................................................................3  
5.2. Pin description.............................................................3  
6. Functional description................................................. 3  
7. Limiting values............................................................. 4  
8. Recommended operating conditions..........................4  
9. Static characteristics....................................................5  
9.1. Test circuits..................................................................6  
9.2. ON resistance..............................................................6  
9.3. ON resistance test circuit and graphs..........................7  
10. Dynamic characteristics............................................ 9  
10.1. Additional dynamic characteristics.............................9  
10.2. Waveforms and test circuit...................................... 10  
11. Package outline........................................................ 12  
12. Abbreviations............................................................14  
13. Revision history........................................................14  
14. Legal information......................................................15  
© Nexperia B.V. 2018. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 9 October 2018  
©
74CBTLV3126_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2018. All rights reserved  
Product data sheet  
Rev. 3 — 9 October 2018  
16 / 16  

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