74HC00PW-Q100 [NEXPERIA]

Quad 2-input NAND gateProduction;


型号：	74HC00PW-Q100
厂家：	Nexperia
描述：	Quad 2-input NAND gateProduction 光电二极管逻辑集成电路
文件：	总12页 (文件大小：235K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

Rev. 5 — 22 October 2021

Product data sheet

1. General description

The 74HC00-Q100; 74HCT00-Q100 is a quad 2-input NAND gate. Inputs include clamp diodes.

This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 2.0 to 6.0 V

CMOS low power dissipation

High noise immunity

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Input levels:

•

For 74HC00-Q100: CMOS level

For 74HCT00-Q100: TTL level

•

Complies with JEDEC standards:

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)

•

Multiple package options

DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of

solder joints

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC00D-Q100

74HCT00D-Q100

-40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74HC00PW-Q100 -40 °C to +125 °C

74HCT00PW-Q100

TSSOP14

plastic thin shrink small outline package; 14 leads; SOT402-1

body width 4.4 mm

74HC00BQ-Q100

74HCT00BQ-Q100

-40 °C to +125 °C

DHVQFN14 plastic dual in-line compatible thermal

enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 × 3 × 0.85 mm

SOT762-1

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

4. Functional diagram

10 3B

12 4A

13 4B

4Y 11

mna212

mna246

mna211

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74HC00

74HCT00

terminal 1

index area

74HC00

74HCT00

(1)

GND

001aal324

Transparent top view

GND

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

001aal323

Fig. 4. Pin configuration SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

Fig. 5. Pin configuration SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description

Symbol

Description

data input

1A, 2A, 3A, 4A

1B, 2B, 3B, 4B

1Y, 2Y, 3Y, 4Y

GND

1, 4, 9, 12

2, 5, 10, 13

3, 6, 8, 11

data input

data output

ground (0 V)

supply voltage

V_CC

74HC_HCT00_Q100

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Product data sheet

Rev. 5 — 22 October 2021

2 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care.

Input

Output

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

Unit

V_CC

I_IK

supply voltage

-0.5

input clamping current

output clamping current

output current

V_I< -0.5 V or V_I> V_CC+ 0.5 V

V_O< -0.5 V or V_O> V_CC+ 0.5 V

-0.5 V < V_O< V_CC+ 0.5 V

[1]

±20

±25

I_OK

I_O

I_CC

I_GND

T_stg

P_tot

supply current

ground current

-50

-65

storage temperature

total power dissipation

+150 °C

500 mW

[2]

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SOT108-1 (SO14) package: P_totderates linearly with 10.1 mW/K above 100 °C.

For SOT402-1 (TSSOP14) package: P_totderates linearly with 7.3 mW/K above 81 °C.

For SOT762-1 (DHVQFN14) package: P_totderates linearly with 9.6 mW/K above 98 °C.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter

Conditions

74HC00-Q100

74HCT00-Q100

Unit

Min

Typ

Max

Min

Typ

Max

V_CC

V_I

supply voltage

2.0

5.0

6.0

V_CC

+125

625

139

4.5

5.0

5.5

V_CC

input voltage

V_O

output voltage

+25

T_amb

Δt/ΔV

ambient temperature

input transition rise and fall rate

-40

+125 °C

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

ns/V

1.67

139 ns/V

ns/V

74HC_HCT00_Q100

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Product data sheet

Rev. 5 — 22 October 2021

3 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Typ

Max

Min

Max

Min

Max

74HC00-Q100

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_I= V_IHor V_IL

1.2

2.4

3.2

0.8

2.1

2.8

1.5

3.15

4.2

V_IL

LOW-level

input voltage

0.5

1.35

1.8

0.5

1.35

1.8

V_OH

HIGH-level

output voltage

I_O= -20 μA; V_CC= 2.0 V

2.0

4.5

1.9

4.4

1.9

4.4

5.9

3.7

5.2

I_O= -20 μA; V_CC= 4.5 V

I_O= -20 μA; V_CC= 6.0 V

I_O= -4.0 mA; V_CC= 4.5 V

I_O= -5.2 mA; V_CC= 6.0 V

6.0

5.9

4.32

5.81

3.84

5.34

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 20 μA; V_CC= 2.0 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 20 μA; V_CC= 6.0 V

I_O= 4.0 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

0.1

0.4

±1

0.1

0.15

0.16

0.33

±1

I_I

input leakage V_I= V_CCor GND; V_CC= 6.0 V

current

μA

I_CC

C_I

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

μA

input

3.5

capacitance

74HCT00-Q100

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

1.6

1.2

2.0

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= -20 μA

4.5

4.4

3.7

I_O= -4.0 mA

4.32

3.84

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 μA

0.1

0.4

I_O= 4 mA

0.15

0.33

74HC_HCT00_Q100

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Product data sheet

Rev. 5 — 22 October 2021

4 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Typ

Max

Min

Max

Min

Max

I_I

input leakage V_I= V_CCor GND; V_CC= 6.0 V

current

±1

μA

I_CC

ΔI_CC

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

additional

per input pin;

150

675

735 μA

supply current V_I= V_CC- 2.1 V; I_O= 0 A;

other inputs at V_CCor GND;

V_CC= 4.5 V to 5.5 V

C_I

input

3.5

capacitance

10. Dynamic characteristics

Table 7. Dynamic characteristics

GND = 0 V; C_L= 50 pF; for test circuit see Fig. 7.

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Typ

Max

Min

Max

Min

Max

74HC00-Q100

t_pd

propagation delay nA, nB to nY; see Fig. 6

V_CC= 2.0 V

[1]

[2]

115

135 ns

27 ns

V_CC= 4.5 V

V_CC= 5.0 V; C_L= 15 pF

V_CC= 6.0 V

23 ns

t_t

transition time

see Fig. 6

V_CC= 2.0 V

110 ns

22 ns

19 ns

V_CC= 4.5 V

V_CC= 6.0 V

C_PD

power dissipation per package;

capacitance V_I= GND to V_CC

[3]

[1]

74HCT00-Q100

t_pd

propagation delay nA, nB to nY; see Fig. 6

V_CC= 4.5 V

29 ns

22 ns

V_CC= 5.0 V; C_L= 15 pF

t_t

transition time

power dissipation per package;

capacitance V_I= GND to V_CC- 1.5 V

V_CC= 4.5 V; see Fig. 6

[2]

[3]

C_PD

[1] t_pdis the same as t_PHLand t_PLH

[2] t_tis the same as t_THLand t_TLH

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW):

P_D= C_PD× V_CC²× f_i× N + Σ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ (C_L× V_CC²× f_o) = sum of outputs.

74HC_HCT00_Q100

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Product data sheet

Rev. 5 — 22 October 2021

5 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

10.1. Waveforms and test circuit

nA, nB input

GND

PLH

PHL

nY output

TLH

THL

001aai814

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 6. Input to output propagation delays

Table 8. Measurement points

Type

Input

V_M

Output

V_M

V_X

V_Y

74HC00-Q100

74HCT00-Q100

0.5V_CC

1.3 V

0.5V_CC

1.3 V

0.1V_CC

0.9V_CC

90 %

negative

pulse

10 %

GND

90 %

positive

pulse

10 %

GND

DUT

001aah768

Test data is given in Table 9.

Definitions test circuit:

R_T= termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= load capacitance including jig and probe capacitance.

Fig. 7. Test circuit for measuring switching times

Table 9. Test data

Type

Input

V_I

Load

Test

t_r, t_f

C_L

74HC00-Q100

74HCT00-Q100

V_CC

3.0 V

6.0 ns

15 pF, 50 pF

t_PLH, t_PHL

74HC_HCT00_Q100

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Product data sheet

Rev. 5 — 22 October 2021

6 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

11. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

(A )

pin 1 index

detail X

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

UNIT

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

1.75

1.27

0.05

1.05

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Fig. 8. Package outline SOT108-1 (SO14)

74HC_HCT00_Q100

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Product data sheet

Rev. 5 — 22 October 2021

7 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

1.1

0.65

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig. 9. Package outline SOT402-1 (TSSOP14)

74HC_HCT00_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 22 October 2021

8 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

SOT762-1

detail X

terminal 1

index area

terminal 1

index area

A B

4 mm

scale

Dimensions (mm are the original dimensions)

(1) (1)

(1)

Unit

max

nom

min

0.05 0.30

0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5

0.00 0.18 2.9 1.35 2.4 0.85

3.1 1.65 2.6 1.15

0.5

0.4 0.1 0.05 0.05 0.1

0.2 0.3

Note

sot762-1_po

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

15-04-10

15-05-05

SOT762-1

MO-241

Fig. 10. Package outline SOT762-1 (DHVQFN14)

74HC_HCT00_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 22 October 2021

9 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

CMOS

DUT

ESD

HBM

MIL

Complementary Metal-Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Military

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

20211022 Product data sheet

Section 9: V_OLcondition for 74HCT00 corrected. (Errata)

Change notice Supersedes

74HC_HCT00_Q100 v.5

Modifications:

74HC_HCT00_Q100 v.4

74HC_HCT00_Q100 v.3

74HC_HCT00_Q100 v.2

•

74HC_HCT00_Q100 v.4

Modifications:

20210810

Product data sheet

•

Section 2 updated.

74HC_HCT00_Q100 v.3

Modifications:

20200319

Product data sheet

•

The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Section 2 updated.

Table 4: Derating values for P_tottotal power dissipation updated.

74HC_HCT00_Q100 v.2

Modifications:

20151124

General description changed.

20120712 Product data sheet

Product data sheet

74HC_HCT00_Q100 v.1

•

74HC_HCT00_Q100 v.1

74HC_HCT00_Q100

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Product data sheet

Rev. 5 — 22 October 2021

10 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

equipment, nor in applications where failure or malfunction of an Nexperia

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Data sheet status

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

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Definition

[1][2]

status [3]

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products are for illustrative purposes only. Nexperia makes no representation

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without further testing or modification.

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

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data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

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[2] The term 'short data sheet' is explained in section "Definitions".

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

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74HC_HCT00_Q100

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Product data sheet

Rev. 5 — 22 October 2021

11 / 12

Nexperia

74HC00-Q100; 74HCT00-Q100

Quad 2-input NAND gate

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................2

5.1. Pinning.........................................................................2

5.2. Pin description.............................................................2

6. Functional description................................................. 3

7. Limiting values............................................................. 3

8. Recommended operating conditions..........................3

9. Static characteristics....................................................4

10. Dynamic characteristics............................................ 5

10.1. Waveforms and test circuit........................................ 6

11. Package outline.......................................................... 7

12. Abbreviations............................................................10

13. Revision history........................................................10

14. Legal information......................................................11

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 22 October 2021

74HC_HCT00_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 22 October 2021

12 / 12

74HC00PW-Q100 [NEXPERIA]

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