74HC373D-Q100 [NEXPERIA]
Octal D-type transparent latch; 3-stateProduction;
| 型号： | 74HC373D-Q100 |
| 厂家： | 
Nexperia |
| 描述： | Octal D-type transparent latch; 3-stateProduction 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Rev. 2 — 22 July 2020
Product data sheet
1. General description
The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch with 3-state outputs.
The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at
the inputs enter the latches. In this condition the latches are transparent, a latch output will change
each time its corresponding D-input changes. When LE is LOW the latches store the information
that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH
on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does
not affect the state of the latches. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
•
•
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
•
Input levels:
•
•
For 74HC373-Q100: CMOS level
For 74HCT373-Q100: TTL level
•
•
•
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
•
•
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC373D-Q100
74HCT373D-Q100
-40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74HC373PW-Q100 -40 °C to +125 °C
74HCT373PW-Q100
TSSOP20
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT360-1
SOT764-1
74HC373BQ-Q100 -40 °C to +125 °C
74HCT373BQ-Q100
DHVQFN20 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 × 4.5 × 0.85 mm
4. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
Q0
2
3
4
Q1
5
Q2
6
7
Q3
8
9
LATCH
1 TO 8
3-STATE
OUTPUTS
Q4
Q5
Q6
Q7
13
14
17
18
12
15
16
19
LE
11
1
OE
001aae050
Fig. 1. Functional diagram
1
OE
LE
EN
C1
11
11
LE
3
2
1D
D0
Q0
3
4
2
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
5
D1
D2
D3
Q1
Q2
Q3
5
6
7
6
8
9
8
9
13
14
17
18
12
15
16
19
13
14
12
15
D4
D5
D6
D7
Q4
Q5
Q6
Q7
17
18
16
19
OE
1
001aae048
001aae049
Fig. 2. Logic symbol
Fig. 3. IEC logic symbol
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
2 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
LE
LE
LE
LE
D
Q
001aae051
Fig. 4. Logic diagram (one latch)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig. 5. Logic diagram
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
3 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
5. Pinning information
5.1. Pinning
74HC373-Q100
74HCT373-Q100
terminal 1
index area
74HC373-Q100
74HCT373-Q100
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
1
20
19
18
17
16
15
14
13
12
11
OE
Q0
V
CC
2
3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
D0
4
D1
5
Q1
(1)
GND
6
Q2
7
D2
8
D3
aaa-003968
9
Q3
Transparent top view
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
10
GND
aaa-003967
Fig. 6. Pin configuration SOT163-1 (SO20) and
SOT360-1 (TSSOP20)
Fig. 7. Pin configuration SOT764-1 (DHVQFN20)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
OE
1
3-state output enable input (active LOW)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
2, 5, 6, 9, 12, 15, 16, 19
3-state latch output
data input
D0, D1, D2, D3, D4, D5, D6, D7
3, 4, 7, 8, 13, 14, 17, 18
GND
LE
10
11
20
ground (0 V)
latch enable input (active HIGH)
supply voltage
VCC
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
4 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
6. Functional description
Table 3. Functional description
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care; Z = high-impedance OFF-state.
Operating mode
Control
Input
Internal latches
Output
OE
LE
Dn
L
Qn
L
Enable and read register
(transparent mode)
L
H
L
H
l
H
L
H
L
Latch and read register
L
L
h
H
X
H
Z
Latch register and disable
outputs
H
X
X
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7
Unit
V
VCC
IIK
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to (VCC + 0.5 V)
-
±20
±20
±35
+70
-70
mA
mA
mA
mA
mA
°C
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
-
ground current
storage temperature
total power dissipation
-65
-
+150
500
[1]
mW
[1] For SOT163-1 (SO20) package: Ptot derates linearly with 12.3 mW/K above 109 °C.
For SOT360-1 (TSSOP20) package: Ptot derates linearly with 10.0 mW/K above 100 °C.
For SOT764-1 (DHVQFN20) package: Ptot derates linearly with 12.9 mW/K above 111 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC373-Q100
74HCT373-Q100
Unit
Min
Typ
Max
Min
4.5
Typ
Max
VCC
VI
supply voltage
2.0
5.0
6.0
VCC
VCC
+125
625
139
83
5.0
5.5
VCC
VCC
V
V
V
input voltage
0
0
-
0
0
-
VO
output voltage
-
+25
-
-
+25
-
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
-
-40
-
+125 °C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
ns/V
-
1.67
-
-
1.67
-
139 ns/V
-
-
-
ns/V
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
5 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 25 °C
Tamb = -40 °C Tamb = -40 °C Unit
to 85 °C to 125 °C
Min Typ Max Min
Max
Min Max
74HC373-Q100
VIH
HIGH-level input
voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
-
-
1.5
-
-
1.5
-
V
V
V
V
V
V
3.15 2.4
3.15
3.15
-
-
4.2
-
3.2
0.8
-
4.2
-
4.2
VIL
LOW-level input
voltage
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
-
2.1 1.35
-
2.8
-
1.8
VOH
HIGH-level output VI = VIH or VIL
voltage
-
-
-
-
-
-
-
IO = -20 μA; VCC = 2.0 V
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -6.0 mA; VCC = 4.5 V
IO = -7.8 mA; VCC = 6.0 V
5.9
3.98 4.32
5.48 5.81
3.84
5.34
VOL
LOW-level output VI = VIH or VIL
voltage
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
0.1
0.15 0.26
0.16 0.26
0.33
0.33
±1.0
II
input leakage
current
-
±0.1
±0.5
8.0
-
±1.0 μA
±10.0 μA
160 μA
IOZ
ICC
CI
OFF-state output
current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
-
-
-
-
-
-
-
±5.0
80
-
-
-
-
supply current
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
input capacitance
3.5
-
pF
74HCT373-Q100
VIH
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level input
voltage
0.8
0.8
0.8
VOH
HIGH-level output VI = VIH or VIL
voltage
IO = -20 μA; VCC = 4.5 V
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = -6.0 mA; VCC = 4.5 V
LOW-level output VI = VIH or VIL
3.98 4.32
3.84
VOL
voltage
IO = 20 μA; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
-
-
-
0.0
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
V
0.16 0.26
±0.1
0.33
±1.0
II
input leakage
current
VI = VCC or GND; VCC = 5.5 V
-
±1.0 μA
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
6 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Symbol Parameter
Conditions
Tamb = 25 °C
Tamb = -40 °C Tamb = -40 °C Unit
to 85 °C to 125 °C
Min Typ Max Min
Max
Min Max
IOZ
OFF-state output
current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND
-
-
±0.5
-
±5.0
-
±10 μA
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160 μA
ΔICC
additional supply
current
VI = VCC - 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
LE
OE
-
-
-
-
30
108
-
-
-
-
135
675
450
-
-
-
-
-
147 μA
735 μA
490 μA
150 540
100 360
CI
input capacitance
3.5
-
-
pF
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 12.
Symbol Parameter
Conditions
Tamb = 25 °C
Tamb = -40 °C
to +85 °C
Tamb = -40 °C Unit
to +125 °C
Min Typ Max
Min
Max
Min
Max
74HC373-Q100
tpd
propagation
delay
Dn to Qn; see Fig. 8
VCC = 2.0 V
[1]
-
-
-
-
41
15
12
12
150
30
-
-
-
-
-
190
38
-
-
-
-
-
225 ns
VCC = 4.5 V
45
-
ns
ns
ns
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
33
38
LE to Qn; see Fig. 9
VCC = 2.0 V
-
-
-
-
50
18
15
14
175
35
-
-
-
-
-
220
44
-
-
-
-
-
265 ns
VCC = 4.5 V
53
-
ns
ns
ns
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
30
37
45
ten
tdis
tt
enable time
disable time
transition time
OE to Qn; see Fig. 10
VCC = 2.0 V
[2]
[3]
[4]
-
-
-
44
16
13
150
30
-
-
-
190
38
-
-
-
225 ns
VCC = 4.5 V
45
38
ns
ns
VCC = 6.0 V
26
33
OE to Qn; see Fig. 10
VCC = 2.0 V
-
-
-
47
17
14
150
30
-
-
-
190
38
-
-
-
225 ns
VCC = 4.5 V
45
38
ns
ns
VCC = 6.0 V
26
33
Qn; see Fig. 8 and Fig. 9
VCC = 2.0 V
-
-
-
14
5
60
12
10
-
-
-
75
15
13
-
-
-
90
18
15
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
7 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Symbol Parameter
Conditions
Tamb = 25 °C
Min Typ Max
Tamb = -40 °C
to +85 °C
Tamb = -40 °C Unit
to +125 °C
Min
Max
Min
Max
tW
pulse width
set-up time
hold time
LE HIGH; see Fig. 9
VCC = 2.0 V
80
16
14
17
6
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
17
20
tsu
Dn to LE; see Fig. 11
VCC = 2.0 V
50
10
9
14
5
-
-
-
65
13
11
-
-
-
75
15
13
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
th
Dn to LE; see Fig. 11
VCC = 2.0 V
+5
+5
+5
-
-8
-3
-2
45
-
-
-
-
5
5
5
-
-
-
-
-
5
5
5
-
-
-
-
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
CPD
power dissipation per latch; VI = GND to VCC [5]
capacitance
74HCT373-Q100
tpd
propagation
delay
Dn to Qn; see Fig. 8
VCC = 4.5 V
[1]
-
-
17
14
30
-
-
-
38
-
-
-
45
-
ns
ns
VCC = 5 V; CL = 15 pF
LE to Qn; see Fig. 9
VCC = 4.5 V
-
-
-
16
13
19
32
-
-
-
-
40
-
-
-
-
48
-
ns
ns
ns
VCC = 5 V; CL = 15 pF
ten
tdis
tt
enable time
disable time
transition time
pulse width
set-up time
hold time
OE to Qn; VCC = 4.5 V;
see Fig. 10
[2]
[3]
[4]
32
40
48
OE to Qn; VCC = 4.5 V;
see Fig. 10
-
-
18
5
30
12
-
-
-
38
15
-
-
-
45
18
-
ns
ns
ns
ns
ns
pF
Qn; VCC = 4.5 V;
see Fig. 8 and Fig. 9
tW
tsu
th
LE HIGH; VCC = 4.5 V;
see Fig. 9
16
12
4
4
20
15
4
24
18
4
Dn to LE; VCC = 4.5 V;
see Fig. 11
6
-
-
-
Dn to LE; VCC = 4.5 V;
see Fig. 11
-1
41
-
-
-
CPD
power dissipation per latch;
capacitance VI = GND to (VCC - 1.5 V)
[5]
-
-
-
-
-
-
[1] tpd is the same as tPLH and tPHL
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of outputs.
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
8 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
10.1. Waveforms
Dn input
V
M
t
t
PHL
PLH
90 %
V
Qn output
M
10 %
TLH
t
t
THL
001aae082
Measurement points are given in Table 8.
Fig. 8. Propagation delay input (Dn) to output (Qn) and transition time output (Qn)
LE input
V
M
t
W
t
t
PHL
PLH
90 %
V
Qn output
M
10 %
t
t
TLH
THL
001aae083
Measurement points are given in Table 8.
Fig. 9. Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and transition time output (Qn)
V
I
OE input
V
M
GND
t
t
PLZ
PZL
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
10%
V
OL
t
t
PZH
PHZ
V
OH
90%
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae307
Measurement points are given in Table 8.
Fig. 10. 3-state enable and disable time
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74HC_HCT373_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
9 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
V
h
LE input
M
t
t
su
su
t
t
h
V
Dn input
M
001aae084
Measurement points are given in Table 8.
Fig. 11. Set-up and hold time data input (Dn) to latch enable input (LE)
Table 8. Measurement points
Type
Input
VM
Output
VM
74HC373-Q100
74HCT373-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
I
V
O
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig. 12. Test circuit for measuring switching times
Table 9. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC373-Q100
VCC
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT373-Q100 3 V
open
GND
VCC
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74HC_HCT373_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
10 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
11. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig. 13. Package outline SOT163-1 (SO20)
©
74HC_HCT373_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
11 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig. 14. Package outline SOT360-1 (TSSOP20)
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
12 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
terminal 1
index area
e
C
1
v
w
C
C
A B
y
y
e
b
C
1
2
9
L
1
10
E
e
h
20
11
19
12
X
D
h
0
2.5
5 mm
scale
Dimensions (mm are the original dimensions)
(1) (1)
(1)
Unit
A
A
b
c
D
D
h
E
E
e
e
1
L
v
w
y
y
1
1
h
max 1.00 0.05 0.30
4.6 3.15 2.6 1.15
0.5
nom
min
mm
0.90 0.02 0.25 0.2 4.5 3.00 2.5 1.00 0.5 3.5 0.4 0.1 0.05 0.05 0.1
0.80 0.00 0.18 4.4 2.85 2.4 0.85 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot764-1_po
Issue date
References
Outline
version
European
projection
IEC
- - -
JEDEC
JEITA
- - -
03-01-27
14-12-12
SOT764-1
MO-241
Fig. 15. Package outline SOT764-1 (DHVQFN20)
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
13 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
ESD
HBM
MIL
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20200722 Product data sheet
Change notice Supersedes
- 74HC_HCT373_Q100 v.1
74HC_HCT373_Q100 v.2
Modifications:
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated.
Table 4: Derating values for Ptot total power dissipation updated.
Table 6: Conditions IOZ updated.
Fig. 15: Package outline drawing SOT764-1 (DHVQFN20) updated.
74HC_HCT373_Q100 v.1
20120810
Product data sheet
-
-
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
14 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
14. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
74HC_HCT373_Q100
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
15 / 16
Nexperia
74HC373-Q100; 74HCT373-Q100
Octal D-type transparent latch; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Functional diagram.......................................................2
5. Pinning information......................................................4
5.1. Pinning.........................................................................4
5.2. Pin description.............................................................4
6. Functional description................................................. 5
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................5
9. Static characteristics....................................................6
10. Dynamic characteristics............................................ 7
10.1. Waveforms.................................................................9
11. Package outline........................................................ 11
12. Abbreviations............................................................14
13. Revision history........................................................14
14. Legal information......................................................15
© Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 22 July 2020
©
74HC_HCT373_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 2 — 22 July 2020
16 / 16
相关型号：
74HC373D-T
IC HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, Bus Driver/Transceiver
NXP
74HC373D/T3
IC HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SOP-20, Bus Driver/Transceiver
NXP
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