74HC373DB,118 [NXP]
74HC(T)373 - Octal D-type transparent latch; 3-state SSOP2 20-Pin;
| 型号： | 74HC373DB,118 |
| 厂家： | 
NXP |
| 描述： | 74HC(T)373 - Octal D-type transparent latch; 3-state SSOP2 20-Pin 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总26页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 03 — 20 January 2006
Product data sheet
1. General description
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all latches.
The 74HC373; HCT373 consists of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
D input changes.
When LE is LOW the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373; 74HCT373 is functionally identical to:
• 74HC533; 74HCT533: but inverted outputs
• 74HC563; 74HCT563: but inverted outputs and different pin arrangement
• 74HC573; 74HCT573: but different pin arrangement
2. Features
■ 3-state non-inverting outputs for bus oriented applications
■ Common 3-state output enable input
■ Functionally identical to the 74HC563; 74HCT563, 74HC573; 74HCT573 and
74HC533; 74HCT533
■ ESD protection:
◆ HBM EIA/JESD22-A114-C exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol Parameter
74HC373
Conditions
Min
Typ
Max Unit
tPHL, tPLH propagation delay
Dn to Qn
VCC = 5 V; CL = 15 pF
-
-
-
-
12
15
3.5
45
-
-
-
-
ns
ns
pF
pF
LE to Qn
Ci
input capacitance
[1]
CPD
power dissipation
capacitance
per latch; VI = GND to VCC
VCC = 5 V; CL = 15 pF
74HCT373
tPHL, tPLH propagation delay
Dn to Qn
-
-
-
-
14
13
3.5
41
-
-
-
-
ns
ns
pF
pF
LE to Qn
Ci
input capacitance
[1]
CPD
power dissipation
capacitance
per latch;
VI = GND to (VCC − 1.5 V)
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Type number Package
Temperature range Name
Description
Version
74HC373
74HC373N
74HC373D
−40 °C to +125 °C
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
SOT163-1
−40 °C to +125 °C
plastic small outline package; 20 leads;
body width 7.5 mm
74HC373DB
−40 °C to +125 °C
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
SOT360-1
74HC373PW −40 °C to +125 °C
74HC373BQ −40 °C to +125 °C
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
2 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 2:
Ordering information …continued
Type number Package
Temperature range Name
Description
Version
74HCT373
74HCT373N
74HCT373D
−40 °C to +125 °C
−40 °C to +125 °C
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
SOT163-1
plastic small outline package; 20 leads;
body width 7.5 mm
74HCT373DB −40 °C to +125 °C
74HCT373PW −40 °C to +125 °C
74HCT373BQ −40 °C to +125 °C
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
SOT360-1
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
5. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
4
2
5
7
6
8
9
LATCH
1 TO 8
3-STATE
OUTPUTS
13
14
17
18
12
15
16
19
LE
11
1
OE
001aae050
Fig 1. Functional diagram
1
OE
LE
EN
11
C1
11
3
2
1D
D0
Q0
LE
3
2
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
5
6
9
D1
D2
D3
Q1
Q2
Q3
4
7
5
6
8
9
13
14
17
18
12
15
16
19
13
14
17
18
12
15
16
19
D4
D5
D6
D7
Q4
Q5
Q6
Q7
OE
1
001aae048
001aae049
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
3 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
LE
LE
LE
LE
D
Q
001aae051
Fig 4. Logic diagram (one latch)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig 5. Logic diagram
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
4 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
6. Pinning information
6.1 Pinning
74HC373
74HCT373
74HC373
74HCT373
terminal 1
index area
1
2
20
19
18
17
16
15
14
13
12
11
OE
V
CC
Q0
D0
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
3
4
D1
5
Q1
6
Q2
7
D2
(1)
GND
8
D3
9
Q3
10
GND
001aae047
Transparent top view
001aae046
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or input.
Fig 6. Pin configuration DIP20, SO20,
SSOP20 and TSSOP20
Fig 7. Pin configuration DHVQFN20
6.2 Pin description
Table 3:
Pin description
Symbol
OE
Q0
Pin
1
Description
3-state output enable input (active LOW)
3-state latch output 0
data input 0
2
D0
3
D1
4
data input 1
Q1
5
3-state latch output 1
3-state latch output 2
data input 2
Q2
6
D2
7
D3
8
data input 3
Q3
9
3-state latch output 3
ground (0 V)
GND
LE
10
11
12
13
14
latch enable input (active HIGH)
3-state latch output 4
data input 4
Q4
D4
D5
data input 5
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
5 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 3:
Symbol
Q5
Pin description …continued
Pin
15
16
17
18
19
20
Description
3-state latch output 5
Q6
3-state latch output 6
data input 6
D6
D7
data input 7
Q7
3-state latch output 7
supply voltage
VCC
7. Functional description
7.1 Function table
Table 4:
Function table[1]
Operating mode
Control
Input
Internal
latches
Output
OE
LE
Dn
L
Qn
L
Enable and
L
H
L
read register
(transparent mode)
H
H
H
Latch and
L
L
l
L
L
read register
h
X
H
X
H
Z
Latch register and
disable outputs
H
X
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
6 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max Unit
VCC
IIK
supply voltage
−0.5 +7
V
input clamping current
output clamping current
VI < −0.5 V or VI > VCC + 0.5 V
-
-
±20
mA
mA
IOK
VO < −0.5 V or
±20
VO > VCC + 0.5 V
IO
output current
VO = −0.5 V to (VCC + 0.5 V)
-
±35
+70
−70
mA
mA
mA
ICC
IGND
Tstg
Ptot
quiescent supply current
ground current
-
-
storage temperature
total power dissipation
DIP20 package
−65
+150 °C
[1]
[2]
[3]
[3]
[4]
-
-
750
500
500
500
500
mW
SO20 package
mW
mW
mW
mW
SSOP20 package
TSSOP20 package
DHVQFN20 package
-
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO20: Ptot derates linearly with 8 mW/K above 70 °C.
[3] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol Parameter
74HC373
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
2.0
5.0
6.0
V
input voltage
0
-
VCC
VCC
+125
1000
500
400
V
VO
output voltage
0
-
V
Tamb
tr, tf
ambient temperature
input rise and fall time
−40
+25
°C
ns
ns
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
6.0
-
74HCT373
VCC
supply voltage
4.5
0
5.0
-
5.5
V
VI
input voltage
VCC
VCC
+125
500
V
VO
output voltage
0
-
V
Tamb
tr, tf
ambient temperature
input rise and fall time
−40
-
+25
6.0
°C
ns
VCC = 4.5 V
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
7 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
10. Static characteristics
Table 7:
Static characteristics 74HC373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Tamb = 25 °C
VIH HIGH-state input voltage
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
1.5
3.15
4.2
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
V
V
V
V
V
V
VCC = 4.5 V
-
VCC = 6.0 V
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 2.0 V
0.5
VCC = 4.5 V
-
1.35
VCC = 6.0 V
-
1.8
VOH
VI = VIH or VIL
-
-
-
-
-
-
-
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −6.0 mA; VCC = 4.5 V
IO = −7.8 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
V
V
V
V
V
VOL
LOW-state output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
0
0.1
V
0
0.1
V
0
0.1
V
0.15
0.26
0.26
±0.1
±0.5
V
0.16
V
ILI
input leakage current
-
-
µA
µA
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
ICC
Ci
quiescent supply current
input capacitance
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
-
-
8.0
-
µA
3.5
pF
Tamb = −40 °C to +85 °C
VIH HIGH-state input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −6.0 mA; VCC = 4.5 V
IO = −7.8 mA; VCC = 6.0 V
1.9
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
4.4
5.9
3.84
5.34
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
8 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 7:
Static characteristics 74HC373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-state output voltage
VI = VIH or VIL
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.1
V
0.1
V
0.33
0.33
±1.0
±5.0
V
V
ILI
input leakage current
µA
µA
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
ICC
quiescent supply current
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
80
µA
Tamb = −40 °C to +125 °C
VIH HIGH-state input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
-
VCC = 6.0 V
4.2
-
VIL
LOW-state input voltage
HIGH-state output voltage
VCC = 2.0 V
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
VCC = 6.0 V
VOH
VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −6.0 mA; VCC = 4.5 V
IO = −7.8 mA; VCC = 6.0 V
VI = VIH or VIL
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
VOL
LOW-state output voltage
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
IO = 20 µA; VCC = 6.0 V
IO = 6.0 mA; VCC = 4.5 V
IO = 7.8 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
V
V
V
V
V
ILI
input leakage current
µA
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
±10.0 µA
ICC
quiescent supply current
VCC = 6.0 V; IO = 0 A;
VI = VCC or GND
-
-
160 µA
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
9 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 8:
Static characteristics 74HCT373
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
VIL
HIGH-state input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
2.0
-
1.6
1.2
-
V
V
LOW-state input voltage
HIGH-state output voltage
0.8
VOH
IO = −20 µA; VCC = 4.5 V
IO = −6.0 mA; VCC = 4.5 V
VI = VIH or VIL
4.4
4.5
-
-
V
V
3.98
4.32
VOL
LOW-state output voltage
IO = 20 µA; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
-
-
-
-
0.0
0.1
V
0.16
0.26
±0.1
±0.5
V
ILI
input leakage current
-
-
µA
µA
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
8.0
µA
VCC = 5.5 V
∆ICC
additional quiescent supply
current
VI = VCC − 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
-
-
-
-
30
108
540
360
-
µA
µA
µA
pF
LE
150
100
3.5
OE
Ci
input capacitance
Tamb = −40 °C to +85 °C
VIH
VIL
HIGH-state input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
2.0
-
-
-
-
V
V
LOW-state input voltage
HIGH-state output voltage
0.8
VOH
IO = −20 µA; VCC = 4.5 V
IO = −6.0 µA; VCC = 4.5 V
VI = VIH or VIL
4.4
-
-
-
-
V
V
3.84
VOL
LOW-state output voltage
IO = 20 µA; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
-
-
-
-
-
-
-
-
0.1
V
0.33
±1.0
±5.0
V
ILI
input leakage current
µA
µA
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
80
µA
VCC = 5.5 V
∆ICC
additional quiescent supply
current
VI = VCC − 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
LE
OE
-
-
-
-
-
-
135
675
450
µA
µA
µA
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
10 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 8:
Static characteristics 74HCT373 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VIH
VIL
HIGH-state input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
2.0
-
-
-
-
V
V
LOW-state input voltage
HIGH-state output voltage
0.8
VOH
IO = −20 µA; VCC = 4.5 V
IO = −6.0 mA; VCC = 4.5 V
VI = VIH or VIL
4.4
3.7
-
-
-
-
V
V
VOL
LOW-state output voltage
IO = 20 µA; VCC = 4.5 V
IO = 6.0 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
-
-
-
-
-
-
-
-
0.1
V
0.4
V
ILI
input leakage current
±1.0
±10
µA
µA
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND per input pin;
other inputs at VCC or GND; IO = 0 A
ICC
quiescent supply current
VI = VCC or GND; IO = 0 A;
-
-
160
µA
VCC = 5.5 V
∆ICC
additional quiescent supply
current
VI = VCC − 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
Dn
LE
OE
-
-
-
-
-
-
147
735
490
µA
µA
µA
11. Dynamic characteristics
Table 9:
Dynamic characteristics 74HC373
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL
tPLH
,
propagation delay
Dn to Qn
see Figure 8
VCC = 2.0 V
-
-
-
-
41
15
12
12
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
LE to Qn
see Figure 9
VCC = 2.0 V
-
-
-
-
50
18
15
14
175
35
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
30
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
11 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 9:
Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
per latch; VI = GND to VCC
Min
Typ
Max
Unit
tPZH
tPZL
,
3-state output enable time OE to
Qn
-
-
-
44
16
13
150
30
ns
ns
ns
26
tPHZ
tPLZ
,
3-state output disable time OE to
Qn
-
-
-
47
17
14
150
30
ns
ns
ns
26
tTHL
tTLH
,
output transition time
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
-
-
-
14
5
60
12
10
ns
ns
ns
4
tW
80
16
14
17
6
-
-
-
ns
ns
ns
5
tsu
50
10
9
14
5
-
-
-
ns
ns
ns
4
th
+5
+5
+5
-
−8
−3
−2
45
-
-
-
-
ns
ns
ns
pF
[1]
CPD
power dissipation capacitance
Tamb = −40 °C to +85 °C
tPHL
tPLH
,
propagation delay
Dn to Qn
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
190
38
ns
ns
ns
33
LE to Qn
-
-
-
-
-
-
220
44
ns
ns
ns
37
tPZH
tPZL
,
3-state output enable time OE to
Qn
-
-
-
-
-
-
190
38
ns
ns
ns
33
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
12 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 9:
Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
tPHZ
tPLZ
,
3-state output disable time OE to
Qn
-
-
-
-
-
-
190
38
ns
ns
ns
33
tTHL
tTLH
,
output transition time
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
-
-
-
-
-
-
75
15
13
ns
ns
ns
tW
tsu
th
100
20
-
-
-
-
-
-
ns
ns
ns
17
65
13
11
-
-
-
-
-
-
ns
ns
ns
5
5
5
-
-
-
-
-
-
ns
ns
ns
Tamb = −40 °C to +125 °C
tPHL
tPLH
,
propagation delay
Dn to Qn
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
38
LE to Qn
-
-
-
-
-
-
265
53
ns
ns
ns
45
tPZH
tPZL
,
,
3-state output enable time OE to
Qn
-
-
-
-
-
-
225
45
ns
ns
ns
38
tPHZ
tPLZ
3-state output disable time OE to
Qn
-
-
-
-
-
-
225
45
ns
ns
ns
38
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
13 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 9:
Dynamic characteristics 74HC373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
tTHL
tTLH
Conditions
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
,
output transition time
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
-
-
-
-
-
-
90
18
15
ns
ns
ns
tW
tsu
th
120
24
-
-
-
-
-
-
ns
ns
ns
20
75
15
13
-
-
-
-
-
-
ns
ns
ns
5
5
5
-
-
-
-
-
-
ns
ns
ns
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
Table 10: Dynamic characteristics 74HCT373
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL
tPLH
,
propagation delay
Dn to Qn
see Figure 8
VCC = 4.5 V
-
-
17
14
30
-
ns
ns
VCC = 5 V; CL = 15 pF
see Figure 9
LE to Qn
VCC = 4.5 V
-
-
-
16
13
19
32
-
ns
ns
ns
VCC = 5 V; CL = 15 pF
tPZH
tPZL
,
,
3-state output enable time OE to Qn VCC = 4.5 V; see Figure 10
32
tPHZ
tPLZ
3-state output disable time OE to Qn VCC = 4.5 V; see Figure 10
-
-
18
5
30
12
ns
ns
tTHL
,
output transition time
VCC = 4.5 V; see Figure 8
tTLH
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
14 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
Table 10: Dynamic characteristics 74HCT373 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
16
12
4
Typ
4
Max
Unit
ns
tW
pulse width LE HIGH
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 11
VCC = 4.5 V; see Figure 11
-
-
-
-
tsu
th
set-up time Dn to LE
6
ns
hold time Dn to LE
−1
41
ns
[1]
CPD
power dissipation capacitance
per latch;
-
pF
VI = GND to (VCC − 1.5 V)
Tamb = −40 °C to +85 °C
tPHL
tPLH
,
propagation delay
Dn to Qn
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
-
-
-
-
-
-
38
40
40
ns
ns
ns
LE to Qn
tPZH
tPZL
,
,
3-state output enable time OE to Qn VCC = 4.5 V; see Figure 10
tPHZ
tPLZ
3-state output disable time OE to Qn VCC = 4.5 V; see Figure 10
-
-
-
-
38
15
ns
ns
tTHL
,
output transition time
VCC = 4.5 V; see Figure 8
tTLH
tW
tsu
th
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
VCC = 4.5 V; see Figure 9
VCC = 4.5 V; see Figure 11
VCC = 4.5 V; see Figure 11
20
15
4
-
-
-
-
-
-
ns
ns
ns
Tamb = −40 °C to +125 °C
tPHL
tPLH
,
propagation delay
Dn to Qn
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 9
-
-
-
-
-
-
45
48
48
ns
ns
ns
LE to Qn
tPZH
tPZL
,
,
3-state output enable time OE to Qn VCC = 4.5 V, see Figure 10
tPHZ
tPLZ
3-state output disable time OE to Qn VCC = 4.5 V; see Figure 10
-
-
-
-
45
18
ns
ns
tTHL
,
output transition time
VCC = 4.5 V; see Figure 8
tTLH
tW
tsu
th
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
VCC = 4.5 V; see Figure 8
VCC = 4.5 V; see Figure 11
VCC = 4.5 V; see Figure 11
24
18
4
-
-
-
-
-
-
ns
ns
ns
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
15 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
12. Waveforms
Dn input
V
M
t
t
PHL
PLH
90 %
V
Qn output
M
10 %
TLH
t
t
THL
001aae082
Measurement points are given in Table 11.
Fig 8. Propagation delay input (Dn) to output (Qn) and transition time output (Qn)
LE input
V
M
t
W
t
t
PHL
PLH
90 %
Qn output
V
M
10 %
t
t
TLH
THL
001aae083
Measurement points are given in Table 11.
Fig 9. Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and
transition time output (Qn)
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
16 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
V
I
OE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
10%
V
OL
t
t
PZH
PHZ
V
OH
90%
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae307
Measurement points are given in Table 11.
Fig 10. 3-state enable and disable time
V
h
LE input
M
t
t
su
su
t
t
h
V
Dn input
M
001aae084
Measurement points are given in Table 11.
Fig 11. Set-up and hold time data input (Dn) to latch enable input (LE)
Table 11: Measurement points
Type
Input
VM
Output
VM
74HC373
0.5VCC
1.3 V
0.5VCC
1.3 V
74HCT373
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
17 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
PULSE
GENERATOR
open
DUT
R
T
C
L
001aad983
Test data is given in Table 12.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 12. Load circuitry for measuring switching times
Table 12: Test data
Type
Input
VI
Load
CL
S1 position
tr, tf
6 ns
6 ns
RL
tPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC373
VCC
3 V
15 pF, 50 pF 1 kΩ
15 pF, 50 pF 1 kΩ
open
open
GND
GND
VCC
VCC
74HCT373
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
18 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
13. Package outline
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT146-1
MS-001
SC-603
Fig 13. Package outline SOT146-1 (DIP20)
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
19 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 14. Package outline SOT163-1 (SO20)
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
20 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 15. Package outline SOT339-1 (SSOP20)
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
21 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 16. Package outline SOT360-1 (TSSOP20)
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
22 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 17. Package outline SOT764-1 (DHVQFN20)
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
23 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
14. Abbreviations
Table 13: Abbreviations
Acronym
CMOS
ESD
Description
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 14: Revision history
Document ID
74HC_HCT373_3
Modifications:
Release date Data sheet status Change notice Doc. number Supersedes
20060120 Product data sheet 74HC_HCT373_CNV_2
-
-
• The format of this data sheet is redesigned to comply with the current presentation and
information standard of Philips Semiconductors.
• Added type numbers 74HC373BQ and 74HCT373BQ (package DHVQFN20).
• Added family specifications.
• Added abbreviations list.
74HC_HCT373_CNV_2 19970827
Product
-
-
-
specification
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
24 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
16. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
17. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
makes no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
19. Trademarks
Notice — All referenced brands, product names, service names and
18. Disclaimers
trademarks are the property of their respective owners.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
20. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
74HC_HCT373_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 20 January 2006
25 of 26
74HC373; 74HCT373
Philips Semiconductors
Octal D-type transparent latch; 3-state
21. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 6
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Contact information . . . . . . . . . . . . . . . . . . . . 25
9
10
11
12
13
14
15
16
17
18
19
20
© Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 20 January 2006
Document number: 74HC_HCT373_3
Published in The Netherlands
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明