74HC3G16DP [NEXPERIA]

Triple buffer gateProduction;
74HC3G16DP
型号: 74HC3G16DP
厂家: Nexperia    Nexperia
描述:

Triple buffer gateProduction

光电二极管 逻辑集成电路
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74HC3G16  
Triple buffer gate  
Rev. 3 — 17 April 2019  
Product data sheet  
1. General description  
The 74HC3G16 is a triple buffer. Inputs include clamp diodes. This enables the use of current  
limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 V to 6.0 V  
CMOS input levels  
Complies with JEDEC standard no. 7 A  
Symmetrical output impedance  
High noise immunity  
Low-power dissipation  
Balanced propagation delays  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC3G16DP  
-40 °C to +125 °C  
TSSOP8  
plastic thin shrink small outline package; 8 leads;  
body width 3 mm; lead length 0.5 mm  
SOT505-2  
4. Marking  
Table 2. Marking  
Type number  
Marking code [1]  
74HC3G16DP  
P6  
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.  
 
 
 
 
 
Nexperia  
74HC3G16  
Triple buffer gate  
5. Functional diagram  
1
1
1
3
6
7
5
2
1
2
3
1A  
3Y  
2A  
1Y  
3A  
2Y  
7
6
5
1
mna744  
mna745  
Fig. 1. Logic symbol  
Fig. 2. IEC logic symbol  
6. Pinning information  
6.1. Pinning  
74HC3G16  
1
2
3
4
8
7
6
5
1A  
3Y  
V
CC  
1Y  
3A  
2Y  
2A  
GND  
aaa-019747  
Fig. 3. Pin configuration SOT505-2 (TSSOP8)  
6.2. Pin description  
Table 3. Pin description  
Symbol  
Pin  
1, 3, 6  
7, 5, 2  
4
Description  
1A, 2A, 3A  
1Y, 2Y, 3Y  
GND  
data input  
data output  
ground (0 V)  
supply voltage  
VCC  
8
7. Functional description  
Table 4. Function table  
H = HIGH voltage level; L = LOW voltage level.  
Input  
nA  
L
Output  
nY  
L
H
H
©
74HC3G16  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 17 April 2019  
2 / 9  
 
 
 
 
 
Nexperia  
74HC3G16  
Triple buffer gate  
8. Limiting values  
Table 5. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Max  
+7.0  
±20  
±20  
±25  
50  
Unit  
V
VCC  
IIK  
supply voltage  
-0.5  
input clamping current  
output clamping current  
output current  
VI < -0.5 V or VI > VCC + 0.5 V  
VO < -0.5 V or VO > VCC + 0.5 V  
VO = -0.5 V to (VCC + 0.5 V)  
[1]  
[1]  
-
mA  
mA  
mA  
mA  
mA  
°C  
IOK  
IO  
-
-
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
ground current  
-50  
-65  
-
-
storage temperature  
total power dissipation  
+150  
300  
Tamb = -40 °C to +125 °C  
[2]  
mW  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.  
9. Recommended operating conditions  
Table 6. Recommended operating conditions  
Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
6.0  
Unit  
V
VCC  
VI  
supply voltage  
2.0  
5.0  
input voltage  
0
0
-
VCC  
VCC  
+125  
625  
139  
83  
V
VO  
output voltage  
-
+25  
-
V
Tamb  
Δt/ΔV  
ambient temperature  
input transition rise and fall rate  
-40  
-
°C  
VCC = 2.0 V  
VCC = 4.5 V  
VCC = 6.0 V  
ns/V  
ns/V  
ns/V  
-
1.67  
-
-
10. Static characteristics  
Table 7. Static characteristics  
Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
-40 °C to +125 °C Unit  
Min  
Typ [1] Max  
Min  
1.5  
3.15  
4.2  
-
Max  
-
VIH  
HIGH-level input voltage VCC = 2.0 V  
VCC = 4.5 V  
1.5  
1.2  
2.4  
3.2  
0.8  
2.1  
2.8  
-
-
V
V
V
V
V
V
3.15  
-
VCC = 6.0 V  
4.2  
-
-
VIL  
LOW-level input voltage VCC = 2.0 V  
VCC = 4.5 V  
-
-
-
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
-
VCC = 6.0 V  
-
©
74HC3G16  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 17 April 2019  
3 / 9  
 
 
 
 
Nexperia  
74HC3G16  
Triple buffer gate  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
Min Typ [1] Max  
-40 °C to +125 °C Unit  
Min  
Max  
VOH  
HIGH-level output  
VI = VIH or VIL  
voltage  
IO = -20 μA; VCC = 2.0 V  
1.9  
4.4  
2.0  
4.5  
-
-
-
-
-
1.9  
4.4  
5.9  
3.7  
5.2  
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V  
IO = -20 μA; VCC = 6.0 V  
IO = -4.0 mA; VCC = 4.5 V  
IO = -5.2 mA; VCC = 6.0 V  
5.9  
6.0  
4.13  
5.63  
4.32  
5.81  
VOL  
LOW-level output  
voltage  
VI = VIH or VIL  
IO = 20 μA; VCC = 2.0 V  
IO = 20 μA; VCC = 4.5 V  
IO = 20 μA; VCC = 6.0 V  
IO = 4.0 mA; VCC = 4.5 V  
IO = 5.2 mA; VCC = 6.0 V  
VI = VCC or GND; VCC = 6.0 V  
-
-
-
-
-
-
-
0
0.1  
0.1  
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
0.4  
0.4  
±1.0  
20  
V
0
V
0
0.15  
0.16  
-
0.1  
V
0.33  
0.33  
±1.0  
10  
V
V
II  
input leakage current  
supply current  
μA  
μA  
ICC  
per input pin; VI = VCC or GND;  
IO = 0 A; VCC = 6.0 V  
-
CI  
input capacitance  
-
1.5  
-
-
-
pF  
[1] All typical values are measured at Tamb = 25 °C.  
11. Dynamic characteristics  
Table 8. Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 5.  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
Typ [1]  
-40 °C to +125 °C Unit  
Min  
Max  
Min  
Max  
tpd  
propagation delay nA to nY; see Fig. 4  
[2]  
[3]  
[4]  
VCC = 2.0 V  
VCC = 4.5 V  
VCC = 6.0 V  
-
-
-
29  
9
95  
19  
16  
-
-
-
125  
25  
ns  
ns  
ns  
8
20  
tt  
transition time  
nY; see Fig. 4  
VCC = 2.0 V  
VCC = 4.5 V  
VCC = 6.0 V  
-
-
-
-
18  
6
95  
19  
16  
-
-
-
-
-
125  
25  
20  
-
ns  
ns  
ns  
pF  
5
CPD  
power dissipation VI = GND to VCC  
capacitance  
10  
[1] All typical values are measured at Tamb = 25 °C.  
[2] tpd is the same as tPLH and tPHL  
[3] tt is the same as tTLH and tTHL  
.
.
[4] CPD is used to determine the dynamic power dissipation (PD in μW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ(CL × VCC2 × fo) = sum of outputs.  
©
74HC3G16  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 17 April 2019  
4 / 9  
 
 
Nexperia  
74HC3G16  
Triple buffer gate  
11.1. Waveforms and test circuit  
V
I
input  
nA  
V
V
M
M
GND  
t
t
PHL  
PLH  
V
OH  
90 %  
output  
nY  
V
V
M
M
10 %  
V
OL  
t
t
TLH  
THL  
001aad982  
Measurement points are given in Table 9.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig. 4. Propagation delay data input (nA) to data output (nY) and transition time output (nY)  
Table 9. Measurement points  
Input  
VM  
Output  
VM  
0.5 × VCC  
0.5 × VCC  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
0 V  
t
W
V
V
CC  
CC  
V
I
V
O
R
L
S1  
G
open  
DUT  
R
T
C
L
001aad983  
Test data is given in Table 10.  
Definitions for test circuit:  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator;  
CL = Load capacitance including jig and probe capacitance;  
RL = Load resistance; S1 = Test selection switch.  
Fig. 5. Test circuit for measuring switching times  
Table 10. Test data  
Input  
Load  
CL  
S1 position  
VI  
tr, tf  
RL  
tPHL, tPLH  
GND to VCC  
≤ 6 ns  
50 pF  
1 kΩ  
open  
©
74HC3G16  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 17 April 2019  
5 / 9  
 
 
 
 
 
Nexperia  
74HC3G16  
Triple buffer gate  
12. Package outline  
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm  
SOT505-2  
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
detail X  
1
4
e
w
M
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT  
v
w
y
Z
θ
1
2
3
p
max.  
0.15  
0.00  
0.95  
0.75  
0.38  
0.22  
0.18  
0.08  
3.1  
2.9  
3.1  
2.9  
4.1  
3.9  
0.47  
0.33  
0.70  
0.35  
8°  
0°  
mm  
1.1  
0.65  
0.5  
0.2  
0.13  
0.1  
0.25  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
02-01-16  
SOT505-2  
- - -  
Fig. 6. Package outline SOT505-2 (TSSOP8)  
©
74HC3G16  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 17 April 2019  
6 / 9  
 
Nexperia  
74HC3G16  
Triple buffer gate  
13. Abbreviations  
Table 11. Abbreviations  
Acronym  
Description  
CMOS  
DUT  
ESD  
HBM  
MM  
Complementary Metal-Oxide Semiconductor  
Device Under Test  
ElectroStatic Discharge  
Human Body Model  
Machine Model  
14. Revision history  
Table 12. Revision history  
Document ID  
74HC3G16 v.3  
Modifications:  
Release date  
20190417  
Data sheet status  
Change notice Supersedes  
- 74HC_HCT3G16 v.2  
Product data sheet  
The format of this data sheet has been redesigned to comply with the identity guidelines  
of Nexperia.  
Legal texts have been adapted to the new company name where appropriate.  
Type number 74HCT3G16DP (SOT505-2) removed.  
Type numbers 74HC3G16GD and 74HCT3G16GD (SOT996-2) removed.  
74HC_HCT3G16 v.2  
Modifications:  
20161007  
Type numbers 74HCT3G16DC and 74HCT3G16DC removed.  
20151015 Product data sheet  
Product data sheet  
-
74HC_HCT3G16 v.1  
74HC_HCT3G16 v.1  
-
-
©
74HC3G16  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 17 April 2019  
7 / 9  
 
 
Nexperia  
74HC3G16  
Triple buffer gate  
injury, death or severe property or environmental damage. Nexperia and its  
suppliers accept no liability for inclusion and/or use of Nexperia products in  
such equipment or applications and therefore such inclusion and/or use is at  
the customer’s own risk.  
15. Legal information  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Data sheet status  
Document status Product  
Definition  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. Nexperia makes no representation  
or warranty that such applications will be suitable for the specified use  
without further testing or modification.  
[1][2]  
status [3]  
Objective [short]  
data sheet  
Development  
This document contains data from  
the objective specification for  
product development.  
Customers are responsible for the design and operation of their applications  
and products using Nexperia products, and Nexperia accepts no liability for  
any assistance with applications or customer product design. It is customer’s  
sole responsibility to determine whether the Nexperia product is suitable  
and fit for the customer’s applications and products planned, as well as  
for the planned application and use of customer’s third party customer(s).  
Customers should provide appropriate design and operating safeguards to  
minimize the risks associated with their applications and products.  
Preliminary [short]  
data sheet  
Qualification  
Production  
This document contains data from  
the preliminary specification.  
Product [short]  
data sheet  
This document contains the product  
specification.  
[1] Please consult the most recently issued document before initiating or  
completing a design.  
Nexperia does not accept any liability related to any default, damage, costs  
or problem which is based on any weakness or default in the customer’s  
applications or products, or the application or use by customer’s third party  
customer(s). Customer is responsible for doing all necessary testing for the  
customer’s applications and products using Nexperia products in order to  
avoid a default of the applications and the products or of the application or  
use by customer’s third party customer(s). Nexperia does not accept any  
liability in this respect.  
[2] The term 'short data sheet' is explained in section "Definitions".  
[3] The product status of device(s) described in this document may have  
changed since this document was published and may differ in case of  
multiple devices. The latest product status information is available on  
the internet at https://www.nexperia.com.  
Definitions  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those  
given in the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. Nexperia does not give any representations or  
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with the same product type number(s) and title. A short data sheet is  
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full data sheet, which is available on request via the local Nexperia sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
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data sheet shall define the specification of the product as agreed between  
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systems or equipment, nor in applications where failure or malfunction  
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©
74HC3G16  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 17 April 2019  
8 / 9  
 
Nexperia  
74HC3G16  
Triple buffer gate  
Contents  
1. General description......................................................1  
2. Features and benefits.................................................. 1  
3. Ordering information....................................................1  
4. Marking..........................................................................1  
5. Functional diagram.......................................................2  
6. Pinning information......................................................2  
6.1. Pinning.........................................................................2  
6.2. Pin description.............................................................2  
7. Functional description................................................. 2  
8. Limiting values............................................................. 3  
9. Recommended operating conditions..........................3  
10. Static characteristics..................................................3  
11. Dynamic characteristics.............................................4  
11.1. Waveforms and test circuit........................................ 5  
12. Package outline.......................................................... 6  
13. Abbreviations..............................................................7  
14. Revision history..........................................................7  
15. Legal information........................................................8  
© Nexperia B.V. 2019. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 17 April 2019  
©
74HC3G16  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 17 April 2019  
9 / 9  

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NXP

74HC3G34DP-Q100H

74HC(T)3G34-Q100 - Dual non-inverting Schmitt trigger TSSOP 8-Pin
NXP

74HC3G34GD

Triple buffer gate
NXP