74HC4046APW-Q100 [NEXPERIA]
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74HC4046A-Q100
Phase-locked loop with VCO
Rev. 2 — 8 June 2023
Product data sheet
1. General description
The 74HC4046A-Q100 is a high-speed Si-gate CMOS device. It is specified in compliance with
JEDEC standard no 7A.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
Low power consumption
VCO-Inhibit control for ON/OFF keying and for low standby power consumption
Center frequency up to 17 MHz (typical) at VCC = 4.5 V
Choice of three phase comparators:
•
•
•
PC1: EXCLUSIVE-OR
PC2: Edge-triggered J-K flip-flop
PC3: Edge-triggered RS flip-flop
•
•
•
Excellent Voltage Controlled Oscillator (VCO) linearity
Low frequency drift with supply voltage and temperature variations
Operating power supply voltage range:
•
•
VCO section 3.0 V to 6.0 V
Digital section 2.0 V to 6.0 V
•
•
Zero voltage offset due to operational amplifier buffering
ESD protection:
•
•
HBM: ANSI/ESDA/Jedec JS-001 Class 2 exceeds 2 kV
CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1 kV
3. Applications
•
•
•
•
•
•
•
FM modulation and demodulation
Frequency synthesis and multiplication
Frequency discrimination
Tone decoding
Data synchronization and conditioning
Voltage-to-frequency conversion
Motor-speed control
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
Version
74HC4046APW-Q100
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
5. Block diagram
C1
6
7
4
3
14
C1A
C1B
VCO_OUT
COMP_IN SIG_IN
4046A
PHASE
COMPARATOR
1
PC1_OUT 2
R2 12
R2
VCO
PC2_OUT 13
PCP_OUT 1
PHASE
COMPARATOR
2
R3
R1 11
R1
R4
C2
PHASE
COMPARATOR
3
PC3_OUT 15
5
10
9
INH
DEM_OUT VCO_IN
R
S
aaa-020201
Fig. 1. Block diagram
6. Functional diagram
2
PC1_OUT
PC3_OUT
PC2_OUT
PCP_OUT
COMP_IN
SIG_IN
3
15
13
1
Ø
2
13
15
1
PC1_OUT
14
SIG_IN
COMP_IN
C1A
14
3
PC2_OUT
PC3_OUT
PCP_OUT
C1A
C1B
6
6
7
C1B
7
4046A
4
VCO_OUT
R1
11
12
9
R1
11
12
9
∏
#
VCO
10
4
DEM_OUT
VCO_OUT
aaa-020203
R2
R2
10
DEM_OUT
∏
#
VCO_IN
INH
VCO_IN
INH
5
5
aaa-020202
Fig. 2. Logic symbol
Fig. 3. IEC logic symbol
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74HC4046A_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
2 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
C1
6
7
4
3
14
C1A C1B VCO_OUT COMP_IN SIG_IN
PC1_OUT
2
V
ref
R2 12
R2
VCO
S
D
Q
PC3_OUT 15
R1 11
R1
Q
D
R
DEM_OUT 10
V
CC
P
UP
`1'
`1'
D
Q
Q
CP
R
R
S
R3
13 PC2_OUT
D
N
R4
C2
D
Q
Q
GND
CP
DOWN
1
PCP_OUT
R
D
5
9
INH
VCO_IN
aaa-020204
Fig. 4. Logic diagram
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74HC4046A_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
3 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
7. Pinning information
7.1. Pinning
PW package
SOT403-1 (TSSOP16)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PCP_OUT
V
CC
PC1_OUT
COMP_IN
VCO_OUT
INH
PC3_OUT
SIG_IN
PC2_OUT
R2
C1A
R1
C1B
DEM_OUT
VCO_IN
GND
aaa-035384
7.2. Pin description
Table 2. Pin description
Symbol
Pin
1
Description
PCP_OUT
PC1_OUT
COMP_IN
VCO_OUT
INH
phase comparator pulse output
phase comparator 1 output
comparator input
2
3
4
VCO output
5
inhibit input
C1A
6
capacitor C1 connection A
capacitor C1 connection B
ground (0 V)
C1B
7
GND
8
VCO_IN
DEM_OUT
R1
9
VCO input
10
11
12
13
14
15
16
demodulator output
resistor R1 connection
resistor R2 connection
phase comparator 2 output
signal input
R2
PC2_OUT
SIG_IN
PC3_OUT
VCC
phase comparator 3 output
supply voltage
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74HC4046A_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
4 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
8. Functional description
The 74HC4046A-Q100 is a phase-locked-loop circuit that comprises a linear VCO and three
different phase comparators (PC1, PC2 and PC3). It has a common signal input amplifier and a
common comparator input (see Fig. 1). The signal input can be directly coupled to a large voltage
signal, or indirectly coupled (with a series capacitor) to a small voltage signal. A self-bias input
circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive
low-pass filter, the 74HC4046A-Q100 forms a second-order loop PLL. The excellent VCO linearity
is achieved by the use of linear op amp techniques.
8.1. VCO
The VCO requires one external capacitor C1 (between pins C1A and C1B) and one external
resistor R1 (between pins R1 and GND). Alternatively, it requires two external resistors R1 and
R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the
frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if necessary
(see Fig. 4).
The high input impedance of the VCO simplifies the design of the low-pass filters by giving
the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter,
a demodulator output of the VCO input voltage is provided at pin DEM_OUT. In contrast to
conventional techniques, where the DEM_OUT voltage is one threshold voltage lower than the
VCO input voltage, the DEM_OUT voltage equals the VCO input. If DEM_OUT is used, a series
resistor (Rs) should be connected from pin DEM_OUT to GND. If unused, DEM_OUT should be
left open. The VCO output (pin VCO_OUT) can be connected directly to the comparator input (pin
COMP_IN) or connected via a frequency divider. When the VCO input DC level is held constant,
the VCO output signal has a duty cycle of 50 % (maximum expected deviation 1 %). A LOW-level
at the inhibit input (pin INH) enables the VCO and demodulator, while a HIGH-level turns off both to
minimize standby power consumption.
8.2. Phase comparators
The input signal can be coupled to the self-biasing amplifier at pin SIG_IN, when the signal swing is
between the standard HC family input logic levels. Capacitive coupling is required for signals with
smaller swings.
8.2.1. Phase Comparator 1 (PC1)
This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must
have a 50 % duty cycle to obtain the maximum locking range. The transfer characteristic of PC1,
assuming ripple (fr = 2fi) is suppressed, is:
where:
•
•
VDEM_OUT is the demodulator output at pin DEM_OUT
VDEM_OUT = VPC1_OUT (via low-pass filter)
The phase comparator gain is:
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74HC4046A_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
5 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
PC1 is fed to the VCO input via the low-pass filter and provided at the demodulator output at pin
DEM_OUT (VDEM_OUT). The average output voltage from PC1 is the result of the phase differences
of signals (SIG_IN) and the comparator input (COMP_IN). These phase differences are shown in
Fig. 5. The average of VDEM_OUT is equal to 0.5VCC when no signal or noise is present at SIG_IN.
Using this input, the VCO oscillates at the center frequency (f0). Typical waveforms for the PC1
loop locked at f0 are shown in Fig. 6.
The frequency capture range (2fc) is defined as the frequency range of input signals on which the
PLL locks when it was initially out-of-lock. The frequency lock range (2fL) is the frequency range of
the input signals on which the loop stays locked when it was initially in lock. The capture range is
smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter characteristics and can be made as
large as the lock range. This configuration remains locked even with very noisy input signals.
Typical behavior of this type of phase comparator is that it can lock to input frequencies close to the
harmonics of the VCO center frequency.
V
CC
V
DEM_OUT
(V)
1/2 V
CC
0
0
π/2
π
Ø
DEM_OUT(rad)
aaa-020206
Fig. 5. Phase comparator 1; average output voltage as a function of input phase
difference
SIG_IN
COMP_IN
VCO_OUT
PC1_OUT
V
CC
VCO_IN
GND
aaa-020207
Fig. 6. Typical waveforms for PLL using phase comparator 1; loop-locked at f0
©
74HC4046A_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
6 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
8.2.2. Phase Comparator 2 (PC2)
PC2 is a positive edge-triggered phase and frequency detector. When the PLL uses this
comparator, positive signal transitions control the loop and the duty cycles of SIG_IN and
COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state
output stage. The circuit functions as an up-down counter (see Fig. 4) where SIG_IN causes an
up-count and COMP_IN a down count. The transfer function of PC2, assuming ripple (fr = fi) is
suppressed, is:
where:
•
•
VDEM_OUT is the demodulator output at pin DEM_OUT
VDEM_OUT = VPC2_OUT (via low-pass filter)
The phase comparator gain is:
VDEM_OUT is the resultant of the initial phase differences of SIG_IN and COMP_IN as shown
in Fig. 7. Typical waveforms for the PC2 loop locked at fo are shown in Fig. 8.
When the SIG_IN and COMP_IN frequencies are equal but the phase of SIG_IN leads that
of COMP_IN, the p-type output driver at PC2_OUT is held ‘ON’. The time that it is held 'ON’
corresponds with the phase difference (ΦDEM_OUT). When the phase of SIG_IN lags that of
COMP_IN, the n-type driver is held ‘ON’.
When the SIG_IN frequency is higher than the COMP_IN frequency, the p-type output driver is
held ‘ON’ for most of the input signal cycle time. For the remainder of the cycle time, both n- and
p-type drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN frequency,
the n-type driver is held ‘ON’ for most of the cycle. The voltage at capacitor (C2) of the low-pass
filter, connected to PC2_OUT, varies until the phase and frequency of the signal and comparator
inputs are equal. At this stable point, the voltage on C2 remains constant as the PC2 output is
in 3-state and the VCO_IN input is in a high-impedance state. In this condition, the signal at the
phase comparator pulse output (PCP_OUT) is a HIGH level and can be used for indicating a
locked condition.
Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full frequency
range of the VCO. The power dissipation due to the low-pass filter is reduced because both n- and
p-type output drivers are ‘OFF’ for most of the signal input cycle. The PLL lock range for this type of
phase comparator is equal to the capture range and is independent of the low-pass filter. With no
signal present at SIG_IN the VCO adjust, via PC2, to its lowest frequency.
©
74HC4046A_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
7 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
V
CC
V
DEM_OUT
(V)
1/2 V
CC
0
-2π
0
2π
Ø
DEM_OUT(rad)
aaa-020208
Fig. 7. Phase comparator 2; average output voltage as a function of input phase
difference
SIG_IN
COMP_IN
VCO_OUT
V
CC
PC2_OUT
high impedance OFF - state
GND
VCO_IN
PCP_OUT
aaa-020209
Fig. 8. Typical waveforms for PLL using phase comparator 2; loop-locked at f0
8.2.3. Phase Comparator 3 (PC3)
PC3 is a positive edge-triggered sequential phase detector using an RS-type flip-flop. When the
PLL is using this comparator, positive signal transitions control the loop and the duty factors of
SIG_IN and COMP_IN are not important. The transfer characteristic of PC3, assuming ripple
(fr = fi) is suppressed, is:
where:
•
•
VDEM_OUT is the demodulator output at pin DEM_OUT
VDEM_OUT = VPC3_OUT (via low-pass filter)
The phase comparator gain is:
©
74HC4046A_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
8 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
PC3 is fed to the VCO via the low-pass filter and present at the demodulator output at pin
DEM_OUT. The average output from PC3 is the resultant of the phase differences of SIG_IN and
COMP_IN, see Fig. 9. Typical waveforms for the PC3 loop locked at fo are shown in Fig. 10.
The phase-to-output response characteristic of PC3 (Fig. 9) differs from PC2 in that the phase
angle between SIG_IN and COMP_IN varies between 0° and 360°. It is 180° at the center
frequency. Also PC3 gives a greater voltage swing than PC2 for input phase differences. As a
result, the ripple content of the VCO input signal is higher. The PLL lock range for this type of
phase comparator and the capture range are dependent on the low-pass filter. With no signal
present at SIG_IN, the VCO adjusts to its lowest frequency via PC3.
V
CC
V
DEM_OUT
(V)
1/2 V
CC
0
0
π
2π
aaa-020210
Ø
DEM_OUT(rad)
Fig. 9. Phase comparator 3; average output voltage as a function of input phase
difference
SIG_IN
COMP_IN
VCO_OUT
PC3_OUT
V
CC
VCO_IN
GND
aaa-020211
Fig. 10. Typical waveforms for PLL using phase comparator 3; loop-locked at f0
©
74HC4046A_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
9 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
9. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7
Unit
V
VCC
IIK
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
-0.5 V < VO < VCC + 0.5 V
-
±20
±20
±25
+50
-
mA
mA
mA
mA
mA
°C
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[1]
mW
[1] For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
10. Recommended operating conditions
Table 4. Recommended operating conditions
Symbol Parameter
Conditions
Min
3.0
2.0
0
Typ
5.0
5.0
-
Max
6.0
Unit
V
VCC
supply voltage
when VCO is not used
6.0
V
VI
input voltage
VCC
VCC
V
VO
output voltage
0
-
V
Δt/ΔV
input transition rise and
fall rate
pin INH
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
625
139
83
ns/V
ns/V
ns/V
°C
1.67
-
-
Tamb
ambient temperature
-40
+25
+125
©
74HC4046A_Q100
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
10 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
11. Static characteristics
Table 5. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to Unit
+125 °C
Min Typ Max Min Max Min Max
Phase comparator section
VIH
HIGH-level
input voltage
SIG_IN, COMP_IN; DC coupled
VCC = 2.0 V
1.5 1.2
3.15 2.4
4.2 3.2
-
-
-
1.5
3.15
4.2
-
-
-
1.5
3.15
4.2
-
-
-
V
V
V
VCC = 4.5 V
VCC = 6.0 V
VIL
LOW-level
input voltage
SIG_IN, COMP_IN; DC coupled
VCC = 2.0 V
-
-
-
0.8 0.5
2.1 1.35
2.8 1.8
-
-
-
0.5
1.35
1.8
-
-
-
0.5
V
VCC = 4.5 V
1.35 V
VCC = 6.0 V
1.8
V
VOH
HIGH-level
output voltage
PCP_OUT, PCn_OUT; VI = VIH or VIL
IO = -20 μA; VCC = 2.0 V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -4 mA; VCC = 4.5 V
IO = -5.2 mA; VCC = 6.0 V
PCP_OUT, PCn_OUT; VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
SIG_IN, COMP_IN; VI = VCC or GND
VCC = 2.0 V
1.9 2.0
4.4 4.5
5.9 6.0
3.98 4.32
5.48 5.81
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
3.84
5.34
VOL
LOW-level
output voltage
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
0.1
0.15 0.26
0.16 0.26
0.33
0.33
II
input leakage
current
-
-
-
-
-
-
-
-
±3
±7
-
-
-
-
±4
±9
-
-
-
-
±5 μA
±11 μA
±27 μA
±45 μA
VCC = 3.0 V
VCC = 4.5 V
±18
±30
±23
±38
VCC = 6.0 V
IOZ
OFF-state
PC2_OUT; VI = VIH or VIL;
output current VO = VCC or GND
VCC = 6.0 V
-
-
±0.5
-
±5
-
±10 μA
RI
input
SIG_IN, COMP_IN;
resistance
VI at self-bias operating point; ΔVI = 0.5 V;
see Fig. 11, Fig. 12 and Fig. 13
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
800
250
150
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
kΩ
kΩ
kΩ
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Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 2 — 8 June 2023
11 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to Unit
+125 °C
Min Typ Max Min Max Min Max
VCO section
VIH
HIGH-level
INH
input voltage
VCC = 3.0 V
2.1 1.7
3.15 2.4
4.2 3.2
-
-
-
2.1
3.15
4.2
-
-
-
2.1
3.15
4.2
-
-
-
V
V
V
VCC = 4.5 V
VCC = 6.0 V
VIL
LOW-level
INH
input voltage
VCC = 3.0 V
-
-
-
1.3 0.9
2.1 1.35
2.8 1.8
-
-
-
0.9
1.35
1.8
-
-
-
0.9
V
VCC = 4.5 V
1.35 V
VCC = 6.0 V
1.8
V
VOH
HIGH-level
output voltage
VCO_OUT; VI = VIH or VIL
IO = -20 μA; VCC = 3.0 V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -4 mA; VCC = 4.5 V
IO = -5.2 mA; VCC = 6.0 V
VCO_OUT; VI = VIH or VIL
IO = 20 μA; VCC = 3.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
C1A, C1B; VI = VIH or VIL
IO = 4 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
INH, VCO_IN; VI = VCC or GND
VCC = 6.0 V
2.9 3.0
4.4 4.5
5.9 6.0
3.98 4.32
5.48 5.81
-
-
-
-
-
2.9
4.4
-
-
-
-
-
2.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
3.84
5.34
VOL
LOW-level
output voltage
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
0.1
0.15 0.26
0.16 0.26
0.33
0.33
-
-
-
-
0.40
0.40
-
-
0.47
0.47
-
-
0.54 V
0.54 V
II
input leakage
current
-
3
-
-
-
-
±0.1
300
300
-
-
-
-
±1
-
-
-
-
-
±1 μA
R1
R2
C1
resistor 1
resistor 2
capacitor 1
VCC = 3.0 V to 6.0 V
VCC = 3.0 V to 6.0 V
VCC = 3.0 V to 6.0 V
[1]
[1]
-
-
-
kΩ
kΩ
pF
3
-
40
no
-
limit
VVCO_IN input voltage
VCO_IN; over the range specified for R1;
on pin VCO_IN for linearity see Fig. 21 and Fig. 22
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
1.1
1.1
1.1
-
-
-
1.9
3.4
4.9
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
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Product data sheet
Rev. 2 — 8 June 2023
12 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to Unit
+125 °C
Min Typ Max Min Max Min Max
Demodulator section
Rs
series
resistance
at Rs > 300 kΩ, the leakage current can
influence VDEM_OUT
VCC = 3.0 V to 6.0 V
50
-
300
-
-
-
-
kΩ
Voffset
offset voltage
VCO_IN to DEM_OUT;
VI = VVCO_IN = 0.5VCC
;
values taken over Rs range; see Fig. 14
VCC = 3.0 V
-
-
-
±30
±20
±10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mV
mV
mV
VCC = 4.5 V
VCC = 6.0 V
Rdyn
dynamic
resistance
DEM_OUT; VDEM_OUT = 0.5VCC
VCC = 3.0 V to 6.0 V
-
25
-
-
-
-
-
Ω
General
ICC
supply current VCO disabled; COMP_IN, INH and
SIG_IN at VCC; VCO_IN at GND; II at pins
COMP_IN and SIGN_IN to be excluded
VCC = 6.0 V
-
-
-
8
-
-
-
80
-
-
-
160 μA
pF
CI
input
INH
3.5
-
capacitance
[1] The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2 are/is > 10 kΩ.
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Nexperia B.V. 2023. All rights reserved
Product data sheet
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13 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
11.1. Graphs
aaa-020213
800
I
I
(µA)
R
I
(kΩ)
V
I
V
= 3.0 V
CC
600
400
200
0
4.5 V
6.0 V
self-bias operating point
0
V
(V)
I
1/2 V
-0.25
1/2 V
1/2 V
+0.25
CC
CC
CC
V (V)
I
aaa-020212
Fig. 11. Typical input resistance curve at SIG_IN and
COMP_IN
Fig. 12. Input resistance at SIG_IN, COMP_IN with
ΔVI = 0.5 V at self-bias point
aaa-020215
+60
V
offset
(mV)
aaa-020214
+5
+40
V
= 6.0 V
CC
I
I
(µA)
V
= 3.0 V
CC
4.5 V
3.0 V
+20
0
4.5 V
0
3.0 V
6.0 V
-20
-40
4.5 V
6.0 V
1/2 V
-2
1/2 V
1/2 V
(V)
+2
CC
CC
CC
V
VCO_IN
-5
1/2 V
___ Rs = 50 kΩ
- - - Rs = 300 kΩ
-0.25
1/2 V
1/2 V
+0.25
CC
CC
CC
V (V)
I
Fig. 13. Input current at SIG_IN, COMP_IN with
ΔVI = 0.5 V at self-bias point
Fig. 14. Offset voltage at demodulator output as
a function of VVCO_IN and Rs
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Product data sheet
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14 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
12. Dynamic characteristics
Table 6. Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to Unit
+125 °C
Min Typ Max Min Typ Max Min Max
Phase comparator section
tpd
propagation SIG_IN, COMP_IN to PC1_OUT;
delay see Fig. 15
[1]
[1]
[1]
[1]
[1]
[1]
VCC = 2.0 V
-
-
-
63 200
-
-
-
-
-
-
250
50
-
-
-
300 ns
60 ns
51 ns
VCC = 4.5 V
VCC = 6.0 V
23
18
40
34
43
SIG_IN, COMP_IN to PCP_OUT;
see Fig. 15
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
96 340
-
-
-
-
-
-
425
85
-
-
-
510 ns
102 ns
87 ns
35
28
68
58
72
SIG_IN, COMP_IN to PC3_OUT;
see Fig. 15
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
77 270
-
-
-
-
-
-
340
68
-
-
-
405 ns
81 ns
69 ns
28
22
54
46
58
ten
enable time SIG_IN, COMP_IN to PC2_OUT;
see Fig. 16
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
83 280
-
-
-
-
-
-
350
70
-
-
-
420 ns
84 ns
71 ns
30
24
56
48
60
tdis
disable time SIG_IN, COMP_IN to PC2_OUT;
see Fig. 16
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
99 325
-
-
-
-
-
-
405
81
-
-
-
490 ns
98 ns
83 ns
36
29
65
55
69
tt
transition
time
PC1_OUT, PC3_OUT, PCP_OUT;
see Fig. 15
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
19
7
75
15
13
-
-
-
-
-
-
95
19
16
-
-
-
110 ns
22 ns
19 ns
6
Vi(p-p)
peak-to-peak SIGN_IN, COMP_IN; AC coupled;
input voltage fi = 1 MHz
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mV
11
15
33
mV
mV
mV
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to Unit
+125 °C
Min Typ Max Min Typ Max Min Max
VCO section
f0
center
frequency
VVCO_IN = 0.5VCC; duty cycle = 50 %;
R1 = 3 kΩ; R2 = ∞ Ω; C1 = 40 pF;
see Fig. 19 and Fig. 20
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 6.0 V
7.0 10.0
11.0 17.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
-
19.0
13.0 21.0
Δf/f
relative
frequency
variation
R1 = 100 kΩ; R2 = ∞ Ω; C1 = 100 pF;
see Fig. 21 and Fig. 22
VCC = 3.0 V
-
-
-
1.0
0.4
0.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
%
%
%
VCC = 4.5 V
VCC = 6.0 V
Δf/ΔT
frequency
VVCO_IN = 0.5VCC; R1 = 100 kΩ;
variation with R2 = ∞ Ω; C1 = 100 pF;
temperature see Fig. 17 and Fig. 18
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.20
0.15
0.14
-
-
-
-
-
-
-
-
-
-
-
-
-
%/K
%/K
%/K
%
-
δ
duty cycle
VCO_OUT; VCC = 3.0 V to 6.0 V
50
General
CPD
power
dissipation
capacitance
[2]
[3]
-
24
-
-
-
-
-
-
pF
[1] tpd is the same as tPLH and tPHL. tdis is the same as tPLZ and tPHZ. ten is the same as tPZL and tPZH. tt is the same as tTLH and tTHL
.
[2] Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator sections, see
Fig. 23, Fig. 24 and Fig. 25
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
Σ(CL x VCC 2 x fo) = sum of outputs.
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Product data sheet
Rev. 2 — 8 June 2023
16 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
12.1. Waveforms and graphs
V
I
SIG_IN
COMP_IN
V
V
M
M
GND
t
t
PLH
PHL
V
OH
PC1_OUT
PC3_OUT
PCP_OUT
V
V
M
M
V
OL
t
t
TLH
THL
aaa-020216
VM = 0.5VCC; VI = GND to VCC
.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 15. Waveforms showing input (SIG_IN, COMP_IN) to output (PC1_OUT, PC3_OUT, PCP_OUT) propagation
delays and the output transition times
V
V
I
I
SIG_IN
SIG_IN
V
V
M
M
GND
GND
V
V
I
I
COMP_IN
V
COMP_IN
V
M
M
GND
GND
t
t
PZL
PZH
t
t
PLZ
PHZ
V
V
OH
OH
90 %
V
V
M
PC2_OUT
PC2_OUT
M
10 %
V
V
OL
OL
aaa-020218
VM = 0.5VCC; VI = GND to VCC
.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 16. Waveforms showing the enable and disable times for PC2_OUT
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
25
f
25
f
25
f
(%)
(%)
(%)
V
= 3 V
V
= 3 V
CC
3 V
5 V
CC
20
15
10
5
20
15
10
5
20
15
10
5
6 V
V
= 6 V
5 V
CC
5 V
6 V
3 V
A
5 V
6 V
5 V
6 V
3 V
0
0
0
3 V
4.5 V
5 V
6 V
-5
-5
-5
-10
-15
-20
-10
-15
-20
-25
-10
-15
-20
-25
-25
-50
0
50
(a)
100
150
(°C)
-50
0
50
(b)
100
150
(°C)
-50
0
50
(c)
100
150
(°C)
T
T
T
amb
amb
amb
aaa-020259
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
In (b), the frequency stability for R1 = R2 = 10 kΩ at 5 V is also given (curve A). The total VCO bias current
sets this curve, and is not simply the addition of the two 10 kΩ stability curves. C1 = 100 pF; VVCO_IN = 0.5VCC
This curve is set as follows:
;
___ Without offset R2 = ∞ Ω: (a) R1 = 3 kΩ; (b) R1 = 10 kΩ; (c) R1 = 300 kΩ.
- - - With offset R1 = ∞ Ω: (a) R2 = 3 kΩ; (b) R2 = 10 kΩ; (c) R2 = 300 kΩ.
Fig. 17. Frequency stability of the VCO as a function of ambient temperature
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18 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
25
f
25
f
25
f
(%)
(%)
(%)
V
= 3 V
V
= 3 V
CC
CC
20
15
10
5
20
15
10
5
20
15
10
5
V
= 6 V
5 V
CC
5 V
6 V
5 V
6 V
3 V
0
0
0
-5
-5
-5
-10
-15
-20
-10
-15
-20
-25
-10
-15
-20
-25
-25
-50
0
50
(a)
100
150
(°C)
-50
0
50
(b)
100
150
(°C)
-50
0
50
(c)
100
150
(°C)
T
T
T
amb
amb
amb
aaa-020362
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
___ With offset; R1 = ∞ Ω: (a) R2 = 3 kΩ; (b) R2 = 10 kΩ; (c) R2 = 300 kΩ.
Fig. 18. Frequency stability of the VCO as a function of ambient temperature
30
80
f
VCO
V
= 6 V
CC
(MHz)
f
VCO
(kHz)
V
= 6 V
CC
25
4.5 V
60
20
15
10
5
4.5 V
3 V
40
20
0
3 V
0
0
2
4
6
0
2
4
6
V
(V)
V
(V)
VCO_IN
VCO_IN
(a)
(b)
aaa-020363
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
(a) R1 = 3 kΩ; C1 = 40 pF (b) R1 = 3 kΩ; C1 = 100 nF
Fig. 19. Graphs showing VCO frequency as a function of the VCO input voltage
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Product data sheet
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19 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
1000
500
V
= 6 V
CC
f
f
VCO
VCO
(Hz)
(kHz)
V
= 6 V
CC
800
600
400
200
0
400
300
200
100
0
4.5 V
4.5 V
3 V
3 V
0
2
4
6
0
2
4
6
V
(V)
V
(V)
VCO_IN
VCO_IN
(a)
(b)
aaa-020364
To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.
(a) R1 = 300 kΩ; C1 = 40 pF (b) R1 = 300 kΩ; C1 = 100 nF
Fig. 20. Graphs showing VCO frequency as a function of the VCO input voltage
10
V
= 3 V
CC
f
VCO
(%)
C1 = 1 µF
5
f
4.5 V
6 V
f
2
f
0
f
0'
V
= 4.5 V
CC
C1 = 100 pF
f
1
0
6 V
V
V
4.5 V
0
C1 = 40 pF
min
1/2 V
max
V
VCO_IN
CC
aaa-020365
ΔV = 0.5 V over the VCC range.
3 V
-5
2
3
1
10
10
10
R1 (kΩ)
aaa-020367
linearity =
R2 = ∞ Ω; ΔV = 0.5 V
Fig. 21. Definition of VCO frequency linearity
Fig. 22. Frequency linearity as a function of R1, C1
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
aaa-020368
aaa-020369
6
6
5
4
3
2
10
10
P
P
R2
(µW)
R1
(µW)
5
4
3
2
10
10
10
10
10
10
10
10
V
=
CC
V
=
CC
6 V
6 V
4.5 V
3 V
4.5 V
3 V
2
3
2
3
1
10
10
10
1
10
10
10
R1 (kΩ)
R2 (kΩ)
R2 = ∞ Ω; CL = 50 pF; VVCO_IN = 0.5VCC
Tamb = 25 °C
;
R1 = ∞ Ω; CL = 50 pF; VVCO_IN = GND;
Tamb = 25 °C
___ C1 = 40 pF; - - - C1 = 1 μF
___ C1 = 40 pF; - - - C1 = 1 μF
Fig. 23. Power dissipation as a function of R1
Fig. 24. Power dissipation as a function of R2
aaa-020370
3
10
P
DEM
(µW)
2
10
V
CC
6 V
=
4.5 V
3 V
10
2
3
10
10
10
R
S
(kΩ)
R1 = R2 = ∞ Ω; VVCO_IN = 0.5VCC; Tamb = 25 °C
Fig. 25. Typical power dissipation of demodulator sections as a function of Rs
13. Application information
This information is a guide for the approximation of values of external components to be used with
the 74HC4046A-Q100 in a phase-locked-loop system.
References should be made to Fig. 29, Fig. 30 and Fig. 31 as indicated in Table 8.
Values of the selected components should be within the ranges shown in Table 7.
Table 7. Survey of components
Component
Value
R1
between 3 kΩ and 300 kΩ
between 3 kΩ and 300 kΩ
parallel value > 2.7 kΩ
> 40 pF
R2
R1 + R2
C1
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21 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
Table 8. Design considerations for VCO section
Subject
Phase
Design consideration
comparator
VCO frequency
without extra
offset
PC1, PC2 or PC3 VCO frequency characteristic. With R2 = ∞ Ω and R1 within the range
3 kΩ < R1 < 300 kΩ, the characteristics of the VCO operation is as shown in
Fig. 26a. (Due to R1, C1 time constant a small offset remains when R2 = ∞ Ω).
PC1
Selection of R1 and C1. Given f0, determine the values of R1 and C1 using Fig. 29.
PC2 or PC3
Given fmax and f0, determine the values of R1 and C1 using Fig. 29;
use Fig. 31 to obtain 2fL and then use it to calculate fmin
.
VCO frequency
with extra offset
PC1, PC2 or PC3 VCO frequency characteristic. With R1 and R2 within the
ranges 3 kΩ < R1 < 300 kΩ and 3 kΩ < R2 < 300 kΩ.
The characteristics of the VCO operation are as shown in Fig. 26b.
PC1, PC2 or PC3 Selection of R1, R2 and C1. Given f0 and fL determine the value
of product R1C1 by using Fig. 31. Calculate foff from the equation
foff = f0 - 1.6fL. Obtain the values of C1 and R2 by using Fig. 30.
Calculate the value of R1 from the value of C1 and the product R1C1.
PLL conditions
no signal at pin
SIG_IN
PC1
PC2
PC3
VCO adjusts to f0 with ΦDEM_OUT = 90° and VVCO_IN = 0.5VCC, see Fig. 5
VCO adjusts to f0 with ΦDEM_OUT = -360° and VVCO_IN = minimum, see Fig. 7
VCO adjusts to f0 with ΦDEM_OUT = -360° and VVCO_IN = minimum, see Fig. 9
f
VCO
f
max
due to
R , C
2f
f
0
L
1
1
f
min
0.9 V
1/2 V
V
-0.9 V
V
CC
CC
CC
VCO_IN
aaa-020371
a. Operating without offset; f0 = center frequency; 2fL = frequency lock range.
f
VCO
f
max
due to
R , C
f
2f
L
0
1
1
f
min
f
off
due to
R , C
2
1
0.9 V
1/2 V
V
-0.9 V
V
CC
CC
CC
VCO_IN
aaa-020372
b. Operating with offset; f0 = center frequency; 2fL = frequency lock range.
Fig. 26. Frequency characteristic of VCO
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22 / 32
Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
Table 9. General design considerations
Subject
Phase comparator
Design consideration
PLL frequency capture range
PC1, PC2 or PC3
PC1 or PC3
PC2
Loop filter component selection, see Fig. 27 and Fig. 28
PLL locks on harmonics at
center frequency
yes
no
Noise rejection at signal input
PC1
high
PC2 or PC3
low
AC ripple content when PLL is PC1
fr = 2fi; large ripple content at ΦDEM_OUT = 90°
fr = fi; small ripple content at ΦDEM_OUT = 0°
fr = fi; large ripple content at ΦDEM_OUT = 180°
locked
PC2
PC3
F
(jω)
R3
-1/
τ
C2
input
output
ω
(a)
(b)
(c)
aaa-020446
R3 ≥ 500 Ω.
A small capture range (2fc) is obtained if
(a)
(b) amplitude characteristics
(c) pole-zero diagram
Fig. 27. Simple loop filter for PLL without offset
F
(jω)
m
R3
-1/
τ2
-1/
τ3
R4
C2
input
output
R4
R3 + R4
m =
1/
1/
ω
τ3
τ2
(a)
(b)
(c)
aaa-020447
R3 + R4 ≥ 500 Ω.
(a)
(b) amplitude characteristics
(c) pole-zero diagram
Fig. 28. Simple loop filter for PLL with offset
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
aaa-020448
8
7
6
5
4
3
2
10
f
o
R1 = 3 kΩ
10 kΩ
(Hz)
10
V
=
CC
10
10
10
10
10
150 kΩ
300 kΩ
5 V
4.5 V
6 V
5 V
4.5 V
3 V
5 V
4.5 V
3 V
5 V
4.5 V
3 V
10
2
3
4
5
6
7
1
10
10
10
10
10
10
10
C1 (pF)
To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
Interpolation for various values of R1 can be easily calculated because a constant R1C1 product produces almost
the same VCO output frequency.
R2 = ∞ Ω; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 °C.
Fig. 29. Typical value of VCO center frequency (f0) as a function of C1
aaa-020449
8
10
f
off
R2 = 3 kΩ
10 kΩ
(Hz)
7
6
5
4
3
2
10
V
=
CC
5 V
4.5 V
150 kΩ
300 kΩ
10
10
10
10
10
6 V
5 V
4.5 V
3 V
5 V
4.5 V
5 V
4.5 V
3 V
10
2
3
4
5
6
7
1
10
10
10
10
10
10
10
C1 (pF)
To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
Interpolation for various values of R2 can be easily calculated because a constant R2C1 product produces almost
the same VCO output frequency.
R1 = ∞ Ω; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 °C.
Fig. 30. Typical value of frequency offset as a function of C1
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
aaa-020450
8
7
6
5
4
3
2
10
2f
L
(Hz)
10
10
10
10
10
10
V
= 6 V
5 V
CC
4.5 V
3 V
10
10
-7
-6
-5
-4
-3
-2
-1
10
10
10
10
10
10
1
R1C1 (pF)
VVCO_IN = 0.9 V to (VCC - 0.9) V; R2 = ∞ Ω.
VCO gain:
Fig. 31. Typical frequency lock range (2fL) as a function of the product R1C1
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
13.1. PLL design example
The frequency synthesizer used in the design example shown in Fig. 32 has the following
parameters:
•
•
•
•
Output frequency: 2 MHz to 3 MHz
Frequency steps: 100 kHz
Settling time: 1 ms
Overshoot: < 20 %
The open loop gain is:
where:
•
•
•
•
Kp(s) = phase comparator gain
Kf(s) = low-pass filter transfer gain
Ko(s) = Kv/s VCO gain
Kn = 1⁄n divider ratio
The programmable counter ratio Kn can be found as follows:
The values of R1, R2 and C1; R2 = 10 kΩ (adjustable) set the VCO.
The values can be determined using the information in Table 8 and Table 9.
With f0 = 2.5 MHz and fL = 500 kHz, the following values (VCC = 5.0 V) are given:
•
•
•
R1 = 10 kΩ
R2 = 10 kΩ
C1 = 500 pF
The VCO gain is:
The gain of the phase comparator is:
The transfer gain of the filter is calculated as follows:
Where:
The characteristic equation is:
It results in:
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
The natural frequency ωn is defined as:
and the damping value (ζ) given as:
In Fig. 33, the output frequency response to a step of input frequency is shown.
The overshoot and settling time percentages are now used to determine ωn. Fig. 33 shows that the
damping ratio ζ = 0.45 produces an overshoot of less than 20 % and settle to within 5 % at ωnt = 5.
The required settling time is 1 ms. It results in:
Rewriting the equation for natural frequency results in:
The maximum overshoot occurs at Nmax
:
When C2 = 470 nF, then:
R3 can be calculated:
74HC4046A-Q100
K
K
K
o
p
f
100 kHz
PHASE
COMPARATOR
PC2
R3
9
13
4
OSCILLATOR
74HCU04
DIVIDE - BY 10
74HC191
14
3
f
VCO
6
out
11
12
7
5
R4
C2
R1
R2
K
n
1 MHz
C1
PROGRAMMABLE
DIVIDER
4 x 74HC161
aaa-030586
Fig. 32. Frequency synthesizer
aaa-020452
1.6
(t)
-0.6
ζ = 0.3
0.5
ω
Θ (t)
e
Θ /ω
e n
e
ω /ω
e
n
0.707
1.0
1.2
0.8
0.4
0
-0.2
ζ = 5.0
ζ = 2.0
0.2
0.6
1.0
0
2
4
6
8
ω
(t)
n
Fig. 33. Type 2, second order frequency step response
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
aaa-020453
N = 30
3.1
(1)
Frequency
(MHz)
3.0
N stepped from 29 to 30
2.9
2.1
2.0
1.9
step input
N stepped from 21 to 20
0
0.5
1
1.5
2
2.5
time (ms)
The output frequency is proportional to the VCO control voltage. As a result, the PLL frequency response can
be observed with an oscilloscope by monitoring pin VCO_IN of the VCO. The average frequency response, as
calculated by the Laplace method, is found experimentally by smoothing this voltage at pin VCO_IN using a
simple RC filter. The filter has a long time constant when compared with the phase detector sampling rate, but
short when compared with the PLL response time.
Fig. 34. Frequency compared to the time response
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
14. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 35. Package outline SOT403-1 (TSSOP16)
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
15. Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
CMOS
DUT
ESD
HBM
PLL
Charged Device Model
Complementary Metal Oxide Semiconductors
Device Under Test
ElectroStatic Discharge
Human Body Model
Phase-Locked Loop
VCO
Voltage Controlled Oscillator
16. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20230608 Product data sheet
Section 2 updated.
Change notice Supersedes
74HC4046A_Q100 v.2
Modifications:
-
-
•
74HC4046A_Q100 v.1
20191127
Product data sheet
-
-
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
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17. Legal information
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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[1][2]
status [3]
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This document contains the product
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Limiting values — Stress above one or more limiting values (as defined in
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Short data sheet — A short data sheet is an extract from a full data sheet
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Nexperia
74HC4046A-Q100
Phase-locked loop with VCO
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Block diagram...............................................................2
6. Functional diagram.......................................................2
7. Pinning information......................................................4
7.1. Pinning.........................................................................4
7.2. Pin description.............................................................4
8. Functional description................................................. 5
8.1. VCO.............................................................................5
8.2. Phase comparators......................................................5
8.2.1. Phase Comparator 1 (PC1)......................................5
8.2.2. Phase Comparator 2 (PC2)......................................7
8.2.3. Phase Comparator 3 (PC3)......................................8
9. Limiting values........................................................... 10
10. Recommended operating conditions......................10
11. Static characteristics................................................11
11.1. Graphs..................................................................... 14
12. Dynamic characteristics.......................................... 15
12.1. Waveforms and graphs............................................17
13. Application information........................................... 21
13.1. PLL design example................................................26
14. Package outline........................................................ 29
15. Abbreviations............................................................30
16. Revision history........................................................30
17. Legal information......................................................31
© Nexperia B.V. 2023. All rights reserved
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For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 8 June 2023
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74HC4046APW-T
IC PLL FREQUENCY SYNTHESIZER, PDSO16, SOT-403-1, TSSOP-16, PLL or Frequency Synthesis Circuit
NXP
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