74HC4520-Q100 [NEXPERIA]
Dual 4-bit synchronous binary counter;![74HC4520-Q100](http://pdffile.icpdf.com/pdf2/p00337/img/icpdf/74HC4520-Q10_2072031_icpdf.jpg)
型号: | 74HC4520-Q100 |
厂家: | ![]() |
描述: | Dual 4-bit synchronous binary counter |
文件: | 总13页 (文件大小:226K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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74HC4520-Q100;
74HCT4520-Q100
Dual 4-bit synchronous binary counter
Rev. 2 — 14 February 2019
Product data sheet
1. General description
The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters
with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions
(nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either
the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW
transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the
counter. The other clock input may be used as a clock enable input. A HIGH on nMR resets the
counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. It
enables the use of current limiting resistors to interface inputs to voltages in excess of VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
Complies with JEDEC standard no. 7A
Input levels:
•
•
For 74HC4520-Q100: CMOS level
For 74HCT4520-Q100: TTL level
•
ESD protection:
•
•
•
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
3. Applications
•
•
•
Multistage synchronous counting
Multistage asynchronous counting
Frequency dividers
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC4520D-Q100
74HCT4520D-Q100
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
5. Functional diagram
1Q0
1Q1
1Q2
1Q3
3
4
5
6
1
2
1CP0
1CP1
7
9
1MR
2Q0 11
2Q1 12
2Q2 13
2Q3 14
2CP0
10 2CP1
15 2MR
001aae698
Fig. 1. Functional diagram
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17 18
nCP0
nCP1
nMR
1
10 11 12 13 14 15
0
1
2
3
4
nQ0
nQ1
nQ2
nQ
3
001aae707
Fig. 2. Timing diagram
nQ0
nQ1
nQ2
nQ3
Q
Q
Q
Q
Q
Q
Q
FF1
CP
FF2
CP
FF3
CP
FF4
CP
nCP1
nCP0
Q
RD
RD
RD
RD
nMR
aaa-015608
Fig. 3. Logic diagram for one counter
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
2 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
6. Pinning information
6.1. Pinning
74HC4520-Q100
74HCT4520-Q100
1
2
3
4
5
6
7
8
16
V
1CP0
1CP1
1Q0
CC
15
14
13
12
11
10
9
2MR
2Q3
1Q1
2Q2
1Q2
2Q1
1Q3
2Q0
1MR
GND
2CP1
2CP0
aaa-015632
Fig. 4. Pin configuration SOT109-1 (SO16)
6.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1CP0, 2CP0
1CP1, 2CP1
1Q0 to 1Q3
1MR, 2MR
GND
1, 9
clock input (LOW-to-HIGH edge-triggered)
2, 10
clock input (HIGH-to-LOW edge-triggered)
3, 4, 5, 6
output
7, 15
asynchronous master reset input (active HIGH)
8
ground (0 V)
output
2Q0 to 2Q3
VCC
11, 12, 13, 14
16
supply voltage
7. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition.
nCP0
nCP1
nMR
Mode
↑
H
↓
L
L
L
L
L
L
H
counter advances
counter advances
no change
L
↓
X
↑
X
↑
no change
L
↓
no change
H
X
no change
X
nQ0 to nQ3 = LOW
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
3 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7.0
±20
±20
±25
50
Unit
V
VCC
IIK
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to VCC + 0.5 V
-
mA
mA
mA
mA
mA
°C
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
-
storage temperature
total power dissipation
+150
500
[1]
mW
[1] For SO16 package: above 70 °C the value of Ptot derates linearly at 8 mW/K.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC4520-Q100
74HCT4520-Q100
Unit
Min
Typ
Max
Min
4.5
Typ
Max
VCC
VI
supply voltage
2.0
5.0
6.0
VCC
VCC
+125
625
139
83
5.0
5.5
VCC
VCC
V
V
V
input voltage
0
0
-
0
0
-
VO
output voltage
-
+25
-
-
+25
-
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
-
-40
-
+125 °C
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
ns/V
-
1.67
-
-
1.67
-
139 ns/V
-
-
-
ns/V
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min Typ
Max
Min
Max
Min
Max
74HC4520-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
3.15
3.15
3.15
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
4 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
Symbol Parameter
Conditions
25 °C
Min Typ
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Max
Min
Max
Min
Max
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = -20 μA; VCC = 2.0 V
1.9
4.4
2.0
4.5
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
IO = -20 μA; VCC = 4.5 V
IO = -20 μA; VCC = 6.0 V
IO = -4.0; VCC = 4.5 V
IO = -5.2; VCC = 6.0 V
5.9
6.0
5.9
3.98
5.48
4.32
5.81
3.84
5.34
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 20 μA; VCC = 2.0 V
IO = 20 μA; VCC = 4.5 V
IO = 20 μA; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
0
0.1
0.1
0.15
0.16
-
0.26
0.26
±0.1
0.33
0.33
±1.0
II
input leakage VI = VCC or GND; VCC = 6.0 V
current
±1.0 μA
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
8.0
-
-
-
80.0
-
-
-
160.0 μA
input
3.5
-
pF
capacitance
74HCT4520-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = -20 μA
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = -4.0 mA
3.98
4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA
-
-
-
0
0.15
-
0.1
-
-
-
0.1
-
-
-
0.1
0.4
V
V
IO = 4.0 mA
0.26
±0.1
0.33
±1.0
II
input leakage VI = VCC or GND; VCC = 5.5 V
current
±1.0 μA
ICC
ΔICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80.0
-
160.0 μA
additional
per input pin; VI = VCC - 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
pin nCP0, nCP1
pin nMR
-
-
-
80
150
3.5
288
540
-
-
-
-
360
675
-
-
-
-
392 μA
735 μA
CI
input
-
pF
capacitance
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
5 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 7.
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Typ Max Min Max Min Max
74HC4520-Q100
tpd
propagation nCP0 to nQn; see Fig. 5
[1]
[1]
delay
VCC = 2.0 V
-
-
-
-
77
28
24
22
240
48
-
-
-
-
-
300
60
-
-
-
-
-
360 ns
72 ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
-
41
51
61 ns
nCP1 to nQn; see Fig. 5
VCC = 2.0 V
-
-
-
-
77
28
24
22
240
48
-
-
-
-
-
300
60
-
-
-
-
-
360 ns
72 ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
-
ns
41
51
61 ns
tPHL
HIGH to LOW nMR to nQn; see Fig. 5
propagation
delay
VCC = 2.0 V
-
-
-
-
44
16
13
13
150
30
-
-
-
-
-
190
38
-
-
-
-
-
225 ns
45 ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
-
ns
26
33
38 ns
tt
transition
time
nQn; see Fig. 5
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
[2]
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
110 ns
22 ns
19 ns
6
tW
pulse width
nCP0, nCP1 HIGH or LOW;
see Fig. 6
VCC = 2.0 V
VCC = 4.5 V
80
16
14
22
8
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
VCC = 6.0 V
6
17
20
nMR HIGH; see Fig. 6
VCC = 2.0 V
120
24
39
14
11
-
-
-
150
30
-
-
-
180
36
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
20
26
31
trec
recovery time nMR to nCP0, nCP1; see Fig. 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
-28
-10
-8
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
tsu
set-up time
nCP0 to nCP1; nCP1 to nCP0;
see Fig. 5
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
14
5
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
4
17
20
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
6 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Typ Max Min Max Min Max
fmax
maximum
frequency
nCP0, nCP1; see Fig. 6
VCC = 2.0 V
6
30
-
19
58
68
69
29
-
-
-
-
-
4.8
24
-
-
-
-
-
-
4
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
35
-
28
-
24
-
CPD
power
VI = GND to VCC; VCC = 5 V;
fi = 1 MHz
[3]
dissipation
capacitance
74HCT4520-Q100
tpd
propagation nCP0 to nQn; see Fig. 5
[1]
[1]
delay
VCC = 4.5 V
-
-
28
24
53
-
-
-
66
-
-
-
80 ns
ns
VCC = 5.0 V; CL = 15 pF
nCP1 to nQn; see Fig. 5
-
VCC = 4.5 V
-
-
25
24
53
-
-
-
66
-
-
-
80 ns
ns
VCC = 5.0 V; CL = 15 pF
-
tPHL
HIGH to LOW nMR to nQn; see Fig. 5
propagation
delay
VCC = 4.5 V
-
-
16
13
35
-
-
-
44
-
-
-
53 ns
ns
VCC = 5.0 V; CL = 15 pF
-
tt
transition
time
nQn; see Fig. 5
VCC = 4.5 V
[2]
-
7
15
-
19
-
22 ns
tW
pulse width
nCP0, nCP1 HIGH or LOW;
see Fig. 6
VCC = 4.5 V
nMR HIGH; see Fig. 6
VCC = 4.5 V
20
20
0
10
12
-8
-
-
-
25
25
0
-
-
-
30
30
0
-
-
-
ns
ns
ns
trec
recovery time nMR to nCP0, nCP1; see Fig. 6
VCC = 4.5 V
tsu
set-up time
nCP0 to nCP1; nCP1 to nCP0;
see Fig. 5
VCC = 4.5 V
16
6
-
20
-
24
-
ns
fmax
maximum
frequency
nCP0, nCP1; see Fig. 6
VCC = 4.5 V
30
-
58
64
24
-
-
-
24
-
-
-
-
20
-
-
-
-
MHz
MHz
pF
VCC = 5.0 V; CL = 15 pF
CPD
power
VI = GND to VCC - 1.5 V; VCC = 5 V; [3]
fi = 1 MHz
-
-
-
dissipation
capacitance
[1] tpd is the same as tPHL and tPLH
.
[2] tt is the same as tTHL and tTLH
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
7 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
11.1. Waveforms and test circuit
V
I
V
M
nCP0 input
0 V
V
I
nCP1 input
0 V
V
M
0 V
t
t
su
su
V
I
nMR input
0 V
V
M
t
t
t
PHL
PHL
PLH
V
OH
90 %
nQn output
V
M
10 %
V
OL
t
t
t
t
001aae702
Measurement points are given in Table 8.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Fig. 5. nCP0 and nCP1 set-up times, propagation delays and output transition times
1/f
max
V
I
nCP1 input
(nCP0 = LOW)
V
V
M
0 V
t
t
W
V
I
nCP0 input
(nCP1 = HIGH)
M
0 V
W
V
I
V
nMR input
0 V
M
t
W
t
rec
001aae701
Measurement points are given in Table 8.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Fig. 6. nMR recovery time, minimum nCP0, nCP1, nMR pulse widths and maximum frequency
Table 8. Measurement points
Type
Input
VM
Output
VM
VI
74HC4520-Q100
74HCT4520-Q100
0.5 × VCC
1.3 V
GND to VCC
GND to 3 V
0.5 × VCC
1.3 V
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
8 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
I
V
O
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Test circuit definitions:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistance.
S1 = Test selection switch
Fig. 7. Test circuit for measuring switching times
Table 9. Test data
Type
Input
Load
S1 position
tPHL, tPLH
open
VI
tr, tf
6 ns
6 ns
CL
RL
74HC4520-Q100
GND to VCC
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74HCT4520-Q100 GND to 3 V
open
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
9 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 8. Package outline SOT109-1 (SO16)
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
10 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
13. Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
DUT
ESD
HBM
MIL
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20190214
Data sheet status
Change notice Supersedes
74HC_HCT4520_Q100 v.2
Modifications:
Product data sheet
-
74HC_HCT4520_Q100 v.1
•
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
•
•
Legal texts have been adapted to the new company name where appropriate.
Type number 74HC4520PW-Q100 (SOT403-1) removed.
74HC_HCT4520_Q100 v.1
20141204
Product data sheet
-
-
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
11 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
equipment, nor in applications where failure or malfunction of an Nexperia
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15. Legal information
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Definition
[1][2]
status [3]
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This document contains the product
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[1] Please consult the most recently issued document before initiating or
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©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
12 / 13
Nexperia
74HC4520-Q100; 74HCT4520-Q100
Dual 4-bit synchronous binary counter
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 4
9. Recommended operating conditions..........................4
10. Static characteristics..................................................4
11. Dynamic characteristics.............................................6
11.1. Waveforms and test circuit........................................ 8
12. Package outline........................................................ 10
13. Abbreviations............................................................11
14. Revision history........................................................11
15. Legal information......................................................12
© Nexperia B.V. 2019. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 14 February 2019
©
74HC_HCT4520_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 14 February 2019
13 / 13
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