74HC573D-Q100_技术文档

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

Rev. 6 — 10 February 2021

Product data sheet

1. General description

The 74HC573-Q100; 74HCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs.

The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at

the inputs enter the latches. In this condition the latches are transparent, a latch output will change

each time its corresponding D-input changes. When LE is LOW the latches store the information

that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH

on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does

not affect the state of the latches. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of V_CC

.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Input levels:

•

For 74HC573-Q100: CMOS level

For 74HCT573-Q100: TTL level

•

Inputs and outputs on opposite sides of package allowing easy interface with microprocessors

Useful as input or output port for microprocessors and microcomputers

3-state non-inverting outputs for bus-oriented applications

Common 3-state output enable input

Multiple package options

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2 000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

•

DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of

solder joints

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC573D-Q100

74HCT573D-Q100

-40 °C to +125 °C

SO20

plastic small outline package; 20 leads;

body width 7.5 mm

SOT163-1

74HC573PW-Q100 -40 °C to +125 °C

74HCT573PW-Q100

TSSOP20

plastic thin shrink small outline package;

20 leads; body width 4.4 mm

SOT360-1

SOT764-1

74HC573BQ-Q100

74HCT573BQ-Q100

-40 °C to +125 °C

DHVQFN20 plastic dual in-line compatible thermal

enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 × 4.5 × 0.85 mm

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

4. Functional diagram

2

3

4

5

6

7

8

9

19

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

18

17

16

15

14

13

12

LATCH

1 to 8

3-STATE

OUTPUTS

LE

11

1

OE

mna809

Fig. 1. Functional diagram

D0

D1

D2

D3

D4

D5

D6

D7

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

LATCH

1

LATCH

2

LATCH

3

LATCH

4

LATCH

5

LATCH

6

LATCH

7

LATCH

8

LE

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

001aae075

Fig. 2. Logic diagram

11

C1

1

EN1

1

2

19

1D

OE

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

D0

D1

D2

D3

D4

D5

D6

D7

Q0

3

4

5

6

7

18

17

16

15

14

Q1

Q2

Q3

Q4

Q5

Q6

Q7

8

9

13

12

LE

11

mna807

mna808

Fig. 3. Logic symbol

Fig. 4. IEC logic symbol

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

2 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

5. Pinning information

5.1. Pinning

74HC573-Q100

74HCT573-Q100

terminal 1

index area

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

74HC573-Q100

74HCT573-Q100

1

2

20

19

18

17

16

15

14

13

12

11

OE

D0

V

CC

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

LE

3

D1

GND(1)

4

D2

5

D3

6

D4

aaa-003604

7

D5

8

D6

Transparent top view

9

D7

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

10

GND

aaa-003603

Fig. 5. Pin configuration SOT163-1 (SO20) and

SOT360-1 (TSSOP20)

Fig. 6. Pin configuration SOT764-1 (DHVQFN20)

5.2. Pin description

Table 2. Pin description

Symbol

Description

OE

1

3-state output enable input (active LOW)

data input

D0, D1, D2, D3, D4, D5, D6, D7

2, 3, 4, 5, 6, 7, 8, 9

GND

10

11

ground (0 V)

LE

latch enable input (active HIGH)

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

V_CC

19, 18, 17, 16, 15, 14, 13, 12

20

3-state latch output

supply voltage

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

3 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;

Z = high-impedance OFF-state.

Operating mode

Control

Input

Internal latches Output

Qn

OE

LE

Dn

L

H

l

Enable and read register

(transparent mode)

L

H

L

H

L

H

L

Latch and read register

L

h

l

H

L

H

Z

Latch register and disable outputs H

h

H

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

+7

Unit

V

V_CC

I_IK

supply voltage

-0.5

input clamping current

output clamping current

output current

V_I< -0.5 V or V_I> V_CC+ 0.5 V

V_O< -0.5 V or V_O> V_CC+ 0.5 V

V_O= -0.5 V to (V_CC+ 0.5 V)

-

±20

±35

+70

-

mA

°C

I_OK

I_O

-

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

-70

-65

-

storage temperature

total power dissipation

+150

500

[1]

mW

[1] For SOT163-1 (SO20) package: P_totderates linearly with 12.3 mW/K above 109 °C.

For SOT360-1 (TSSOP20) package: P_totderates linearly with 10.0 mW/K above 100 °C.

For SOT764-1 (DHVQFN20) package: P_totderates linearly with 12.9 mW/K above 111 °C.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter

Conditions

74HC573-Q100

74HCT573-Q100

Unit

Min

Typ

Max

Min

Typ

Max

5.5

V_CC

V_I

supply voltage

input voltage

2.0

5.0

6.0

V_CC

+125

625

139

83

4.5

5.0

V

0

-

0

-

V_CC

V_O

output voltage

ambient temperature

-

+25

-

+25

-

T_amb

Δt/ΔV

-40

-

-40

-

+125 °C

input transition rise and fall V_CC= 2.0 V

-

139

-

ns/V

rate

V_CC= 4.5 V

-

1.67

-

1.67

-

ns/V

V_CC= 6.0 V

-

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

4 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Typ

Max

Min

Max

Min

Max

74HC573-Q100

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_I= V_IHor V_IL

1.5

1.2

2.4

3.2

0.8

2.1

2.8

-

1.5

-

1.5

-

V

3.15

4.2

-

4.2

-

4.2

-

V_IL

LOW-level

input voltage

-

0.5

1.35

1.8

-

0.5

1.35

1.8

-

0.5

1.35

1.8

V_OH

HIGH-level

output voltage

I_O= -20 μA; V_CC= 2.0 V

1.9

4.4

5.9

2.0

4.5

6.0

-

1.9

4.4

-

1.9

4.4

5.9

3.7

5.2

-

V

I_O= -20 μA; V_CC= 4.5 V

I_O= -20 μA; V_CC= 6.0 V

I_O= -6.0 mA; V_CC= 4.5 V

I_O= -7.8 mA; V_CC= 6.0 V

5.9

3.98 4.32

5.48 5.81

3.84

5.34

V_OL

LOW-level

V_I= V_IHor V_IL

output voltage

I_O= 20 μA; V_CC= 2.0 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 20 μA; V_CC= 6.0 V

I_O= 6.0 mA; V_CC= 4.5 V

I_O= 7.8 mA; V_CC= 6.0 V

-

0

0.1

-

0.1

-

0.1

0.4

V

0.1

0.15 0.26

0.16 0.26

0.33

±1.0

I_I

input leakage V_I= V_CCor GND; V_CC= 6.0 V

current

-

±0.1

±0.5

8.0

-

±1.0 μA

±10.0 μA

160 μA

pF

I_OZ

I_CC

C_I

OFF-state

output current V_O= V_CCor GND

V_I= V_IHor V_IL; V_CC= 6.0 V;

-

±5.0

80

-

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

-

input

3.5

capacitance

74HCT573-Q100

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

1.6

1.2

-

2.0

-

2.0

-

V

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= -20 μA

4.4

4.5

-

4.4

-

4.4

3.7

-

V

I_O= -6 mA

3.98 4.32

3.84

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 20 μA

-

0

0.1

-

0.1

-

0.1

0.4

V

I_O= 6.0 mA

0.16 0.26

0.33

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

5 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Typ

Max

Min

Max

Min

Max

±1.0 μA

I_I

input leakage V_I= V_CCor GND; V_CC= 5.5 V

current

-

±0.1

-

±1.0

±5.0

80

-

I_OZ

I_CC

ΔI_CC

OFF-state

output current V_O= V_CCor GND

V_I= V_IHor V_IL; V_CC= 5.5 V;

-

±0.5

8.0

±10 μA

160 μA

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

additional

V_I= V_CC- 2.1 V;

supply current other inputs at V_CCor GND;

V_CC= 4.5 V to 5.5 V; I_O= 0 A

per input pin; Dn inputs

per input pin; LE input

per input pin; OE input

-

35

65

126

234

450

-

158

293

563

-

172 μA

319 μA

613 μA

125

3.5

C_I

input

-

pF

capacitance

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit see Fig. 11.

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Typ

Max

Min

Max

Min

Max

74HC573-Q100

t_pd

propagation

delay

Dn to Qn; see Fig. 7

V_CC= 2.0 V

[1]

-

47

17

14

150

30

-

190

38

-

225 ns

45 ns

ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

-

26

33

38 ns

LE to Qn; see Fig. 8

V_CC= 2.0 V

-

50

18

15

14

150

30

-

190

38

-

225 ns

45 ns

V_CC= 4.5 V

V_CC= 5 V; C_L= 15 pF

V_CC= 6.0 V

-

ns

26

33

38 ns

t_en

enable time

disable time

OE to Qn; see Fig. 9

V_CC= 2.0 V

[2]

[3]

-

44

16

13

140

28

-

175

35

-

210 ns

42 ns

36 ns

V_CC= 4.5 V

V_CC= 6.0 V

24

30

t_dis

OE to Qn; see Fig. 9

V_CC= 2.0 V

-

55

20

16

150

30

-

190

38

-

225 ns

45 ns

38 ns

V_CC= 4.5 V

V_CC= 6.0 V

26

33

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

6 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

Symbol Parameter

Conditions

25 °C

Typ

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Max

Min

Max

Min

Max

t_t

transition time Qn; see Fig. 7

V_CC= 2.0 V

[4]

-

14

5

60

12

10

-

75

15

13

-

90 ns

V_CC= 4.5 V

18 ns

15 ns

V_CC= 6.0 V

4

t_W

t_su

t_h

pulse width

set-up time

hold time

LE HIGH; see Fig. 8

V_CC= 2.0 V

80

16

14

5

-

100

20

-

120

24

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

4

17

20

Dn to LE; see Fig. 10

V_CC= 2.0 V

50

10

9

11

4

-

65

13

11

-

75

15

13

-

ns

V_CC= 4.5 V

V_CC= 6.0 V

3

Dn to LE; see Fig. 10

V_CC= 2.0 V

5

-

3

1

-

5

-

5

-

ns

pF

V_CC= 4.5 V

V_CC= 6.0 V

1

C_PD

power

dissipation

capacitance

C_L= 50 pF; f = 1 MHz;

V_I= GND to V_CC

[5]

26

74HCT573-Q100

t_pd

propagation

delay

Dn to Qn; see Fig. 7

V_CC= 4.5 V

[1]

-

20

17

35

-

44

-

53 ns

ns

V_CC= 5 V; C_L= 15 pF

LE to Qn; see Fig. 8

V_CC= 4.5 V

-

18

15

35

-

44

-

53 ns

ns

V_CC= 5 V; C_L= 15 pF

OE to Qn; see Fig. 9

V_CC= 4.5 V

-

t_en

t_dis

t_t

enable time

disable time

[2]

[3]

[4]

-

17

18

5

30

12

-

38

15

-

45 ns

18 ns

OE to Qn; see Fig. 9

V_CC= 4.5 V

transition time Qn; see Fig. 7

V_CC= 4.5 V

-

t_W

pulse width

LE HIGH; see Fig. 8

V_CC= 4.5 V

16

5

20

24

-

ns

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

7 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

Symbol Parameter

Conditions

25 °C

Typ

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min

Max

Min

Max

Min

Max

t_su

set-up time

hold time

Dn to LE; see Fig. 10

V_CC= 4.5 V

13

7

-

16

-

20

-

ns

t_h

Dn to LE; see Fig. 10

V_CC= 4.5 V

9

-

4

-

11

-

15

-

ns

C_PD

power

dissipation

capacitance

C_L= 50 pF; f = 1 MHz;

V_I= GND to V_CC- 1.5 V

[5]

26

pF

[1] t_pdis the same as t_PLHand t_PHL

[2] t_enis the same as t_PZHand t_PZL

[3] t_disis the same as t_PLZand t_PHZ

[4] t_tis the same as t_THLand t_TLH

.

[5] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of outputs.

10.1. Waveforms and test circuit

Dn input

V

M

t

PHL

PLH

90 %

V

Qn output

M

10 %

TLH

t

THL

001aae082

Measurement points are given in Table 8.

Fig. 7. Propagation delay data input (Dn) to output (Qn) and output transition time

LE input

V

M

t

W

t

PHL

PLH

90 %

V

Qn output

M

10 %

t

TLH

THL

001aae083

Measurement points are given in Table 8.

Fig. 8. Pulse width latch enable input (LE), propagation delay latch enable input (LE) to output (Qn) and output

transition time

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

8 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

V

I

OE input

V

M

GND

t

PLZ

PZL

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

10%

V

OL

t

PZH

PHZ

V

OH

90%

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aae307

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 9. Enable and disable times

V

h

LE input

M

t

su

t

h

V

Dn input

M

001aae084

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 10. Set-up and hold times for data input (Dn) to latch input (LE)

Table 8. Measurement points

Type

Input

V_M

Output

V_M

74HC573-Q100

74HCT573-Q100

0.5V_CC

1.3 V

0.5V_CC

1.3 V

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

9 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

I

V

O

R

L

S1

G

open

DUT

R

T

C

L

001aad983

Test data is given in Table 9.

Definitions test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

R_L= Load resistance.

S1 = Test selection switch.

Fig. 11. Test circuit for measuring switching times

Table 9. Test data

Type

Input

V_I

Load

C_L

S1 position

t_PHL, t_PLH

open

t_r, t_f

6 ns

R_L

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

V_CC

74HC573-Q100

74HCT573-Q100

V_CC

3 V

15 pF, 50 pF 1 kΩ

open

GND

V_CC

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

10 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

11. Package outline

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig. 12. Package outline SOT163-1 (SO20)

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

11 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

1

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig. 13. Package outline SOT360-1 (TSSOP20)

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

12 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

SOT764-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

terminal 1

index area

e

C

1

v

w

C

A B

y

e

b

C

1

2

9

L

1

10

E

e

h

20

11

19

12

X

D

h

0

2.5

5 mm

scale

Dimensions (mm are the original dimensions)

(1) (1)

(1)

Unit

A

b

c

D

h

E

e

1

L

v

w

y

1

h

max 1.00 0.05 0.30

4.6 3.15 2.6 1.15

0.5

nom

min

mm

0.90 0.02 0.25 0.2 4.5 3.00 2.5 1.00 0.5 3.5 0.4 0.1 0.05 0.05 0.1

0.80 0.00 0.18 4.4 2.85 2.4 0.85 0.3

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot764-1_po

Issue date

References

Outline

version

European

projection

IEC

- - -

JEDEC

JEITA

- - -

03-01-27

14-12-12

SOT764-1

MO-241

Fig. 14. Package outline SOT764-1 (DHVQFN20)

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

13 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

CMOS

DUT

ESD

HBM

MIL

Complementary Metal Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Military

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

20210210 Product data sheet

Type numbers 74HC573DB-Q100 and 74HCT573DB-Q100 (SOT339-1) removed.

20200310 Product data sheet 74HC_HCT573_Q100 v.4

Change notice Supersedes

74HC_HCT573_Q100 v.6

Modifications:

- 74HC_HCT573_Q100 v.5

•

74HC_HCT573_Q100 v.5

Modifications:

-

•

The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Section 1 and Section 2 updated.

Section 7: Derating values for P_tottotal power dissipation updated.

74HC_HCT573_Q100 v.4

Modifications:

20150126

Product data sheet

-

74HC_HCT573_Q100 v.3

•

Table 7: Power dissipation capacitance condition for 74HCT573-Q100 is corrected.

74HC_HCT573_Q100 v.3

Modifications:

20130305

Product data sheet

-

74HC_HCT573_Q100 v.2

•

74HC573DB-Q100 and 74HCT573DB-Q100 added.

74HC_HCT573_Q100 v.2

74HC_HCT573_Q100 v.1

20120816

20120802

Product data sheet

-

74HC_HCT573_Q100 v.1

-

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

14 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

equipment, nor in applications where failure or malfunction of an Nexperia

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. Nexperia and its suppliers accept

no liability for inclusion and/or use of Nexperia products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

14. Legal information

Data sheet status

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Document status Product

Definition

[1][2]

status [3]

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Disclaimers

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Suitability for use in automotive applications — This Nexperia product

has been qualified for use in automotive applications. Unless otherwise

agreed in writing, the product is not designed, authorized or warranted to

be suitable for use in life support, life-critical or safety-critical systems or

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

15 / 16

Nexperia

74HC573-Q100; 74HCT573-Q100

Octal D-type transparent latch; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description.............................................................3

6. Functional description................................................. 4

7. Limiting values............................................................. 4

8. Recommended operating conditions..........................4

9. Static characteristics....................................................5

10. Dynamic characteristics............................................ 6

10.1. Waveforms and test circuit........................................ 8

11. Package outline........................................................ 11

12. Abbreviations............................................................14

13. Revision history........................................................14

14. Legal information......................................................15

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 10 February 2021

©

74HC_HCT573_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 10 February 2021

16 / 16


型号：	74HC573D-Q100
厂家：	Nexperia
描述：	Octal D-type transparent latch; 3-stateProduction 驱动光电二极管逻辑集成电路
文件：	总16页 (文件大小：269K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HC573D-Q100 [NEXPERIA]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E