74HCT4046AD_技术文档

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Rev. 5 — 8 June 2023

Product data sheet

1. General description

The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance

with JEDEC standard no 7A.

2. Features and benefits

•

Low power consumption

•

VCO-Inhibit control for ON/OFF keying and for low standby power consumption

Center frequency up to 17 MHz (typical) at V_CC= 4.5 V

Choice of three phase comparators:

•

PC1: EXCLUSIVE-OR

PC2: Edge-triggered J-K flip-flop

PC3: Edge-triggered RS flip-flop

•

Excellent Voltage Controlled Oscillator (VCO) linearity

Low frequency drift with supply voltage and temperature variations

Operating power supply voltage range:

•

VCO section 3.0 V to 6.0 V

Digital section 2.0 V to 6.0 V

•

Zero voltage offset due to operational amplifier buffering

ESD protection:

•

HBM: ANSI/ESDA/Jedec JS-001 Class 2 exceeds 2 kV

CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1 kV

3. Applications

•

FM modulation and demodulation

Frequency synthesis and multiplication

Frequency discrimination

Tone decoding

Data synchronization and conditioning

Voltage-to-frequency conversion

Motor-speed control

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

4. Ordering information

Table 1. Ordering information

Type number

Package

Name

Description

Version

74HC4046AD

74HCT4046AD

SO16

plastic small outline package; 16 leads; body width 3.9 mm

plastic shrink small outline package; 16 leads; body width 5.3 mm

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT109-1

SOT338-1

SOT403-1

74HC4046ADB

74HCT4046ADB

SSOP16

74HC4046APW

74HCT4046APW

TSSOP16

5. Block diagram

C1

6

7

4

3

14

C1A

C1B

VCO_OUT

COMP_IN SIG_IN

4046A

PHASE

COMPARATOR

1

PC1_OUT 2

R2 12

R2

VCO

PC2_OUT 13

PCP_OUT 1

PHASE

COMPARATOR

2

R3

R1 11

R1

R4

C2

PHASE

COMPARATOR

3

PC3_OUT 15

5

10

9

INH

DEM_OUT VCO_IN

R

S

aaa-020201

Fig. 1. Block diagram

6. Functional diagram

2

PC1_OUT

PC3_OUT

PC2_OUT

PCP_OUT

COMP_IN

SIG_IN

3

15

13

1

Ø

2

13

15

1

PC1_OUT

PC2_OUT

PC3_OUT

PCP_OUT

14

SIG_IN

COMP_IN

C1A

14

3

C1A

C1B

6

7

C1B

7

4046A

4

VCO_OUT

R1

11

12

9

R1

11

12

9

∏

#

VCO

10

4

DEM_OUT

VCO_OUT

aaa-020203

R2

10

DEM_OUT

∏

#

VCO_IN

INH

VCO_IN

INH

5

aaa-020202

Fig. 2. Logic symbol

Fig. 3. IEC logic symbol

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74HC_HCT4046A

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Product data sheet

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

C1

6

7

4

3

14

C1A C1B VCO_OUT COMP_IN SIG_IN

PC1_OUT

2

V

ref

R2 12

R2

VCO

S

D

Q

PC3_OUT 15

R1 11

R1

Q

D

R

DEM_OUT 10

V

CC

P

UP

`1'

D

Q

CP

R

S

R3

13 PC2_OUT

D

N

R4

C2

D

Q

GND

CP

DOWN

1

PCP_OUT

R

D

5

9

INH

VCO_IN

aaa-020204

Fig. 4. Logic diagram

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Product data sheet

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

7. Pinning information

7.1. Pinning

D package

SOT109-1 (SO16)

1

2

3

4

5

6

7

8

16

V

PCP_OUT

PC1_OUT

COMP_IN

VCO_OUT

INH

DB package

SOT338-1 (SSOP16)

CC

15

14

13

12

11

10

9

PC3_OUT

SIG_IN

PC2_OUT

R2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PCP_OUT

PC1_OUT

COMP_IN

VCO_OUT

INH

V

CC

PC3_OUT

SIG_OUT

PC2_OUT

R2

C1A

R1

C1A

R1

C1B

DEM_OUT

VCO_IN

C1B

DEM_OUT

VCO_IN

GND

aaa-035382

aaa-035383

PW package

SOT403-1 (TSSOP16)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PCP_OUT

PC1_OUT

COMP_IN

VCO_OUT

INH

V

CC

PC3_OUT

SIG_IN

PC2_OUT

R2

C1A

R1

C1B

DEM_OUT

VCO_IN

GND

aaa-035384

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Product data sheet

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

7.2. Pin description

Table 2. Pin description

Symbol

1

Description

PCP_OUT

PC1_OUT

COMP_IN

VCO_OUT

INH

phase comparator pulse output

phase comparator 1 output

comparator input

2

3

4

VCO output

5

inhibit input

C1A

6

capacitor C1 connection A

capacitor C1 connection B

ground (0 V)

C1B

7

GND

8

VCO_IN

DEM_OUT

R1

9

VCO input

10

11

12

13

14

15

16

demodulator output

resistor R1 connection

resistor R2 connection

phase comparator 2 output

signal input

R2

PC2_OUT

SIG_IN

PC3_OUT

V_CC

phase comparator 3 output

supply voltage

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Product data sheet

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

8. Functional description

The 74HC4046A; 74HCT4046A is a phase-locked-loop circuit that comprises a linear VCO and

three different phase comparators (PC1, PC2 and PC3). It has a common signal input amplifier and

a common comparator input (see Fig. 1). The signal input can be directly coupled to a large voltage

signal, or indirectly coupled (with a series capacitor) to a small voltage signal. A self-bias input

circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive

low-pass filter, the 74HC4046A; 74HCT4046A forms a second-order loop PLL. The excellent VCO

linearity is achieved by the use of linear op amp techniques.

8.1. VCO

The VCO requires one external capacitor C1 (between pins C1A and C1B) and one external

resistor R1 (between pins R1 and GND). Alternatively, it requires two external resistors R1 and

R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the

frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if necessary

(see Fig. 4).

The high input impedance of the VCO simplifies the design of the low-pass filters by giving

the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter,

a demodulator output of the VCO input voltage is provided at pin DEM_OUT. In contrast to

conventional techniques, where the DEM_OUT voltage is one threshold voltage lower than the

VCO input voltage, the DEM_OUT voltage equals the VCO input. If DEM_OUT is used, a series

resistor (R_s) should be connected from pin DEM_OUT to GND. If unused, DEM_OUT should be

left open. The VCO output (pin VCO_OUT) can be connected directly to the comparator input (pin

COMP_IN) or connected via a frequency divider. When the VCO input DC level is held constant,

the VCO output signal has a duty cycle of 50 % (maximum expected deviation 1 %). A LOW-level

at the inhibit input (pin INH) enables the VCO and demodulator, while a HIGH-level turns off both to

minimize standby power consumption.

The only difference between the 74HC4046A and 74HCT4046A is the input level specification of

the INH input. A HIGH on the INH input disables the VCO section. The input level specification for

the SIG_IN and COMP_IN inputs are identical for both 74HC4046A and 74HCT4046A.

8.2. Phase comparators

The input signal can be coupled to the self-biasing amplifier at pin SIG_IN, when the signal swing is

between the standard HC/T family input logic levels. Capacitive coupling is required for signals with

smaller swings.

8.2.1. Phase Comparator 1 (PC1)

This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies (f_i) must

have a 50 % duty cycle to obtain the maximum locking range. The transfer characteristic of PC1,

assuming ripple (f_r= 2f_i) is suppressed, is:

where:

•

V_{DEM_OUT}is the demodulator output at pin DEM_OUT

V_{DEM_OUT}= V_{PC1_OUT}(via low-pass filter)

The phase comparator gain is:

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Product data sheet

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

PC1 is fed to the VCO input via the low-pass filter and provided at the demodulator output at pin

DEM_OUT (V_{DEM_OUT}). The average output voltage from PC1 is the result of the phase differences

of signals (SIG_IN) and the comparator input (COMP_IN). These phase differences are shown in

Fig. 5. The average of V_{DEM_OUT}is equal to 0.5V_CCwhen no signal or noise is present at SIG_IN.

Using this input, the VCO oscillates at the center frequency (f₀). Typical waveforms for the PC1

loop locked at f₀are shown in Fig. 6.

The frequency capture range (2f_c) is defined as the frequency range of input signals on which the

PLL locks when it was initially out-of-lock. The frequency lock range (2f_L) is the frequency range of

the input signals on which the loop stays locked when it was initially in lock. The capture range is

smaller or equal to the lock range.

With PC1, the capture range depends on the low-pass filter characteristics and can be made as

large as the lock range. This configuration remains locked even with very noisy input signals.

Typical behavior of this type of phase comparator is that it can lock to input frequencies close to the

harmonics of the VCO center frequency.

V

CC

V

DEM_OUT

(V)

1/2 V

CC

0

π/2

π

Ø

DEM_OUT(rad)

aaa-020206

Fig. 5. Phase comparator 1; average output voltage as a function of input phase

difference

SIG_IN

COMP_IN

VCO_OUT

PC1_OUT

V

CC

VCO_IN

GND

aaa-020207

Fig. 6. Typical waveforms for PLL using phase comparator 1; loop-locked at f₀

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Product data sheet

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

8.2.2. Phase Comparator 2 (PC2)

PC2 is a positive edge-triggered phase and frequency detector. When the PLL uses this

comparator, positive signal transitions control the loop and the duty cycles of SIG_IN and

COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state

output stage. The circuit functions as an up-down counter (see Fig. 4) where SIG_IN causes an

up-count and COMP_IN a down count. The transfer function of PC2, assuming ripple (f_r= f_i) is

suppressed, is:

where:

•

V_{DEM_OUT}is the demodulator output at pin DEM_OUT

V_{DEM_OUT}= V_{PC2_OUT}(via low-pass filter)

The phase comparator gain is:

V_{DEM_OUT}is the resultant of the initial phase differences of SIG_IN and COMP_IN as shown

in Fig. 7. Typical waveforms for the PC2 loop locked at f_oare shown in Fig. 8.

When the SIG_IN and COMP_IN frequencies are equal but the phase of SIG_IN leads that

of COMP_IN, the p-type output driver at PC2_OUT is held ‘ON’. The time that it is held 'ON’

corresponds with the phase difference (Φ_{DEM_OUT}). When the phase of SIG_IN lags that of

COMP_IN, the n-type driver is held ‘ON’.

When the SIG_IN frequency is higher than the COMP_IN frequency, the p-type output driver is

held ‘ON’ for most of the input signal cycle time. For the remainder of the cycle time, both n- and

p-type drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN frequency,

the n-type driver is held ‘ON’ for most of the cycle. The voltage at capacitor (C2) of the low-pass

filter, connected to PC2_OUT, varies until the phase and frequency of the signal and comparator

inputs are equal. At this stable point, the voltage on C2 remains constant as the PC2 output is

in 3-state and the VCO_IN input is in a high-impedance state. In this condition, the signal at the

phase comparator pulse output (PCP_OUT) is a HIGH level and can be used for indicating a

locked condition.

Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full frequency

range of the VCO. The power dissipation due to the low-pass filter is reduced because both n- and

p-type output drivers are ‘OFF’ for most of the signal input cycle. The PLL lock range for this type of

phase comparator is equal to the capture range and is independent of the low-pass filter. With no

signal present at SIG_IN the VCO adjust, via PC2, to its lowest frequency.

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Product data sheet

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8 / 37

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

V

CC

V

DEM_OUT

(V)

1/2 V

CC

0

-2π

0

2π

aaa-020208

Ø

DEM_OUT(rad)

Fig. 7. Phase comparator 2; average output voltage as a function of input phase

difference

SIG_IN

COMP_IN

VCO_OUT

V

CC

PC2_OUT

high impedance OFF - state

GND

VCO_IN

PCP_OUT

aaa-020209

Fig. 8. Typical waveforms for PLL using phase comparator 2; loop-locked at f₀

8.2.3. Phase Comparator 3 (PC3)

PC3 is a positive edge-triggered sequential phase detector using an RS-type flip-flop. When the

PLL is using this comparator, positive signal transitions control the loop and the duty factors of

SIG_IN and COMP_IN are not important. The transfer characteristic of PC3, assuming ripple

(f_r= f_i) is suppressed, is:

where:

•

V_{DEM_OUT}is the demodulator output at pin DEM_OUT

V_{DEM_OUT}= V_{PC3_OUT}(via low-pass filter)

The phase comparator gain is:

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Product data sheet

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

PC3 is fed to the VCO via the low-pass filter and present at the demodulator output at pin

DEM_OUT. The average output from PC3 is the resultant of the phase differences of SIG_IN and

COMP_IN, see Fig. 9. Typical waveforms for the PC3 loop locked at f_oare shown in Fig. 10.

The phase-to-output response characteristic of PC3 (Fig. 9) differs from PC2 in that the phase

angle between SIG_IN and COMP_IN varies between 0° and 360°. It is 180° at the center

frequency. Also PC3 gives a greater voltage swing than PC2 for input phase differences. As a

result, the ripple content of the VCO input signal is higher. The PLL lock range for this type of

phase comparator and the capture range are dependent on the low-pass filter. With no signal

present at SIG_IN, the VCO adjusts to its lowest frequency via PC3.

V

CC

V

DEM_OUT

(V)

1/2 V

CC

0

π

2π

aaa-020210

Ø

DEM_OUT(rad)

Fig. 9. Phase comparator 3; average output voltage as a function of input phase

difference

SIG_IN

COMP_IN

VCO_OUT

PC3_OUT

V

CC

VCO_IN

GND

aaa-020211

Fig. 10. Typical waveforms for PLL using phase comparator 3; loop-locked at f₀

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

9. Limiting values

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

+7

Unit

V

V_CC

I_IK

supply voltage

-0.5

input clamping current

output clamping current

output current

V_I< -0.5 V or V_I> V_CC+ 0.5 V

V_O< -0.5 V or V_O> V_CC+ 0.5 V

-0.5 V < V_O< V_CC+ 0.5 V

-

±20

±25

+50

-

mA

°C

I_OK

I_O

-

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

-50

-65

-

storage temperature

total power dissipation

+150

500

T_amb= -40 °C to +125 °C

[1]

mW

[1] For SOT109-1 (SO16) package: P_totderates linearly with 12.4 mW/K above 110 °C.

For SOT338-1 (SSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

For SOT403-1 (TSSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

10. Recommended operating conditions

Table 4. Recommended operating conditions

Symbol Parameter

Conditions

74HC4046A

74HCT4046A

Unit

Min

3.0

2.0

0

Typ

5.0

-

Max

6.0

Min

Typ

5.0

-

Max

V_CC

supply voltage

4.5

0

5.5

V

when VCO is not used

6.0

V_I

input voltage

V_CC

V_O

output voltage

0

-

0

-

Δt/ΔV

input transition rise and

fall rate

pin INH

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

1.67

-

625

139

83

-

ns/V

1.67

-

139 ns/V

ns/V

+125 °C

-

T_amb

ambient temperature

-40

+25

+125

-40

+25

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

11. Static characteristics

11.1. Static characteristics 74HC4046A

Table 5. Static characteristics 74HC4046A

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C

-40 °C to

+85 °C

-40 °C to Unit

+125 °C

Min Typ Max Min Max Min Max

Phase comparator section

V_IH

HIGH-level

input voltage

SIG_IN, COMP_IN; DC coupled

V_CC= 2.0 V

1.5 1.2

3.15 2.4

4.2 3.2

-

1.5

3.15

4.2

-

1.5

3.15

4.2

-

V

V_CC= 4.5 V

V_CC= 6.0 V

V_IL

LOW-level

input voltage

SIG_IN, COMP_IN; DC coupled

V_CC= 2.0 V

-

0.8 0.5

2.1 1.35

2.8 1.8

-

0.5

1.35

1.8

-

0.5

V

V_CC= 4.5 V

1.35 V

V_CC= 6.0 V

1.8

V

V_OH

HIGH-level

output voltage

PCP_OUT, PCn_OUT; V_I= V_IHor V_IL

I_O= -20 μA; V_CC= 2.0 V

I_O= -20 μA; V_CC= 4.5 V

I_O= -20 μA; V_CC= 6.0 V

I_O= -4 mA; V_CC= 4.5 V

I_O= -5.2 mA; V_CC= 6.0 V

PCP_OUT, PCn_OUT; V_I= V_IHor V_IL

I_O= 20 μA; V_CC= 2.0 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 20 μA; V_CC= 6.0 V

I_O= 4 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

SIG_IN, COMP_IN; V_I= V_CCor GND

V_CC= 2.0 V

1.9 2.0

4.4 4.5

5.9 6.0

3.98 4.32

5.48 5.81

-

1.9

4.4

-

1.9

4.4

5.9

3.7

5.2

-

V

5.9

3.84

5.34

V_OL

LOW-level

output voltage

-

0

0.1

-

0.1

-

0.1

0.4

V

0.1

0.15 0.26

0.16 0.26

0.33

I_I

input leakage

current

-

±3

±7

-

±4

±9

-

±5 μA

±11 μA

±27 μA

±45 μA

V_CC= 3.0 V

V_CC= 4.5 V

±18

±30

±23

±38

V_CC= 6.0 V

I_OZ

OFF-state

output current

PC2_OUT; V_I= V_IHor V_IL; V_O= V_CCor GND

V_CC= 6.0 V

-

±0.5

-

±5

-

±10 μA

R_I

input

SIG_IN, COMP_IN;

resistance

V_Iat self-bias operating point; ΔV_I= 0.5 V;

see Fig. 11, Fig. 12 and Fig. 13

V_CC= 3.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

800

250

150

-

kΩ

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to Unit

+125 °C

Min Typ Max Min Max Min Max

VCO section

V_IH

HIGH-level

INH

input voltage

V_CC= 3.0 V

2.1 1.7

3.15 2.4

4.2 3.2

-

2.1

3.15

4.2

-

2.1

3.15

4.2

-

V

V_CC= 4.5 V

V_CC= 6.0 V

V_IL

LOW-level

INH

input voltage

V_CC= 3.0 V

-

1.3 0.9

2.1 1.35

2.8 1.8

-

0.9

1.35

1.8

-

0.9

V

V_CC= 4.5 V

1.35 V

V_CC= 6.0 V

1.8

V

V_OH

HIGH-level

output voltage

VCO_OUT; V_I= V_IHor V_IL

I_O= -20 μA; V_CC= 3.0 V

I_O= -20 μA; V_CC= 4.5 V

I_O= -20 μA; V_CC= 6.0 V

I_O= -4 mA; V_CC= 4.5 V

I_O= -5.2 mA; V_CC= 6.0 V

VCO_OUT; V_I= V_IHor V_IL

I_O= 20 μA; V_CC= 3.0 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 20 μA; V_CC= 6.0 V

I_O= 4 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

C1A, C1B; V_I= V_IHor V_IL

I_O= 4 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

INH, VCO_IN; V_I= V_CCor GND

V_CC= 6.0 V

2.9 3.0

4.4 4.5

5.9 6.0

3.98 4.32

5.48 5.81

-

2.9

4.4

-

2.9

4.4

5.9

3.7

5.2

-

V

5.9

3.84

5.34

V_OL

LOW-level

output voltage

-

0

0.1

-

0.1

-

0.1

0.4

V

0.1

0.15 0.26

0.16 0.26

0.33

-

0.40

-

0.47

-

0.54 V

I_I

input leakage

current

-

3

-

±0.1

300

-

±1

-

±1 μA

R1

R2

C1

resistor 1

resistor 2

capacitor 1

V_CC= 3.0 V to 6.0 V

[1]

-

kΩ

pF

3

-

40

no

-

limit

V_{VCO_IN}input voltage

VCO_IN; over the range specified for R1;

on pin VCO_IN for linearity see Fig. 21 and Fig. 22

V_CC= 3.0 V

V_CC= 4.5 V

V_CC= 6.0 V

1.1

-

1.9

3.4

4.9

-

V

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Product data sheet

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13 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to Unit

+125 °C

Min Typ Max Min Max Min Max

Demodulator section

R_s

series

resistance

at R_s> 300 kΩ, the leakage current can

influence V_{DEM_OUT}

V_CC= 3.0 V to 6.0 V

50

-

300

-

kΩ

V_offset

offset voltage

VCO_IN to DEM_OUT;

V_I= V_{VCO_IN}= 0.5V_CC

;

values taken over R_srange; see Fig. 14

V_CC= 3.0 V

-

±30

±20

±10

-

mV

V_CC= 4.5 V

V_CC= 6.0 V

R_dyn

dynamic

resistance

DEM_OUT; V_{DEM_OUT}= 0.5V_CC

V_CC= 3.0 V to 6.0 V

-

25

-

Ω

General

I_CC

supply current VCO disabled; COMP_IN, INH and

SIG_IN at V_CC; VCO_IN at GND; I_Iat pins

COMP_IN and SIGN_IN to be excluded

V_CC= 6.0 V

-

8

-

80

-

160 μA

pF

C_I

input

INH

3.5

-

capacitance

[1] The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2 are/is > 10 kΩ.

11.2. Static characteristics 74HCT4046A

Table 6. Static characteristics 74HCT4046A

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to Unit

+125 °C

Min Typ Max Min Max Min Max

Phase comparator section

V_IH

HIGH-level

input voltage

SIG_IN, COMP_IN; DC coupled

V_CC= 4.5 V

3.15 2.4

-

3.15

-

3.15

-

V

V_IL

LOW-level

input voltage

SIG_IN, COMP_IN; DC coupled

V_CC= 4.5 V

-

2.1 1.35

1.35

1.35 V

V_OH

HIGH-level

output voltage

PCP_OUT, PCn_OUT; V_I= V_IHor V_IL

I_O= -20 μA; V_CC= 4.5 V

I_O= -4 μA; V_CC= 4.5 V

4.4 4.5

-

4.4

-

4.4

3.7

-

V

3.98 4.32

3.84

V_OL

LOW-level

output voltage

PCP_OUT, PCn_OUT; V_I= V_IHor V_IL

I_O= 20 μA; V_CC= 4.5 V

I_O= 4 mA; V_CC= 4.5 V

-

0

0.1

-

0.1

-

0.1

0.4

V

0.15 0.26

0.33

I_I

input leakage

current

SIG_IN, COMP_IN; V_I= V_CCor GND

V_CC= 5.5 V

-

±30

-

±38

±5

-

±45 μA

±10 μA

I_OZ

OFF-state

output current V_O= V_CCor GND

PC2_OUT; V_I= V_IHor V_IL;

V_CC= 5.5 V

±0.5

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Product data sheet

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14 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to Unit

+125 °C

Min Typ Max Min Max Min Max

R_I

input

SIG_IN, COMP_IN;

resistance

V_Iat self-bias operating point; ΔV_I= 0.5 V;

see Fig. 11, Fig. 12 and Fig. 13

V_CC= 4.5 V

-

250

-

kΩ

VCO section

V_IH

HIGH-level

INH

input voltage

V_CC= 4.5 V to 5.5 V

INH

2.0 1.6

2.0

-

2.0

-

V

V_IL

LOW-level

input voltage

V_CC= 4.5 V to 5.5 V

VCO_OUT; V_I= V_IHor V_IL

I_O= -20 μA; V_CC= 4.5 V

I_O= -4 mA; V_CC= 4.5 V

VCO_OUT; V_I= V_IHor V_IL

I_O= 20 μA; V_CC= 4.5 V

I_O= 4 mA; V_CC= 4.5 V

C1A, C1B; V_I= V_IHor V_IL

I_O= 4 mA; V_CC= 4.5 V

-

1.2 0.8

0.8

V_OH

HIGH-level

output voltage

4.4 4.5

-

4.4

-

4.4

3.7

-

V

3.98 4.32

3.84

V_OL

LOW-level

output voltage

-

0

0.1

-

0.1

-

0.1

0.4

V

0.15 0.26

0.33

-

0.40

±0.1

-

0.47

±1

-

0.54 V

±1 μA

I_I

input leakage

current

INH, VCO_IN; V_CC= 5.5 V;

V_I= V_CCor GND

R1

R2

C1

resistor 1

resistor 2

capacitor 1

V_CC= 4.5 V

[1]

3

-

300

-

kΩ

pF

40

no

limit

V_{VCO_IN}input voltage

VCO_IN; over the range specified for R1;

on pin VCO_IN for linearity see Fig. 21 and Fig. 22

V_CC= 4.5 V

1.1

50

-

3.4

-

V

Demodulator section

R_s

series

at R_s> 300 kΩ, the leakage current can

influence V_{DEM_OUT}

resistance

V_CC= 4.5 V

300

kΩ

V_offset

offset voltage

VCO_IN to DEM_OUT;

V_I= V_{VCO_IN}= 0.5V_CC

;

values taken over R_srange; see Fig. 14

V_CC= 4.5 V

-

±20

25

-

mV

Ω

R_dyn

dynamic

DEM_OUT; V_{DEM_OUT}= 0.5V_CC

V_CC= 4.5 V

resistance

General

I_CC

supply current VCO disabled; COMP_IN, INH and

SIG_IN at V_CC; VCO_IN at GND; I_Iat pins

COMP_IN and SIGN_IN to be excluded

V_CC= 6 V

-

8

-

80

-

160 μA

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Product data sheet

Rev. 5 — 8 June 2023

15 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to Unit

+125 °C

Min Typ Max Min Max Min Max

ΔI_CC

additional

INH; V_I= V_CC- 2.1 V; COMP_IN and

supply current SIG_IN at V_CC; VCO_IN at GND; I_Iat pins

COMP_IN and SIGN_IN to be excluded

V_CC= 4.5 V to 5.5 V

-

100 360

3.5

-

450

-

490 μA

pF

C_I

input

INH

-

capacitance

[1] The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2 are/is > 10 kΩ.

11.3. Graphs

aaa-020213

800

I

(µA)

R

I

(kΩ)

V

I

V

= 3.0 V

CC

600

400

200

0

4.5 V

6.0 V

self-bias operating point

0

V

(V)

I

1/2 V

-0.25

1/2 V

+0.25

CC

V (V)

I

aaa-020212

Fig. 11. Typical input resistance curve at SIG_IN and

COMP_IN

Fig. 12. Input resistance at SIG_IN, COMP_IN with

ΔV_I= 0.5 V at self-bias point

aaa-020215

+60

V

offset

(mV)

aaa-020214

+5

+40

V

= 6.0 V

CC

I

(µA)

V

= 3.0 V

CC

4.5 V

3.0 V

+20

0

4.5 V

0

3.0 V

6.0 V

-20

-40

4.5 V

6.0 V

1/2 V

-2

1/2 V

(V)

+2

CC

V

VCO_IN

-5

1/2 V

___ R_s= 50 kΩ

- - - R_s= 300 kΩ

-0.25

1/2 V

+0.25

CC

V (V)

I

Fig. 13. Input current at SIG_IN, COMP_IN with

ΔV_I= 0.5 V at self-bias point

Fig. 14. Offset voltage at demodulator output as

a function of V_{VCO_IN}and R_s

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Product data sheet

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16 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

12. Dynamic characteristics

12.1. Dynamic characteristics 74HC4046A

Table 7. Dynamic characteristics 74HC4046A

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF.

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to Unit

+125 °C

Min Typ Max Min Typ Max Min Max

Phase comparator section

t_pd

propagation SIG_IN, COMP_IN to PC1_OUT;

delay see Fig. 15

[1]

V_CC= 2.0 V

-

63 200

-

250

50

-

300 ns

60 ns

51 ns

V_CC= 4.5 V

V_CC= 6.0 V

23

18

40

34

43

SIG_IN, COMP_IN to PCP_OUT;

see Fig. 15

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

96 340

-

425

85

-

510 ns

102 ns

87 ns

35

28

68

58

72

SIG_IN, COMP_IN to PC3_OUT;

see Fig. 15

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

77 270

-

340

68

-

405 ns

81 ns

69 ns

28

22

54

46

58

t_en

enable time SIG_IN, COMP_IN to PC2_OUT;

see Fig. 16

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

83 280

-

350

70

-

420 ns

84 ns

71 ns

30

24

56

48

60

t_dis

disable time SIG_IN, COMP_IN to PC2_OUT;

see Fig. 16

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

99 325

-

405

81

-

490 ns

98 ns

83 ns

36

29

65

55

69

t_t

transition

time

PC1_OUT, PC3_OUT, PCP_OUT;

see Fig. 15

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

19

7

75

15

13

-

95

19

16

-

110 ns

22 ns

19 ns

6

V_i(p-p)

peak-to-peak SIGN_IN, COMP_IN; AC coupled;

input voltage f_i= 1 MHz

V_CC= 2.0 V

V_CC= 3.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

9

-

mV

11

15

33

mV

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Product data sheet

Rev. 5 — 8 June 2023

17 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Symbol Parameter

Conditions

25 °C

-40 °C to +85 °C -40 °C to Unit

+125 °C

Min Typ Max Min Typ Max Min Max

VCO section

f₀

center

frequency

V_{VCO_IN}= 0.5V_CC; duty cycle = 50 %;

R1 = 3 kΩ; R2 = ∞ Ω; C1 = 40 pF;

see Fig. 19 and Fig. 20

V_CC= 3.0 V

V_CC= 4.5 V

V_CC= 5.0 V

V_CC= 6.0 V

7.0 10.0

11.0 17.0

-

MHz

-

19.0

13.0 21.0

Δf/f

relative

frequency

variation

R1 = 100 kΩ; R2 = ∞ Ω; C1 = 100 pF;

see Fig. 21 and Fig. 22

V_CC= 3.0 V

-

1.0

0.4

0.3

-

%

V_CC= 4.5 V

V_CC= 6.0 V

Δf/ΔT

frequency

V_{VCO_IN}= 0.5V_CC; R1 = 100 kΩ;

variation with R2 = ∞ Ω; C1 = 100 pF;

temperature see Fig. 17 and Fig. 18

V_CC= 3.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

0.20

0.15

0.14

-

%/K

%

-

δ

duty cycle

VCO_OUT; V_CC= 3.0 V to 6.0 V

50

General

C_PD

power

dissipation

capacitance

[2]

[3]

-

24

-

pF

[1] t_pdis the same as t_PLHand t_PHL. t_disis the same as t_PLZand t_PHZ. t_enis the same as t_PZLand t_PZH. t_tis the same as t_TLHand t_THL

.

[2] Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator sections, see

Fig. 23, Fig. 24 and Fig. 25

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = total load switching outputs;

Σ(C_L× V_CC²× f_o) = sum of outputs.

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Product data sheet

Rev. 5 — 8 June 2023

18 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

12.2. Dynamic characteristics 74HCT4046A

Table 8. Dynamic characteristics 74HCT4046A

GND = 0 V; t_r= t_f= 6 ns; C_L= 50 pF.

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to Unit

+125 °C

Min Typ Max Min Max Min Max

Phase comparator section

t_pd

propagation

delay

V_CC= 4.5 V; see Fig. 15

[1]

SIG_IN, COMP_IN to PC1_OUT

SIG_IN, COMP_IN to PCP_OUT

SIG_IN, COMP_IN to PC3_OUT

-

23

35

28

30

40

68

54

56

-

50

85

68

70

-

60 ns

102 ns

81 ns

84 ns

t_en

enable time

disable time

SIG_IN, COMP_IN to PC2_OUT;

V_CC= 4.5 V; see Fig. 16

[1]

t_dis

t_t

SIG_IN, COMP_IN to PC2_OUT;

V_CC= 4.5 V; see Fig. 16

-

36

7

65

15

-

81

19

-

98 ns

22 ns

transition time PC1_OUT, PC3_OUT, PCP_OUT;

V_CC= 4.5 V; see Fig. 15

V_i(p-p)

peak-to-peak

input voltage

SIGN_IN, COMP_IN; AC coupled;

V_CC= 4.5 V; f_i= 1 MHz

15

-

mV

VCO section

f₀

center

frequency

V_{VCO_IN}= 0.5V_CC; duty cycle = 50 %;

R1 = 3 kΩ; R2 = ∞ Ω; C1 = 40 pF;

see Fig. 19 and Fig. 20

V_CC= 4.5 V

V_CC= 5.0 V

11.0 17.0

-

MHz

%

-

19.0

0.4

Δf/f

relative

R1 = 100 kΩ; R2 = ∞ Ω; C1 = 100 pF;

V_CC= 4.5 V; see Fig. 21 and Fig. 22

frequency

variation

Δf/ΔT

frequency

variation with

temperature

V_{VCO_IN}= 0.5V_CC; R1 = 100 kΩ;

R2 = ∞ Ω; C1 = 100 pF; V_CC= 4.5 V;

see Fig. 17 and Fig. 18

-

0.15

-

%/K

δ

duty cycle

VCO_OUT; V_CC= 4.5 V

-

50

24

-

%

General

C_PD

power

dissipation

capacitance

[2]

[3]

pF

[1] t_pdis the same as t_PLHand t_PHL. t_disis the same as t_PLZand t_PHZ. t_enis the same as t_PZLand t_PZH. t_tis the same as t_TLHand t_THL

.

[2] Applies to the phase comparator section only (VCO disabled).

For power dissipation of the VCO and demodulator sections, see Fig. 23, Fig. 24 and Fig. 25

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = total load switching outputs;

Σ(C_L× V_CC²× f_o) = sum of outputs.

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Product data sheet

Rev. 5 — 8 June 2023

19 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

12.3. Waveforms and graphs

V

I

SIG_IN

COMP_IN

V

M

GND

t

PLH

PHL

V

OH

PC1_OUT

PC3_OUT

PCP_OUT

V

M

V

OL

t

THL

TLH

aaa-020216

V_M= 0.5V_CC; V_I= GND to V_CC

.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 15. Waveforms showing input (SIG_IN, COMP_IN) to output (PC1_OUT, PC3_OUT, PCP_OUT) propagation

delays and the output transition times

V

I

SIG_IN

V

M

GND

V

I

COMP_IN

V

COMP_IN

V

M

GND

t

PZL

PZH

t

PLZ

PHZ

V

OH

90 %

V

M

PC2_OUT

M

10 %

V

OL

aaa-020218

V_M= 0.5V_CC; V_I= GND to V_CC

.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 16. Waveforms showing the enable and disable times for PC2_OUT

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Product data sheet

Rev. 5 — 8 June 2023

20 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

25

f

25

f

25

f

(%)

V

= 3 V

V

= 3 V

CC

3 V

5 V

CC

20

15

10

5

20

15

10

5

20

15

10

5

6 V

V

= 6 V

5 V

CC

5 V

6 V

3 V

A

5 V

6 V

5 V

6 V

3 V

0

3 V

4.5 V

5 V

6 V

-5

-10

-15

-20

-10

-15

-20

-25

-10

-15

-20

-25

-50

0

50

(a)

100

150

(°C)

-50

0

50

(b)

100

150

(°C)

-50

0

50

(c)

100

150

(°C)

T

amb

aaa-020259

To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.

In (b), the frequency stability for R1 = R2 = 10 kΩ at 5 V is also given (curve A). The total VCO bias current

sets this curve, and is not simply the addition of the two 10 kΩ stability curves. C1 = 100 pF; V_{VCO_IN}= 0.5V_CC

This curve is set as follows:

;

___ Without offset R2 = ∞ Ω: (a) R1 = 3 kΩ; (b) R1 = 10 kΩ; (c) R1 = 300 kΩ.

- - - With offset R1 = ∞ Ω: (a) R2 = 3 kΩ; (b) R2 = 10 kΩ; (c) R2 = 300 kΩ.

Fig. 17. Frequency stability of the VCO as a function of ambient temperature

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Product data sheet

Rev. 5 — 8 June 2023

21 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

25

f

25

f

25

f

(%)

V

= 3 V

V

= 3 V

CC

20

15

10

5

20

15

10

5

20

15

10

5

V

= 6 V

5 V

CC

5 V

6 V

5 V

6 V

3 V

0

-5

-10

-15

-20

-10

-15

-20

-25

-10

-15

-20

-25

-50

0

50

(a)

100

150

(°C)

-50

0

50

(b)

100

150

(°C)

-50

0

50

(c)

100

150

(°C)

T

amb

aaa-020362

To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.

___ With offset; R1 = ∞ Ω: (a) R2 = 3 kΩ; (b) R2 = 10 kΩ; (c) R2 = 300 kΩ.

Fig. 18. Frequency stability of the VCO as a function of ambient temperature

30

80

f

VCO

V

= 6 V

CC

(MHz)

f

VCO

(kHz)

V

= 6 V

CC

25

4.5 V

60

20

15

10

5

4.5 V

3 V

40

20

0

3 V

0

2

4

6

0

2

4

6

V

(V)

V

(V)

VCO_IN

(a)

(b)

aaa-020363

To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.

(a) R1 = 3 kΩ; C1 = 40 pF (b) R1 = 3 kΩ; C1 = 100 nF

Fig. 19. Graphs showing VCO frequency as a function of the VCO input voltage

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74HC_HCT4046A

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Product data sheet

Rev. 5 — 8 June 2023

22 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

1000

500

V

= 6 V

CC

f

VCO

(Hz)

(kHz)

V

= 6 V

CC

800

600

400

200

0

400

300

200

100

0

4.5 V

3 V

0

2

4

6

0

2

4

6

V

(V)

V

(V)

VCO_IN

(a)

(b)

aaa-020364

To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF.

(a) R1 = 300 kΩ; C1 = 40 pF (b) R1 = 300 kΩ; C1 = 100 nF

Fig. 20. Graphs showing VCO frequency as a function of the VCO input voltage

10

V

= 3 V

CC

f

VCO

(%)

C1 = 1 µF

5

f

4.5 V

6 V

f

2

f

0

f

0'

V

= 4.5 V

CC

C1 = 100 pF

f

1

0

6 V

V

4.5 V

0

C1 = 40 pF

min

1/2 V

max

V

VCO_IN

CC

aaa-020365

ΔV = 0.5 V over the V_CCrange.

3 V

-5

2

3

1

10

R1 (kΩ)

aaa-020367

linearity =

R2 = ∞ Ω; ΔV = 0.5 V

Fig. 21. Definition of VCO frequency linearity

Fig. 22. Frequency linearity as a function of R1, C1

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74HC_HCT4046A

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Product data sheet

Rev. 5 — 8 June 2023

23 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

aaa-020368

aaa-020369

6

5

4

3

2

10

P

R2

(µW)

R1

(µW)

5

4

3

2

10

V

=

CC

V

=

CC

6 V

4.5 V

3 V

4.5 V

3 V

2

3

2

3

1

10

1

10

R1 (kΩ)

R2 (kΩ)

R2 = ∞ Ω; C_L= 50 pF; V_{VCO_IN}= 0.5V_CC

T_amb= 25 °C

;

R1 = ∞ Ω; C_L= 50 pF; V_{VCO_IN}= GND;

T_amb= 25 °C

___ C1 = 40 pF; - - - C1 = 1 μF

Fig. 23. Power dissipation as a function of R1

Fig. 24. Power dissipation as a function of R2

aaa-020370

3

10

P

DEM

(µW)

2

10

V

CC

6 V

=

4.5 V

3 V

10

2

3

10

R

S

(kΩ)

R1 = R2 = ∞ Ω; V_{VCO_IN}= 0.5V_CC; T_amb= 25 °C

Fig. 25. Typical power dissipation of demodulator sections as a function of R_s

13. Application information

This information is a guide for the approximation of values of external components to be used with

the 74HC4046A; 74HCT4046A in a phase-locked-loop system.

References should be made to Fig. 29, Fig. 30 and Fig. 31 as indicated in Table 10.

Values of the selected components should be within the ranges shown in Table 9.

Table 9. Survey of components

Component

Value

R1

between 3 kΩ and 300 kΩ

parallel value > 2.7 kΩ

> 40 pF

R2

R1 + R2

C1

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Product data sheet

Rev. 5 — 8 June 2023

24 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Table 10. Design considerations for VCO section

Subject

Phase

Design consideration

comparator

VCO frequency

without extra

offset

PC1, PC2 or PC3 VCO frequency characteristic. With R2 = ∞ Ω and R1 within the range

3 kΩ < R1 < 300 kΩ, the characteristics of the VCO operation is as shown in

Fig. 26a. (Due to R1, C1 time constant a small offset remains when R2 = ∞ Ω).

PC1

Selection of R1 and C1. Given f₀, determine the values of R1 and C1 using Fig. 29.

PC2 or PC3

Given f_maxand f₀, determine the values of R1 and C1 using Fig. 29;

use Fig. 31 to obtain 2f_Land then use it to calculate f_min

.

VCO frequency

with extra offset

PC1, PC2 or PC3 VCO frequency characteristic. With R1 and R2 within the

ranges 3 kΩ < R1 < 300 kΩ and 3 kΩ < R2 < 300 kΩ.

The characteristics of the VCO operation are as shown in Fig. 26b.

PC1, PC2 or PC3 Selection of R1, R2 and C1. Given f₀and f_Ldetermine the value

of product R1C1 by using Fig. 31. Calculate f_offfrom the equation

f_off= f₀- 1.6f_L. Obtain the values of C1 and R2 by using Fig. 30.

Calculate the value of R1 from the value of C1 and the product R1C1.

PLL conditions

no signal at pin

SIG_IN

PC1

PC2

PC3

VCO adjusts to f₀with Φ_{DEM_OUT}= 90° and V_{VCO_IN}= 0.5V_CC, see Fig. 5

VCO adjusts to f₀with Φ_{DEM_OUT}= -360° and V_{VCO_IN}= minimum, see Fig. 7

VCO adjusts to f₀with Φ_{DEM_OUT}= -360° and V_{VCO_IN}= minimum, see Fig. 9

f

VCO

f

max

due to

R , C

2f

f

0

L

1

f

min

0.9 V

1/2 V

V

-0.9 V

V

CC

VCO_IN

aaa-020371

a. Operating without offset; f₀= center frequency; 2f_L= frequency lock range.

f

VCO

f

max

due to

R , C

f

2f

L

0

1

f

min

f

off

due to

R , C

2

1

0.9 V

1/2 V

V

-0.9 V

V

CC

VCO_IN

aaa-020372

b. Operating with offset; f₀= center frequency; 2f_L= frequency lock range.

Fig. 26. Frequency characteristic of VCO

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Product data sheet

Rev. 5 — 8 June 2023

25 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Table 11. General design considerations

Subject

Phase comparator

Design consideration

PLL frequency capture range

PC1, PC2 or PC3

PC1 or PC3

PC2

Loop filter component selection, see Fig. 27 and Fig. 28

PLL locks on harmonics at

center frequency

yes

no

Noise rejection at signal input

PC1

high

PC2 or PC3

low

AC ripple content when PLL is PC1

f_r= 2f_i; large ripple content at Φ_{DEM_OUT}= 90°

f_r= f_i; small ripple content at Φ_{DEM_OUT}= 0°

f_r= f_i; large ripple content at Φ_{DEM_OUT}= 180°

locked

PC2

PC3

F

(jω)

R3

-1/

τ

C2

input

output

ω

(a)

(b)

(c)

aaa-020446

R3 ≥ 500 Ω.

A small capture range (2f_c) is obtained if

(a)

(b) amplitude characteristics

(c) pole-zero diagram

Fig. 27. Simple loop filter for PLL without offset

F

(jω)

m

R3

-1/

τ2

-1/

τ3

R4

C2

input

output

R4

R3 + R4

m =

1/

ω

τ3

τ2

(a)

(b)

(c)

aaa-020447

R3 + R4 ≥ 500 Ω.

(a)

(b) amplitude characteristics

(c) pole-zero diagram

Fig. 28. Simple loop filter for PLL with offset

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Product data sheet

Rev. 5 — 8 June 2023

26 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

aaa-020448

8

7

6

5

4

3

2

10

f

o

R1 = 3 kΩ

10 kΩ

(Hz)

10

V

=

CC

10

150 kΩ

300 kΩ

5 V

4.5 V

6 V

5 V

4.5 V

3 V

5 V

4.5 V

3 V

5 V

4.5 V

3 V

10

2

3

4

5

6

7

1

10

C1 (pF)

To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.

Interpolation for various values of R1 can be easily calculated because a constant R1C1 product produces almost

the same VCO output frequency.

R2 = ∞ Ω; V_{VCO_IN}= 0.5V_CC; INH = GND; T_amb= 25 °C.

Fig. 29. Typical value of VCO center frequency (f₀) as a function of C1

aaa-020449

8

10

f

off

R2 = 3 kΩ

10 kΩ

(Hz)

7

6

5

4

3

2

10

V

=

CC

5 V

4.5 V

150 kΩ

300 kΩ

10

6 V

5 V

4.5 V

3 V

5 V

4.5 V

5 V

4.5 V

3 V

10

2

3

4

5

6

7

1

10

C1 (pF)

To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.

Interpolation for various values of R2 can be easily calculated because a constant R2C1 product produces almost

the same VCO output frequency.

R1 = ∞ Ω; V_{VCO_IN}= 0.5V_CC; INH = GND; T_amb= 25 °C.

Fig. 30. Typical value of frequency offset as a function of C1

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Product data sheet

Rev. 5 — 8 June 2023

27 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

aaa-020450

8

7

6

5

4

3

2

10

2f

L

(Hz)

10

V

= 6 V

5 V

CC

4.5 V

3 V

10

-7

-6

-5

-4

-3

-2

-1

10

1

R1C1 (pF)

V_{VCO_IN}= 0.9 V to (V_CC- 0.9) V; R2 = ∞ Ω.

VCO gain:

Fig. 31. Typical frequency lock range (2f_L) as a function of the product R1C1

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74HC_HCT4046A

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Product data sheet

Rev. 5 — 8 June 2023

28 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

13.1. PLL design example

The frequency synthesizer used in the design example shown in Fig. 32 has the following

parameters:

•

Output frequency: 2 MHz to 3 MHz

Frequency steps: 100 kHz

Settling time: 1 ms

Overshoot: < 20 %

The open loop gain is:

where:

•

K_p(s) = phase comparator gain

K_f(s) = low-pass filter transfer gain

K_o(s) = K_v/s VCO gain

K_n= ¹⁄_ndivider ratio

The programmable counter ratio K_ncan be found as follows:

The values of R1, R2 and C1; R2 = 10 kΩ (adjustable) set the VCO.

The values can be determined using the information in Table 10 and Table 11.

With f₀= 2.5 MHz and f_L= 500 kHz, the following values (V_CC= 5.0 V) are given:

•

R1 = 10 kΩ

R2 = 10 kΩ

C1 = 500 pF

The VCO gain is:

The gain of the phase comparator is:

The transfer gain of the filter is calculated as follows:

Where:

The characteristic equation is:

It results in:

©

74HC_HCT4046A

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Product data sheet

Rev. 5 — 8 June 2023

29 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

The natural frequency ω_nis defined as:

and the damping value (ζ) given as:

In Fig. 33, the output frequency response to a step of input frequency is shown.

The overshoot and settling time percentages are now used to determine ω_n. Fig. 33 shows that the

damping ratio ζ = 0.45 produces an overshoot of less than 20 % and settle to within 5 % at ω_nt = 5.

The required settling time is 1 ms. It results in:

Rewriting the equation for natural frequency results in:

The maximum overshoot occurs at N_max

:

When C2 = 470 nF, then:

R3 can be calculated:

74HC4046A; 74HCT4046A

K

o

p

f

100 kHz

PHASE

COMPARATOR

PC2

R3

9

13

4

OSCILLATOR

74HCU04

DIVIDE - BY 10

74HC191

14

3

f

VCO

6

out

11

12

7

5

R4

C2

R1

R2

K

n

1 MHz

C1

PROGRAMMABLE

DIVIDER

4 x 74HC161

aaa-020451

Fig. 32. Frequency synthesizer

aaa-020452

1.6

(t)

-0.6

ζ = 0.3

0.5

ω

Θ (t)

e

Θ /ω

e n

e

ω /ω

e

n

0.707

1.0

1.2

0.8

0.4

0

-0.2

ζ = 5.0

ζ = 2.0

0.2

0.6

1.0

0

2

4

6

8

ω

(t)

n

Fig. 33. Type 2, second order frequency step response

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74HC_HCT4046A

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Product data sheet

Rev. 5 — 8 June 2023

30 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

aaa-020453

3.1

(1)

Frequency

N = 30

(MHz)

3.0

N stepped from 29 to 30

2.9

2.1

2.0

1.9

step input

N stepped from 21 to 20

0

0.5

1

1.5

2

2.5

time (ms)

The output frequency is proportional to the VCO control voltage. As a result, the PLL frequency response can

be observed with an oscilloscope by monitoring pin VCO_IN of the VCO. The average frequency response, as

calculated by the Laplace method, is found experimentally by smoothing this voltage at pin VCO_IN using a

simple RC filter. The filter has a long time constant when compared with the phase detector sampling rate, but

short when compared with the PLL response time.

Fig. 34. Frequency compared to the time response

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Product data sheet

Rev. 5 — 8 June 2023

31 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

14. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.0100

0.0075

0.010 0.057

0.004 0.049

0.019

0.014

0.39

0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig. 35. Package outline SOT109-1 (SO16)

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74HC_HCT4046A

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Product data sheet

Rev. 5 — 8 June 2023

32 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A

X

c

y

H

E

v

M

A

Z

9

16

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

8

1

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

3

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

mm

2

0.2

0.13

0.1

0.25

0.65

1.25

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT338-1

MO-150

Fig. 36. Package outline SOT338-1 (SSOP16)

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74HC_HCT4046A

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Product data sheet

Rev. 5 — 8 June 2023

33 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

1

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig. 37. Package outline SOT403-1 (TSSOP16)

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74HC_HCT4046A

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Product data sheet

Rev. 5 — 8 June 2023

34 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

15. Abbreviations

Table 12. Abbreviations

Acronym

Description

CDM

CMOS

DUT

ESD

HBM

PLL

Charged Device Model

Complementary Metal Oxide Semiconductors

Device Under Test

ElectroStatic Discharge

Human Body Model

Phase-Locked Loop

VCO

Voltage Controlled Oscillator

16. Revision history

Table 13. Revision history

Document ID

Release date Data sheet status

20230608 Product data sheet

Change notice Supersedes

74HC_HCT4046A v.5

Modifications:

-

74HC_HCT4046A v.4

•

Type number 74HCT4046APW (SOT403-1 / TSSOP16) added.

Section 2 updated.

Section 9: Derating values for P_tottotal power dissipation updated.

74HC_HCT4046A v.4

Modifications:

20190806

Product data sheet

-

74HC_HCT4046A v.3

•

The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Typo corrected in Fig. 19 and Fig. 20.

74HC_HCT4046A v.3

Modifications:

20160608

Product data sheet

-

74HC_HCT4046A_CNV v.2

•

The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•

Legal texts have been adapted to the new company name where appropriate.

74HC_HCT4046A_CNV v.2 19971125

Product specification

Objective specification

-

74HC_HCT4046A v.1

-

74HC_HCT4046A v.1

19930901

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Product data sheet

Rev. 5 — 8 June 2023

35 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

17. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

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sold subject to the general terms and conditions of commercial sale, as

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terms and conditions with regard to the purchase of Nexperia products by

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©

74HC_HCT4046A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 8 June 2023

36 / 37

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Applications.................................................................. 1

4. Ordering information....................................................2

5. Block diagram...............................................................2

6. Functional diagram.......................................................2

7. Pinning information......................................................4

7.1. Pinning.........................................................................4

7.2. Pin description.............................................................5

8. Functional description................................................. 6

8.1. VCO.............................................................................6

8.2. Phase comparators......................................................6

8.2.1. Phase Comparator 1 (PC1)......................................6

8.2.2. Phase Comparator 2 (PC2)......................................8

8.2.3. Phase Comparator 3 (PC3)......................................9

9. Limiting values........................................................... 11

10. Recommended operating conditions......................11

11. Static characteristics................................................12

11.1. Static characteristics 74HC4046A............................12

11.2. Static characteristics 74HCT4046A......................... 14

11.3. Graphs..................................................................... 16

12. Dynamic characteristics.......................................... 17

12.1. Dynamic characteristics 74HC4046A...................... 17

12.2. Dynamic characteristics 74HCT4046A.................... 19

12.3. Waveforms and graphs............................................20

13. Application information........................................... 24

13.1. PLL design example................................................29

14. Package outline........................................................ 32

15. Abbreviations............................................................35

16. Revision history........................................................35

17. Legal information......................................................36

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 8 June 2023

©

74HC_HCT4046A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 8 June 2023

37 / 37


型号：	74HCT4046AD
厂家：	Nexperia
描述：	Phase-locked-loop with VCOProduction 光电二极管
文件：	总37页 (文件大小：561K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HCT4046AD [NEXPERIA]

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