74HCT595PW_技术文档

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output

latches; 3-state

Rev. 11 — 10 September 2021

Product data sheet

1. General description

The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage

register and 3-state outputs. Both the shift and storage register have separate clocks. The device

features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous

reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH

transitions of the SHCP input. The data in the shift register is transferred to the storage register

on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift

register will always be one clock pulse ahead of the storage register. Data in the storage register

appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the

outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the

state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors

to interface inputs to voltages in excess of V_CC

.

2. Features and benefits

•

Wide supply voltage range from 2.0 to 6.0 V

•

CMOS low power dissipation

High noise immunity

8-bit serial input

8-bit serial or parallel output

Storage register with 3-state outputs

Shift register with direct clear

100 MHz (typical) shift out frequency

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standards:

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

•

Input levels:

•

For 74HC595: CMOS level

For 74HCT595: TTL level

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

•

Multiple package options

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Applications

•

Serial-to-parallel data conversion

Remote control holding register

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

4. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74HC595D

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74HCT595D

74HC595PW

74HCT595PW

74HC595BQ

74HCT595BQ

TSSOP16

plastic thin shrink small outline package; 16 leads; SOT403-1

body width 4.4 mm

DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 16 terminals;

body 2.5 × 3.5 × 0.85 mm

SOT763-1

74HC595BZ

-40 °C to +125 °C

DHXQFN16 plastic, leadless dual in-line compatible thermal

enhanced extreme thin quad flat package;

no leads; 16 terminals; 0.4 mm pitch;

SOT8016-1

body 2 mm × 2.4 mm × 0.48 mm

5. Functional diagram

14 DS

11 SHCP

10 MR

8-STAGE SHIFT REGISTER

Q7S

9

12 STCP

13 OE

8-BIT STORAGE REGISTER

3-STATE OUTPUTS

Q0

15

Q1 Q2 Q3 Q4 Q5 Q6 Q7

1

2

3

4

5

6

7

mna554

Fig. 1. Functional diagram

13

12

EN3

C2

11

12

10

11

SHCP

SRG8

STCP

R

9

15

1

C1/

Q7S

Q0

Q1

Q2

Q3

Q4

Q5

Q6

14

15

1

1D

2D

3

2

14

3

DS

3

4

5

6

7

Q7

7

MR

10

OE

9

13

mna552

mna553

Fig. 2. Logic symbol

Fig. 3. IEC logic symbol

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74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

2 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

STAGE 0

Q

STAGES 1 TO 6

STAGE 7

D Q

DS

Q7S

D

Q

FF7

CP

FF0

CP

R

SHCP

MR

D

Q

D

Q

LATCH

CP

LATCH

CP

STCP

OE

mna555

Q0

Q1 Q2 Q3 Q4 Q5 Q6

Q7

Fig. 4. Logic diagram

6. Pinning information

6.1. Pinning

74HC595

74HCT595

terminal 1

index area

2

3

4

5

6

7

15

14

13

12

11

10

Q2

Q0

Q3

Q4

Q5

Q6

Q7

DS

74HC595

74HCT595

OE

STCP

SHCP

MR

1

2

3

4

5

6

7

8

16

V

Q1

Q2

CC

(1)

GND

15

14

13

12

11

10

9

Q0

Q3

DS

Q4

OE

001aao243

Q5

STCP

SHCP

MR

Q6

Transparent top view

Q7

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

GND

Q7S

001aao242

Fig. 5. Pin configuration for SOT109-1 (SO16) and

SOT403-1 (TSSOP16)

Fig. 6. Pin configuration for SOT763-1 (DHVQFN16)

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74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

3 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

74HC595

terminal 1

index area

2

3

4

5

6

7

15

14

13

12

11

10

Q2

Q3

Q4

Q5

Q6

Q7

Q0

DS

OE

STCP

SHCP

MR

(1)

GND

aaa-032839

Transparent top view

(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered,

the solder land should remain floating or connected to GND.

Fig. 7. Pin configuration SOT8016-1 (DHXQFN16)

6.2. Pin description

Table 2. Pin description

Symbol

Description

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

15, 1, 2, 3, 4, 5, 6, 7

parallel data output

ground (0 V)

GND

Q7S

MR

8

9

serial data output

10

11

12

13

14

15

16

master reset (active LOW)

shift register clock input

storage register clock input

output enable input (active LOW)

serial data input

SHCP

STCP

OE

DS

Q0

parallel data output 0

supply voltage

V_CC

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74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

4 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

7. Functional description

Table 3. Function table

H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition;

X = don’t care; NC = no change; Z = high-impedance OFF-state.

Control

Input Output

Function

SHCP STCP OE

MR

L

DS

X

Q7S Qn

X

↑

X

↑

L

H

L

NC

L

a LOW-level on MR only affects the shift registers

empty shift register loaded into storage register

L

X

L

X

Z

shift register clear; parallel outputs in high-impedance OFF-state

H

Q6S NC

logic HIGH-level shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).

X

↑

L

H

X

NC

QnS contents of shift register stages (internal QnS) are transferred to the

storage register and parallel output stages

Q6S QnS contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

SHCP

DS

STCP

MR

OE

Q0

Z-state

Q1

Z-state

Q6

Q7

Q7S

mna556

Fig. 8. Timing diagram

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74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

5 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

8. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

+7

Unit

V

V_CC

I_IK

supply voltage

-0.5

input clamping current

output clamping current

output current

V_I< -0.5 V or V_I> V_CC+ 0.5 V

V_O< -0.5 V or V_O> V_CC+ 0.5 V

V_O= -0.5 V to (V_CC+ 0.5 V)

pin Q7S

-

±20

mA

I_OK

I_O

-

±25

±35

70

mA

°C

pins Qn

-

I_CC

supply current

I_GND

T_stg

P_tot

ground current

-70

-65

-

storage temperature

total power dissipation

+150

500

250

SOT109-1; SOT403-1; SOT763-1

SOT8016-1

[1]

mW

-

[1] For SOT109-1 (SO16) package: P_totderates linearly with 12.4 mW/K above 110 °C.

For SOT403-1 (TSSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

For SOT763-1 (DHVQFN16) package: P_totderates linearly with 11.2 mW/K above 106 °C.

9. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter

Conditions

74HC595

74HCT595

Unit

Min

Typ

Max

6.0

Min

Typ

Max

5.5

V_CC

-

V_CC

V_I

supply voltage

input voltage

output voltage

2.0

5.0

4.5

5.0

V

0

-

V_CC

625

139

83

0

-

V

V_O

-

V

Δt/ΔV

input transition rise and fall

rate

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

-

ns/V

-

1.67

-

1.67

-

139 ns/V

ns/V

+125 °C

-

T_amb

ambient temperature

-40

+25

+125

-40

+25

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74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

6 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

10. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Typ

Max

Min

Max

74HC595

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_CC= 2.0 V

V_CC= 4.5 V

V_CC= 6.0 V

V_I= V_IHor V_IL

all outputs

1.5

1.2

2.4

3.2

0.8

2.1

2.8

-

1.5

-

V

3.15

4.2

-

4.2

-

V_IL

LOW-level

input voltage

-

0.5

1.35

1.8

-

0.5

1.35

1.8

V_OH

HIGH-level

output voltage

I_O= -20 μA; V_CC= 2.0 V

1.9

4.4

5.9

2.0

4.5

6.0

-

1.9

4.4

5.9

-

V

I_O= -20 μA; V_CC= 4.5 V

I_O= -20 μA; V_CC= 6.0 V

Q7S output

I_O= -4 mA; V_CC= 4.5 V

I_O= -5.2 mA; V_CC= 6.0 V

Qn bus driver outputs

I_O= -6 mA; V_CC= 4.5 V

I_O= -7.8 mA; V_CC= 6.0 V

V_I= V_IHor V_IL

3.84

5.34

4.32

5.81

-

3.7

5.2

-

V

3.84

5.34

4.32

5.81

-

3.7

5.2

-

V

V_OL

LOW-level

output voltage

all outputs

I_O= 20 μA; V_CC= 2.0 V

I_O= 20 μA; V_CC= 4.5 V

I_O= 20 μA; V_CC= 6.0 V

Q7S output

-

0

0.1

-

0.1

V

I_O= 4 mA; V_CC= 4.5 V

I_O= 5.2 mA; V_CC= 6.0 V

Qn bus driver outputs

I_O= 6 mA; V_CC= 4.5 V

I_O= 7.8 mA; V_CC= 6.0 V

-

0.15

0.16

0.33

-

0.4

V

-

0.15

0.16

-

0.33

±1.0

-

0.4

V

I_I

input leakage V_I= V_CCor GND; V_CC= 6.0 V

current

±1.0

μA

I_OZ

I_CC

C_I

OFF-state

output current V_O= V_CCor GND

V_I= V_IHor V_IL; V_CC= 6.0 V;

-

±5.0

80

-

±10

160

-

μA

pF

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 6.0 V

input

3.5

capacitance

©

74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

7 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Symbol Parameter

74HCT595

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Typ

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

1.6

1.2

-

2.0

-

V

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

all outputs

I_O= -20 μA

4.4

3.84

3.7

4.5

-

4.4

3.7

-

V

Q7S output

I_O= -4 mA

4.32

Qn bus driver outputs

I_O= -6 mA

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

all outputs

I_O= 20 μA

-

0

0.1

-

0.1

0.4

V

Q7S output

I_O= 4.0 mA

0.15

0.33

Qn bus driver outputs

I_O= 6.0 mA

-

0.16

-

0.33

±1.0

-

0.4

V

I_I

input leakage V_I= V_CCor GND; V_CC= 5.5 V

current

±1.0

μA

I_OZ

I_CC

ΔI_CC

OFF-state

output current V_O= V_CCor GND

V_I= V_IHor V_IL; V_CC= 5.5 V;

-

±5.0

80

-

±10

160

μA

supply current V_I= V_CCor GND; I_O= 0 A;

V_CC= 5.5 V

additional

per input pin;

supply current other inputs at V_CCor GND;

I_O= 0 A; V_I= V_CC- 2.1 V;

V_CC= 4.5 V to 5.5 V

pins MR, SHCP, STCP, OE

pin DS

-

150

25

675

113

-

735

123

-

μA

pF

C_I

input

3.5

capacitance

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74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

8 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

11. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 14.

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min Typ[1] Max

Min

Max

Min

Max

74HC595

t_pd

propagation

delay

SHCP to Q7S; see Fig. 9

V_CC= 2 V

[2]

-

52

19

15

160

32

-

200

40

-

240 ns

V_CC= 4.5 V

48

41

ns

V_CC= 6 V

27

34

STCP to Qn; see Fig. 10

V_CC= 2 V

-

55

20

16

175

35

-

220

44

-

265 ns

V_CC= 4.5 V

53

45

ns

V_CC= 6 V

30

37

t_PHL

HIGH to LOW MR to Q7S; see Fig. 12

propagation

delay

V_CC= 2 V

-

47

17

14

175

35

-

220

44

-

265 ns

V_CC= 4.5 V

53

45

ns

V_CC= 6 V

30

37

t_en

enable time

disable time

pulse width

OE to Qn; see Fig. 13

V_CC= 2 V

[3]

[4]

-

47

17

14

150

30

-

190

38

-

225 ns

V_CC= 4.5 V

45

38

ns

V_CC= 6 V

26

33

t_dis

OE to Qn; see Fig. 13

V_CC= 2 V

-

41

15

12

150

30

-

190

38

-

225 ns

V_CC= 4.5 V

45

38

ns

V_CC= 6 V

27

33

t_W

SHCP HIGH or LOW; see Fig. 9

V_CC= 2 V

75

15

13

17

6

-

95

19

16

-

110

22

-

ns

V_CC= 4.5 V

V_CC= 6 V

5

19

STCP HIGH or LOW;

see Fig. 10

V_CC= 2 V

V_CC= 4.5 V

V_CC= 6 V

75

15

13

11

4

-

95

19

16

-

110

22

-

ns

3

19

MR LOW; see Fig. 12

V_CC= 2 V

75

15

13

17

6

-

95

19

16

-

110

22

-

ns

V_CC= 4.5 V

V_CC= 6 V

5

19

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74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

9 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min Typ[1] Max

Min

Max

Min

Max

t_su

set-up time

DS to SHCP; see Fig. 11

V_CC= 2 V

50

10

9

11

4

-

65

13

11

-

75

15

13

-

ns

V_CC= 4.5 V

V_CC= 6 V

3

SHCP to STCP; see Fig. 11

V_CC= 2 V

75

15

13

22

8

-

95

19

16

-

110

22

-

ns

V_CC= 4.5 V

V_CC= 6 V

7

19

t_h

hold time

DS to SHCP; see Fig. 11

V_CC= 2 V

3

-6

-2

-

3

-

3

-

ns

V_CC= 4.5 V

V_CC= 6 V

t_rec

recovery time MR to SHCP; see Fig. 12

V_CC= 2 V

V_CC= 4.5 V

V_CC= 6 V

50

10

9

-19

-7

-

65

13

11

-

75

15

13

-

ns

-6

f_max

maximum

frequency

SHCP or STCP;

see Fig. 9 and Fig. 10

V_CC= 2 V

9

30

35

-

30

91

-

4.8

24

28

-

4

20

24

-

MHz

pF

V_CC= 4.5 V

V_CC= 6 V

108

115

C_PD

power

f_i= 1 MHz; V_I= GND to V_CC

[5]

[6]

dissipation

capacitance

74HCT595; V_CC= 4.5 V to 5.5 V

t_pd

propagation

delay

SHCP to Q7S; see Fig. 9

STCP to Qn; see Fig. 10

[2]

-

25

24

23

42

40

-

53

50

-

63

60

ns

t_PHL

HIGH to LOW MR to Q7S; see Fig. 12

propagation

delay

t_en

t_dis

t_W

enable time

disable time

pulse width

OE to Qn; see Fig. 13

[3]

[4]

-

21

18

6

35

30

-

44

38

-

53

45

-

ns

OE to Qn; see Fig. 13

-

SHCP HIGH or LOW; see Fig. 9

16

20

24

STCP HIGH or LOW;

see Fig. 10

5

-

MR LOW; see Fig. 12

20

16

8

5

8

-

25

20

-

30

24

-

ns

t_su

set-up time

DS to SHCP; see Fig. 11

SHCP to STCP; see Fig. 11

©

74HC_HCT595

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 11 — 10 September 2021

10 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Symbol Parameter

Conditions

25 °C

-40 °C to

+85 °C

-40 °C to

+125 °C

Unit

Min Typ[1] Max

Min

Max

Min

Max

t_h

hold time

DS to SHCP; see Fig. 11

3

-2

-7

-

3

-

3

-

ns

t_rec

f_max

recovery time MR to SHCP; see Fig. 12

10

30

13

24

-

15

20

-

ns

maximum

frequency

SHCP and STCP;

see Fig. 9 and Fig. 10

52

MHz

C_PD

power

dissipation

capacitance

f_i= 1 MHz;

V_I= GND to V_CC- 1.5 V

[5]

[6]

-

130

-

pF

[1] Typical values are measured at nominal supply voltage.

[2] t_pdis the same as t_PHLand t_PLH

[3] t_enis the same as t_PZLand t_PZH

[4] t_disis the same as t_PLZand t_PHZ

.

[5] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i+ Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

Σ(C_L× V_CC²× f_o) = sum of outputs;

C_L= output load capacitance in pF;

V_CC= supply voltage in V.

[6] All 9 outputs switching.

11.1. Waveforms and test circuit

1/f

max

V

I

SHCP input

GND

V

M

t

W

t

PHL

PLH

V

OH

V

Q7S output

V

M

OL

mna557

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 9. Shift clock pulse, maximum frequency and input to output propagation delays

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74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

11 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

V

I

SHCP input

GND

V

M

t

1/f

max

su

V

I

STCP input

GND

V

M

t

W

t

PHL

PLH

V

OH

V

Qn output

M

V

OL

mna558

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 10. Storage clock to output propagation delays

V

I

V

SHCP input

M

GND

t

su

M

t

h

V

I

V

DS input

GND

V

OH

V

Q7S output

M

V

OL

mna560

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 11. Data set-up and hold times

V

I

V

MR input

M

GND

t

rec

W

V

I

SHCP input

Q7S output

V

M

GND

t

PHL

V

OH

V

M

V

OL

mna561

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 12. Master reset to output propagation delays

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74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

12 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

t

r

f

90 %

V

OE input

M

10 %

t

PZL

PLZ

Qn output

V

LOW-to-OFF

OFF-to-LOW

M

10 %

t

PHZ

PZH

90 %

Qn output

V

HIGH-to-OFF

OFF-to-HIGH

M

outputs

enabled

outputs

enabled

outputs

disabled

msa697

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 13. Enable and disable times

Table 8. Measurement points

Type

Input

V_M

Output

V_M

74HC595

0.5V_CC

1.3 V

0.5V_CC

1.3 V

74HCT595

©

74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

13 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

I

V

O

R

L

S1

G

open

DUT

R

T

C

L

001aad983

Test data is given in Table 9.

Definitions for test circuit:

C_L= load capacitance including jig and probe capacitance.

R_L= load resistance.

R_T= termination resistance should be equal to the output impedance Z_oof the pulse generator.

S1 = test selection switch.

Fig. 14. Test circuit for measuring switching times

Table 9. Test data

Type

Input

V_I

Load

C_L

S1 position

t_PHL, t_PLH

open

t_r, t_f

6 ns

R_L

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

V_CC

74HC595

V_CC

3 V

50 pF

1 kΩ

74HCT595

open

GND

V_CC

©

74HC_HCT595

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 11 — 10 September 2021

14 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

12. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.0100

0.0075

0.010 0.057

0.004 0.049

0.019

0.014

0.39

0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig. 15. Package outline SOT109-1 (SO16)

©

74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

15 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

1

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig. 16. Package outline SOT403-1 (TSSOP16)

©

74HC_HCT595

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 11 — 10 September 2021

16 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

SOT763-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

7

L

1

8

9

E

h

e

16

15

10

D

h

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

1

b

c

E

h

e

y

D

E

L

v

w

y

1

h

max.

0.05 0.30

0.00 0.18

3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT763-1

- - -

MO-241

- - -

Fig. 17. Package outline SOT763-1 (DHVQFN16)

©

74HC_HCT595

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 11 — 10 September 2021

17 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

DHXQFN16: plastic, leadless dual in-line compatible thermal enhanced extreme thin quad flat package;

no leads; 16 terminals; 0.4 mm pitch; body 2 mm x 2.4 mm x 0.48 mm

SOT8016-1

z

C

2x

D

A

B

A

E

pin 1

index area

A

3

seating

plane

A

1

detail X

C

z

C

2x

M

y

1

y

C

B

C A

w

D

1

C

pin 1

index area

2

7

1

8

e

E

1

(12x)

9

pin1 I.D.

16

L

(16x)

15

10

M

u

v

C A B

b

M

C

(16x)

X

Dimensions (mm are the original dimensions)

0

1

2 mm

scale

Unit

A

b

D

1

E

e

k

L

u

v

w

y

1

z

1

3

1

max 0.48 0.05

nom 0.45 0.02

min 0.42 0.00

0.23

0.18

0.13

1.40

2.4 1.35

1.30

1.00

0.95

0.90

0.35

0.30

0.25

0.15

(typ)

2.0

mm

0.4

0.1 0.05

0.1 0.05 0.05 0.05

0.2

sot8016-1_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

20-09-18

20-09-22

SOT8016-1

Fig. 18. Package outline SOT8016-1 (DHXQFN16)

©

74HC_HCT595

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 11 — 10 September 2021

18 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

13. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

20210910 Product data sheet

Change notice Supersedes

- 74HC_HCT595 v.10

74HC_HCT595 v.11

Modifications:

•

Type numbers 74HC595DB and 74HCT595DB (SOT338-1/SSOP16) removed.

Section 2updated.

74HC_HCT595 v.10

Modifications:

20210429

Product data sheet

-

74HC_HCT595 v.9

•

Type number 74HC595BZ (SOT8016-1 / DHXQFN16) added.

Table 4: Derating values for P_tottotal power dissipation updated.

74HC_HCT595 v.9

Modifications:

20170228

Product data sheet

-

74HC_HCT595 v.8

•

The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

Legal texts have been adapted to the new company name where appropriate.

74HC_HCT595 v.8

Modifications:

20160225

Type numbers 74HC595N and 74HCT595N (SOT38-4) removed.

20150126 Product data sheet 74HC_HCT595 v.6

Table 7: Power dissipation capacitance condition for 74HCT595 is corrected.

Product data sheet

-

74HC_HCT595 v.7

•

74HC_HCT595 v.7

Modifications:

-

•

74HC_HCT595 v.6

Modifications:

20111212

Product data sheet

-

74HC_HCT595 v.5

•

Legal pages updated.

74HC_HCT595 v.5

20110628

20030604

19980604

Product data sheet

Product specification

-

74HC_HCT595 v.4

74HC_HCT595_CNV v.3

-

74HC_HCT595_CNV v.3

©

74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

19 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

15. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

©

74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

20 / 21

Nexperia

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Applications.................................................................. 1

4. Ordering information....................................................2

5. Functional diagram.......................................................2

6. Pinning information......................................................3

6.1. Pinning.........................................................................3

6.2. Pin description.............................................................4

7. Functional description................................................. 5

8. Limiting values............................................................. 6

9. Recommended operating conditions..........................6

10. Static characteristics..................................................7

11. Dynamic characteristics.............................................9

11.1. Waveforms and test circuit.......................................11

12. Package outline........................................................ 15

13. Abbreviations............................................................19

14. Revision history........................................................19

15. Legal information......................................................20

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 10 September 2021

©

74HC_HCT595

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Product data sheet

Rev. 11 — 10 September 2021

21 / 21


型号：	74HCT595PW
厂家：	Nexperia
描述：	8-bit serial-in, serial or parallel-out shift register with output latches; 3-stateProduction 光电二极管输出元件逻辑集成电路触发器
文件：	总21页 (文件大小：322K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74HCT595PW [NEXPERIA]

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