74LV00BQ [NEXPERIA]
Quad 2-input NAND gateProduction;型号: | 74LV00BQ |
厂家: | Nexperia |
描述: | Quad 2-input NAND gateProduction 逻辑集成电路 |
文件: | 总12页 (文件大小:227K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LV00
Quad 2-input NAND gate
Rev. 5 — 10 September 2021
Product data sheet
1. General description
The 74LV00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess VCC
.
2. Features and benefits
•
Wide supply voltage range from 1.0 to 5.5 V
CMOS low power dissipation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
Complies with JEDEC standards:
•
•
•
•
•
•
•
•
•
•
•
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
•
ESD protection:
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
•
•
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LV00D
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV00PW
74LV00BQ
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
SOT762-1
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Nexperia
74LV00
Quad 2-input NAND gate
4. Functional diagram
1
2
3
&
&
&
1
2
1A
1B
1Y
2Y
3Y
3
6
8
4
5
4
5
2A
2B
6
9
9
3A
8
10 3B
10
A
B
12 4A
13 4B
12
13
4Y 11
Y
11
&
mna212
mna246
mna211
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram (one gate)
5. Pinning information
5.1. Pinning
74LV00
terminal 1
index area
2
3
4
5
6
13
12
11
10
9
1B
4B
4A
4Y
3B
3A
1Y
2A
2B
2Y
74LV00
(1)
CC
V
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
4B
4A
4Y
3B
3A
3Y
1Y
2A
001aah092
2B
Transparent top view
2Y
(1) This is not a supply pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to VCC
GND
8
aaa-033972
Fig. 4. Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
Fig. 5. Pin configuration SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
data input
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
data input
data output
ground (0 V)
supply voltage
VCC
14
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
2 / 12
Nexperia
74LV00
Quad 2-input NAND gate
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Input
Output
nA
L
nB
X
nY
H
X
L
H
H
H
L
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max Unit
supply voltage
-0.5
+7.0
±20
±50
±25
50
V
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to (VCC + 0.5 V)
[1]
[1]
-
mA
mA
mA
mA
mA
IOK
-
-
IO
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-50
-65
-
-
storage temperature
total power dissipation
+150 °C
500 mW
Tamb = -40 °C to +125 °C
[2]
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
V
VCC
VI
supply voltage
[1]
1.0
3.3
5.5
VCC
VCC
+125
500
200
100
50
input voltage
0
-
V
VO
output voltage
0
-
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
+25
°C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
3 / 12
Nexperia
74LV00
Quad 2-input NAND gate
9. Static characteristics
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
0.9
1.4
2.0
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.2 V
-
-
-
-
0.9
-
V
V
V
V
V
V
V
V
VCC = 2.0 V
-
-
1.4
-
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
2.0
0.7VCC
-
-
-
-
-
-
0.7VCC
-
VIL
LOW-level
input voltage
-
-
-
-
0.3
0.6
0.8
0.3VCC
-
-
-
-
0.3
0.6
0.8
0.3VCC
VCC = 2.0 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL
VOH
HIGH-level
output voltage
IO = -100 μA; VCC = 1.2 V
IO = -100 μA; VCC = 2.0 V
IO = -100 μA; VCC = 2.7 V
IO = -100 μA; VCC = 3.0 V
IO = -100 μA; VCC = 4.5 V
IO = -6 mA; VCC = 3.0 V
IO = -12 mA; VCC = 4.5 V
VI = VIH or VIL
-
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
1.8
2.5
2.8
4.3
2.4
3.6
1.8
2.5
2.8
4.3
2.2
3.5
VOL
LOW-level
output voltage
IO = 100 μA; VCC = 1.2 V
IO = 100 μA; VCC = 2.0 V
IO = 100 μA; VCC = 2.7 V
IO = 100 μA; VCC = 3.0 V
IO = 100 μA; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
IO = 12 mA; VCC = 4.5 V
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
V
0.2
0.2
0.2
0.2
0.40
0.55
1.0
0.2
0.2
0.2
0.2
0.50
0.65
1.0
V
0
V
0
V
0
V
0.25
0.35
-
V
V
II
input leakage VI = VCC or GND; VCC = 5.5 V
current
μA
ICC
ΔICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
-
20.0
500
-
-
-
-
40
850
-
μA
μA
pF
additional
per input; VI = VCC - 0.6 V;
supply current VCC = 2.7 V to 3.6 V
input
3.5
capacitance
[1] Typical values are measured at Tamb = 25 °C.
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
4 / 12
Nexperia
74LV00
Quad 2-input NAND gate
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; For test circuit see Fig. 7.
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
tpd
propagation delay nA, nB to nY; see Fig. 6
[2]
[3]
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
-
-
-
-
45
15
11
7
-
-
-
-
-
-
ns
ns
ns
ns
26
18
-
31
23
-
VCC = 3.0 V to 3.6 V;
CL = 15 pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
[3]
[4]
-
-
-
9.0
6.5
22
15
11
-
-
-
-
18
14
-
ns
ns
pF
CPD
power dissipation
capacitance
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[4] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
Σ(CL x VCC 2 x fo) = sum of the outputs.
10.1. Waveform and test circuit
V
I
V
nA, nB input
GND
M
t
t
PLH
PHL
V
OH
V
nY output
M
V
OL
001aah088
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 6. The input (nA, nB) to output (nY) propagation delays
Table 8. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
< 2.7 V
0.5VCC
1.5 V
0.5VCC
0.5VCC
1.5 V
2.7 V to 3.6 V
≥ 4.5 V
0.5VCC
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
5 / 12
Nexperia
74LV00
Quad 2-input NAND gate
V
CC
V
V
O
I
PULSE
GENERATOR
DUT
C
50 pF
R
L
1 kΩ
L
R
T
001aaa663
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Fig. 7. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
VCC
Input
VI
tr, tf
< 2.7 V
VCC
2.7 V
VCC
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
2.7 V to 3.6 V
≥ 4.5 V
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
6 / 12
Nexperia
74LV00
Quad 2-input NAND gate
11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig. 8. Package outline SOT108-1 (SO14)
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
7 / 12
Nexperia
74LV00
Quad 2-input NAND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig. 9. Package outline SOT402-1 (TSSOP14)
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
8 / 12
Nexperia
74LV00
Quad 2-input NAND gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
E
D
A
A
1
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
v
w
C
C
A B
y
y
C
1
e
b
2
6
L
1
7
8
E
h
e
14
k
13
9
D
h
X
k
0
2
4 mm
w
scale
Dimensions (mm are the original dimensions)
(1) (1)
(1)
Unit
A
A
b
c
D
D
h
E
E
e
e
k
L
v
y
y
1
1
h
1
max
nom
min
1
0.05 0.30
0.02 0.25 0.2 3.0 1.50 2.5 1.00 0.5
0.00 0.18 2.9 1.35 2.4 0.85
3.1 1.65 2.6 1.15
0.5
0.4 0.1 0.05 0.05 0.1
0.2 0.3
mm
2
Note
sot762-1_po
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
15-04-10
15-05-05
SOT762-1
MO-241
Fig. 10. Package outline SOT762-1 (DHVQFN14)
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
9 / 12
Nexperia
74LV00
Quad 2-input NAND gate
12. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
74LV00 v.5
Release date
20210910
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV00 v.4
Modifications:
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Type number 74LV00DB (SOT337-1/SSOP14) removed.
Section 1 and Section 2 updated.
Section 7: Derating values for Ptot total power dissipation have been updated.
74LV00 v.4
20151209
Type number 74LV00N (SOT27-1) removed.
20071220 Product data sheet
Product data sheet
-
74LV00 v.3
Modifications:
•
74LV00 v.3
-
74LV00 v.2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 3: DHVQFN14 package added.
Section 7: derating values added for DHVQFN14 package.
Section 11: outline drawing added for DHVQFN14 package.
74LV00 v.2
74LV00 v.1
19980420
19970203
Product specification
Product specification
-
-
74LV00 v.1
-
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
10 / 12
Nexperia
74LV00
Quad 2-input NAND gate
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
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Trademarks
Suitability for use — Nexperia products are not designed, authorized or
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©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
11 / 12
Nexperia
74LV00
Quad 2-input NAND gate
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description.............................................................2
6. Functional description................................................. 3
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................3
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 5
10.1. Waveform and test circuit..........................................5
11. Package outline.......................................................... 7
12. Abbreviations............................................................10
13. Revision history........................................................10
14. Legal information......................................................11
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 10 September 2021
©
74LV00
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 10 September 2021
12 / 12
相关型号:
74LV00D-T
IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14, Gate
NXP
74LV00DB-T
IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 5.30 MM, PLASTIC, MO-150, SOT337-1, SSOP-14, Gate
NXP
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