74LV4094PW_技术文档

74LV4094

8-stage shift-and-store bus register

Rev. 8 — 18 March 2021

Product data sheet

1. General description

The 74LV4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and

3-state outputs. Both the shift and storage register have separate clocks. The device features a

serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the

LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions

of the CP input to allow cascading when clock edges are fast. The same data is available at QS2

on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow.

The data in the shift register is transferred to the storage register when the STR input is HIGH.

Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH.

A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE

input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of

current limiting resistors to interface inputs to voltages in excess V_CC

.

2. Features and benefits

•

Optimized for low voltage applications over a wide supply voltage range from 1.0 V to 3.6 V

Accepts TTL input levels between V_CC= 2.7 V and V_CC= 3.6 V

Typical output ground bounce < 0.8 V at V_CC= 3.3 V and T_amb= 25 °C

Typical HIGH-level output voltage (V_OH) undershoot: > 2 V at V_CC= 3.3 V and T_amb= 25 °C

CMOS low power dissipation

Direct interface with TTL levels

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standards

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

•

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Applications

•

Serial-to-parallel data conversion

Remote control holding register

Nexperia

74LV4094

8-stage shift-and-store bus register

4. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LV4094D

74LV4094DB

74LV4094PW

-40 °C to +125 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

SOT338-1

SOT403-1

SSOP16

TSSOP16

plastic shrink small outline package; 16 leads;

body width 5.3 mm

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

5. Functional diagram

3

1

C2

15

EN3

CP

STR

QS1

9

SRG8

3

QS2

QP0

QP1

10

4

C1/

2

4

5

1D

2D

3

5

6

QP2

QP3

QP4

QP5

QP6

QP7

6

2

D

7

14

13

12

11

9

14

13

12

11

OE

15

10

001aaf111

001aaf112

Fig. 1. Functional diagram

Fig. 2. Logic symbol

D

2

8-STAGE SHIFT

REGISTER

QS2

QS1

10

9

CP

3

STR

OE

8-BIT STORAGE

REGISTER

1

15

3-STATE OUTPUTS

QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7

14 13 12 11

4

5

6

7

001aaf119

Fig. 3. Logic diagram

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

2 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

STAGE 0

STAGES 1 TO 6

STAGE 7

D

Q

D

Q

D

Q

QS1

QS2

CP

D

Q

FF 0

FF 7

CP

LE

LATCH

D

Q

D

Q

LE

LATCH 0

LATCH 7

STR

OE

001aag799

QP0

QP2

QP4

QP6

QP1

QP3

QP5

QP7

Fig. 4. Logic diagram

6. Pinning information

6.1. Pinning

74LV4094

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

STR

D

V

CC

OE

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

STR

D

V

CC

CP

QP4

QP5

QP6

QP7

QS2

QS1

OE

CP

QP4

QP5

QP6

QP7

QS2

QS1

QP0

QP1

QP2

QP3

GND

QP0

QP1

QP2

QP3

GND

001aan680

aaa-033164

Fig. 6. Pin configuration SOT338-1 (SSOP16) and

SOT403-1 (TSSOP16)

Fig. 5. Pin configuration SOT109-1 (SO16)

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

3 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

6.2. Pin description

Table 2. Pin description

Symbol

1

Description

STR

strobe input

D

2

data input

CP

3

clock input

QP0 to QP7

GND

QS1, QS2

OE

4, 5, 6, 7, 14, 13, 12, 11

parallel output

ground supply voltage

serial output

8

9,10

15

16

output enable input

supply voltage

V_CC

7. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = HIGH-impedance OFF-state; NC = no change;

↑ = positive-going transition; ↓ = negative-going transition;

Q6S = the data in register stage 6 before the LOW to HIGH clock transition;

Q7S = the data in register stage 7 before the HIGH to LOW clock transition.

Inputs

Parallel outputs

Serial outputs

CP

↑

OE

L

STR

X

D

X

L

QP0

Z

QPn

QS1

Q6S

NC

QS2

NC

Z

↓

L

X

Z

Q7S

NC

↑

H

L

NC

L

NC

Q6S

NC

↑

H

QPn -1

NC

↑

H

NC

↓

H

NC

Q7S

CLOCK INPUT

DATA INPUT

STROBE INPUT

OUTPUT ENABLE INPUT

INTERNAL Q0S (FF 0)

OUTPUT QP0

Z-state

INTERNAL Q6S (FF 6)

OUTPUT QP6

Z-state

SERIAL OUTPUT QS1

SERIAL OUTPUT QS2

001aaf117

At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the

QSn outputs.

Fig. 7. Timing diagram

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

4 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

8. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

+7

Unit

V

V_CC

I_IK

supply voltage

-0.5

input clamping current

output clamping current

output current

V_I< -0.5 V or V_I> V_CC+ 0.5 V

V_O< -0.5 V or V_O> V_CC+ 0.5 V

V_O= -0.5 V to (V_CC+ 0.5 V)

-

±20

±50

±25

+50

-

mA

I_OK

I_O

-

I_CC

I_GND

T_stg

P_tot

supply current

-

ground current

-50

-65

-

storage temperature

total power dissipation

+150 °C

500 mW

T_amb= -40 °C to +125 °C

[1]

[1] For SOT109-1 (SO16) package: P_totderates linearly with 12.4 mW/K above 110 °C.

For SOT338-1 (SSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

For SOT403-1 (TSSOP16) package: P_totderates linearly with 8.5 mW/K above 91 °C.

9. Recommended operating conditions

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V

V_CC

V_I

supply voltage

[1]

1.0

3.3

3.6

V_CC

+125

500

200

100

input voltage

0

-

V

V_O

output voltage

-

V

T_amb

Δt/ΔV

ambient temperature

input transition rise and fall rate

-40

-

+25

°C

V_CC= 1.0 V to 2.0 V

V_CC= 2.0 V to 2.7 V

V_CC= 2.7 V to 3.6 V

-

ns/V

-

[1] The static characteristics are guaranteed from V_CC= 1.2 V to V_CC= 5.5 V, but LV devices are guaranteed to function down to

V_CC= 1.0 V (with input levels GND or V_CC).

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

5 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

10. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

-40 °C to 85 °C

-40 °C to +125 °C Unit

Min

Typ[1]

Max

Min

V_CC

1.4

2.0

-

Max

V_IH

HIGH-level input

voltage

V_CC= 1.2 V

V_CC

0.6

-

V

V_CC= 2.0 V

1.4

-

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

2.0

-

0.4

-

V_IL

LOW-level input

voltage

-

GND

0.6

0.8

GND

0.6

0.8

V_CC= 2.0 V

-

V_CC= 2.7 V to 3.6 V

-

V_OH

HIGH-level output V_I= V_IHor V_IL; all pins

voltage

I_O= -100 μA; V_CC= 1.2 V

-

1.2

2.0

2.7

3.0

-

V

I_O= -100 μA; V_CC= 2.0 V

I_O= -100 μA; V_CC= 2.7 V

I_O= -100 μA; V_CC= 3.0 V

V_I= V_IHor V_IL; pins QPn

I_O= -6 mA; V_CC= 3.0 V

V_I= V_IHor V_IL; all pins

1.8

2.5

2.8

1.8

2.5

2.8

2.40

2.82

-

2.20

-

V

V_OL

LOW-level output

voltage

I_O= 100 μA; V_CC= 1.2 V

I_O= 100 μA; V_CC= 2.0 V

I_O= 100 μA; V_CC= 2.7 V

I_O= 100 μA; V_CC= 3.0 V

V_I= V_IHor V_IL; pins QPn

I_O= 6 mA; V_CC= 3.0 V

-

0

-

V

0.2

-

0.25

-

0.40

±1.0

-

0.50

±1.0

V

I_I

input leakage

current

V_I= V_CCor GND; V_CC= 3.6 V

μA

I_OZ

I_CC

ΔI_CC

C_I

OFF-state output

current

V_I= V_IHor V_IL; V_O= V_CCor GND;

V_CC= 3.6 V

-

±5.0

20.0

500.0

-

±10.0

160

850

-

μA

pF

supply current

V_I= V_CCor GND; I_O= 0 A;

V_CC= 3.6 V

additional supply

current

per input; V_I= V_CC- 0.6 V;

V_CC= 2.7 V to 3.6 V

-

input capacitance

3.5

[1] All typical values are measured at T_amb= 25 °C.

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

6 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

11. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); C_L= 50 pF unless otherwise specified; for test circuit see Fig. 12.

Symbol Parameter

Conditions

-40 °C to 85 °C

-40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

t_pd

propagation

delay

CP to QS1; see Fig. 8

V_CC= 1.2 V

[2]

-

90

31

23

17

14

-

ns

V_CC= 2.0 V

58

43

34

-

70

51

41

-

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 3.3 V; C_L= 15 pF

CP to QS2; see Fig. 8

V_CC= 1.2 V

[3]

[2]

-

80

27

20

14

13

-

ns

V_CC= 2.0 V

51

38

30

-

61

45

36

-

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 3.3 V; C_L= 15 pF

CP to QPn; see Fig. 8

V_CC= 1.2 V

[3]

[2]

-

115

39

29

22

18

-

ns

V_CC= 2.0 V

75

55

44

-

90

66

53

-

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 3.3 V; C_L= 15 pF

STR to QPn; see Fig. 9

V_CC= 1.2 V

[3]

[2]

-

105

36

26

20

17

-

ns

V_CC= 2.0 V

68

50

40

-

82

60

48

-

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 3.3 V; C_L= 15 pF

OE to QPn; see Fig. 10

V_CC= 1.2 V

[3]

[2]

t_en

enable time

disable time

-

100

34

-

ns

V_CC= 2.0 V

65

48

38

77

56

45

V_CC= 2.7 V

25

V_CC= 3.0 V to 3.6 V

OE to QPn; see Fig. 10

V_CC= 1.2 V

[3]

[2]

19

t_dis

-

65

24

18

14

-

ns

V_CC= 2.0 V

40

32

26

49

37

30

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

[3]

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

7 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

Symbol Parameter

Conditions

-40 °C to 85 °C

-40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

t_W

pulse width

CP HIGH or LOW; see Fig. 8

V_CC= 2.0 V

34

25

20

9

6

5

-

41

30

24

-

ns

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

STR HIGH; see Fig. 9

V_CC= 2.0 V

[3]

34

25

20

9

6

5

-

41

30

24

-

ns

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

D to CP; see Fig. 11

V_CC= 1.2 V

t_su

set-up time

-

25

9

-

ns

V_CC= 2.0 V

22

16

13

26

19

15

V_CC= 2.7 V

6

V_CC= 3.0 V to 3.6 V

CP to STR; see Fig. 9

V_CC= 1.2 V

[3]

5

-

50

17

13

10

-

ns

V_CC= 2.0 V

43

31

25

51

38

30

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

D to CP; see Fig. 11

V_CC= 1.2 V

t_h

hold time

-

-10

-4

-

ns

V_CC= 2.0 V

5

+5

V_CC= 2.7 V

-3

V_CC= 3.0 V to 3.6 V

CP to STR; see Fig. 9

V_CC= 1.2 V

-2

-

-25

-9

-

ns

V_CC= 2.0 V

5

+5

V_CC= 2.7 V

-6

V_CC= 3.0 V to 3.6 V

CP; see Fig. 8

-5

f_max

maximum

frequency

V_CC= 2.0 V

14

19

24

-

52

70

87

95

83

-

12

16

20

-

MHz

pF

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 3.3 V; C_L= 15 pF

[3]

[4]

C_PD

power

C_L= 50 pF; f = 1 MHz;

V_I= GND to V_CC

-

dissipation

capacitance

[1] All typical values are measured at T_amb= 25 °C.

[2] t_pdis the same as t_PLHand t_PHL; t_enis the same as t_PZHand t_PZL; t_disis the same as t_PLZand t_PHZ

.

[3] All typical values are measured at V_CC= 3.3 V.

[4] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PDx V_CC²x f_ix N + ∑(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

∑(C_Lx V_CC²x f_o) = sum of outputs.

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

8 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

11.1. Waveforms and test circuit

1/f

max

V

I

CP input

QPn, QS1 output

QS2 output

V

M

GND

t

W

t

PHL

PLH

V

OH

V

M

V

OL

t

PHL

PLH

V

OH

V

M

V

OL

001aaf113

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 8. Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse

width and the maximum frequency (CP)

V

I

CP input

STR input

QPn output

V

M

GND

t

h

su

M

V

I

V

GND

t

W

t

PHL

PLH

V

OH

V

M

V

OL

001aaf114

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 9. Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock set-up

and hold times for strobe input

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

9 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

V

I

V

M

OE input

GND

t

PZL

t

PLZ

V

CC

output

V

M

LOW-to-OFF

OFF-to-LOW

V

X

V

OL

t

PHZ

PZH

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

enabled

outputs

disabled

001aaf116

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 10. Enable and disable times

V

I

V

CP input

M

GND

t

su

t

h

V

I

V

D input

M

GND

V

OH

V

QPn, QS1, QS2 output

M

V

OL

001aaf115

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 11. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times

Table 8. Measurement points

Supply voltage

V_CC

Input

V_M

Output

V_M

V_X

V_Y

< 2.7 V

0.5V_CC

1.5 V

0.5V_CC

1.5 V

V_OL+ 0.1V_CC

V_OL+ 0.3 V

V_OH- 0.1V_CC

V_OH- 0.3 V

2.7 V to 3.6 V

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

10 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

V

CC

R

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig. 12. Test circuit for measuring switching times

Table 9. Test data

Supply voltage Input

Load

C_L

V_EXT

V_CC

V_I

t_r, t_f

R_L

t_PHL, t_PLH

open

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

2V_CC

< 2.7 V

V_CC

2.7 V

≤ 2.5 ns

50 pF

1 kΩ

2.7 V to 3.6 V

15 pF, 50 pF 1 kΩ

open

GND

2V_CC

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

11 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

12. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.0100

0.0075

0.010 0.057

0.004 0.049

0.019

0.014

0.39

0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig. 13. Package outline SOT109-1 (SO16)

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

12 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A

X

c

y

H

E

v

M

A

Z

9

16

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

8

1

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

3

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

mm

2

0.2

0.13

0.1

0.25

0.65

1.25

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT338-1

MO-150

Fig. 14. Package outline SOT338-1 (SSOP16)

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

13 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

1

0.2

0.13

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig. 15. Package outline SOT403-1 (TSSOP16)

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

14 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

13. Abbreviations

Table 10. Abbreviations

Acronym

Description

CMOS

DUT

ESD

HBM

MM

Complementary Metal Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

Release date Data sheet status

Change notice Supersedes

74LV4094 v.8

Modifications:

20210318

Type number 74LV4094DB (SOT338-1 / SSOP16) added.

20210205 Product data sheet 74LV4094 v.6

Product data sheet

-

74LV4094 v.7

•

74LV4094 v.7

Modifications:

-

•

Type number 74LV4094DB (SOT338-1 / SSOP16) removed.

Section 1 and Section 2 updated.

Section 8: Derating values for P_tottotal power dissipation updated.

74LV4094 v.6

Modifications:

20181114

Product data sheet

-

74LV4094 v.5

•

The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Fig. 7 corrected.

74LV4094 v.5

Modifications:

20160318

Product data sheet

-

74LV4094 v.4

•

Type number 74LV4094N (SOT38-4) removed.

74LV4094 v.4

Modifications:

20111219

Product data sheet

-

74LV4094 v.3

•

Legal pages updated.

74LV4094 v.3

74LV4094 v.2

74LV4094 v.1

20110307

20060629

19980623

Product data sheet

Product specification

-

74LV4094 v.2

74LV4094 v.1

-

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

15 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

15. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

16 / 17

Nexperia

74LV4094

8-stage shift-and-store bus register

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Applications.................................................................. 1

4. Ordering information....................................................2

5. Functional diagram.......................................................2

6. Pinning information......................................................3

6.1. Pinning.........................................................................3

6.2. Pin description.............................................................4

7. Functional description................................................. 4

8. Limiting values............................................................. 5

9. Recommended operating conditions..........................5

10. Static characteristics..................................................6

11. Dynamic characteristics.............................................7

11.1. Waveforms and test circuit........................................ 9

12. Package outline........................................................ 12

13. Abbreviations............................................................15

14. Revision history........................................................15

15. Legal information......................................................16

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 18 March 2021

©

74LV4094

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 18 March 2021

17 / 17


型号：	74LV4094PW
厂家：	Nexperia
描述：	8-stage shift-and-store bus registerProduction 逻辑集成电路
文件：	总17页 (文件大小：277K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LV4094PW [NEXPERIA]

相关型号：

74LV4094PW,118

74LV423

74LV423D

74LV423D-T

74LV423DB

74LV423DB-T

74LV423N

74LV423PW

74LV423PW-T

74LV423PWDH

74LV4316

74LV4316D