74LVC162373ADGG [NEXPERIA]

16-bit D-type transparent latch; 30 Ohm series termination resistors; 5 V tolerant inputs/outputs; 3-stateProduction;


型号：	74LVC162373ADGG
厂家：	Nexperia
描述：	16-bit D-type transparent latch; 30 Ohm series termination resistors; 5 V tolerant inputs/outputs; 3-stateProduction
文件：	总14页 (文件大小：241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination

resistors; 5 V tolerant inputs/outputs; 3-state

Rev. 6 — 16 September 2021

Product data sheet

1. General description

The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with 30 Ω

termination resistors and 3-state outputs. The 74LVCH162373A has separate D-type inputs with

bus hold for each latch. Both devices can be used as two 8-bit transparent latches or a single 16-

bit transparent latch. Both devices feature two latch enables (1LE and 2LE) and two output enables

(1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches.

In this condition the latches are transparent, a latch output will change each time its corresponding

D-input changes. When nLE is LOW the latches store the information that was present at the inputs

a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to

assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the

latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

These devices are fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the devices

when they are powered down.

2. Features and benefits

•

Overvoltage tolerant inputs to 5.5 V

•

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Multibyte flow-through standard pinout architecture

Multiple low inductance supply pins for minimum noise and ground bounce

Direct interface with TTL levels

All data inputs have bus hold (74LVCH162373A only)

I_OFFcircuitry provides partial Power-down mode operation

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-B exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC162373ADGG

74LVCH162373ADGG

-40 °C to +125 °C

TSSOP48

plastic thin shrink small outline package;

48 leads; body width 6.1 mm

SOT362-1

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

4. Functional diagram

1EN

1OE

1LE

2OE

2LE

2EN

1OE

2OE

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

1LE

2LE

mgu768

mgu770

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

1D0

1Q0

2D0

2Q0

LATCH

LE LE

1LE

2LE

1OE

2OE

to 7 other channels

mgu769

Fig. 3. Logic diagram

input

to internal circuit

mna428

Fig. 4. Bus hold circuit

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

2 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

5. Pinning information

5.1. Pinning

1OE

1Q0

1Q1

GND

1Q2

1Q3

48 1LE

47 1D0

46 1D1

GND

44 1D2

43 1D3

1Q4

1Q5

1D4

40 1D5

GND 10

1Q6 11

1Q7 12

2Q0 13

2Q1 14

GND 15

2Q2 16

2Q3 17

GND

1D6

1D7

2D0

2D1

GND

2D2

2D3

162373A

2Q4 19

2Q5 20

GND 21

2Q6 22

2Q7 23

2OE 24

2D4

2D5

GND

2D6

2D7

2LE

001aaa336

Fig. 5. Pin configuration SOT362-1 (TSSOP48)

5.2. Pin description

Table 2. Pin description

Symbol

Description

1OE, 2OE

1, 24

output enable input (active LOW)

ground (0 V)

GND

4, 10, 15, 21, 28, 34, 39, 45

7, 18, 31, 42

V_CC

supply voltage

1LE, 2LE

48, 25

latch enable input (active HIGH)

data input

1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7

2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7

47, 46, 44, 43, 41, 40, 38, 37

36, 35, 33, 32, 30, 29, 27, 26

data input

1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7 2, 3, 5, 6, 8, 9, 11, 12

data output

2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7 13, 14, 16, 17, 19, 20, 22, 23

data output

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

3 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

6. Functional description

Table 3. Functional table (per section of 8 bits)

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;

Z = high-impedance OFF-state.

Operating modes

Input

Internal Latch Output nQn

nOE

nLE

nDn

Enable and read register

(transparent mode)

Latch and read register

Latch register and disable outputs H

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

-0.5

-50

-0.5

Max

+6.5

Unit

supply voltage

input clamping current

input voltage

V_I< 0 V

V_I

[1]

+6.5

±50

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

output HIGH or LOW state

output 3-state

V_O

[2]

-0.5

V_CC+ 0.5

+6.5

±50

I_O

output current

V_O= 0 V to V_CC

°C

I_CC

I_GND

T_stg

P_tot

supply current

100

ground current

-100

-65

storage temperature

total power dissipation

+150

500

T_amb= -40 °C to +125 °C

[3]

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SOT362-1 (TSSOP48) packages: P_totderates linearly with 12.2 mW/K above 109 °C.

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

4 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol

Parameter

Conditions

Min

1.65

1.2

Typ

Max Unit

V_CC

supply voltage

3.6

functional

V_I

input voltage

5.5

V_CC

5.5

V_O

output voltage

output HIGH or LOW state

output 3-state

T_amb

ambient temperature

in free air

-40

+125 °C

Δt/ΔV

input transition rise and fall rate

V_CC= 1.65 V to 2.7 V

V_CC= 2.7 V to 3.6 V

ns/V

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

V_IH

HIGH-level input V_CC= 1.2 V

voltage

1.08

V_CC= 1.65 V to 1.95 V

0.65 × V_CC

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

1.7

2.0

0.12

2.0

0.12

V_IL

LOW-level input V_CC= 1.2 V

voltage

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35 × V_CC

0.7

0.35 × V_CC

0.7

0.8

V_OH

HIGH-level

output voltage

I_O= -100 μA;

V_CC- 0.2

V_CC

V_CC- 0.3

V_CC= 1.65 V to 3.6 V

I_O= -2 mA; V_CC= 1.65 V

I_O= -4 mA; V_CC= 2.3 V

I_O= -6 mA; V_CC= 2.7 V

I_O= -12 mA; V_CC= 3.0 V

1.2

1.7

2.2

1.05

1.55

2.05

2.0

V_OL

LOW-level output V_I= V_IHor V_IL

voltage

I_O= 100 μA;

0.2

0.3

V_CC= 1.65 V to 3.6 V

I_O= 2 mA; V_CC= 1.65 V

I_O= 4 mA; V_CC= 2.3 V

I_O= 6 mA; V_CC= 2.7 V

I_O= 12 mA; V_CC= 3.0 V

0.45

0.6

0.65

0.8

0.4

0.6

0.55

±5

0.8

I_I

input leakage

current

V_CC= 3.6 V;

V_I= 5.5 V or GND [2]

±0.1

±20

μA

I_OZ

OFF-state output V_I= V_IHor V_IL; V_CC= 3.6 V;

current V_O= 5.5 V or GND [2]

0.1

±5

±20

μA

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

5 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

Symbol Parameter

Conditions

-40 °C to +85 °C

-40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

I_OFF

I_CC

power-off

leakage current

V_CC= 0 V; V_Ior V_O= 5.5 V

0.1

±10

±20

μA

supply current

V_CC= 3.6 V;

V_I= V_CCor GND; I_O= 0 A

0.1

ΔI_CC

additional supply per input pin;

500

5000

current

V_CC= 2.7 V to 3.6 V;

V_I= V_CC- 0.6 V; I_O= 0 A

C_I

input

capacitance

V_CC= 0 V to 3.6 V;

V_I= GND to V_CC

5.0

I_BHL

bus hold LOW

current

V_CC= 1.65; V_I= 0.58 V [3][4]

V_CC= 2.3; V_I= 0.7 V

V_CC= 3.0; V_I= 0.8 V

V_CC= 1.65; V_I= 1.07 V [3][4]

V_CC= 2.3; V_I= 1.7 V

V_CC= 3.0; V_I= 2.0 V

V_CC= 1.95 V [3][5]

V_CC= 2.7 V

μA

I_BHH

bus hold HIGH

current

-10

-30

-75

200

300

500

-10

-25

-60

I_BHLO

bus hold LOW

overdrive current

200

300

500

-200

-300

-500

V_CC= 3.6 V

I_BHHO

bus hold HIGH

overdrive current

V_CC= 1.95 V [3][5]

V_CC= 2.7 V

-200

-300

-500

V_CC= 3.6 V

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 °C.

[2] The bus hold circuit is switched off when V_I> V_CCallowing 5.5 V on the input pin.

[3] Valid for data inputs (74LVCH162373A) only; control inputs do not have a bus hold circuit.

[4] The specified sustaining current at the data inputs holds the input below the specified V_Ilevel.

[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 10.

Symbol Parameter

Conditions

-40 °C to +85 °C

Min Typ[1] Max

-40 °C to +125 °C Unit

Min

Max

t_pd

propagation delay nDn to nQn; see Fig. 6

V_CC= 1.2 V

[2]

6.6

3.5

3.0

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

1.5

1.0

15.0

7.4

6.7

5.9

1.5

1.0

1.5

1.0

17.2

8.5

7.5

V_CC= 3.0 V to 3.6 V

nLE to nQn; see Fig. 7

V_CC= 1.2 V

7.6

4.0

3.7

3.4

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.4

1.7

1.5

16.0

7.9

7.0

6.1

2.4

1.7

1.5

18.5

9.1

9.0

8.0

V_CC= 3.0 V to 3.6 V

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

6 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

Symbol Parameter

Conditions

-40 °C to +85 °C

Min Typ[1] Max

-40 °C to +125 °C Unit

Min

Max

t_en

enable time

nOE to nQn; see Fig. 8

V_CC= 1.2 V

[2]

7.1

4.0

4.2

3.2

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.7

1.5

1.0

15.6

8.2

7.5

6.1

1.7

1.5

1.0

17.9

9.4

9.5

8.0

V_CC= 3.0 V to 3.6 V

nOE to nQn; see Fig. 8

V_CC= 1.2 V

t_dis

disable time

[2]

4.2

2.3

3.2

2.9

V_CC= 1.65 V

2.5

1.0

1.5

8.5

4.6

4.8

4.6

2.5

1.0

1.5

9.8

5.3

6.0

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nLE HIGH; see Fig. 7

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

t_W

t_su

t_h

pulse width

set-up time

hold time

5.0

4.0

3.0

5.0

4.0

3.0

V_CC= 3.0 V to 3.6 V

nDn to nLE; see Fig. 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.0

3.0

2.5

2.0

3.0

2.5

2.0

V_CC= 3.0 V to 3.6 V

nDn to nLE; see Fig. 9

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

2.5

2.0

0.9

+0.9

2.5

2.0

0.9

+0.9

-1.0

V_CC= 3.0 V to 3.6 V

per input; V_I= GND to V_CC

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

t_sk(o)

C_PD

output skew time

[3]

[4]

1.0

1.5

power dissipation

capacitance

10.8

13.0

15.0

[1] Typical values are measured at T_amb= 25 °C and V_CC= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PDx V_CC²x f_ix N + Σ(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

Σ(C_Lx V_CC²x f_o) = sum of the outputs

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

7 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

10.1. Waveforms and test circuit

nDn input

GND

PLH

PHL

nQn output

mna429

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 6. Input (nDn) to output (nQn) propagation delays

nLE input

GND

PLH

PHL

nQn output

mna430

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 7. Latch enable (nLE) pulse width, and the latch enable input to output (nQn) propagation delays

nOE input

GND

PLZ

PZL

nQn output

LOW-to-OFF

OFF-to-LOW

PZH

PHZ

nQn output

HIGH-to-OFF

OFF-to-HIGH

GND

outputs

enabled

outputs

disabled

outputs

enabled

mna432

Measurement points are given in Table 8.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 8. 3-state enable and disable times

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

8 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

nDn input

GND

nLE input

GND

mna431

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 9. Data set-up and hold times for the nDn input to the nLE input

Table 8. Measurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

V_X

V_Y

1.2 V

V_CC

2.7 V

0.5 x V_CC

1.5 V

0.5 x V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH- 0.15 V

V_OH- 0.3 V

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

3.0 V to 3.6 V

1.5 V

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

EXT

DUT

001aae331

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig. 10. Test circuit for measuring switching times

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

9 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

Table 9. Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2 x V_CC

t_PHZ, t_PZH

GND

1.2 V

V_CC

2.7 V

≤ 2 ns

≤ 2.5 ns

30 pF

50 pF

1 kΩ

500 Ω

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

open

GND

open

GND

open

GND

3.0 V to 3.6 V

open

GND

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

10 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

11. Package outline

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

(A )

pin 1 index

detail X

5 mm

2.5

scale

Dimensions (mm are the original dimensions)

Unit

max

(1)

(2)

0.15 1.05

0.05 0.85

0.28 0.2 12.6 6.2

0.17 0.1 12.4 6.0

8.3

7.9

0.8 0.50

0.4 0.35

0.8

0.4

mm nom 1.2

min

0.25

0.5

0.25 0.08 0.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

sot362-1_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

03-02-19

13-08-05

SOT362-1

MO-153

Fig. 11. Package outline SOT362-1 (TSSOP48)

74LVC_LVCH162373A

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Product data sheet

Rev. 6 — 16 September 2021

11 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym

CDM

CMOS

DUT

Description

Charged Device Model

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

- 74LVC_LVCH162373A v.5

74LVC_LVCH162373A v.6 20210916

Product data sheet

Modifications:

•

Type number 74LVCH162373ADL (SOT370-1/SSOP48) removed.

Section 1 and Section 2 updated.

74LVC_LVCH162373A v.5 20210414

Product data sheet

74LVC_LVCH162373A v.4

Modifications:

•

The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•

Legal texts have been adapted to the new company name where appropriate.

Type number 74LVC162373ADL (SOT370-1/SSOP48) removed.

Section 7: Derating values for P_tottotal power dissipation have been updated.

Fig. 11: Package outline drawing of SOT362-1/TSSOP48 has changed.

74LVC_LVCH162373A v.4 20130514

Modifications:

74LVC_LVCH162373A v.3 20130118

Product data sheet

Type numbers: 74LVC162373ADGG and 74LVC162373ADL added.

Product data sheet 74LVC_LVCH162373A v.2

74LVC_LVCH162373A v.3

•

Modifications:

•

The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•

Legal texts have been adapted to the new company name where appropriate.

Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges.

74LVC_LVCH162373A v.2 20040205

74LVC_LVCH162373A v.1 19980805

Product specification

74LVC_LVCH162373A v.1

74LVC_LVCH162373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 16 September 2021

12 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

14. Legal information

the customer’s own risk.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

Data sheet status

document, and as such is not complete, exhaustive or legally binding.

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

74LVC_LVCH162373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 16 September 2021

13 / 14

Nexperia

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description.............................................................3

6. Functional description................................................. 4

7. Limiting values............................................................. 4

8. Recommended operating conditions..........................5

9. Static characteristics....................................................5

10. Dynamic characteristics............................................ 6

10.1. Waveforms and test circuit........................................ 8

11. Package outline........................................................ 11

12. Abbreviations............................................................12

13. Revision history........................................................12

14. Legal information......................................................13

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 16 September 2021

74LVC_LVCH162373A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 16 September 2021

14 / 14

74LVC162373ADGG [NEXPERIA]

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